summaryrefslogtreecommitdiffstats
path: root/arch/powerpc/boot
diff options
context:
space:
mode:
Diffstat (limited to 'arch/powerpc/boot')
-rw-r--r--arch/powerpc/boot/Makefile23
-rw-r--r--arch/powerpc/boot/cuboot-c2k.c189
-rw-r--r--arch/powerpc/boot/dts/c2k.dts366
-rw-r--r--arch/powerpc/boot/dts/fsl/t104xqds.dtsi2
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts331
-rw-r--r--arch/powerpc/boot/mpc8xx.c3
-rw-r--r--arch/powerpc/boot/mpsc.c169
-rw-r--r--arch/powerpc/boot/mv64x60.c581
-rw-r--r--arch/powerpc/boot/mv64x60.h70
-rw-r--r--arch/powerpc/boot/mv64x60_i2c.c204
-rw-r--r--arch/powerpc/boot/ops.h1
-rw-r--r--arch/powerpc/boot/serial.c4
12 files changed, 16 insertions, 1927 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index 26d5d2a5b8e99..deea20c334df4 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -23,19 +23,23 @@ all: $(obj)/zImage
compress-$(CONFIG_KERNEL_GZIP) := CONFIG_KERNEL_GZIP
compress-$(CONFIG_KERNEL_XZ) := CONFIG_KERNEL_XZ
+ifdef CROSS32_COMPILE
+ BOOTCC := $(CROSS32_COMPILE)gcc
+ BOOTAR := $(CROSS32_COMPILE)ar
+else
+ BOOTCC := $(CC)
+ BOOTAR := $(AR)
+endif
+
BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
-fno-strict-aliasing -Os -msoft-float -pipe \
-fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
-D$(compress-y)
-BOOTCC := $(CC)
ifdef CONFIG_PPC64_BOOT_WRAPPER
BOOTCFLAGS += -m64
else
BOOTCFLAGS += -m32
-ifdef CROSS32_COMPILE
- BOOTCC := $(CROSS32_COMPILE)gcc
-endif
endif
BOOTCFLAGS += -isystem $(shell $(BOOTCC) -print-file-name=include)
@@ -49,6 +53,8 @@ endif
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -traditional -nostdinc
+BOOTARFLAGS := -cr$(KBUILD_ARFLAGS)
+
ifdef CONFIG_DEBUG_INFO
BOOTCFLAGS += -g
endif
@@ -120,7 +126,7 @@ src-wlib-$(CONFIG_40x) += 4xx.c planetcore.c
src-wlib-$(CONFIG_44x) += 4xx.c ebony.c bamboo.c
src-wlib-$(CONFIG_PPC_8xx) += mpc8xx.c planetcore.c fsl-soc.c
src-wlib-$(CONFIG_PPC_82xx) += pq2.c fsl-soc.c planetcore.c
-src-wlib-$(CONFIG_EMBEDDED6xx) += mpsc.c mv64x60.c mv64x60_i2c.c ugecon.c fsl-soc.c
+src-wlib-$(CONFIG_EMBEDDED6xx) += ugecon.c fsl-soc.c
src-wlib-$(CONFIG_XILINX_VIRTEX) += uartlite.c
src-wlib-$(CONFIG_CPM) += cpm-serial.c
@@ -143,8 +149,8 @@ src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
- cuboot-c2k.c gamecube-head.S \
- gamecube.c wii-head.S wii.c holly.c \
+ gamecube-head.S gamecube.c \
+ wii-head.S wii.c holly.c \
fixed-head.S mvme5100.c
src-plat-$(CONFIG_AMIGAONE) += cuboot-amigaone.c
src-plat-$(CONFIG_PPC_PS3) += ps3-head.S ps3-hvcall.S ps3.c
@@ -202,7 +208,7 @@ quiet_cmd_bootas = BOOTAS $@
cmd_bootas = $(BOOTCC) -Wp,-MD,$(depfile) $(BOOTAFLAGS) -c -o $@ $<
quiet_cmd_bootar = BOOTAR $@
- cmd_bootar = $(CROSS32AR) -cr$(KBUILD_ARFLAGS) $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
+ cmd_bootar = $(BOOTAR) $(BOOTARFLAGS) $@.$$$$ $(filter-out FORCE,$^); mv $@.$$$$ $@
$(obj-libfdt): $(obj)/%.o: $(srctree)/scripts/dtc/libfdt/%.c FORCE
$(call if_changed_dep,bootcc)
@@ -339,7 +345,6 @@ image-$(CONFIG_MVME7100) += dtbImage.mvme7100
# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
image-$(CONFIG_STORCENTER) += cuImage.storcenter
image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
-image-$(CONFIG_PPC_C2K) += cuImage.c2k
image-$(CONFIG_GAMECUBE) += dtbImage.gamecube
image-$(CONFIG_WII) += dtbImage.wii
image-$(CONFIG_MVME5100) += dtbImage.mvme5100
diff --git a/arch/powerpc/boot/cuboot-c2k.c b/arch/powerpc/boot/cuboot-c2k.c
deleted file mode 100644
index 9309c51f1d65d..0000000000000
--- a/arch/powerpc/boot/cuboot-c2k.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * GEFanuc C2K platform code.
- *
- * Author: Remi Machet <rmachet@slac.stanford.edu>
- *
- * Originated from prpmc2800.c
- *
- * 2008 (c) Stanford University
- * 2007 (c) MontaVista, Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-#include "types.h"
-#include "stdio.h"
-#include "io.h"
-#include "ops.h"
-#include "elf.h"
-#include "mv64x60.h"
-#include "cuboot.h"
-#include "ppcboot.h"
-
-static u8 *bridge_base;
-
-static void c2k_bridge_setup(u32 mem_size)
-{
- u32 i, v[30], enables, acc_bits;
- u32 pci_base_hi, pci_base_lo, size, buf[2];
- unsigned long cpu_base;
- int rc;
- void *devp, *mv64x60_devp;
- u8 *bridge_pbase, is_coherent;
- struct mv64x60_cpu2pci_win *tbl;
- int bus;
-
- bridge_pbase = mv64x60_get_bridge_pbase();
- is_coherent = mv64x60_is_coherent();
-
- if (is_coherent)
- acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB
- | MV64x60_PCI_ACC_CNTL_SWAP_NONE
- | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES
- | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES;
- else
- acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE
- | MV64x60_PCI_ACC_CNTL_SWAP_NONE
- | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES
- | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-
- mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent);
- mv64x60_devp = find_node_by_compatible(NULL, "marvell,mv64360");
- if (mv64x60_devp == NULL)
- fatal("Error: Missing marvell,mv64360 device tree node\n\r");
-
- enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE));
- enables |= 0x007ffe00; /* Disable all cpu->pci windows */
- out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables);
-
- /* Get the cpu -> pci i/o & mem mappings from the device tree */
- devp = NULL;
- for (bus = 0; ; bus++) {
- char name[] = "pci ";
-
- name[strlen(name)-1] = bus+'0';
-
- devp = find_node_by_alias(name);
- if (devp == NULL)
- break;
-
- if (bus >= 2)
- fatal("Error: Only 2 PCI controllers are supported at" \
- " this time.\n");
-
- mv64x60_config_pci_windows(bridge_base, bridge_pbase, bus, 0,
- mem_size, acc_bits);
-
- rc = getprop(devp, "ranges", v, sizeof(v));
- if (rc == 0)
- fatal("Error: Can't find marvell,mv64360-pci ranges"
- " property\n\r");
-
- /* Get the cpu -> pci i/o & mem mappings from the device tree */
-
- for (i = 0; i < rc; i += 6) {
- switch (v[i] & 0xff000000) {
- case 0x01000000: /* PCI I/O Space */
- tbl = mv64x60_cpu2pci_io;
- break;
- case 0x02000000: /* PCI MEM Space */
- tbl = mv64x60_cpu2pci_mem;
- break;
- default:
- continue;
- }
-
- pci_base_hi = v[i+1];
- pci_base_lo = v[i+2];
- cpu_base = v[i+3];
- size = v[i+5];
-
- buf[0] = cpu_base;
- buf[1] = size;
-
- if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base))
- fatal("Error: Can't translate PCI address " \
- "0x%x\n\r", (u32)cpu_base);
-
- mv64x60_config_cpu2pci_window(bridge_base, bus,
- pci_base_hi, pci_base_lo, cpu_base, size, tbl);
- }
-
- enables &= ~(3<<(9+bus*5)); /* Enable cpu->pci<bus> i/o,
- cpu->pci<bus> mem0 */
- out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE),
- enables);
- };
-}
-
-static void c2k_fixups(void)
-{
- u32 mem_size;
-
- mem_size = mv64x60_get_mem_size(bridge_base);
- c2k_bridge_setup(mem_size); /* Do necessary bridge setup */
-}
-
-#define MV64x60_MPP_CNTL_0 0xf000
-#define MV64x60_MPP_CNTL_2 0xf008
-#define MV64x60_GPP_IO_CNTL 0xf100
-#define MV64x60_GPP_LEVEL_CNTL 0xf110
-#define MV64x60_GPP_VALUE_SET 0xf118
-
-static void c2k_reset(void)
-{
- u32 temp;
-
- udelay(5000000);
-
- if (bridge_base != 0) {
- temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0));
- temp &= 0xFFFF0FFF;
- out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp);
-
- temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
- temp |= 0x00000004;
- out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
-
- temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
- temp |= 0x00000004;
- out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
-
- temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2));
- temp &= 0xFFFF0FFF;
- out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp);
-
- temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL));
- temp |= 0x00080000;
- out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp);
-
- temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL));
- temp |= 0x00080000;
- out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp);
-
- out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET),
- 0x00080004);
- }
-
- for (;;);
-}
-
-static bd_t bd;
-
-void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
- unsigned long r6, unsigned long r7)
-{
- CUBOOT_INIT();
-
- fdt_init(_dtb_start);
-
- bridge_base = mv64x60_get_bridge_base();
-
- platform_ops.fixups = c2k_fixups;
- platform_ops.exit = c2k_reset;
-
- if (serial_console_init() < 0)
- exit();
-}
diff --git a/arch/powerpc/boot/dts/c2k.dts b/arch/powerpc/boot/dts/c2k.dts
deleted file mode 100644
index c5beb72d18b7a..0000000000000
--- a/arch/powerpc/boot/dts/c2k.dts
+++ /dev/null
@@ -1,366 +0,0 @@
-/* Device Tree Source for GEFanuc C2K
- *
- * Author: Remi Machet <rmachet@slac.stanford.edu>
- *
- * Originated from prpmc2800.dts
- *
- * 2008 (c) Stanford University
- * 2007 (c) MontaVista, Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- */
-
-/dts-v1/;
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- model = "C2K";
- compatible = "GEFanuc,C2K";
- coherency-off;
-
- aliases {
- pci0 = &PCI0;
- pci1 = &PCI1;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "PowerPC,7447";
- reg = <0>;
- clock-frequency = <996000000>; /* 996 MHz */
- bus-frequency = <166666667>; /* 166.6666 MHz */
- timebase-frequency = <41666667>; /* 166.6666/4 MHz */
- i-cache-line-size = <32>;
- d-cache-line-size = <32>;
- i-cache-size = <32768>;
- d-cache-size = <32768>;
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x40000000>; /* 1GB */
- };
-
- system-controller@d8000000 { /* Marvell Discovery */
- #address-cells = <1>;
- #size-cells = <1>;
- model = "mv64460";
- compatible = "marvell,mv64360";
- clock-frequency = <166666667>; /* 166.66... MHz */
- reg = <0xd8000000 0x00010000>;
- virtual-reg = <0xd8000000>;
- ranges = <0xd4000000 0xd4000000 0x01000000 /* PCI 0 I/O Space */
- 0x80000000 0x80000000 0x08000000 /* PCI 0 MEM Space */
- 0xd0000000 0xd0000000 0x01000000 /* PCI 1 I/O Space */
- 0xa0000000 0xa0000000 0x08000000 /* PCI 1 MEM Space */
- 0xd8100000 0xd8100000 0x00010000 /* FPGA */
- 0xd8110000 0xd8110000 0x00010000 /* FPGA USARTs */
- 0xf8000000 0xf8000000 0x08000000 /* User FLASH */
- 0x00000000 0xd8000000 0x00010000 /* Bridge's regs */
- 0xd8140000 0xd8140000 0x00040000>; /* Integrated SRAM */
-
- mdio@2000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,mv64360-mdio";
- reg = <0x2000 4>;
- PHY0: ethernet-phy@0 {
- interrupts = <76>; /* GPP 12 */
- interrupt-parent = <&PIC>;
- reg = <0>;
- };
- PHY1: ethernet-phy@1 {
- interrupts = <76>; /* GPP 12 */
- interrupt-parent = <&PIC>;
- reg = <1>;
- };
- PHY2: ethernet-phy@2 {
- interrupts = <76>; /* GPP 12 */
- interrupt-parent = <&PIC>;
- reg = <2>;
- };
- };
-
- ethernet-group@2000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,mv64360-eth-group";
- reg = <0x2000 0x2000>;
- ethernet@0 {
- device_type = "network";
- compatible = "marvell,mv64360-eth";
- reg = <0>;
- interrupts = <32>;
- interrupt-parent = <&PIC>;
- phy = <&PHY0>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- };
- ethernet@1 {
- device_type = "network";
- compatible = "marvell,mv64360-eth";
- reg = <1>;
- interrupts = <33>;
- interrupt-parent = <&PIC>;
- phy = <&PHY1>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- };
- ethernet@2 {
- device_type = "network";
- compatible = "marvell,mv64360-eth";
- reg = <2>;
- interrupts = <34>;
- interrupt-parent = <&PIC>;
- phy = <&PHY2>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- };
- };
-
- SDMA0: sdma@4000 {
- compatible = "marvell,mv64360-sdma";
- reg = <0x4000 0xc18>;
- virtual-reg = <0xd8004000>;
- interrupt-base = <0>;
- interrupts = <36>;
- interrupt-parent = <&PIC>;
- };
-
- SDMA1: sdma@6000 {
- compatible = "marvell,mv64360-sdma";
- reg = <0x6000 0xc18>;
- virtual-reg = <0xd8006000>;
- interrupt-base = <0>;
- interrupts = <38>;
- interrupt-parent = <&PIC>;
- };
-
- BRG0: brg@b200 {
- compatible = "marvell,mv64360-brg";
- reg = <0xb200 0x8>;
- clock-src = <8>;
- clock-frequency = <133333333>;
- current-speed = <115200>;
- };
-
- BRG1: brg@b208 {
- compatible = "marvell,mv64360-brg";
- reg = <0xb208 0x8>;
- clock-src = <8>;
- clock-frequency = <133333333>;
- current-speed = <115200>;
- };
-
- CUNIT: cunit@f200 {
- reg = <0xf200 0x200>;
- };
-
- MPSCROUTING: mpscrouting@b400 {
- reg = <0xb400 0xc>;
- };
-
- MPSCINTR: mpscintr@b800 {
- reg = <0xb800 0x100>;
- virtual-reg = <0xd800b800>;
- };
-
- MPSC0: mpsc@8000 {
- compatible = "marvell,mv64360-mpsc";
- reg = <0x8000 0x38>;
- virtual-reg = <0xd8008000>;
- sdma = <&SDMA0>;
- brg = <&BRG0>;
- cunit = <&CUNIT>;
- mpscrouting = <&MPSCROUTING>;
- mpscintr = <&MPSCINTR>;
- cell-index = <0>;
- interrupts = <40>;
- interrupt-parent = <&PIC>;
- };
-
- MPSC1: mpsc@9000 {
- compatible = "marvell,mv64360-mpsc";
- reg = <0x9000 0x38>;
- virtual-reg = <0xd8009000>;
- sdma = <&SDMA1>;
- brg = <&BRG1>;
- cunit = <&CUNIT>;
- mpscrouting = <&MPSCROUTING>;
- mpscintr = <&MPSCINTR>;
- cell-index = <1>;
- interrupts = <42>;
- interrupt-parent = <&PIC>;
- };
-
- wdt@b410 { /* watchdog timer */
- compatible = "marvell,mv64360-wdt";
- reg = <0xb410 0x8>;
- };
-
- i2c@c000 {
- compatible = "marvell,mv64360-i2c";
- reg = <0xc000 0x20>;
- virtual-reg = <0xd800c000>;
- interrupts = <37>;
- interrupt-parent = <&PIC>;
- };
-
- PIC: pic {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- compatible = "marvell,mv64360-pic";
- reg = <0x0000 0x88>;
- interrupt-controller;
- };
-
- mpp@f000 {
- compatible = "marvell,mv64360-mpp";
- reg = <0xf000 0x10>;
- };
-
- gpp@f100 {
- compatible = "marvell,mv64360-gpp";
- reg = <0xf100 0x20>;
- };
-
- PCI0: pci@80000000 {
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- compatible = "marvell,mv64360-pci";
- reg = <0x0cf8 0x8>;
- ranges = <0x01000000 0x0 0x00000000 0xd4000000 0x0 0x01000000
- 0x02000000 0x0 0x80000000 0x80000000 0x0 0x08000000>;
- bus-range = <0 255>;
- clock-frequency = <66000000>;
- interrupt-pci-iack = <0x0c34>;
- interrupt-parent = <&PIC>;
- interrupt-map-mask = <0x0000 0x0 0x0 0x7>;
- interrupt-map = <
- /* Only one interrupt line for PMC0 slot (INTA) */
- 0x0000 0 0 1 &PIC 88
- >;
- };
-
-
- PCI1: pci@a0000000 {
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- compatible = "marvell,mv64360-pci";
- reg = <0x0c78 0x8>;
- ranges = <0x01000000 0x0 0x00000000 0xd0000000 0x0 0x01000000
- 0x02000000 0x0 0x80000000 0xa0000000 0x0 0x08000000>;
- bus-range = <0 255>;
- clock-frequency = <66000000>;
- interrupt-pci-iack = <0x0cb4>;
- interrupt-parent = <&PIC>;
- interrupt-map-mask = <0xf800 0x00 0x00 0x7>;
- interrupt-map = <
- /* IDSEL 0x01: PMC1 ? */
- 0x0800 0 0 1 &PIC 88
- /* IDSEL 0x02: cPCI bridge */
- 0x1000 0 0 1 &PIC 88
- /* IDSEL 0x03: USB controller */
- 0x1800 0 0 1 &PIC 91
- /* IDSEL 0x04: SATA controller */
- 0x2000 0 0 1 &PIC 95
- >;
- };
-
- cpu-error@70 {
- compatible = "marvell,mv64360-cpu-error";
- reg = <0x0070 0x10 0x0128 0x28>;
- interrupts = <3>;
- interrupt-parent = <&PIC>;
- };
-
- sram-ctrl@380 {
- compatible = "marvell,mv64360-sram-ctrl";
- reg = <0x0380 0x80>;
- interrupts = <13>;
- interrupt-parent = <&PIC>;
- };
-
- pci-error@1d40 {
- compatible = "marvell,mv64360-pci-error";
- reg = <0x1d40 0x40 0x0c28 0x4>;
- interrupts = <12>;
- interrupt-parent = <&PIC>;
- };
-
- pci-error@1dc0 {
- compatible = "marvell,mv64360-pci-error";
- reg = <0x1dc0 0x40 0x0ca8 0x4>;
- interrupts = <16>;
- interrupt-parent = <&PIC>;
- };
-
- mem-ctrl@1400 {
- compatible = "marvell,mv64360-mem-ctrl";
- reg = <0x1400 0x60>;
- interrupts = <17>;
- interrupt-parent = <&PIC>;
- };
- /* Devices attached to the device controller */
- devicebus@45c {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "marvell,mv64306-devctrl";
- reg = <0x45C 0x88>;
- interrupts = <1>;
- interrupt-parent = <&PIC>;
- ranges = <0 0 0xd8100000 0x10000
- 2 0 0xd8110000 0x10000
- 4 0 0xf8000000 0x8000000>;
- fpga@0,0 {
- compatible = "sbs,fpga-c2k";
- reg = <0 0 0x10000>;
- };
- fpga_usart@2,0 {
- compatible = "sbs,fpga_usart-c2k";
- reg = <2 0 0x10000>;
- };
- nor_flash@4,0 {
- compatible = "cfi-flash";
- reg = <4 0 0x8000000>; /* 128MB */
- bank-width = <4>;
- device-width = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@0 {
- label = "boot";
- reg = <0x00000000 0x00080000>;
- };
- partition@40000 {
- label = "kernel";
- reg = <0x00080000 0x00400000>;
- };
- partition@440000 {
- label = "initrd";
- reg = <0x00480000 0x00B80000>;
- };
- partition@1000000 {
- label = "rootfs";
- reg = <0x01000000 0x06800000>;
- };
- partition@7800000 {
- label = "recovery";
- reg = <0x07800000 0x00800000>;
- read-only;
- };
- };
- };
- };
- chosen {
- stdout-path = &MPSC0;
- };
-};
diff --git a/arch/powerpc/boot/dts/fsl/t104xqds.dtsi b/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
index 2fd4cbe7098f8..6154797322524 100644
--- a/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t104xqds.dtsi
@@ -269,7 +269,7 @@
i2c@118000 {
pca9547@77 {
- compatible = "philips,pca9547";
+ compatible = "nxp,pca9547";
reg = <0x77>;
};
rtc@68 {
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
deleted file mode 100644
index fc89e00b765cf..0000000000000
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * SBC8349E Device Tree Source
- *
- * Copyright 2007 Wind River Inc.
- *
- * Paul Gortmaker (see MAINTAINERS for contact information)
- *
- * -based largely on the Freescale MPC834x_MDS dts.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-/dts-v1/;
-
-/ {
- model = "SBC8349E";
- compatible = "SBC834xE";
- #address-cells = <1>;
- #size-cells = <1>;
-
- aliases {
- ethernet0 = &enet0;
- ethernet1 = &enet1;
- serial0 = &serial0;
- serial1 = &serial1;
- pci0 = &pci0;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- PowerPC,8349@0 {
- device_type = "cpu";
- reg = <0x0>;
- d-cache-line-size = <32>;
- i-cache-line-size = <32>;
- d-cache-size = <32768>;
- i-cache-size = <32768>;
- timebase-frequency = <0>; // from bootloader
- bus-frequency = <0>; // from bootloader
- clock-frequency = <0>; // from bootloader
- };
- };
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>; // 256MB at 0
- };
-
- soc8349@e0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- device_type = "soc";
- ranges = <0x0 0xe0000000 0x00100000>;
- reg = <0xe0000000 0x00000200>;
- bus-frequency = <0>;
-
- wdt@200 {
- compatible = "mpc83xx_wdt";
- reg = <0x200 0x100>;
- };
-
- i2c@3000 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- compatible = "fsl-i2c";
- reg = <0x3000 0x100>;
- interrupts = <14 0x8>;
- interrupt-parent = <&ipic>;
- dfsrr;
- };
-
- i2c@3100 {
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- compatible = "fsl-i2c";
- reg = <0x3100 0x100>;
- interrupts = <15 0x8>;
- interrupt-parent = <&ipic>;
- dfsrr;
- };
-
- spi@7000 {
- cell-index = <0>;
- compatible = "fsl,spi";
- reg = <0x7000 0x1000>;
- interrupts = <16 0x8>;
- interrupt-parent = <&ipic>;
- mode = "cpu";
- };
-
- dma@82a8 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
- reg = <0x82a8 4>;
- ranges = <0 0x8100 0x1a8>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- cell-index = <0>;
- dma-channel@0 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- reg = <0 0x80>;
- cell-index = <0>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@80 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- reg = <0x80 0x80>;
- cell-index = <1>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@100 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- reg = <0x100 0x80>;
- cell-index = <2>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- dma-channel@180 {
- compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
- reg = <0x180 0x28>;
- cell-index = <3>;
- interrupt-parent = <&ipic>;
- interrupts = <71 8>;
- };
- };
-
- /* phy type (ULPI or SERIAL) are only types supported for MPH */
- /* port = 0 or 1 */
- usb@22000 {
- compatible = "fsl-usb2-mph";
- reg = <0x22000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupt-parent = <&ipic>;
- interrupts = <39 0x8>;
- phy_type = "ulpi";
- port0;
- };
-
- enet0: ethernet@24000 {
- #address-cells = <1>;
- #size-cells = <1>;
- cell-index = <0>;
- device_type = "network";
- model = "TSEC";
- compatible = "gianfar";
- reg = <0x24000 0x1000>;
- ranges = <0x0 0x24000 0x1000>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <32 0x8 33 0x8 34 0x8>;
- interrupt-parent = <&ipic>;
- tbi-handle = <&tbi0>;
- phy-handle = <&phy0>;
- linux,network-index = <0>;
-
- mdio@520 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,gianfar-mdio";
- reg = <0x520 0x20>;
-
- phy0: ethernet-phy@19 {
- interrupt-parent = <&ipic>;
- interrupts = <20 0x8>;
- reg = <0x19>;
- };
-
- phy1: ethernet-phy@1a {
- interrupt-parent = <&ipic>;
- interrupts = <21 0x8>;
- reg = <0x1a>;
- };
-
- tbi0: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
- };
-
- enet1: ethernet@25000 {
- #address-cells = <1>;
- #size-cells = <1>;
- cell-index = <1>;
- device_type = "network";
- model = "TSEC";
- compatible = "gianfar";
- reg = <0x25000 0x1000>;
- ranges = <0x0 0x25000 0x1000>;
- local-mac-address = [ 00 00 00 00 00 00 ];
- interrupts = <35 0x8 36 0x8 37 0x8>;
- interrupt-parent = <&ipic>;
- tbi-handle = <&tbi1>;
- phy-handle = <&phy1>;
- linux,network-index = <1>;
-
- mdio@520 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,gianfar-tbi";
- reg = <0x520 0x20>;
-
- tbi1: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
- };
-
- serial0: serial@4500 {
- cell-index = <0>;
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550";
- reg = <0x4500 0x100>;
- clock-frequency = <0>;
- interrupts = <9 0x8>;
- interrupt-parent = <&ipic>;
- };
-
- serial1: serial@4600 {
- cell-index = <1>;
- device_type = "serial";
- compatible = "fsl,ns16550", "ns16550";
- reg = <0x4600 0x100>;
- clock-frequency = <0>;
- interrupts = <10 0x8>;
- interrupt-parent = <&ipic>;
- };
-
- crypto@30000 {
- compatible = "fsl,sec2.0";
- reg = <0x30000 0x10000>;
- interrupts = <11 0x8>;
- interrupt-parent = <&ipic>;
- fsl,num-channels = <4>;
- fsl,channel-fifo-len = <24>;
- fsl,exec-units-mask = <0x7e>;
- fsl,descriptor-types-mask = <0x01010ebf>;
- };
-
- /* IPIC
- * interrupts cell = <intr #, sense>
- * sense values match linux IORESOURCE_IRQ_* defines:
- * sense == 8: Level, low assertion
- * sense == 2: Edge, high-to-low change
- */
- ipic: pic@700 {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <2>;
- reg = <0x700 0x100>;
- device_type = "ipic";
- };
- };
-
- localbus@e0005000 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "fsl,mpc8349-localbus", "simple-bus";
- reg = <0xe0005000 0x1000>;
- interrupts = <77 0x8>;
- interrupt-parent = <&ipic>;
- ranges = <0x0 0x0 0xff800000 0x00800000 /* 8MB Flash */
- 0x1 0x0 0xf8000000 0x00002000 /* 8KB EEPROM */
- 0x2 0x0 0x10000000 0x04000000 /* 64MB SDRAM */
- 0x3 0x0 0x10000000 0x04000000>; /* 64MB SDRAM */
-
- flash@0,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "intel,28F640J3A", "cfi-flash";
- reg = <0x0 0x0 0x800000>;
- bank-width = <2>;
- device-width = <1>;
-
- partition@0 {
- label = "u-boot";
- reg = <0x00000000 0x00040000>;
- read-only;
- };
-
- partition@40000 {
- label = "user";
- reg = <0x00040000 0x006c0000>;
- };
-
- partition@700000 {
- label = "legacy u-boot";
- reg = <0x00700000 0x00100000>;
- read-only;
- };
-
- };
- };
-
- pci0: pci@e0008500 {
- interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
- interrupt-map = <
-
- /* IDSEL 0x11 */
- 0x8800 0x0 0x0 0x1 &ipic 48 0x8
- 0x8800 0x0 0x0 0x2 &ipic 17 0x8
- 0x8800 0x0 0x0 0x3 &ipic 18 0x8
- 0x8800 0x0 0x0 0x4 &ipic 19 0x8>;
-
- interrupt-parent = <&ipic>;
- interrupts = <0x42 0x8>;
- bus-range = <0 0>;
- ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
- 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
- 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
- clock-frequency = <66666666>;
- #interrupt-cells = <1>;
- #size-cells = <2>;
- #address-cells = <3>;
- reg = <0xe0008500 0x100 /* internal registers */
- 0xe0008300 0x8>; /* config space access registers */
- compatible = "fsl,mpc8349-pci";
- device_type = "pci";
- };
-};
diff --git a/arch/powerpc/boot/mpc8xx.c b/arch/powerpc/boot/mpc8xx.c
index add55a7f184fa..c9bd9285c5489 100644
--- a/arch/powerpc/boot/mpc8xx.c
+++ b/arch/powerpc/boot/mpc8xx.c
@@ -24,7 +24,7 @@ u32 mpc885_get_clock(u32 crystal)
{
u32 *immr;
u32 plprcr;
- int mfi, mfn, mfd, pdf, div;
+ int mfi, mfn, mfd, pdf;
u32 ret;
immr = fsl_get_immr();
@@ -43,7 +43,6 @@ u32 mpc885_get_clock(u32 crystal)
}
pdf = (plprcr >> 1) & 0xf;
- div = (plprcr >> 20) & 3;
mfd = (plprcr >> 22) & 0x1f;
mfn = (plprcr >> 27) & 0x1f;
diff --git a/arch/powerpc/boot/mpsc.c b/arch/powerpc/boot/mpsc.c
deleted file mode 100644
index 425ad88cce8d9..0000000000000
--- a/arch/powerpc/boot/mpsc.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * MPSC/UART driver for the Marvell mv64360, mv64460, ...
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include "types.h"
-#include "string.h"
-#include "stdio.h"
-#include "io.h"
-#include "ops.h"
-
-
-#define MPSC_CHR_1 0x000c
-
-#define MPSC_CHR_2 0x0010
-#define MPSC_CHR_2_TA (1<<7)
-#define MPSC_CHR_2_TCS (1<<9)
-#define MPSC_CHR_2_RA (1<<23)
-#define MPSC_CHR_2_CRD (1<<25)
-#define MPSC_CHR_2_EH (1<<31)
-
-#define MPSC_CHR_4 0x0018
-#define MPSC_CHR_4_Z (1<<29)
-
-#define MPSC_CHR_5 0x001c
-#define MPSC_CHR_5_CTL1_INTR (1<<12)
-#define MPSC_CHR_5_CTL1_VALID (1<<15)
-
-#define MPSC_CHR_10 0x0030
-
-#define MPSC_INTR_CAUSE 0x0000
-#define MPSC_INTR_CAUSE_RCC (1<<6)
-#define MPSC_INTR_MASK 0x0080
-
-#define SDMA_SDCM 0x0008
-#define SDMA_SDCM_AR (1<<15)
-#define SDMA_SDCM_AT (1<<31)
-
-static volatile char *mpsc_base;
-static volatile char *mpscintr_base;
-static u32 chr1, chr2;
-
-static int mpsc_open(void)
-{
- chr1 = in_le32((u32 *)(mpsc_base + MPSC_CHR_1)) & 0x00ff0000;
- chr2 = in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & ~(MPSC_CHR_2_TA
- | MPSC_CHR_2_TCS | MPSC_CHR_2_RA | MPSC_CHR_2_CRD
- | MPSC_CHR_2_EH);
- out_le32((u32 *)(mpsc_base + MPSC_CHR_4), MPSC_CHR_4_Z);
- out_le32((u32 *)(mpsc_base + MPSC_CHR_5),
- MPSC_CHR_5_CTL1_INTR | MPSC_CHR_5_CTL1_VALID);
- out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_EH);
- return 0;
-}
-
-static void mpsc_putc(unsigned char c)
-{
- while (in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & MPSC_CHR_2_TCS);
-
- out_le32((u32 *)(mpsc_base + MPSC_CHR_1), chr1 | c);
- out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_TCS);
-}
-
-static unsigned char mpsc_getc(void)
-{
- u32 cause = 0;
- unsigned char c;
-
- while (!(cause & MPSC_INTR_CAUSE_RCC))
- cause = in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE));
-
- c = in_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2));
- out_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2), c);
- out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE),
- cause & ~MPSC_INTR_CAUSE_RCC);
-
- return c;
-}
-
-static u8 mpsc_tstc(void)
-{
- return (u8)((in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE))
- & MPSC_INTR_CAUSE_RCC) != 0);
-}
-
-static void mpsc_stop_dma(volatile char *sdma_base)
-{
- out_le32((u32 *)(mpsc_base + MPSC_CHR_2),MPSC_CHR_2_TA | MPSC_CHR_2_RA);
- out_le32((u32 *)(sdma_base + SDMA_SDCM), SDMA_SDCM_AR | SDMA_SDCM_AT);
-
- while ((in_le32((u32 *)(sdma_base + SDMA_SDCM))
- & (SDMA_SDCM_AR | SDMA_SDCM_AT)) != 0)
- udelay(100);
-}
-
-static volatile char *mpsc_get_virtreg_of_phandle(void *devp, char *prop)
-{
- void *v;
- int n;
-
- n = getprop(devp, prop, &v, sizeof(v));
- if (n != sizeof(v))
- goto err_out;
-
- devp = find_node_by_linuxphandle((u32)v);
- if (devp == NULL)
- goto err_out;
-
- n = getprop(devp, "virtual-reg", &v, sizeof(v));
- if (n == sizeof(v))
- return v;
-
-err_out:
- return NULL;
-}
-
-int mpsc_console_init(void *devp, struct serial_console_data *scdp)
-{
- void *v;
- int n, reg_set;
- volatile char *sdma_base;
-
- n = getprop(devp, "virtual-reg", &v, sizeof(v));
- if (n != sizeof(v))
- goto err_out;
- mpsc_base = v;
-
- sdma_base = mpsc_get_virtreg_of_phandle(devp, "sdma");
- if (sdma_base == NULL)
- goto err_out;
-
- mpscintr_base = mpsc_get_virtreg_of_phandle(devp, "mpscintr");
- if (mpscintr_base == NULL)
- goto err_out;
-
- n = getprop(devp, "cell-index", &v, sizeof(v));
- if (n != sizeof(v))
- goto err_out;
- reg_set = (int)v;
-
- mpscintr_base += (reg_set == 0) ? 0x4 : 0xc;
-
- /* Make sure the mpsc ctlrs are shutdown */
- out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0);
- out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0);
- out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0);
- out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0);
-
- mpsc_stop_dma(sdma_base);
-
- scdp->open = mpsc_open;
- scdp->putc = mpsc_putc;
- scdp->getc = mpsc_getc;
- scdp->tstc = mpsc_tstc;
- scdp->close = NULL;
-
- return 0;
-
-err_out:
- return -1;
-}
diff --git a/arch/powerpc/boot/mv64x60.c b/arch/powerpc/boot/mv64x60.c
deleted file mode 100644
index d9bb302b91d28..0000000000000
--- a/arch/powerpc/boot/mv64x60.c
+++ /dev/null
@@ -1,581 +0,0 @@
-/*
- * Marvell hostbridge routines
- *
- * Author: Mark A. Greer <source@mvista.com>
- *
- * 2004, 2005, 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include "types.h"
-#include "elf.h"
-#include "page.h"
-#include "string.h"
-#include "stdio.h"
-#include "io.h"
-#include "ops.h"
-#include "mv64x60.h"
-
-#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
-
-#define MV64x60_CPU2MEM_WINDOWS 4
-#define MV64x60_CPU2MEM_0_BASE 0x0008
-#define MV64x60_CPU2MEM_0_SIZE 0x0010
-#define MV64x60_CPU2MEM_1_BASE 0x0208
-#define MV64x60_CPU2MEM_1_SIZE 0x0210
-#define MV64x60_CPU2MEM_2_BASE 0x0018
-#define MV64x60_CPU2MEM_2_SIZE 0x0020
-#define MV64x60_CPU2MEM_3_BASE 0x0218
-#define MV64x60_CPU2MEM_3_SIZE 0x0220
-
-#define MV64x60_ENET2MEM_BAR_ENABLE 0x2290
-#define MV64x60_ENET2MEM_0_BASE 0x2200
-#define MV64x60_ENET2MEM_0_SIZE 0x2204
-#define MV64x60_ENET2MEM_1_BASE 0x2208
-#define MV64x60_ENET2MEM_1_SIZE 0x220c
-#define MV64x60_ENET2MEM_2_BASE 0x2210
-#define MV64x60_ENET2MEM_2_SIZE 0x2214
-#define MV64x60_ENET2MEM_3_BASE 0x2218
-#define MV64x60_ENET2MEM_3_SIZE 0x221c
-#define MV64x60_ENET2MEM_4_BASE 0x2220
-#define MV64x60_ENET2MEM_4_SIZE 0x2224
-#define MV64x60_ENET2MEM_5_BASE 0x2228
-#define MV64x60_ENET2MEM_5_SIZE 0x222c
-#define MV64x60_ENET2MEM_ACC_PROT_0 0x2294
-#define MV64x60_ENET2MEM_ACC_PROT_1 0x2298
-#define MV64x60_ENET2MEM_ACC_PROT_2 0x229c
-
-#define MV64x60_MPSC2MEM_BAR_ENABLE 0xf250
-#define MV64x60_MPSC2MEM_0_BASE 0xf200
-#define MV64x60_MPSC2MEM_0_SIZE 0xf204
-#define MV64x60_MPSC2MEM_1_BASE 0xf208
-#define MV64x60_MPSC2MEM_1_SIZE 0xf20c
-#define MV64x60_MPSC2MEM_2_BASE 0xf210
-#define MV64x60_MPSC2MEM_2_SIZE 0xf214
-#define MV64x60_MPSC2MEM_3_BASE 0xf218
-#define MV64x60_MPSC2MEM_3_SIZE 0xf21c
-#define MV64x60_MPSC_0_REMAP 0xf240
-#define MV64x60_MPSC_1_REMAP 0xf244
-#define MV64x60_MPSC2MEM_ACC_PROT_0 0xf254
-#define MV64x60_MPSC2MEM_ACC_PROT_1 0xf258
-#define MV64x60_MPSC2REGS_BASE 0xf25c
-
-#define MV64x60_IDMA2MEM_BAR_ENABLE 0x0a80
-#define MV64x60_IDMA2MEM_0_BASE 0x0a00
-#define MV64x60_IDMA2MEM_0_SIZE 0x0a04
-#define MV64x60_IDMA2MEM_1_BASE 0x0a08
-#define MV64x60_IDMA2MEM_1_SIZE 0x0a0c
-#define MV64x60_IDMA2MEM_2_BASE 0x0a10
-#define MV64x60_IDMA2MEM_2_SIZE 0x0a14
-#define MV64x60_IDMA2MEM_3_BASE 0x0a18
-#define MV64x60_IDMA2MEM_3_SIZE 0x0a1c
-#define MV64x60_IDMA2MEM_4_BASE 0x0a20
-#define MV64x60_IDMA2MEM_4_SIZE 0x0a24
-#define MV64x60_IDMA2MEM_5_BASE 0x0a28
-#define MV64x60_IDMA2MEM_5_SIZE 0x0a2c
-#define MV64x60_IDMA2MEM_6_BASE 0x0a30
-#define MV64x60_IDMA2MEM_6_SIZE 0x0a34
-#define MV64x60_IDMA2MEM_7_BASE 0x0a38
-#define MV64x60_IDMA2MEM_7_SIZE 0x0a3c
-#define MV64x60_IDMA2MEM_ACC_PROT_0 0x0a70
-#define MV64x60_IDMA2MEM_ACC_PROT_1 0x0a74
-#define MV64x60_IDMA2MEM_ACC_PROT_2 0x0a78
-#define MV64x60_IDMA2MEM_ACC_PROT_3 0x0a7c
-
-#define MV64x60_PCI_ACC_CNTL_WINDOWS 6
-#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c
-#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc
-
-#define MV64x60_PCI0_BAR_ENABLE 0x0c3c
-#define MV64x60_PCI02MEM_0_SIZE 0x0c08
-#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00
-#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04
-#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08
-#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10
-#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14
-#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18
-#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20
-#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24
-#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28
-#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30
-#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34
-#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38
-#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40
-#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44
-#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48
-#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50
-#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54
-#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58
-
-#define MV64x60_PCI1_BAR_ENABLE 0x0cbc
-#define MV64x60_PCI12MEM_0_SIZE 0x0c88
-#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80
-#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84
-#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88
-#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90
-#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94
-#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98
-#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0
-#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4
-#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8
-#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0
-#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4
-#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8
-#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0
-#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4
-#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8
-#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0
-#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4
-#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8
-
-#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000
-
-#define MV64x60_CPU2PCI0_IO_BASE 0x0048
-#define MV64x60_CPU2PCI0_IO_SIZE 0x0050
-#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0
-#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058
-#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060
-#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8
-#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320
-
-#define MV64x60_CPU2PCI1_IO_BASE 0x0090
-#define MV64x60_CPU2PCI1_IO_SIZE 0x0098
-#define MV64x60_CPU2PCI1_IO_REMAP 0x0108
-#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0
-#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8
-#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110
-#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340
-
-struct mv64x60_mem_win {
- u32 hi;
- u32 lo;
- u32 size;
-};
-
-struct mv64x60_pci_win {
- u32 fcn;
- u32 hi;
- u32 lo;
- u32 size;
-};
-
-/* PCI config access routines */
-struct {
- u32 addr;
- u32 data;
-} static mv64x60_pci_cfgio[2] = {
- { /* hose 0 */
- .addr = 0xcf8,
- .data = 0xcfc,
- },
- { /* hose 1 */
- .addr = 0xc78,
- .data = 0xc7c,
- }
-};
-
-u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset)
-{
- out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
- (1 << 31) | (bus << 16) | (devfn << 8) | offset);
- return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data));
-}
-
-void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset,
- u32 val)
-{
- out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr),
- (1 << 31) | (bus << 16) | (devfn << 8) | offset);
- out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val);
-}
-
-/* I/O ctlr -> system memory setup */
-static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = {
- {
- .lo = MV64x60_CPU2MEM_0_BASE,
- .size = MV64x60_CPU2MEM_0_SIZE,
- },
- {
- .lo = MV64x60_CPU2MEM_1_BASE,
- .size = MV64x60_CPU2MEM_1_SIZE,
- },
- {
- .lo = MV64x60_CPU2MEM_2_BASE,
- .size = MV64x60_CPU2MEM_2_SIZE,
- },
- {
- .lo = MV64x60_CPU2MEM_3_BASE,
- .size = MV64x60_CPU2MEM_3_SIZE,
- },
-};
-
-static struct mv64x60_mem_win mv64x60_enet2mem[MV64x60_CPU2MEM_WINDOWS] = {
- {
- .lo = MV64x60_ENET2MEM_0_BASE,
- .size = MV64x60_ENET2MEM_0_SIZE,
- },
- {
- .lo = MV64x60_ENET2MEM_1_BASE,
- .size = MV64x60_ENET2MEM_1_SIZE,
- },
- {
- .lo = MV64x60_ENET2MEM_2_BASE,
- .size = MV64x60_ENET2MEM_2_SIZE,
- },
- {
- .lo = MV64x60_ENET2MEM_3_BASE,
- .size = MV64x60_ENET2MEM_3_SIZE,
- },
-};
-
-static struct mv64x60_mem_win mv64x60_mpsc2mem[MV64x60_CPU2MEM_WINDOWS] = {
- {
- .lo = MV64x60_MPSC2MEM_0_BASE,
- .size = MV64x60_MPSC2MEM_0_SIZE,
- },
- {
- .lo = MV64x60_MPSC2MEM_1_BASE,
- .size = MV64x60_MPSC2MEM_1_SIZE,
- },
- {
- .lo = MV64x60_MPSC2MEM_2_BASE,
- .size = MV64x60_MPSC2MEM_2_SIZE,
- },
- {
- .lo = MV64x60_MPSC2MEM_3_BASE,
- .size = MV64x60_MPSC2MEM_3_SIZE,
- },
-};
-
-static struct mv64x60_mem_win mv64x60_idma2mem[MV64x60_CPU2MEM_WINDOWS] = {
- {
- .lo = MV64x60_IDMA2MEM_0_BASE,
- .size = MV64x60_IDMA2MEM_0_SIZE,
- },
- {
- .lo = MV64x60_IDMA2MEM_1_BASE,
- .size = MV64x60_IDMA2MEM_1_SIZE,
- },
- {
- .lo = MV64x60_IDMA2MEM_2_BASE,
- .size = MV64x60_IDMA2MEM_2_SIZE,
- },
- {
- .lo = MV64x60_IDMA2MEM_3_BASE,
- .size = MV64x60_IDMA2MEM_3_SIZE,
- },
-};
-
-static u32 mv64x60_dram_selects[MV64x60_CPU2MEM_WINDOWS] = {0xe,0xd,0xb,0x7};
-
-/*
- * ENET, MPSC, and IDMA ctlrs on the MV64x60 have separate windows that
- * must be set up so that the respective ctlr can access system memory.
- * Configure them to be same as cpu->memory windows.
- */
-void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
- u8 is_coherent)
-{
- u32 i, base, size, enables, prot = 0, snoop_bits = 0;
-
- /* Disable ctlr->mem windows */
- out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f);
- out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf);
- out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff);
-
- if (is_coherent)
- snoop_bits = 0x2 << 12; /* Writeback */
-
- enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
-
- for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
- if (enables & (1 << i)) /* Set means disabled */
- continue;
-
- base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo))
- << 16;
- base |= snoop_bits | (mv64x60_dram_selects[i] << 8);
- size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size))
- << 16;
- prot |= (0x3 << (i << 1)); /* RW access */
-
- out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base);
- out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size);
- out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base);
- out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size);
- out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base);
- out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].size), size);
- }
-
- out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_0), prot);
- out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_1), prot);
- out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_2), prot);
- out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_0), prot);
- out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_1), prot);
- out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_0), prot);
- out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_1), prot);
- out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_2), prot);
- out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_3), prot);
-
- /* Set mpsc->bridge's reg window to the bridge's internal registers. */
- out_le32((u32 *)(bridge_base + MV64x60_MPSC2REGS_BASE),
- (u32)bridge_pbase);
-
- out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), enables);
- out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), enables);
- out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_BAR_ENABLE), enables);
-}
-
-/* PCI MEM -> system memory, et. al. setup */
-static struct mv64x60_pci_win mv64x60_pci2mem[2] = {
- { /* hose 0 */
- .fcn = 0,
- .hi = 0x14,
- .lo = 0x10,
- .size = MV64x60_PCI02MEM_0_SIZE,
- },
- { /* hose 1 */
- .fcn = 0,
- .hi = 0x94,
- .lo = 0x90,
- .size = MV64x60_PCI12MEM_0_SIZE,
- },
-};
-
-static struct
-mv64x60_mem_win mv64x60_pci_acc[2][MV64x60_PCI_ACC_CNTL_WINDOWS] = {
- { /* hose 0 */
- {
- .hi = MV64x60_PCI0_ACC_CNTL_0_BASE_HI,
- .lo = MV64x60_PCI0_ACC_CNTL_0_BASE_LO,
- .size = MV64x60_PCI0_ACC_CNTL_0_SIZE,
- },
- {
- .hi = MV64x60_PCI0_ACC_CNTL_1_BASE_HI,
- .lo = MV64x60_PCI0_ACC_CNTL_1_BASE_LO,
- .size = MV64x60_PCI0_ACC_CNTL_1_SIZE,
- },
- {
- .hi = MV64x60_PCI0_ACC_CNTL_2_BASE_HI,
- .lo = MV64x60_PCI0_ACC_CNTL_2_BASE_LO,
- .size = MV64x60_PCI0_ACC_CNTL_2_SIZE,
- },
- {
- .hi = MV64x60_PCI0_ACC_CNTL_3_BASE_HI,
- .lo = MV64x60_PCI0_ACC_CNTL_3_BASE_LO,
- .size = MV64x60_PCI0_ACC_CNTL_3_SIZE,
- },
- },
- { /* hose 1 */
- {
- .hi = MV64x60_PCI1_ACC_CNTL_0_BASE_HI,
- .lo = MV64x60_PCI1_ACC_CNTL_0_BASE_LO,
- .size = MV64x60_PCI1_ACC_CNTL_0_SIZE,
- },
- {
- .hi = MV64x60_PCI1_ACC_CNTL_1_BASE_HI,
- .lo = MV64x60_PCI1_ACC_CNTL_1_BASE_LO,
- .size = MV64x60_PCI1_ACC_CNTL_1_SIZE,
- },
- {
- .hi = MV64x60_PCI1_ACC_CNTL_2_BASE_HI,
- .lo = MV64x60_PCI1_ACC_CNTL_2_BASE_LO,
- .size = MV64x60_PCI1_ACC_CNTL_2_SIZE,
- },
- {
- .hi = MV64x60_PCI1_ACC_CNTL_3_BASE_HI,
- .lo = MV64x60_PCI1_ACC_CNTL_3_BASE_LO,
- .size = MV64x60_PCI1_ACC_CNTL_3_SIZE,
- },
- },
-};
-
-static struct mv64x60_mem_win mv64x60_pci2reg[2] = {
- {
- .hi = 0x24,
- .lo = 0x20,
- .size = 0,
- },
- {
- .hi = 0xa4,
- .lo = 0xa0,
- .size = 0,
- },
-};
-
-/* Only need to use 1 window (per hose) to get access to all of system memory */
-void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
- u8 bus, u32 mem_size, u32 acc_bits)
-{
- u32 i, offset, bar_enable, enables;
-
- /* Disable all windows but PCI MEM -> Bridge's regs window */
- enables = ~(1 << 9);
- bar_enable = hose ? MV64x60_PCI1_BAR_ENABLE : MV64x60_PCI0_BAR_ENABLE;
- out_le32((u32 *)(bridge_base + bar_enable), enables);
-
- for (i=0; i<MV64x60_PCI_ACC_CNTL_WINDOWS; i++)
- out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0);
-
- /* If mem_size is 0, leave windows disabled */
- if (mem_size == 0)
- return;
-
- /* Cause automatic updates of PCI remap regs */
- offset = hose ?
- MV64x60_PCI1_PCI_DECODE_CNTL : MV64x60_PCI0_PCI_DECODE_CNTL;
- i = in_le32((u32 *)(bridge_base + offset));
- out_le32((u32 *)(bridge_base + offset), i & ~0x1);
-
- mem_size = (mem_size - 1) & 0xfffff000;
-
- /* Map PCI MEM addr 0 -> System Mem addr 0 */
- mv64x60_cfg_write(bridge_base, hose, bus,
- PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),
- mv64x60_pci2mem[hose].hi, 0);
- mv64x60_cfg_write(bridge_base, hose, bus,
- PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn),
- mv64x60_pci2mem[hose].lo, 0);
- out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size);
-
- acc_bits |= MV64x60_PCI_ACC_CNTL_ENABLE;
- out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0);
- out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits);
- out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size);
-
- /* Set PCI MEM->bridge's reg window to where they are in CPU mem map */
- i = (u32)bridge_base;
- i &= 0xffff0000;
- i |= (0x2 << 1);
- mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
- mv64x60_pci2reg[hose].hi, 0);
- mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0),
- mv64x60_pci2reg[hose].lo, i);
-
- enables &= ~0x1; /* Enable PCI MEM -> System Mem window 0 */
- out_le32((u32 *)(bridge_base + bar_enable), enables);
-}
-
-/* CPU -> PCI I/O & MEM setup */
-struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2] = {
- { /* hose 0 */
- .lo = MV64x60_CPU2PCI0_IO_BASE,
- .size = MV64x60_CPU2PCI0_IO_SIZE,
- .remap_hi = 0,
- .remap_lo = MV64x60_CPU2PCI0_IO_REMAP,
- },
- { /* hose 1 */
- .lo = MV64x60_CPU2PCI1_IO_BASE,
- .size = MV64x60_CPU2PCI1_IO_SIZE,
- .remap_hi = 0,
- .remap_lo = MV64x60_CPU2PCI1_IO_REMAP,
- },
-};
-
-struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2] = {
- { /* hose 0 */
- .lo = MV64x60_CPU2PCI0_MEM_0_BASE,
- .size = MV64x60_CPU2PCI0_MEM_0_SIZE,
- .remap_hi = MV64x60_CPU2PCI0_MEM_0_REMAP_HI,
- .remap_lo = MV64x60_CPU2PCI0_MEM_0_REMAP_LO,
- },
- { /* hose 1 */
- .lo = MV64x60_CPU2PCI1_MEM_0_BASE,
- .size = MV64x60_CPU2PCI1_MEM_0_SIZE,
- .remap_hi = MV64x60_CPU2PCI1_MEM_0_REMAP_HI,
- .remap_lo = MV64x60_CPU2PCI1_MEM_0_REMAP_LO,
- },
-};
-
-/* Only need to set up 1 window to pci mem space */
-void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
- u32 pci_base_lo, u32 cpu_base, u32 size,
- struct mv64x60_cpu2pci_win *offset_tbl)
-{
- cpu_base >>= 16;
- cpu_base |= MV64x60_CPU2PCI_SWAP_NONE;
- out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base);
-
- if (offset_tbl[hose].remap_hi != 0)
- out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi),
- pci_base_hi);
- out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo),
- pci_base_lo >> 16);
-
- size = (size - 1) >> 16;
- out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size);
-}
-
-/* Read mem ctlr to get the amount of mem in system */
-u32 mv64x60_get_mem_size(u8 *bridge_base)
-{
- u32 enables, i, v;
- u32 mem = 0;
-
- enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf;
-
- for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++)
- if (!(enables & (1<<i))) {
- v = in_le32((u32*)(bridge_base
- + mv64x60_cpu2mem[i].size));
- v = ((v & 0xffff) + 1) << 16;
- mem += v;
- }
-
- return mem;
-}
-
-/* Get physical address of bridge's registers */
-u8 *mv64x60_get_bridge_pbase(void)
-{
- u32 v[2];
- void *devp;
-
- devp = find_node_by_compatible(NULL, "marvell,mv64360");
- if (devp == NULL)
- goto err_out;
- if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v))
- goto err_out;
-
- return (u8 *)v[0];
-
-err_out:
- return 0;
-}
-
-/* Get virtual address of bridge's registers */
-u8 *mv64x60_get_bridge_base(void)
-{
- u32 v;
- void *devp;
-
- devp = find_node_by_compatible(NULL, "marvell,mv64360");
- if (devp == NULL)
- goto err_out;
- if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
- goto err_out;
-
- return (u8 *)v;
-
-err_out:
- return 0;
-}
-
-u8 mv64x60_is_coherent(void)
-{
- u32 v;
- void *devp;
-
- devp = finddevice("/");
- if (devp == NULL)
- return 1; /* Assume coherency on */
-
- if (getprop(devp, "coherency-off", &v, sizeof(v)) < 0)
- return 1; /* Coherency on */
- else
- return 0;
-}
diff --git a/arch/powerpc/boot/mv64x60.h b/arch/powerpc/boot/mv64x60.h
deleted file mode 100644
index b827105e6e543..0000000000000
--- a/arch/powerpc/boot/mv64x60.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Author: Mark A. Greer <source@mvista.com>
- *
- * 2007 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef _PPC_BOOT_MV64x60_H_
-#define _PPC_BOOT_MV64x60_H_
-
-#define MV64x60_CPU_BAR_ENABLE 0x0278
-
-#define MV64x60_PCI_ACC_CNTL_ENABLE (1<<0)
-#define MV64x60_PCI_ACC_CNTL_REQ64 (1<<1)
-#define MV64x60_PCI_ACC_CNTL_SNOOP_NONE 0x00000000
-#define MV64x60_PCI_ACC_CNTL_SNOOP_WT 0x00000004
-#define MV64x60_PCI_ACC_CNTL_SNOOP_WB 0x00000008
-#define MV64x60_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c
-#define MV64x60_PCI_ACC_CNTL_ACCPROT (1<<4)
-#define MV64x60_PCI_ACC_CNTL_WRPROT (1<<5)
-#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
-#define MV64x60_PCI_ACC_CNTL_SWAP_NONE 0x00000040
-#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080
-#define MV64x60_PCI_ACC_CNTL_SWAP_WORD 0x000000c0
-#define MV64x60_PCI_ACC_CNTL_SWAP_MASK 0x000000c0
-#define MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000
-#define MV64x60_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100
-#define MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200
-#define MV64x60_PCI_ACC_CNTL_MBURST_MASK 0x00000300
-#define MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000
-#define MV64x60_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400
-#define MV64x60_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800
-#define MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00
-#define MV64x60_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00
-
-struct mv64x60_cpu2pci_win {
- u32 lo;
- u32 size;
- u32 remap_hi;
- u32 remap_lo;
-};
-
-extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2];
-extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2];
-
-u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
- u8 offset);
-void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn,
- u8 offset, u32 val);
-
-void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase,
- u8 is_coherent);
-void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose,
- u8 bus, u32 mem_size, u32 acc_bits);
-void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi,
- u32 pci_base_lo, u32 cpu_base, u32 size,
- struct mv64x60_cpu2pci_win *offset_tbl);
-u32 mv64x60_get_mem_size(u8 *bridge_base);
-u8 *mv64x60_get_bridge_pbase(void);
-u8 *mv64x60_get_bridge_base(void);
-u8 mv64x60_is_coherent(void);
-
-int mv64x60_i2c_open(void);
-int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
- u32 count);
-void mv64x60_i2c_close(void);
-
-#endif /* _PPC_BOOT_MV64x60_H_ */
diff --git a/arch/powerpc/boot/mv64x60_i2c.c b/arch/powerpc/boot/mv64x60_i2c.c
deleted file mode 100644
index 52a3212b6638b..0000000000000
--- a/arch/powerpc/boot/mv64x60_i2c.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Bootloader version of the i2c driver for the MV64x60.
- *
- * Author: Dale Farnsworth <dfarnsworth@mvista.com>
- * Maintained by: Mark A. Greer <mgreer@mvista.com>
- *
- * 2003, 2007 (c) MontaVista, Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express or
- * implied.
- */
-
-#include <stdarg.h>
-#include <stddef.h>
-#include "types.h"
-#include "elf.h"
-#include "page.h"
-#include "string.h"
-#include "stdio.h"
-#include "io.h"
-#include "ops.h"
-#include "mv64x60.h"
-
-/* Register defines */
-#define MV64x60_I2C_REG_SLAVE_ADDR 0x00
-#define MV64x60_I2C_REG_DATA 0x04
-#define MV64x60_I2C_REG_CONTROL 0x08
-#define MV64x60_I2C_REG_STATUS 0x0c
-#define MV64x60_I2C_REG_BAUD 0x0c
-#define MV64x60_I2C_REG_EXT_SLAVE_ADDR 0x10
-#define MV64x60_I2C_REG_SOFT_RESET 0x1c
-
-#define MV64x60_I2C_CONTROL_ACK 0x04
-#define MV64x60_I2C_CONTROL_IFLG 0x08
-#define MV64x60_I2C_CONTROL_STOP 0x10
-#define MV64x60_I2C_CONTROL_START 0x20
-#define MV64x60_I2C_CONTROL_TWSIEN 0x40
-#define MV64x60_I2C_CONTROL_INTEN 0x80
-
-#define MV64x60_I2C_STATUS_BUS_ERR 0x00
-#define MV64x60_I2C_STATUS_MAST_START 0x08
-#define MV64x60_I2C_STATUS_MAST_REPEAT_START 0x10
-#define MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
-#define MV64x60_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
-#define MV64x60_I2C_STATUS_MAST_WR_ACK 0x28
-#define MV64x60_I2C_STATUS_MAST_WR_NO_ACK 0x30
-#define MV64x60_I2C_STATUS_MAST_LOST_ARB 0x38
-#define MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
-#define MV64x60_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
-#define MV64x60_I2C_STATUS_MAST_RD_DATA_ACK 0x50
-#define MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
-#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
-#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
-#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
-#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
-#define MV64x60_I2C_STATUS_NO_STATUS 0xf8
-
-static u8 *ctlr_base;
-
-static int mv64x60_i2c_wait_for_status(int wanted)
-{
- int i;
- int status;
-
- for (i=0; i<1000; i++) {
- udelay(10);
- status = in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_STATUS))
- & 0xff;
- if (status == wanted)
- return status;
- }
- return -status;
-}
-
-static int mv64x60_i2c_control(int control, int status)
-{
- out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
- return mv64x60_i2c_wait_for_status(status);
-}
-
-static int mv64x60_i2c_read_byte(int control, int status)
-{
- out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
- if (mv64x60_i2c_wait_for_status(status) < 0)
- return -1;
- return in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA)) & 0xff;
-}
-
-static int mv64x60_i2c_write_byte(int data, int control, int status)
-{
- out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA), data & 0xff);
- out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff);
- return mv64x60_i2c_wait_for_status(status);
-}
-
-int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size,
- u32 count)
-{
- int i;
- int data;
- int control;
- int status;
-
- if (ctlr_base == NULL)
- return -1;
-
- /* send reset */
- out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SOFT_RESET), 0);
- out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SLAVE_ADDR), 0);
- out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_EXT_SLAVE_ADDR), 0);
- out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_BAUD), (4 << 3) | 0x4);
-
- if (mv64x60_i2c_control(MV64x60_I2C_CONTROL_TWSIEN,
- MV64x60_I2C_STATUS_NO_STATUS) < 0)
- return -1;
-
- /* send start */
- control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
- status = MV64x60_I2C_STATUS_MAST_START;
- if (mv64x60_i2c_control(control, status) < 0)
- return -1;
-
- /* select device for writing */
- data = devaddr & ~0x1;
- control = MV64x60_I2C_CONTROL_TWSIEN;
- status = MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK;
- if (mv64x60_i2c_write_byte(data, control, status) < 0)
- return -1;
-
- /* send offset of data */
- control = MV64x60_I2C_CONTROL_TWSIEN;
- status = MV64x60_I2C_STATUS_MAST_WR_ACK;
- if (offset_size > 1) {
- if (mv64x60_i2c_write_byte(offset >> 8, control, status) < 0)
- return -1;
- }
- if (mv64x60_i2c_write_byte(offset, control, status) < 0)
- return -1;
-
- /* resend start */
- control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN;
- status = MV64x60_I2C_STATUS_MAST_REPEAT_START;
- if (mv64x60_i2c_control(control, status) < 0)
- return -1;
-
- /* select device for reading */
- data = devaddr | 0x1;
- control = MV64x60_I2C_CONTROL_TWSIEN;
- status = MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK;
- if (mv64x60_i2c_write_byte(data, control, status) < 0)
- return -1;
-
- /* read all but last byte of data */
- control = MV64x60_I2C_CONTROL_ACK | MV64x60_I2C_CONTROL_TWSIEN;
- status = MV64x60_I2C_STATUS_MAST_RD_DATA_ACK;
-
- for (i=1; i<count; i++) {
- data = mv64x60_i2c_read_byte(control, status);
- if (data < 0) {
- printf("errors on iteration %d\n", i);
- return -1;
- }
- *buf++ = data;
- }
-
- /* read last byte of data */
- control = MV64x60_I2C_CONTROL_TWSIEN;
- status = MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK;
- data = mv64x60_i2c_read_byte(control, status);
- if (data < 0)
- return -1;
- *buf++ = data;
-
- /* send stop */
- control = MV64x60_I2C_CONTROL_STOP | MV64x60_I2C_CONTROL_TWSIEN;
- status = MV64x60_I2C_STATUS_NO_STATUS;
- if (mv64x60_i2c_control(control, status) < 0)
- return -1;
-
- return count;
-}
-
-int mv64x60_i2c_open(void)
-{
- u32 v;
- void *devp;
-
- devp = find_node_by_compatible(NULL, "marvell,mv64360-i2c");
- if (devp == NULL)
- goto err_out;
- if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v))
- goto err_out;
-
- ctlr_base = (u8 *)v;
- return 0;
-
-err_out:
- return -1;
-}
-
-void mv64x60_i2c_close(void)
-{
- ctlr_base = NULL;
-}
diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h
index fad1862f4b2d3..cd043726ed88c 100644
--- a/arch/powerpc/boot/ops.h
+++ b/arch/powerpc/boot/ops.h
@@ -86,7 +86,6 @@ void start(void);
void fdt_init(void *blob);
int serial_console_init(void);
int ns16550_console_init(void *devp, struct serial_console_data *scdp);
-int mpsc_console_init(void *devp, struct serial_console_data *scdp);
int cpm_console_init(void *devp, struct serial_console_data *scdp);
int mpc5200_psc_console_init(void *devp, struct serial_console_data *scdp);
int uartlite_console_init(void *devp, struct serial_console_data *scdp);
diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c
index 88955095ec07d..48e3743faedfd 100644
--- a/arch/powerpc/boot/serial.c
+++ b/arch/powerpc/boot/serial.c
@@ -120,10 +120,6 @@ int serial_console_init(void)
if (dt_is_compatible(devp, "ns16550") ||
dt_is_compatible(devp, "pnpPNP,501"))
rc = ns16550_console_init(devp, &serial_cd);
-#ifdef CONFIG_EMBEDDED6xx
- else if (dt_is_compatible(devp, "marvell,mv64360-mpsc"))
- rc = mpsc_console_init(devp, &serial_cd);
-#endif
#ifdef CONFIG_CPM
else if (dt_is_compatible(devp, "fsl,cpm1-scc-uart") ||
dt_is_compatible(devp, "fsl,cpm1-smc-uart") ||
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-27 11:01:41 +0000