From c00ab4896ed5f7d89af6f90b809e2c0197c6d170 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Sat, 2 Jul 2016 10:38:05 +0200 Subject: MIPS: Remove cpu_has_safe_index_cacheops Very early versions of the 1004K had an hardware issue that made index cache ops unsafe so they had to be avoided and hit ops be used instead. This may significantly slow down cache maintenance operations. Only very early FPGA versions of the 1004K were affected so let's get rid of the workaround which was only implemented for the DMA cache maintenance operations anyway. Signed-off-by: Ralf Baechle --- arch/mips/mm/c-r4k.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'arch/mips/mm/c-r4k.c') diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index ef7f925dd1b02..645c69c95c9ce 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -66,12 +66,6 @@ static inline void r4k_on_each_cpu(void (*func) (void *info), void *info) preempt_enable(); } -#if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS) -#define cpu_has_safe_index_cacheops 0 -#else -#define cpu_has_safe_index_cacheops 1 -#endif - /* * Must die. */ @@ -744,7 +738,7 @@ static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size) * subset property so we have to flush the primary caches * explicitly */ - if (cpu_has_safe_index_cacheops && size >= dcache_size) { + if (size >= dcache_size) { r4k_blast_dcache(); } else { R4600_HIT_CACHEOP_WAR_IMPL; @@ -781,7 +775,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) return; } - if (cpu_has_safe_index_cacheops && size >= dcache_size) { + if (size >= dcache_size) { r4k_blast_dcache(); } else { R4600_HIT_CACHEOP_WAR_IMPL; @@ -861,7 +855,7 @@ static inline void local_r4k_flush_kernel_vmap_range(void *args) * Aliases only affect the primary caches so don't bother with * S-caches or T-caches. */ - if (cpu_has_safe_index_cacheops && size >= dcache_size) + if (size >= dcache_size) r4k_blast_dcache(); else { R4600_HIT_CACHEOP_WAR_IMPL; -- cgit v1.2.3