summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
blob: 329f8ceeebea1427b13c41b45bec8bea4ed22f73 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
 */

#include "armada-8040.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell 8040 MACCHIATOBin";
	compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
			"marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp1_eth0;
		ethernet2 = &cp1_eth1;
		ethernet3 = &cp1_eth2;
	};

	/* Regulator labels correspond with schematics */
	v_3_3: regulator-3-3v {
		compatible = "regulator-fixed";
		regulator-name = "v_3_3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		status = "okay";
	};

	v_vddo_h: regulator-1-8v {
		compatible = "regulator-fixed";
		regulator-name = "v_vddo_h";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		status = "okay";
	};

	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_xhci_vbus_pins>;
		regulator-name = "v_5v0_usb3_hst_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		status = "okay";
	};

	usb3h0_phy: usb3_phy0 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&v_5v0_usb3_hst_vbus>;
	};

	sfp_eth0: sfp-eth0 {
		/* CON15,16 - CPM lane 4 */
		compatible = "sff,sfp";
		i2c-bus = <&sfpp0_i2c>;
		los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio  = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_sfpp0_pins>;
	};

	sfp_eth1: sfp-eth1 {
		/* CON17,18 - CPS lane 4 */
		compatible = "sff,sfp";
		i2c-bus = <&sfpp1_i2c>;
		los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
	};

	sfp_eth3: sfp-eth3 {
		/* CON13,14 - CPS lane 5 */
		compatible = "sff,sfp";
		i2c-bus = <&sfp_1g_i2c>;
		los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
	};
};

&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

&ap_sdhci0 {
	bus-width = <8>;
	/*
	 * Not stable in HS modes - phy needs "more calibration", so add
	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
	 */
	marvell,xenon-phy-slow-mode;
	no-1-8-v;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	vqmmc-supply = <&v_vddo_h>;
};

&cp0_i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";
};

&cp0_i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	status = "okay";

	i2c-switch@70 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		sfpp0_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		sfpp1_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		sfp_1g_i2c: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};
	};
};

/* J25 UART header */
&cp0_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_uart1_pins>;
	status = "okay";
};

&cp0_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_ge_mdio_pins>;
	status = "okay";

	ge_phy: ethernet-phy@0 {
		reg = <0>;
	};
};

&cp0_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_pcie_pins>;
	num-lanes = <4>;
	num-viewport = <8>;
	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&cp0_pinctrl {
	cp0_ge_mdio_pins: ge-mdio-pins {
		marvell,pins = "mpp32", "mpp34";
		marvell,function = "ge";
	};
	cp0_i2c1_pins: i2c1-pins {
		marvell,pins = "mpp35", "mpp36";
		marvell,function = "i2c1";
	};
	cp0_i2c0_pins: i2c0-pins {
		marvell,pins = "mpp37", "mpp38";
		marvell,function = "i2c0";
	};
	cp0_uart1_pins: uart1-pins {
		marvell,pins = "mpp40", "mpp41";
		marvell,function = "uart1";
	};
	cp0_xhci_vbus_pins: xhci0-vbus-pins {
		marvell,pins = "mpp47";
		marvell,function = "gpio";
	};
	cp0_sfp_1g_pins: sfp-1g-pins {
		marvell,pins = "mpp51", "mpp53", "mpp54";
		marvell,function = "gpio";
	};
	cp0_pcie_pins: pcie-pins {
		marvell,pins = "mpp52";
		marvell,function = "gpio";
	};
	cp0_sdhci_pins: sdhci-pins {
		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
			       "mpp60", "mpp61";
		marvell,function = "sdio";
	};
	cp0_sfpp1_pins: sfpp1-pins {
		marvell,pins = "mpp62";
		marvell,function = "gpio";
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy4 0>;
};

&cp0_sata0 {
	/* CPM Lane 0 - U29 */
	status = "okay";
};

&cp0_sdhci0 {
	/* U6 */
	broken-cd;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins>;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
};

&cp0_usb3_0 {
	/* J38? - USB2.0 only */
	status = "okay";
};

&cp0_usb3_1 {
	/* J38? - USB2.0 only */
	status = "okay";
};

&cp1_ethernet {
	status = "okay";
};

&cp1_eth0 {
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy4 0>;
};

&cp1_eth1 {
	/* CPS Lane 0 - J5 (Gigabit RJ45) */
	status = "okay";
	/* Network PHY */
	phy = <&ge_phy>;
	phy-mode = "sgmii";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy0 1>;
};

&cp1_eth2 {
	/* CPS Lane 5 */
	status = "okay";
	/* Network PHY */
	phy-mode = "2500base-x";
	managed = "in-band-status";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy5 2>;
	sfp = <&sfp_eth3>;
};

&cp1_pinctrl {
	cp1_sfpp1_pins: sfpp1-pins {
		marvell,pins = "mpp8", "mpp10", "mpp11";
		marvell,function = "gpio";
	};
	cp1_spi1_pins: spi1-pins {
		marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
		marvell,function = "spi1";
	};
	cp1_uart0_pins: uart0-pins {
		marvell,pins = "mpp6", "mpp7";
		marvell,function = "uart0";
	};
	cp1_sfp_1g_pins: sfp-1g-pins {
		marvell,pins = "mpp24";
		marvell,function = "gpio";
	};
	cp1_sfpp0_pins: sfpp0-pins {
		marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
		marvell,function = "gpio";
	};
};

/* J27 UART header */
&cp1_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_uart0_pins>;
	status = "okay";
};

&cp1_sata0 {
	/* CPS Lane 1 - U32 */
	/* CPS Lane 3 - U31 */
	status = "okay";
};

&cp1_spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_spi1_pins>;
	status = "okay";

	spi-flash@0 {
		compatible = "st,w25q32";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&cp1_usb3_0 {
	/* CPS Lane 2 - CON7 */
	usb-phy = <&usb3h0_phy>;
	status = "okay";
};