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authorLucas Stach <l.stach@pengutronix.de>2021-07-17 00:03:15 +0200
committerLucas Stach <l.stach@pengutronix.de>2021-10-02 02:48:07 +0200
commit1a9d3ed4f530f95902db1c2c03502e8e0d410330 (patch)
treec16dbde4a9af0203531ac61e6fdae9242bc5789b
parentee4d9dc4e5bb841f7b3f681342b6d76b1c0037af (diff)
downloadlinux-1a9d3ed4f530f95902db1c2c03502e8e0d410330.tar.gz
linux-1a9d3ed4f530f95902db1c2c03502e8e0d410330.tar.xz
arm64: dts: imx8mm: add VPU blk-ctrl
Add the DT node for the VPU blk-ctrl. With this in place the VPU power domains are fully functional. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm.dtsi13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 6009e54266f0..f4a97bd8b7ad 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1170,6 +1170,19 @@
power-domains = <&pgc_gpu>;
};
+ vpu_blk_ctrl: blk-ctrl@38330000 {
+ compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
+ reg = <0x38330000 0x100>;
+ power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
+ <&pgc_vpu_g2>, <&pgc_vpu_h1>;
+ power-domain-names = "bus", "g1", "g2", "h1";
+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MM_CLK_VPU_H1_ROOT>;
+ clock-names = "g1", "g2", "h1";
+ #power-domain-cells = <1>;
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */