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authorLucas Stach <l.stach@pengutronix.de>2021-07-19 18:35:50 +0200
committerLucas Stach <l.stach@pengutronix.de>2021-07-21 22:27:10 +0200
commit04dfc10d25aeabc145b3aca759efd7f3cdd9f8df (patch)
treede26fbb23b01ab1dc6a03bba7a3542cdac3e7019
parenta8c1b365a9ff2c23089e778c2ec9bdf7c1194f90 (diff)
downloadlinux-04dfc10d25aeabc145b3aca759efd7f3cdd9f8df.tar.gz
linux-04dfc10d25aeabc145b3aca759efd7f3cdd9f8df.tar.xz
arm64: dts: imx8mm: add G1 VPU nodeimx8m-power-domains-testing
Not fully validated yet, just to test power domain interaction. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm.dtsi15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 6f20aff3b883..fd81b1ad1972 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1243,6 +1243,21 @@
power-domains = <&pgc_gpu>;
};
+ vpu_g1: video-codec@38300000 {
+ compatible = "nxp,imx8mm-vpu-g1";
+ reg = <0x38300000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
+ clock-names = "g1";
+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
+ <&clk IMX8MM_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
+ <&clk IMX8MM_VPU_PLL>;
+ assigned-clock-rates = <600000000>;
+ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
+ };
+
vpu_blk_ctrl: blk-ctrl@38330000 {
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;