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authorFrieder Schrempf <frieder.schrempf@kontron.de>2020-04-30 12:46:17 +0000
committerLucas Stach <l.stach@pengutronix.de>2021-07-21 22:26:09 +0200
commitbf28cbd49e2b9e20ff88517fb142272b94fb61df (patch)
treef2d9464002fc702c72bcc7a860c8967be5752376
parentd98233a32dd1f2d238bd0c73cf162d54459a47a1 (diff)
downloadlinux-bf28cbd49e2b9e20ff88517fb142272b94fb61df.tar.gz
linux-bf28cbd49e2b9e20ff88517fb142272b94fb61df.tar.xz
arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
According to the documents, the i.MX8M-Mini features a GC320 and a GCNanoUltra GPU core. Etnaviv detects them as: etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 This seems to work fine more or less without any changes to the HWDB, which still might be needed in the future to correct some features, etc. [lst]: Added power domains and switched clock assignments to the new clock defines used for the composite clocks, instead of relying on the backwards compat defines. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm.dtsi31
1 files changed, 31 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 39d651612d0e..a937018556a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1121,6 +1121,37 @@
status = "disabled";
};
+ gpu_3d: gpu@38000000 {
+ compatible = "vivante,gc";
+ reg = <0x38000000 0x8000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+ <&clk IMX8MM_CLK_GPU3D_ROOT>,
+ <&clk IMX8MM_CLK_GPU3D_ROOT>;
+ clock-names = "reg", "bus", "core", "shader";
+ assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
+ <&clk IMX8MM_GPU_PLL_OUT>;
+ assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+ assigned-clock-rates = <0>, <1000000000>;
+ power-domains = <&pgc_gpu>;
+ };
+
+ gpu_2d: gpu@38008000 {
+ compatible = "vivante,gc";
+ reg = <0x38008000 0x8000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MM_CLK_GPU_AHB>,
+ <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
+ <&clk IMX8MM_CLK_GPU2D_ROOT>;
+ clock-names = "reg", "bus", "core";
+ assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
+ <&clk IMX8MM_GPU_PLL_OUT>;
+ assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
+ assigned-clock-rates = <0>, <1000000000>;
+ power-domains = <&pgc_gpu>;
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */