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| author | Marek Vasut <marex@denx.de> | 2020-10-05 15:42:49 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2021-07-21 22:27:09 +0200 |
| commit | e94ba8c37302a223fc352e1a939d7855fe36048e (patch) | |
| tree | cd900069548e5123763664423f6da6d81c34dedc | |
| parent | 1416d0861f74eb85819553b1378a9230504b9e49 (diff) | |
| download | linux-e94ba8c37302a223fc352e1a939d7855fe36048e.tar.gz linux-e94ba8c37302a223fc352e1a939d7855fe36048e.tar.xz | |
drm/exynos: Scale the DSIM PHY HFP/HBP/HSA to lanes and bpp
The value programmed into horizontal porch and sync registers must be
scaled to the correct number of DSI lanes and bpp, make it so.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Guido Günther <agx@sigxcpu.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Michael Tretter <m.tretter@pengutronix.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
To: dri-devel@lists.freedesktop.org
--
NOTE: This depends on https://patchwork.kernel.org/project/dri-devel/list/?series=347439
| -rw-r--r-- | drivers/gpu/drm/bridge/samsung-dsim.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index fbd87a74eb9f..42b49546dd00 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -740,20 +740,23 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) { struct drm_display_mode *m = &dsi->mode; unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; + int bpp; u32 reg; if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { + bpp = mipi_dsi_pixel_format_to_bpp(dsi->format) / 8; + reg = DSIM_CMD_ALLOW(0xf) | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); - reg = DSIM_MAIN_HFP(m->hsync_start - m->hdisplay) - | DSIM_MAIN_HBP(m->htotal - m->hsync_end); + reg = DSIM_MAIN_HFP((m->hsync_start - m->hdisplay) * bpp / dsi->lanes) + | DSIM_MAIN_HBP((m->htotal - m->hsync_end) * bpp / dsi->lanes); samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) - | DSIM_MAIN_HSA(m->hsync_end - m->hsync_start); + | DSIM_MAIN_HSA((m->hsync_end - m->hsync_start) * bpp / dsi->lanes); samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); } reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | |