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| author | Lucas Stach <l.stach@pengutronix.de> | 2020-09-11 14:10:13 +0200 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2020-09-30 17:33:18 +0200 |
| commit | f57358591e6b739acaa6365457401a89588b0840 (patch) | |
| tree | 8f3863a07777f521debd40d44ac2689c1ec753e1 | |
| parent | 67b18939627024e919abb2f1ea3bbef33c7f5ffa (diff) | |
| download | linux-f57358591e6b739acaa6365457401a89588b0840.tar.gz linux-f57358591e6b739acaa6365457401a89588b0840.tar.xz | |
soc: imx: gpcv2: add support for optional resets
Normally the reset for the devices inside the power domain is
triggered automatically from the PGC in the power-up sequencing,
however on i.MX8MM this doesn't work for the GPU power domains.
Add support for triggering the reset explicitly during the power
up sequencing.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
| -rw-r--r-- | Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml | 6 | ||||
| -rw-r--r-- | drivers/soc/imx/gpcv2.c | 13 |
2 files changed, 19 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml index bde09a0b2da3..9773771b9000 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml @@ -62,6 +62,12 @@ properties: power-supply: true + resets: + description: | + A number of phandles to resets that need to be asserted during + power-up sequencing of the domain. + minItems: 1 + required: - '#power-domain-cells' - reg diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index db93fef0c76b..76aa8a67d8a7 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -15,6 +15,7 @@ #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> +#include <linux/reset.h> #include <linux/sizes.h> #include <dt-bindings/power/imx7-power.h> #include <dt-bindings/power/imx8mq-power.h> @@ -112,6 +113,7 @@ struct imx_pgc_domain { struct regulator *regulator; struct clk *clk[GPC_CLK_MAX]; int num_clks; + struct reset_control *reset; unsigned int pgc; @@ -167,6 +169,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) } } + reset_control_assert(domain->reset); + if (domain->bits.pxx) { /* request the domain to power up */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, @@ -189,6 +193,8 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) GPC_PGC_CTRL_PCR, 0); } + reset_control_deassert(domain->reset); + /* request the ADB400 to power up */ if (domain->bits.hskreq) { regmap_update_bits(domain->regmap, GPC_PU_PWRHSK, @@ -577,6 +583,13 @@ static int imx_pgc_domain_probe(struct platform_device *pdev) domain->voltage, domain->voltage); } + domain->reset = devm_reset_control_array_get_optional_exclusive(domain->dev); + if (IS_ERR(domain->reset)) { + if (PTR_ERR(domain->reset) != -EPROBE_DEFER) + dev_err(domain->dev, "Failed to get domain's reset\n"); + return PTR_ERR(domain->reset); + } + ret = imx_pgc_get_clocks(domain); if (ret) { if (ret != -EPROBE_DEFER) |