WIP: prune msm_gpu from adreno interfaces

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

7 files changed, 120 insertions, 132 deletions

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index ec78fa023a1c..ce6dcd5e2ca8 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -33,10 +33,9 @@
 
 static struct platform_device *a3xx_pdev;
 
-static void a3xx_me_init(struct msm_gpu *gpu)
+static void a3xx_me_init(struct adreno_gpu *gpu)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	struct adreno_ringbuffer *ring = adreno_gpu->rb;
+	struct adreno_ringbuffer *ring = gpu->rb;
 
 	OUT_PKT3(ring, CP_ME_INIT, 17);
 	OUT_RING(ring, 0x000003f7);
@@ -61,15 +60,14 @@ static void a3xx_me_init(struct msm_gpu *gpu)
 	gpu->funcs->idle(gpu);
 }
 
-static int a3xx_hw_init(struct msm_gpu *gpu)
+static int a3xx_hw_init(struct adreno_gpu *gpu)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 	uint32_t *ptr, len;
 	int i, ret;
 
-	DBG("%s", gpu->name);
+	DBG("%s", gpu->base.name);
 
-	if (adreno_is_a305(adreno_gpu)) {
+	if (adreno_is_a305(gpu)) {
 		/* Set up 16 deep read/write request queues: */
 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
@@ -86,7 +84,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c);
 		gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c);
 
-	} else if (adreno_is_a320(adreno_gpu)) {
+	} else if (adreno_is_a320(gpu)) {
 		/* Set up 16 deep read/write request queues: */
 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010);
 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010);
@@ -106,7 +104,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff);
 		gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4);
 
-	} else if (adreno_is_a330(adreno_gpu)) {
+	} else if (adreno_is_a330(gpu)) {
 		/* Set up 16 deep read/write request queues: */
 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818);
 		gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818);
@@ -218,8 +216,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 	 */
 
 	/* Load PM4: */
-	ptr = (uint32_t *)(adreno_gpu->pm4->data);
-	len = adreno_gpu->pm4->size / 4;
+	ptr = (uint32_t *)(gpu->pm4->data);
+	len = gpu->pm4->size / 4;
 	DBG("loading PM4 ucode version: %u", ptr[0]);
 
 	gpu_write(gpu, REG_AXXX_CP_DEBUG,
@@ -230,8 +228,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 		gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]);
 
 	/* Load PFP: */
-	ptr = (uint32_t *)(adreno_gpu->pfp->data);
-	len = adreno_gpu->pfp->size / 4;
+	ptr = (uint32_t *)(gpu->pfp->data);
+	len = gpu->pfp->size / 4;
 	DBG("loading PFP ucode version: %u", ptr[0]);
 
 	gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0);
@@ -239,7 +237,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 		gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]);
 
 	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
-	if (adreno_is_a305(adreno_gpu) || adreno_is_a320(adreno_gpu))
+	if (adreno_is_a305(gpu) || adreno_is_a320(gpu))
 		gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS,
 				AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) |
 				AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) |
@@ -254,18 +252,17 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 	return 0;
 }
 
-static void a3xx_destroy(struct msm_gpu *gpu)
+static void a3xx_destroy(struct adreno_gpu *gpu)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 
-	DBG("%s", gpu->name);
+	DBG("%s", gpu->base.name);
 
-	adreno_gpu_cleanup(adreno_gpu);
-	put_device(&adreno_gpu->pdev->dev);
-	kfree(adreno_gpu);
+	adreno_gpu_cleanup(gpu);
+	put_device(&gpu->pdev->dev);
+	kfree(gpu);
 }
 
-static void a3xx_idle(struct msm_gpu *gpu)
+static void a3xx_idle(struct adreno_gpu *gpu)
 {
 	unsigned long t;
 
@@ -281,23 +278,23 @@ static void a3xx_idle(struct msm_gpu *gpu)
 			return;
 	} while(time_before(jiffies, t));
 
-	DRM_ERROR("timeout waiting for %s to idle!\n", gpu->name);
+	DRM_ERROR("timeout waiting for %s to idle!\n", gpu->base.name);
 
 	/* TODO maybe we need to reset GPU here to recover from hang? */
 }
 
-static irqreturn_t a3xx_irq(struct msm_gpu *gpu)
+static irqreturn_t a3xx_irq(struct adreno_gpu *gpu)
 {
 	uint32_t status;
 
 	status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS);
-	DBG("%s: %08x", gpu->name, status);
+	DBG("%s: %08x", gpu->base.name, status);
 
 	// TODO
 
 	gpu_write(gpu, REG_A3XX_RBBM_INT_CLEAR_CMD, status);
 
-	msm_gpu_retire(gpu);
+	msm_gpu_retire(&gpu->base);
 
 	return IRQ_HANDLED;
 }
@@ -342,7 +339,7 @@ static const unsigned int a3xx_registers[] = {
 	0x303c, 0x303c, 0x305e, 0x305f,
 };
 
-static void a3xx_show(struct msm_gpu *gpu, struct seq_file *m)
+static void a3xx_show(struct adreno_gpu *gpu, struct seq_file *m)
 {
 	int i;
 
@@ -351,7 +348,7 @@ static void a3xx_show(struct msm_gpu *gpu, struct seq_file *m)
 			gpu_read(gpu, REG_A3XX_RBBM_STATUS));
 
 	/* dump these out in a form that can be parsed by demsm: */
-	seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
+	seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->base.name);
 	for (i = 0; i < ARRAY_SIZE(a3xx_registers); i += 2) {
 		uint32_t start = a3xx_registers[i];
 		uint32_t end   = a3xx_registers[i+1];
@@ -425,7 +422,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev,
 
 fail:
 	if (adreno_gpu)
-		a3xx_destroy(&adreno_gpu->base);
+		a3xx_destroy(adreno_gpu);
 
 	return ERR_PTR(ret);
 }
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 40274ed379d8..488b55f377b9 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -55,19 +55,17 @@ static const struct adreno_info gpulist[] = {
 #define RB_SIZE    SZ_32K
 #define RB_BLKSIZE 16
 
-int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
+int adreno_get_param(struct adreno_gpu *gpu, uint32_t param, uint64_t *value)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-
 	switch (param) {
 	case MSM_PARAM_GPU_ID:
-		*value = adreno_gpu->info->revn;
+		*value = gpu->info->revn;
 		return 0;
 	case MSM_PARAM_GMEM_SIZE:
-		*value = adreno_gpu->info->gmem;
+		*value = gpu->info->gmem;
 		return 0;
 	default:
-		DBG("%s: invalid param: %u", gpu->name, param);
+		DBG("%s: invalid param: %u", gpu->base.name, param);
 		return -EINVAL;
 	}
 }
@@ -75,24 +73,22 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
 #define rbmemptr(adreno_gpu, member)  \
 	((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
 
-int adreno_hw_init(struct msm_gpu *gpu)
+int adreno_hw_init(struct adreno_gpu *gpu)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-
-	DBG("%s", gpu->name);
+	DBG("%s", gpu->base.name);
 
 	/* Setup REG_CP_RB_CNTL: */
 	gpu_write(gpu, REG_AXXX_CP_RB_CNTL,
 			/* size is log2(quad-words): */
-			AXXX_CP_RB_CNTL_BUFSZ(ilog2(adreno_gpu->rb->size / 8)) |
+			AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
 			AXXX_CP_RB_CNTL_BLKSZ(RB_BLKSIZE));
 
 	/* Setup ringbuffer address: */
-	gpu_write(gpu, REG_AXXX_CP_RB_BASE, adreno_gpu->rb_iova);
-	gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(adreno_gpu, rptr));
+	gpu_write(gpu, REG_AXXX_CP_RB_BASE, gpu->rb_iova);
+	gpu_write(gpu, REG_AXXX_CP_RB_RPTR_ADDR, rbmemptr(gpu, rptr));
 
 	/* Setup scratch/timestamp: */
-	gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(adreno_gpu, fence));
+	gpu_write(gpu, REG_AXXX_SCRATCH_ADDR, rbmemptr(gpu, fence));
 
 	gpu_write(gpu, REG_AXXX_SCRATCH_UMSK, 0x1);
 
@@ -104,25 +100,23 @@ static uint32_t get_wptr(struct adreno_ringbuffer *ring)
 	return ring->cur - ring->start;
 }
 
-uint32_t adreno_last_fence(struct msm_gpu *gpu)
+uint32_t adreno_last_fence(struct adreno_gpu *gpu)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	return adreno_gpu->memptrs->fence;
+	return gpu->memptrs->fence;
 }
 
-void adreno_recover(struct msm_gpu *gpu)
+void adreno_recover(struct adreno_gpu *gpu)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	struct drm_device *dev = gpu->dev;
+	struct drm_device *dev = gpu->base.dev;
 	int ret;
 
 	gpu->funcs->pm_suspend(gpu);
 
 	/* reset ringbuffer: */
-	adreno_gpu->rb->cur = adreno_gpu->rb->start;
+	gpu->rb->cur = gpu->rb->start;
 
 	/* reset completed fence seqno, just discard anything pending: */
-	adreno_gpu->memptrs->fence = gpu->submitted_fence;
+	gpu->memptrs->fence = gpu->base.submitted_fence;
 
 	gpu->funcs->pm_resume(gpu);
 	ret = gpu->funcs->hw_init(gpu);
@@ -132,11 +126,10 @@ void adreno_recover(struct msm_gpu *gpu)
 	}
 }
 
-int adreno_submit(struct msm_gpu *gpu, struct adreno_submit *submit,
+int adreno_submit(struct adreno_gpu *gpu, struct adreno_submit *submit,
 		struct adreno_context *ctx)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	struct adreno_ringbuffer *ring = adreno_gpu->rb;
+	struct adreno_ringbuffer *ring = gpu->rb;
 	unsigned i, ibs = 0;
 
 	for (i = 0; i < submit->nr_cmds; i++) {
@@ -146,7 +139,7 @@ int adreno_submit(struct msm_gpu *gpu, struct adreno_submit *submit,
 			break;
 		case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
 			/* ignore if there has not been a ctx switch: */
-			if (adreno_gpu->lastctx == ctx)
+			if (gpu->lastctx == ctx)
 				break;
 		case MSM_SUBMIT_CMD_BUF:
 			OUT_PKT3(ring, CP_INDIRECT_BUFFER_PFD, 2);
@@ -167,7 +160,7 @@ int adreno_submit(struct msm_gpu *gpu, struct adreno_submit *submit,
 	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
 	OUT_RING(ring, submit->fence);
 
-	if (adreno_is_a3xx(adreno_gpu)) {
+	if (adreno_is_a3xx(gpu)) {
 		/* Flush HLSQ lazy updates to make sure there is nothing
 		 * pending for indirect loads after the timestamp has
 		 * passed:
@@ -181,7 +174,7 @@ int adreno_submit(struct msm_gpu *gpu, struct adreno_submit *submit,
 
 	OUT_PKT3(ring, CP_EVENT_WRITE, 3);
 	OUT_RING(ring, CACHE_FLUSH_TS);
-	OUT_RING(ring, rbmemptr(adreno_gpu, fence));
+	OUT_RING(ring, rbmemptr(gpu, fence));
 	OUT_RING(ring, submit->fence);
 
 	/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
@@ -202,10 +195,9 @@ int adreno_submit(struct msm_gpu *gpu, struct adreno_submit *submit,
 	return 0;
 }
 
-void adreno_flush(struct msm_gpu *gpu)
+void adreno_flush(struct adreno_gpu *gpu)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	uint32_t wptr = get_wptr(adreno_gpu->rb);
+	uint32_t wptr = get_wptr(gpu->rb);
 
 	/* ensure writes to ringbuffer have hit system memory: */
 	mb();
@@ -213,41 +205,39 @@ void adreno_flush(struct msm_gpu *gpu)
 	gpu_write(gpu, REG_AXXX_CP_RB_WPTR, wptr);
 }
 
-void adreno_idle(struct msm_gpu *gpu)
+void adreno_idle(struct adreno_gpu *gpu)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-	uint32_t rptr, wptr = get_wptr(adreno_gpu->rb);
+	uint32_t rptr, wptr = get_wptr(gpu->rb);
 	unsigned long t;
 
 	t = jiffies + ADRENO_IDLE_TIMEOUT;
 
 	/* then wait for CP to drain ringbuffer: */
 	do {
-		rptr = adreno_gpu->memptrs->rptr;
+		rptr = gpu->memptrs->rptr;
 		if (rptr == wptr)
 			return;
 	} while(time_before(jiffies, t));
 
-	DRM_ERROR("timeout waiting for %s to drain ringbuffer!\n", gpu->name);
+	DRM_ERROR("timeout waiting for %s to drain ringbuffer!\n",
+			gpu->base.name);
 
 	/* TODO maybe we need to reset GPU here to recover from hang? */
 }
 
 #ifdef CONFIG_DEBUG_FS
-void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
+void adreno_show(struct adreno_gpu *gpu, struct seq_file *m)
 {
-	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
-
 	seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
-			adreno_gpu->info->revn, adreno_gpu->rev.core,
-			adreno_gpu->rev.major, adreno_gpu->rev.minor,
-			adreno_gpu->rev.patchid);
-
-	seq_printf(m, "fence:    %d/%d\n", adreno_gpu->memptrs->fence,
-			gpu->submitted_fence);
-	seq_printf(m, "rptr:     %d\n", adreno_gpu->memptrs->rptr);
-	seq_printf(m, "wptr:     %d\n", adreno_gpu->memptrs->wptr);
-	seq_printf(m, "rb wptr:  %d\n", get_wptr(adreno_gpu->rb));
+			gpu->info->revn, gpu->rev.core,
+			gpu->rev.major, gpu->rev.minor,
+			gpu->rev.patchid);
+
+	seq_printf(m, "fence:    %d/%d\n", gpu->memptrs->fence,
+			gpu->base.submitted_fence);
+	seq_printf(m, "rptr:     %d\n", gpu->memptrs->rptr);
+	seq_printf(m, "wptr:     %d\n", gpu->memptrs->wptr);
+	seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
 }
 #endif
 
@@ -306,6 +296,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 
 	/* XXX: urgh - pointers to self are fun! */
 	gpu->gem->priv = &gpu->base;
+	gpu->base.gpu = gpu;
 
 	ret = request_firmware(&gpu->pm4, gpu->info->pm4fw, drm->dev);
 	if (ret) {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 831fca8dbe2b..d4aa796df595 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -99,16 +99,16 @@ static inline bool adreno_is_a330(struct adreno_gpu *gpu)
 	return gpu->revn == 330;
 }
 
-int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
-int adreno_hw_init(struct msm_gpu *gpu);
-uint32_t adreno_last_fence(struct msm_gpu *gpu);
-void adreno_recover(struct msm_gpu *gpu);
-int adreno_submit(struct msm_gpu *gpu, struct adreno_submit *submit,
+int adreno_get_param(struct adreno_gpu *gpu, uint32_t param, uint64_t *value);
+int adreno_hw_init(struct adreno_gpu *gpu);
+uint32_t adreno_last_fence(struct adreno_gpu *gpu);
+void adreno_recover(struct adreno_gpu *gpu);
+int adreno_submit(struct adreno_gpu *gpu, struct adreno_submit *submit,
 		struct adreno_context *ctx);
-void adreno_flush(struct msm_gpu *gpu);
-void adreno_idle(struct msm_gpu *gpu);
+void adreno_flush(struct adreno_gpu *gpu);
+void adreno_idle(struct adreno_gpu *gpu);
 #ifdef CONFIG_DEBUG_FS
-void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
+void adreno_show(struct adreno_gpu *gpu, struct seq_file *m);
 #endif
 void adreno_wait_ring(struct adreno_gpu *gpu, uint32_t ndwords);
 
@@ -117,6 +117,15 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 		struct adreno_gem *gem, struct adreno_rev rev);
 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
 
+static inline void gpu_write(struct adreno_gpu *gpu, u32 reg, u32 data)
+{
+	msm_writel(data, gpu->base.mmio + (reg << 2));
+}
+
+static inline u32 gpu_read(struct adreno_gpu *gpu, u32 reg)
+{
+	return msm_readl(gpu->base.mmio + (reg << 2));
+}
 
 /* ringbuffer helpers (the parts that are adreno specific) */
 
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 2f58c5908732..df3f77822d71 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -156,8 +156,8 @@ static int msm_unload(struct drm_device *dev)
 
 	if (gpu) {
 		mutex_lock(&dev->struct_mutex);
-		gpu->funcs->pm_suspend(gpu);
-		gpu->funcs->destroy(gpu);
+		gpu->funcs->pm_suspend(gpu->gpu);
+		gpu->funcs->destroy(gpu->gpu);
 		mutex_unlock(&dev->struct_mutex);
 	}
 
@@ -317,11 +317,11 @@ static void load_gpu(struct drm_device *dev)
 
 	if (gpu) {
 		int ret;
-		gpu->funcs->pm_resume(gpu);
-		ret = gpu->funcs->hw_init(gpu);
+		gpu->funcs->pm_resume(gpu->gpu);
+		ret = gpu->funcs->hw_init(gpu->gpu);
 		if (ret) {
 			dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
-			gpu->funcs->destroy(gpu);
+			gpu->funcs->destroy(gpu->gpu);
 			gpu = NULL;
 		}
 	}
@@ -434,7 +434,7 @@ static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
 
 	if (gpu) {
 		seq_printf(m, "%s Status:\n", gpu->name);
-		gpu->funcs->show(gpu, m);
+		gpu->funcs->show(gpu->gpu, m);
 	}
 
 	return 0;
@@ -600,7 +600,7 @@ static int msm_ioctl_get_param(struct drm_device *dev, void *data,
 	if (!gpu)
 		return -ENXIO;
 
-	return gpu->funcs->get_param(gpu, args->param, &args->value);
+	return gpu->funcs->get_param(gpu->gpu, args->param, &args->value);
 }
 
 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index cc4c179005e9..c7cb3d851377 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -17,7 +17,7 @@
 
 #include "msm_gpu.h"
 #include "msm_gem.h"
-
+#include "adreno/adreno_gpu.h"
 
 /*
  * Power Management:
@@ -160,42 +160,42 @@ static int disable_axi(struct msm_gpu *gpu)
 	return 0;
 }
 
-int msm_gpu_pm_resume(struct msm_gpu *gpu)
+int msm_gpu_pm_resume(struct adreno_gpu *gpu)
 {
 	int ret;
 
-	DBG("%s", gpu->name);
+	DBG("%s", gpu->base.name);
 
-	ret = enable_pwrrail(gpu);
+	ret = enable_pwrrail(&gpu->base);
 	if (ret)
 		return ret;
 
-	ret = enable_clk(gpu);
+	ret = enable_clk(&gpu->base);
 	if (ret)
 		return ret;
 
-	ret = enable_axi(gpu);
+	ret = enable_axi(&gpu->base);
 	if (ret)
 		return ret;
 
 	return 0;
 }
 
-int msm_gpu_pm_suspend(struct msm_gpu *gpu)
+int msm_gpu_pm_suspend(struct adreno_gpu *gpu)
 {
 	int ret;
 
-	DBG("%s", gpu->name);
+	DBG("%s", gpu->base.name);
 
-	ret = disable_axi(gpu);
+	ret = disable_axi(&gpu->base);
 	if (ret)
 		return ret;
 
-	ret = disable_clk(gpu);
+	ret = disable_clk(&gpu->base);
 	if (ret)
 		return ret;
 
-	ret = disable_pwrrail(gpu);
+	ret = disable_pwrrail(&gpu->base);
 	if (ret)
 		return ret;
 
@@ -214,7 +214,7 @@ static void recover_worker(struct work_struct *work)
 	dev_err(dev->dev, "%s: hangcheck recover!\n", gpu->name);
 
 	mutex_lock(&dev->struct_mutex);
-	gpu->funcs->recover(gpu);
+	gpu->funcs->recover(gpu->gpu);
 	mutex_unlock(&dev->struct_mutex);
 
 	msm_gpu_retire(gpu);
@@ -230,7 +230,7 @@ static void hangcheck_timer_reset(struct msm_gpu *gpu)
 static void hangcheck_handler(unsigned long data)
 {
 	struct msm_gpu *gpu = (struct msm_gpu *)data;
-	uint32_t fence = gpu->funcs->last_fence(gpu);
+	uint32_t fence = gpu->funcs->last_fence(gpu->gpu);
 
 	if (fence != gpu->hangcheck_fence) {
 		/* some progress has been made.. ya! */
@@ -255,7 +255,7 @@ static void retire_worker(struct work_struct *work)
 {
 	struct msm_gpu *gpu = container_of(work, struct msm_gpu, retire_work);
 	struct drm_device *dev = gpu->dev;
-	uint32_t fence = gpu->funcs->last_fence(gpu);
+	uint32_t fence = gpu->funcs->last_fence(gpu->gpu);
 
 	mutex_lock(&dev->struct_mutex);
 
@@ -301,7 +301,7 @@ int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 
 	gpu->submitted_fence = submit->base.fence;
 
-	ret = gpu->funcs->submit(gpu, &submit->base, &filp->ctx);
+	ret = gpu->funcs->submit(gpu->gpu, &submit->base, &filp->ctx);
 
 	for (i = 0; i < submit->nr_bos; i++) {
 		struct msm_gem_object *msm_obj = submit->bos[i].obj;
@@ -335,7 +335,7 @@ int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
 static irqreturn_t irq_handler(int irq, void *data)
 {
 	struct msm_gpu *gpu = data;
-	return gpu->funcs->irq(gpu);
+	return gpu->funcs->irq(gpu->gpu);
 }
 
 static const char *clk_names[] = {
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 89164d323478..b1a8e928d488 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -41,6 +41,7 @@
 struct msm_gpu {
 	const char *name;
 	struct drm_device *dev;
+	struct adreno_gpu *gpu;
 	const struct adreno_gpu_funcs *funcs;
 
 	/* list of GEM active objects: */
@@ -71,18 +72,8 @@ struct msm_gpu {
 	struct work_struct recover_work;
 };
 
-static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
-{
-	msm_writel(data, gpu->mmio + (reg << 2));
-}
-
-static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
-{
-	return msm_readl(gpu->mmio + (reg << 2));
-}
-
-int msm_gpu_pm_suspend(struct msm_gpu *gpu);
-int msm_gpu_pm_resume(struct msm_gpu *gpu);
+int msm_gpu_pm_suspend(struct adreno_gpu *gpu);
+int msm_gpu_pm_resume(struct adreno_gpu *gpu);
 
 void msm_gpu_retire(struct msm_gpu *gpu);
 struct msm_gem_submit;
diff --git a/include/drm/drm_adreno.h b/include/drm/drm_adreno.h
index 6b6a32e0a28e..44aa89b25712 100644
--- a/include/drm/drm_adreno.h
+++ b/include/drm/drm_adreno.h
@@ -20,7 +20,7 @@
 
 #include <drm/drmP.h>
 
-struct msm_gpu;
+struct adreno_gpu;
 
 #define ADRENO_SUBMIT_MAX_CMDS 4
 struct adreno_submit {
@@ -39,21 +39,21 @@ struct adreno_context {
 };
 
 struct adreno_gpu_funcs {
-	int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
-	int (*hw_init)(struct msm_gpu *gpu);
-	int (*pm_suspend)(struct msm_gpu *gpu);
-	int (*pm_resume)(struct msm_gpu *gpu);
-	int (*submit)(struct msm_gpu *gpu, struct adreno_submit *submit,
+	int (*get_param)(struct adreno_gpu *gpu, uint32_t param, uint64_t *value);
+	int (*hw_init)(struct adreno_gpu *gpu);
+	int (*pm_suspend)(struct adreno_gpu *gpu);
+	int (*pm_resume)(struct adreno_gpu *gpu);
+	int (*submit)(struct adreno_gpu *gpu, struct adreno_submit *submit,
 			struct adreno_context *ctx);
-	void (*flush)(struct msm_gpu *gpu);
-	void (*idle)(struct msm_gpu *gpu);
-	irqreturn_t (*irq)(struct msm_gpu *irq);
-	uint32_t (*last_fence)(struct msm_gpu *gpu);
-	void (*recover)(struct msm_gpu *gpu);
-	void (*destroy)(struct msm_gpu *gpu);
+	void (*flush)(struct adreno_gpu *gpu);
+	void (*idle)(struct adreno_gpu *gpu);
+	irqreturn_t (*irq)(struct adreno_gpu *irq);
+	uint32_t (*last_fence)(struct adreno_gpu *gpu);
+	void (*recover)(struct adreno_gpu *gpu);
+	void (*destroy)(struct adreno_gpu *gpu);
 #ifdef CONFIG_DEBUG_FS
 	/* show GPU status in debugfs: */
-	void (*show)(struct msm_gpu *gpu, struct seq_file *m);
+	void (*show)(struct adreno_gpu *gpu, struct seq_file *m);
 #endif
 };