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authorLucas Stach <dev@lynxeye.de>2015-01-04 21:16:52 +0100
committerLucas Stach <dev@lynxeye.de>2015-01-04 21:30:25 +0100
commitaedf6675b7fd4fd82bd87f8a2c06aad6d7c6a47d (patch)
tree05751775ec1b84fa1e4153094b7fd4de2a47b7e3
parentca37aa3d9e5794a24d769ddd75a4a2edd13449d6 (diff)
downloadlinux-aedf6675b7fd4fd82bd87f8a2c06aad6d7c6a47d.tar.gz
linux-aedf6675b7fd4fd82bd87f8a2c06aad6d7c6a47d.tar.xz
ARM: tegra: add Tegra20 NAND flash controller node
Add basic controller description to be extended by individual boards. Signed-off-by: Lucas Stach <dev@lynxeye.de>
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 8acf5d85c99d..090e9e490de2 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -360,6 +360,19 @@
status = "disabled";
};
+ nand: nand@70008000 {
+ compatible = "nvidia,tegra20-nand";
+ reg = <0x70008000 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
+ clock-names = "nand";
+ resets = <&tegra_car 13>;
+ reset-names = "nand";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;