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author | Lucas Stach <dev@lynxeye.de> | 2015-01-04 21:13:14 +0100 |
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committer | Lucas Stach <dev@lynxeye.de> | 2015-03-02 20:39:20 +0100 |
commit | 17ce33f9aee6c32aac689f35b3c781c733098e0d (patch) | |
tree | 999df31a8a8c0f200e8c75e22d064bab7f16e712 | |
parent | 6058e235132afc4e6e76f018b682054b52040291 (diff) | |
download | linux-17ce33f9aee6c32aac689f35b3c781c733098e0d.tar.gz linux-17ce33f9aee6c32aac689f35b3c781c733098e0d.tar.xz |
clk: tegra20: init NDFLASH clock to sensible rate
Set up the NAND Flash controller clock to run at 150MHz
instead of the rate set by the bootloader. This is a
conservative rate which also yields good performance.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
-rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 41272dcc9e22..f20424d02518 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1063,6 +1063,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0}, {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0}, {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0}, + {TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0}, {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */ }; |