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| author | Lars Povlsen <lars.povlsen@microchip.com> | 2020-06-15 15:32:36 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2020-07-22 22:28:40 +0200 |
| commit | 14bc6703b387cac2a9bec8f8d6bbffea63db43ea (patch) | |
| tree | c04911318dcffe0aee40b69b2426be08168e004f /arch/arm64/boot/dts/microchip | |
| parent | 6694aee00a4b478d2dd82837f39b5dc9cbedfbcf (diff) | |
| download | linux-14bc6703b387cac2a9bec8f8d6bbffea63db43ea.tar.gz linux-14bc6703b387cac2a9bec8f8d6bbffea63db43ea.tar.xz | |
arm64: dts: sparx5: Add pinctrl support
This add pinctrl support to the Microchip Sparx5 SoC.
Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot/dts/microchip')
| -rw-r--r-- | arch/arm64/boot/dts/microchip/sparx5.dtsi | 26 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 5 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 5 |
3 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 4a54b7d03916..baf4176ce1df 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -109,6 +109,8 @@ }; uart0: serial@600100000 { + pinctrl-0 = <&uart_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00100000 0x20>; clocks = <&ahb_clk>; @@ -120,6 +122,8 @@ }; uart1: serial@600102000 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; compatible = "ns16550a"; reg = <0x6 0x00102000 0x20>; clocks = <&ahb_clk>; @@ -138,5 +142,27 @@ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; }; + gpio: pinctrl@6110101e0 { + compatible = "microchip,sparx5-pinctrl"; + reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 64>; + interrupt-controller; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <2>; + + uart_pins: uart-pins { + pins = "GPIO_10", "GPIO_11"; + function = "uart"; + }; + + uart2_pins: uart2-pins { + pins = "GPIO_26", "GPIO_27"; + function = "uart2"; + }; + + }; + }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 005cf6babb9b..9b2aec400101 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -7,4 +7,9 @@ #include "sparx5_pcb_common.dtsi" /{ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + priority = <200>; + }; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 005cf6babb9b..9b2aec400101 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -7,4 +7,9 @@ #include "sparx5_pcb_common.dtsi" /{ + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 37 GPIO_ACTIVE_LOW>; + priority = <200>; + }; }; |