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authorHaavard Skinnemoen <hskinnemoen@atmel.com>2006-09-25 23:32:13 -0700
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-26 08:48:54 -0700
commit5f97f7f9400de47ae837170bb274e90ad3934386 (patch)
tree514451e6dc6b46253293a00035d375e77b1c65ed /arch/avr32/mach-at32ap/intc.h
parent53e62d3aaa60590d4a69b4e07c29f448b5151047 (diff)
downloadlinux-5f97f7f9400de47ae837170bb274e90ad3934386.tar.gz
linux-5f97f7f9400de47ae837170bb274e90ad3934386.tar.xz
[PATCH] avr32 architecture
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/avr32/mach-at32ap/intc.h')
-rw-r--r--arch/avr32/mach-at32ap/intc.h327
1 files changed, 327 insertions, 0 deletions
diff --git a/arch/avr32/mach-at32ap/intc.h b/arch/avr32/mach-at32ap/intc.h
new file mode 100644
index 000000000000..d289ca2fff13
--- /dev/null
+++ b/arch/avr32/mach-at32ap/intc.h
@@ -0,0 +1,327 @@
+/*
+ * Automatically generated by gen-header.xsl
+ */
+#ifndef __ASM_AVR32_PERIHP_INTC_H__
+#define __ASM_AVR32_PERIHP_INTC_H__
+
+#define INTC_NUM_INT_GRPS 33
+
+#define INTC_INTPR0 0x0
+# define INTC_INTPR0_INTLEV_OFFSET 30
+# define INTC_INTPR0_INTLEV_SIZE 2
+# define INTC_INTPR0_OFFSET_OFFSET 0
+# define INTC_INTPR0_OFFSET_SIZE 24
+#define INTC_INTREQ0 0x100
+# define INTC_INTREQ0_IREQUEST0_OFFSET 0
+# define INTC_INTREQ0_IREQUEST0_SIZE 1
+# define INTC_INTREQ0_IREQUEST1_OFFSET 1
+# define INTC_INTREQ0_IREQUEST1_SIZE 1
+#define INTC_INTPR1 0x4
+# define INTC_INTPR1_INTLEV_OFFSET 30
+# define INTC_INTPR1_INTLEV_SIZE 2
+# define INTC_INTPR1_OFFSET_OFFSET 0
+# define INTC_INTPR1_OFFSET_SIZE 24
+#define INTC_INTREQ1 0x104
+# define INTC_INTREQ1_IREQUEST32_OFFSET 0
+# define INTC_INTREQ1_IREQUEST32_SIZE 1
+# define INTC_INTREQ1_IREQUEST33_OFFSET 1
+# define INTC_INTREQ1_IREQUEST33_SIZE 1
+# define INTC_INTREQ1_IREQUEST34_OFFSET 2
+# define INTC_INTREQ1_IREQUEST34_SIZE 1
+# define INTC_INTREQ1_IREQUEST35_OFFSET 3
+# define INTC_INTREQ1_IREQUEST35_SIZE 1
+# define INTC_INTREQ1_IREQUEST36_OFFSET 4
+# define INTC_INTREQ1_IREQUEST36_SIZE 1
+# define INTC_INTREQ1_IREQUEST37_OFFSET 5
+# define INTC_INTREQ1_IREQUEST37_SIZE 1
+#define INTC_INTPR2 0x8
+# define INTC_INTPR2_INTLEV_OFFSET 30
+# define INTC_INTPR2_INTLEV_SIZE 2
+# define INTC_INTPR2_OFFSET_OFFSET 0
+# define INTC_INTPR2_OFFSET_SIZE 24
+#define INTC_INTREQ2 0x108
+# define INTC_INTREQ2_IREQUEST64_OFFSET 0
+# define INTC_INTREQ2_IREQUEST64_SIZE 1
+# define INTC_INTREQ2_IREQUEST65_OFFSET 1
+# define INTC_INTREQ2_IREQUEST65_SIZE 1
+# define INTC_INTREQ2_IREQUEST66_OFFSET 2
+# define INTC_INTREQ2_IREQUEST66_SIZE 1
+# define INTC_INTREQ2_IREQUEST67_OFFSET 3
+# define INTC_INTREQ2_IREQUEST67_SIZE 1
+# define INTC_INTREQ2_IREQUEST68_OFFSET 4
+# define INTC_INTREQ2_IREQUEST68_SIZE 1
+#define INTC_INTPR3 0xc
+# define INTC_INTPR3_INTLEV_OFFSET 30
+# define INTC_INTPR3_INTLEV_SIZE 2
+# define INTC_INTPR3_OFFSET_OFFSET 0
+# define INTC_INTPR3_OFFSET_SIZE 24
+#define INTC_INTREQ3 0x10c
+# define INTC_INTREQ3_IREQUEST96_OFFSET 0
+# define INTC_INTREQ3_IREQUEST96_SIZE 1
+#define INTC_INTPR4 0x10
+# define INTC_INTPR4_INTLEV_OFFSET 30
+# define INTC_INTPR4_INTLEV_SIZE 2
+# define INTC_INTPR4_OFFSET_OFFSET 0
+# define INTC_INTPR4_OFFSET_SIZE 24
+#define INTC_INTREQ4 0x110
+# define INTC_INTREQ4_IREQUEST128_OFFSET 0
+# define INTC_INTREQ4_IREQUEST128_SIZE 1
+#define INTC_INTPR5 0x14
+# define INTC_INTPR5_INTLEV_OFFSET 30
+# define INTC_INTPR5_INTLEV_SIZE 2
+# define INTC_INTPR5_OFFSET_OFFSET 0
+# define INTC_INTPR5_OFFSET_SIZE 24
+#define INTC_INTREQ5 0x114
+# define INTC_INTREQ5_IREQUEST160_OFFSET 0
+# define INTC_INTREQ5_IREQUEST160_SIZE 1
+#define INTC_INTPR6 0x18
+# define INTC_INTPR6_INTLEV_OFFSET 30
+# define INTC_INTPR6_INTLEV_SIZE 2
+# define INTC_INTPR6_OFFSET_OFFSET 0
+# define INTC_INTPR6_OFFSET_SIZE 24
+#define INTC_INTREQ6 0x118
+# define INTC_INTREQ6_IREQUEST192_OFFSET 0
+# define INTC_INTREQ6_IREQUEST192_SIZE 1
+#define INTC_INTPR7 0x1c
+# define INTC_INTPR7_INTLEV_OFFSET 30
+# define INTC_INTPR7_INTLEV_SIZE 2
+# define INTC_INTPR7_OFFSET_OFFSET 0
+# define INTC_INTPR7_OFFSET_SIZE 24
+#define INTC_INTREQ7 0x11c
+# define INTC_INTREQ7_IREQUEST224_OFFSET 0
+# define INTC_INTREQ7_IREQUEST224_SIZE 1
+#define INTC_INTPR8 0x20
+# define INTC_INTPR8_INTLEV_OFFSET 30
+# define INTC_INTPR8_INTLEV_SIZE 2
+# define INTC_INTPR8_OFFSET_OFFSET 0
+# define INTC_INTPR8_OFFSET_SIZE 24
+#define INTC_INTREQ8 0x120
+# define INTC_INTREQ8_IREQUEST256_OFFSET 0
+# define INTC_INTREQ8_IREQUEST256_SIZE 1
+#define INTC_INTPR9 0x24
+# define INTC_INTPR9_INTLEV_OFFSET 30
+# define INTC_INTPR9_INTLEV_SIZE 2
+# define INTC_INTPR9_OFFSET_OFFSET 0
+# define INTC_INTPR9_OFFSET_SIZE 24
+#define INTC_INTREQ9 0x124
+# define INTC_INTREQ9_IREQUEST288_OFFSET 0
+# define INTC_INTREQ9_IREQUEST288_SIZE 1
+#define INTC_INTPR10 0x28
+# define INTC_INTPR10_INTLEV_OFFSET 30
+# define INTC_INTPR10_INTLEV_SIZE 2
+# define INTC_INTPR10_OFFSET_OFFSET 0
+# define INTC_INTPR10_OFFSET_SIZE 24
+#define INTC_INTREQ10 0x128
+# define INTC_INTREQ10_IREQUEST320_OFFSET 0
+# define INTC_INTREQ10_IREQUEST320_SIZE 1
+#define INTC_INTPR11 0x2c
+# define INTC_INTPR11_INTLEV_OFFSET 30
+# define INTC_INTPR11_INTLEV_SIZE 2
+# define INTC_INTPR11_OFFSET_OFFSET 0
+# define INTC_INTPR11_OFFSET_SIZE 24
+#define INTC_INTREQ11 0x12c
+# define INTC_INTREQ11_IREQUEST352_OFFSET 0
+# define INTC_INTREQ11_IREQUEST352_SIZE 1
+#define INTC_INTPR12 0x30
+# define INTC_INTPR12_INTLEV_OFFSET 30
+# define INTC_INTPR12_INTLEV_SIZE 2
+# define INTC_INTPR12_OFFSET_OFFSET 0
+# define INTC_INTPR12_OFFSET_SIZE 24
+#define INTC_INTREQ12 0x130
+# define INTC_INTREQ12_IREQUEST384_OFFSET 0
+# define INTC_INTREQ12_IREQUEST384_SIZE 1
+#define INTC_INTPR13 0x34
+# define INTC_INTPR13_INTLEV_OFFSET 30
+# define INTC_INTPR13_INTLEV_SIZE 2
+# define INTC_INTPR13_OFFSET_OFFSET 0
+# define INTC_INTPR13_OFFSET_SIZE 24
+#define INTC_INTREQ13 0x134
+# define INTC_INTREQ13_IREQUEST416_OFFSET 0
+# define INTC_INTREQ13_IREQUEST416_SIZE 1
+#define INTC_INTPR14 0x38
+# define INTC_INTPR14_INTLEV_OFFSET 30
+# define INTC_INTPR14_INTLEV_SIZE 2
+# define INTC_INTPR14_OFFSET_OFFSET 0
+# define INTC_INTPR14_OFFSET_SIZE 24
+#define INTC_INTREQ14 0x138
+# define INTC_INTREQ14_IREQUEST448_OFFSET 0
+# define INTC_INTREQ14_IREQUEST448_SIZE 1
+#define INTC_INTPR15 0x3c
+# define INTC_INTPR15_INTLEV_OFFSET 30
+# define INTC_INTPR15_INTLEV_SIZE 2
+# define INTC_INTPR15_OFFSET_OFFSET 0
+# define INTC_INTPR15_OFFSET_SIZE 24
+#define INTC_INTREQ15 0x13c
+# define INTC_INTREQ15_IREQUEST480_OFFSET 0
+# define INTC_INTREQ15_IREQUEST480_SIZE 1
+#define INTC_INTPR16 0x40
+# define INTC_INTPR16_INTLEV_OFFSET 30
+# define INTC_INTPR16_INTLEV_SIZE 2
+# define INTC_INTPR16_OFFSET_OFFSET 0
+# define INTC_INTPR16_OFFSET_SIZE 24
+#define INTC_INTREQ16 0x140
+# define INTC_INTREQ16_IREQUEST512_OFFSET 0
+# define INTC_INTREQ16_IREQUEST512_SIZE 1
+#define INTC_INTPR17 0x44
+# define INTC_INTPR17_INTLEV_OFFSET 30
+# define INTC_INTPR17_INTLEV_SIZE 2
+# define INTC_INTPR17_OFFSET_OFFSET 0
+# define INTC_INTPR17_OFFSET_SIZE 24
+#define INTC_INTREQ17 0x144
+# define INTC_INTREQ17_IREQUEST544_OFFSET 0
+# define INTC_INTREQ17_IREQUEST544_SIZE 1
+#define INTC_INTPR18 0x48
+# define INTC_INTPR18_INTLEV_OFFSET 30
+# define INTC_INTPR18_INTLEV_SIZE 2
+# define INTC_INTPR18_OFFSET_OFFSET 0
+# define INTC_INTPR18_OFFSET_SIZE 24
+#define INTC_INTREQ18 0x148
+# define INTC_INTREQ18_IREQUEST576_OFFSET 0
+# define INTC_INTREQ18_IREQUEST576_SIZE 1
+#define INTC_INTPR19 0x4c
+# define INTC_INTPR19_INTLEV_OFFSET 30
+# define INTC_INTPR19_INTLEV_SIZE 2
+# define INTC_INTPR19_OFFSET_OFFSET 0
+# define INTC_INTPR19_OFFSET_SIZE 24
+#define INTC_INTREQ19 0x14c
+# define INTC_INTREQ19_IREQUEST608_OFFSET 0
+# define INTC_INTREQ19_IREQUEST608_SIZE 1
+# define INTC_INTREQ19_IREQUEST609_OFFSET 1
+# define INTC_INTREQ19_IREQUEST609_SIZE 1
+# define INTC_INTREQ19_IREQUEST610_OFFSET 2
+# define INTC_INTREQ19_IREQUEST610_SIZE 1
+# define INTC_INTREQ19_IREQUEST611_OFFSET 3
+# define INTC_INTREQ19_IREQUEST611_SIZE 1
+#define INTC_INTPR20 0x50
+# define INTC_INTPR20_INTLEV_OFFSET 30
+# define INTC_INTPR20_INTLEV_SIZE 2
+# define INTC_INTPR20_OFFSET_OFFSET 0
+# define INTC_INTPR20_OFFSET_SIZE 24
+#define INTC_INTREQ20 0x150
+# define INTC_INTREQ20_IREQUEST640_OFFSET 0
+# define INTC_INTREQ20_IREQUEST640_SIZE 1
+#define INTC_INTPR21 0x54
+# define INTC_INTPR21_INTLEV_OFFSET 30
+# define INTC_INTPR21_INTLEV_SIZE 2
+# define INTC_INTPR21_OFFSET_OFFSET 0
+# define INTC_INTPR21_OFFSET_SIZE 24
+#define INTC_INTREQ21 0x154
+# define INTC_INTREQ21_IREQUEST672_OFFSET 0
+# define INTC_INTREQ21_IREQUEST672_SIZE 1
+#define INTC_INTPR22 0x58
+# define INTC_INTPR22_INTLEV_OFFSET 30
+# define INTC_INTPR22_INTLEV_SIZE 2
+# define INTC_INTPR22_OFFSET_OFFSET 0
+# define INTC_INTPR22_OFFSET_SIZE 24
+#define INTC_INTREQ22 0x158
+# define INTC_INTREQ22_IREQUEST704_OFFSET 0
+# define INTC_INTREQ22_IREQUEST704_SIZE 1
+# define INTC_INTREQ22_IREQUEST705_OFFSET 1
+# define INTC_INTREQ22_IREQUEST705_SIZE 1
+# define INTC_INTREQ22_IREQUEST706_OFFSET 2
+# define INTC_INTREQ22_IREQUEST706_SIZE 1
+#define INTC_INTPR23 0x5c
+# define INTC_INTPR23_INTLEV_OFFSET 30
+# define INTC_INTPR23_INTLEV_SIZE 2
+# define INTC_INTPR23_OFFSET_OFFSET 0
+# define INTC_INTPR23_OFFSET_SIZE 24
+#define INTC_INTREQ23 0x15c
+# define INTC_INTREQ23_IREQUEST736_OFFSET 0
+# define INTC_INTREQ23_IREQUEST736_SIZE 1
+# define INTC_INTREQ23_IREQUEST737_OFFSET 1
+# define INTC_INTREQ23_IREQUEST737_SIZE 1
+# define INTC_INTREQ23_IREQUEST738_OFFSET 2
+# define INTC_INTREQ23_IREQUEST738_SIZE 1
+#define INTC_INTPR24 0x60
+# define INTC_INTPR24_INTLEV_OFFSET 30
+# define INTC_INTPR24_INTLEV_SIZE 2
+# define INTC_INTPR24_OFFSET_OFFSET 0
+# define INTC_INTPR24_OFFSET_SIZE 24
+#define INTC_INTREQ24 0x160
+# define INTC_INTREQ24_IREQUEST768_OFFSET 0
+# define INTC_INTREQ24_IREQUEST768_SIZE 1
+#define INTC_INTPR25 0x64
+# define INTC_INTPR25_INTLEV_OFFSET 30
+# define INTC_INTPR25_INTLEV_SIZE 2
+# define INTC_INTPR25_OFFSET_OFFSET 0
+# define INTC_INTPR25_OFFSET_SIZE 24
+#define INTC_INTREQ25 0x164
+# define INTC_INTREQ25_IREQUEST800_OFFSET 0
+# define INTC_INTREQ25_IREQUEST800_SIZE 1
+#define INTC_INTPR26 0x68
+# define INTC_INTPR26_INTLEV_OFFSET 30
+# define INTC_INTPR26_INTLEV_SIZE 2
+# define INTC_INTPR26_OFFSET_OFFSET 0
+# define INTC_INTPR26_OFFSET_SIZE 24
+#define INTC_INTREQ26 0x168
+# define INTC_INTREQ26_IREQUEST832_OFFSET 0
+# define INTC_INTREQ26_IREQUEST832_SIZE 1
+#define INTC_INTPR27 0x6c
+# define INTC_INTPR27_INTLEV_OFFSET 30
+# define INTC_INTPR27_INTLEV_SIZE 2
+# define INTC_INTPR27_OFFSET_OFFSET 0
+# define INTC_INTPR27_OFFSET_SIZE 24
+#define INTC_INTREQ27 0x16c
+# define INTC_INTREQ27_IREQUEST864_OFFSET 0
+# define INTC_INTREQ27_IREQUEST864_SIZE 1
+#define INTC_INTPR28 0x70
+# define INTC_INTPR28_INTLEV_OFFSET 30
+# define INTC_INTPR28_INTLEV_SIZE 2
+# define INTC_INTPR28_OFFSET_OFFSET 0
+# define INTC_INTPR28_OFFSET_SIZE 24
+#define INTC_INTREQ28 0x170
+# define INTC_INTREQ28_IREQUEST896_OFFSET 0
+# define INTC_INTREQ28_IREQUEST896_SIZE 1
+#define INTC_INTPR29 0x74
+# define INTC_INTPR29_INTLEV_OFFSET 30
+# define INTC_INTPR29_INTLEV_SIZE 2
+# define INTC_INTPR29_OFFSET_OFFSET 0
+# define INTC_INTPR29_OFFSET_SIZE 24
+#define INTC_INTREQ29 0x174
+# define INTC_INTREQ29_IREQUEST928_OFFSET 0
+# define INTC_INTREQ29_IREQUEST928_SIZE 1
+#define INTC_INTPR30 0x78
+# define INTC_INTPR30_INTLEV_OFFSET 30
+# define INTC_INTPR30_INTLEV_SIZE 2
+# define INTC_INTPR30_OFFSET_OFFSET 0
+# define INTC_INTPR30_OFFSET_SIZE 24
+#define INTC_INTREQ30 0x178
+# define INTC_INTREQ30_IREQUEST960_OFFSET 0
+# define INTC_INTREQ30_IREQUEST960_SIZE 1
+#define INTC_INTPR31 0x7c
+# define INTC_INTPR31_INTLEV_OFFSET 30
+# define INTC_INTPR31_INTLEV_SIZE 2
+# define INTC_INTPR31_OFFSET_OFFSET 0
+# define INTC_INTPR31_OFFSET_SIZE 24
+#define INTC_INTREQ31 0x17c
+# define INTC_INTREQ31_IREQUEST992_OFFSET 0
+# define INTC_INTREQ31_IREQUEST992_SIZE 1
+#define INTC_INTPR32 0x80
+# define INTC_INTPR32_INTLEV_OFFSET 30
+# define INTC_INTPR32_INTLEV_SIZE 2
+# define INTC_INTPR32_OFFSET_OFFSET 0
+# define INTC_INTPR32_OFFSET_SIZE 24
+#define INTC_INTREQ32 0x180
+# define INTC_INTREQ32_IREQUEST1024_OFFSET 0
+# define INTC_INTREQ32_IREQUEST1024_SIZE 1
+#define INTC_INTCAUSE0 0x20c
+# define INTC_INTCAUSE0_CAUSEGRP_OFFSET 0
+# define INTC_INTCAUSE0_CAUSEGRP_SIZE 6
+#define INTC_INTCAUSE1 0x208
+# define INTC_INTCAUSE1_CAUSEGRP_OFFSET 0
+# define INTC_INTCAUSE1_CAUSEGRP_SIZE 6
+#define INTC_INTCAUSE2 0x204
+# define INTC_INTCAUSE2_CAUSEGRP_OFFSET 0
+# define INTC_INTCAUSE2_CAUSEGRP_SIZE 6
+#define INTC_INTCAUSE3 0x200
+# define INTC_INTCAUSE3_CAUSEGRP_OFFSET 0
+# define INTC_INTCAUSE3_CAUSEGRP_SIZE 6
+
+#define INTC_BIT(name) (1 << INTC_##name##_OFFSET)
+#define INTC_MKBF(name, value) (((value) & ((1 << INTC_##name##_SIZE) - 1)) << INTC_##name##_OFFSET)
+#define INTC_GETBF(name, value) (((value) >> INTC_##name##_OFFSET) & ((1 << INTC_##name##_SIZE) - 1))
+
+#define intc_readl(port,reg) readl((port)->regs + INTC_##reg)
+#define intc_writel(port,reg,value) writel((value), (port)->regs + INTC_##reg)
+
+#endif /* __ASM_AVR32_PERIHP_INTC_H__ */