path: root/arch/avr32/mm/cache.c
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authorHaavard Skinnemoen <>2007-11-28 15:04:01 +0100
committerHaavard Skinnemoen <>2007-12-07 14:54:46 +0100
commit2507bc1338e43eadfef5b604d2c47e4f8180718f (patch)
tree4bc3c14114ba96efb8e9e4f2c0925fb92b669a19 /arch/avr32/mm/cache.c
parent8dfe8f29cd371affcc3c6b35658dc4bd95ee7b61 (diff)
[AVR32] Follow the rules when dealing with the OCD system
The current debug trap handling code does a number of things that are illegal according to the AVR32 Architecture manual. Most importantly, it may try to schedule from Debug Mode, thus clearing the D bit, which can lead to "undefined behaviour". It seems like this works in most cases, but several people have observed somewhat unstable behaviour when debugging programs, including soft lockups. So there's definitely something which is not right with the existing code. The new code will never schedule from Debug mode, it will always exit Debug mode with a "retd" instruction, and if something not running in Debug mode needs to do something debug-related (like doing a single step), it will enter debug mode through a "breakpoint" instruction. The monitor code will then return directly to user space, bypassing its own saved registers if necessary (since we don't actually care about the trapped context, only the one that came before.) This adds three instructions to the common exception handling code, including one branch. It does not touch super-hot paths like the TLB miss handler. Signed-off-by: Haavard Skinnemoen <>
Diffstat (limited to 'arch/avr32/mm/cache.c')
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