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| author | Ira Weiny <ira.weiny@intel.com> | 2021-05-27 17:49:18 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2021-06-05 17:24:04 -0700 |
| commit | 07d62eac422c5c8aec6ec1dacdc27423334b2d17 (patch) | |
| tree | b1e526307abb713754a080f27f5ff7119c5fe492 /drivers/cxl | |
| parent | 6630d31c912ed2dfbc035caf0f54709b50ce779e (diff) | |
| download | linux-07d62eac422c5c8aec6ec1dacdc27423334b2d17.tar.gz linux-07d62eac422c5c8aec6ec1dacdc27423334b2d17.tar.xz | |
cxl/pci: Introduce cxl_decode_register_block()
Each register block located in the DVSEC needs to be decoded from 2
words, 'register offset high' and 'register offset low'.
Create a function, cxl_decode_register_block() to perform this decode
and return the bar, offset, and register type of the register block.
Then use the values decoded in cxl_mem_map_regblock() instead of passing
the raw registers.
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/20210528004922.3980613-2-ira.weiny@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'drivers/cxl')
| -rw-r--r-- | drivers/cxl/pci.c | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 8bdae74d7d78..b2f978954daa 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -922,17 +922,13 @@ static struct cxl_mem *cxl_mem_create(struct pci_dev *pdev) return cxlm; } -static void __iomem *cxl_mem_map_regblock(struct cxl_mem *cxlm, u32 reg_lo, u32 reg_hi) +static void __iomem *cxl_mem_map_regblock(struct cxl_mem *cxlm, + u8 bar, u64 offset) { struct pci_dev *pdev = cxlm->pdev; struct device *dev = &pdev->dev; - u64 offset; - u8 bar; int rc; - offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK); - bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo); - /* Basic sanity check that BAR is big enough */ if (pci_resource_len(pdev, bar) < offset) { dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, @@ -974,6 +970,14 @@ static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec) return 0; } +static void cxl_decode_register_block(u32 reg_lo, u32 reg_hi, + u8 *bar, u64 *offset, u8 *reg_type) +{ + *offset = ((u64)reg_hi << 32) | (reg_lo & CXL_REGLOC_ADDR_MASK); + *bar = FIELD_GET(CXL_REGLOC_BIR_MASK, reg_lo); + *reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo); +} + /** * cxl_mem_setup_regs() - Setup necessary MMIO. * @cxlm: The CXL memory device to communicate with. @@ -1009,15 +1013,21 @@ static int cxl_mem_setup_regs(struct cxl_mem *cxlm) for (i = 0; i < regblocks; i++, regloc += 8) { u32 reg_lo, reg_hi; u8 reg_type; + u64 offset; + u8 bar; /* "register low and high" contain other bits */ pci_read_config_dword(pdev, regloc, ®_lo); pci_read_config_dword(pdev, regloc + 4, ®_hi); - reg_type = FIELD_GET(CXL_REGLOC_RBI_MASK, reg_lo); + cxl_decode_register_block(reg_lo, reg_hi, &bar, &offset, + ®_type); + + dev_dbg(dev, "Found register block in bar %u @ 0x%llx of type %u\n", + bar, offset, reg_type); if (reg_type == CXL_REGLOC_RBI_MEMDEV) { - base = cxl_mem_map_regblock(cxlm, reg_lo, reg_hi); + base = cxl_mem_map_regblock(cxlm, bar, offset); if (IS_ERR(base)) return PTR_ERR(base); break; |