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author | Lucas Stach <l.stach@pengutronix.de> | 2021-06-28 21:36:29 +0200 |
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committer | Lucas Stach <l.stach@pengutronix.de> | 2021-07-21 22:27:10 +0200 |
commit | fd324ac75441f703ac3f939df5cfd9585e0c4c30 (patch) | |
tree | e85b4ad414ce9970d6b62a7fe9d832af3cea37a9 /drivers/gpu/drm | |
parent | 0a61267eed91bc0a69f25bbcb3e7ee7d7ad1efe6 (diff) | |
download | linux-fd324ac75441f703ac3f939df5cfd9585e0c4c30.tar.gz linux-fd324ac75441f703ac3f939df5cfd9585e0c4c30.tar.xz |
drm/bridge: samsung-dsim: fix PLL calculation
The PLL in the i.MX8MM has a higher speed PLL with a different
parameter mapping.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r-- | drivers/gpu/drm/bridge/samsung-dsim.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c index 7251c1f2a9df..116ccd0ebd49 100644 --- a/drivers/gpu/drm/bridge/samsung-dsim.c +++ b/drivers/gpu/drm/bridge/samsung-dsim.c @@ -174,8 +174,8 @@ /* DSIM_PLLCTRL */ #define DSIM_FREQ_BAND(x) ((x) << 24) #define DSIM_PLL_EN (1 << 23) -#define DSIM_PLL_P(x) ((x) << 13) -#define DSIM_PLL_M(x) ((x) << 4) +#define DSIM_PLL_P(x) ((x) << 14) +#define DSIM_PLL_M(x) ((x) << 5) #define DSIM_PLL_S(x) ((x) << 1) /* DSIM_PHYCTRL */ @@ -403,7 +403,7 @@ static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, u16 _m, best_m; u8 _s, best_s; - p_min = DIV_ROUND_UP(fin, (12 * MHZ)); + p_min = DIV_ROUND_UP(fin, (30 * MHZ)); p_max = fin / (6 * MHZ); for (_p = p_min; _p <= p_max; ++_p) { @@ -414,12 +414,12 @@ static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, tmp = (u64)fout * (_p << _s); do_div(tmp, fin); _m = tmp; - if (_m < 41 || _m > 125) + if (_m < 41 || _m > 250) continue; tmp = (u64)_m * fin; do_div(tmp, _p); - if (tmp < 500 * MHZ || + if (tmp < 1000 * MHZ || tmp > driver_data->max_freq * MHZ) continue; @@ -463,7 +463,7 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, "failed to find PLL PMS for requested frequency\n"); return 0; } - dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); + dev_info(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); writel(driver_data->reg_values[PLL_TIMER], dsi->reg_base + driver_data->plltmr_reg); |