diff options
| author | 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> | 2021-04-18 22:44:24 +0800 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2021-04-22 01:53:01 +0200 |
| commit | 1101519695d0594f353bced77bc9995c13f31048 (patch) | |
| tree | 3d386c40d02c4dd9ee3be427ec97e21eff1393cd /drivers/pinctrl | |
| parent | 1d0bd580ef83b78a10c0b37f3313eaa59d8c80db (diff) | |
| download | linux-1101519695d0594f353bced77bc9995c13f31048.tar.gz linux-1101519695d0594f353bced77bc9995c13f31048.tar.xz | |
pinctrl: Ingenic: Adjust the sequence of X1830 SSI pin groups.
Adjust the sequence of X1830's SSI related codes to make it consistent
with other Ingenic SoCs.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/1618757073-1724-4-git-send-email-zhouyanjie@wanyeetech.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl')
| -rw-r--r-- | drivers/pinctrl/pinctrl-ingenic.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 02729da8abd6..761e42dc471e 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1473,16 +1473,16 @@ static int x1830_ssi0_gpc_pins[] = { 0x4d, }; static int x1830_ssi0_ce0_pins[] = { 0x50, }; static int x1830_ssi0_ce1_pins[] = { 0x4e, }; static int x1830_ssi1_dt_c_pins[] = { 0x53, }; -static int x1830_ssi1_dr_c_pins[] = { 0x54, }; -static int x1830_ssi1_clk_c_pins[] = { 0x57, }; -static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; -static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; -static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; static int x1830_ssi1_dt_d_pins[] = { 0x62, }; +static int x1830_ssi1_dr_c_pins[] = { 0x54, }; static int x1830_ssi1_dr_d_pins[] = { 0x63, }; +static int x1830_ssi1_clk_c_pins[] = { 0x57, }; static int x1830_ssi1_clk_d_pins[] = { 0x66, }; +static int x1830_ssi1_gpc_c_pins[] = { 0x55, }; static int x1830_ssi1_gpc_d_pins[] = { 0x64, }; +static int x1830_ssi1_ce0_c_pins[] = { 0x58, }; static int x1830_ssi1_ce0_d_pins[] = { 0x67, }; +static int x1830_ssi1_ce1_c_pins[] = { 0x56, }; static int x1830_ssi1_ce1_d_pins[] = { 0x65, }; static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, }; static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, }; |