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| author | Brendan Jackman <jackmanb@google.com> | 2021-01-14 18:17:49 +0000 |
|---|---|---|
| committer | Alexei Starovoitov <ast@kernel.org> | 2021-01-14 18:34:29 -0800 |
| commit | 981f94c3e92146705baf97fb417a5ed1ab1a79a5 (patch) | |
| tree | 3e9cd30902659db0e4de8f9afad972f259d9dcf9 /kernel/bpf/core.c | |
| parent | 462910670e4ac91509829c5549bd0227668176fb (diff) | |
| download | linux-981f94c3e92146705baf97fb417a5ed1ab1a79a5.tar.gz linux-981f94c3e92146705baf97fb417a5ed1ab1a79a5.tar.xz | |
bpf: Add bitwise atomic instructions
This adds instructions for
atomic[64]_[fetch_]and
atomic[64]_[fetch_]or
atomic[64]_[fetch_]xor
All these operations are isomorphic enough to implement with the same
verifier, interpreter, and x86 JIT code, hence being a single commit.
The main interesting thing here is that x86 doesn't directly support
the fetch_ version these operations, so we need to generate a CMPXCHG
loop in the JIT. This requires the use of two temporary registers,
IIUC it's safe to use BPF_REG_AX and x86's AUX_REG for this purpose.
Signed-off-by: Brendan Jackman <jackmanb@google.com>
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
Acked-by: Yonghong Song <yhs@fb.com>
Link: https://lore.kernel.org/bpf/20210114181751.768687-10-jackmanb@google.com
Diffstat (limited to 'kernel/bpf/core.c')
| -rw-r--r-- | kernel/bpf/core.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/bpf/core.c b/kernel/bpf/core.c index 8669e685825f..5bbd4884ff7a 100644 --- a/kernel/bpf/core.c +++ b/kernel/bpf/core.c @@ -1642,6 +1642,9 @@ out: STX_ATOMIC_W: switch (IMM) { ATOMIC_ALU_OP(BPF_ADD, add) + ATOMIC_ALU_OP(BPF_AND, and) + ATOMIC_ALU_OP(BPF_OR, or) + ATOMIC_ALU_OP(BPF_XOR, xor) #undef ATOMIC_ALU_OP case BPF_XCHG: |