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-rw-r--r--Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml94
1 files changed, 94 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
new file mode 100644
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+++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MM DISP blk-ctrl
+
+maintainers:
+ - Lucas Stach <l.stach@pengutronix.de>
+
+description:
+ The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
+ the NoC and ensuring proper power sequencing of the display and MIPI CSI
+ peripherals located in the DISP domain of the SoC.
+
+properties:
+ compatible:
+ items:
+ - const: fsl,imx8mm-disp-blk-ctrl
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#power-domains-cells':
+ const: 1
+
+ power-domains:
+ minItems: 5
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: bus
+ - const: csi-bridge
+ - const: lcdif
+ - const: mipi-dsi
+ - const: mipi-csi
+
+ clocks:
+ minItems: 10
+ maxItems: 10
+
+ clock-names:
+ items:
+ - const: csi-bridge-axi
+ - const: csi-bridge-apb
+ - const: csi-bridge-core
+ - const: lcdif-axi
+ - const: lcdif-apb
+ - const: lcdif-pix
+ - const: dsi-pclk
+ - const: dsi-ref
+ - const: csi-aclk
+ - const: csi-pclk
+
+required:
+ - compatible
+ - reg
+ - power-domains
+ - power-domain-names
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ #include <dt-bindings/power/imx8mm-power.h>
+
+ disp_blk_ctl: blk_ctrl@32e28000 {
+ compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
+ reg = <0x32e28000 0x100>;
+ power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
+ <&pgc_mipi>, <&pgc_mipi>;
+ power-domain-names = "bus", "csi-bridge", "lcdif",
+ "mipi-dsi", "mipi-csi";
+ clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MM_CLK_CSI1_ROOT>,
+ <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MM_CLK_DISP_ROOT>,
+ <&clk IMX8MM_CLK_DSI_CORE>,
+ <&clk IMX8MM_CLK_DSI_PHY_REF>,
+ <&clk IMX8MM_CLK_CSI1_CORE>,
+ <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+ clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
+ "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
+ "dsi-ref", "csi-aclk", "csi-pclk";
+ #power-domain-cells = <1>;
+ };