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Diffstat (limited to 'arch/arm/boot/dts/r8a7792.dtsi')
-rw-r--r--arch/arm/boot/dts/r8a7792.dtsi26
1 files changed, 17 insertions, 9 deletions
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 6ced3c1ec377..8ecfda7a004e 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -88,7 +88,7 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>,
- <0 0xf1002000 0 0x1000>,
+ <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>,
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
@@ -498,7 +498,8 @@
/* I2C doesn't need pinmux */
i2c0: i2c@e6508000 {
- compatible = "renesas,i2c-r8a7792";
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
@@ -510,7 +511,8 @@
};
i2c1: i2c@e6518000 {
- compatible = "renesas,i2c-r8a7792";
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
reg = <0 0xe6518000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
@@ -522,7 +524,8 @@
};
i2c2: i2c@e6530000 {
- compatible = "renesas,i2c-r8a7792";
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
reg = <0 0xe6530000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
@@ -534,7 +537,8 @@
};
i2c3: i2c@e6540000 {
- compatible = "renesas,i2c-r8a7792";
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
reg = <0 0xe6540000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
@@ -546,7 +550,8 @@
};
i2c4: i2c@e6520000 {
- compatible = "renesas,i2c-r8a7792";
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
reg = <0 0xe6520000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
@@ -558,7 +563,8 @@
};
i2c5: i2c@e6528000 {
- compatible = "renesas,i2c-r8a7792";
+ compatible = "renesas,i2c-r8a7792",
+ "renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
@@ -585,7 +591,8 @@
};
msiof0: spi@e6e20000 {
- compatible = "renesas,msiof-r8a7792";
+ compatible = "renesas,msiof-r8a7792",
+ "renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
@@ -599,7 +606,8 @@
};
msiof1: spi@e6e10000 {
- compatible = "renesas,msiof-r8a7792";
+ compatible = "renesas,msiof-r8a7792",
+ "renesas,rcar-gen2-msiof";
reg = <0 0xe6e10000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;