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Diffstat (limited to 'arch/arm64/boot/dts/qcom/qcs404-evb.dtsi')
-rw-r--r--arch/arm64/boot/dts/qcom/qcs404-evb.dtsi43
1 files changed, 38 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 2c3127167e3c..11c0a7137823 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited
+#include <dt-bindings/gpio/gpio.h>
#include "qcs404.dtsi"
#include "pms405.dtsi"
@@ -56,18 +57,41 @@
qcom,controlled-remotely;
};
+&gcc {
+ protected-clocks = <GCC_BIMC_CDSP_CLK>,
+ <GCC_CDSP_CFG_AHB_CLK>,
+ <GCC_CDSP_BIMC_CLK_SRC>,
+ <GCC_CDSP_TBU_CLK>;
+};
+
&pms405_spmi_regulators {
- vdd_s3-supply = <&pms405_s3>;
+ vdd_s3-supply = <&vph_pwr>;
pms405_s3: s3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_apc";
regulator-min-microvolt = <1048000>;
- regulator-max-microvolt = <1352000>;
+ regulator-max-microvolt = <1384000>;
};
};
+&pcie {
+ status = "ok";
+
+ perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&perst_state>;
+};
+
+&pcie_phy {
+ status = "ok";
+
+ vdda-vp-supply = <&vreg_l3_1p05>;
+ vdda-vph-supply = <&vreg_l5_1p8>;
+};
+
&remoteproc_adsp {
status = "ok";
};
@@ -118,7 +142,7 @@
};
vreg_l3_1p05: l3 {
- regulator-min-microvolt = <1050000>;
+ regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1160000>;
};
@@ -184,6 +208,15 @@
};
&tlmm {
+ perst_state: perst {
+ pins = "gpio43";
+ function = "gpio";
+
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
@@ -200,7 +233,7 @@
data {
pins = "sdc1_data";
bias-pull-up;
- dreive-strength = <10>;
+ drive-strength = <10>;
};
rclk {
@@ -225,7 +258,7 @@
data {
pins = "sdc1_data";
bias-pull-up;
- dreive-strength = <2>;
+ drive-strength = <2>;
};
rclk {