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path: root/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
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Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a3xx_gpu.c')
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx_gpu.c67
1 files changed, 51 insertions, 16 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index a31360a7ec46..c97f8f41b159 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -254,9 +254,12 @@ static int a3xx_hw_init(struct adreno_gpu *gpu)
static void a3xx_destroy(struct adreno_gpu *gpu)
{
+ struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(gpu);
DBG("%s", adreno_get_name(gpu));
+ a3xx_bs_fini(a3xx_gpu);
+
adreno_gpu_cleanup(gpu);
put_device(&gpu->pdev->dev);
kfree(gpu);
@@ -365,8 +368,8 @@ static void a3xx_show(struct adreno_gpu *gpu, struct seq_file *m)
static const struct adreno_gpu_funcs funcs = {
.get_param = adreno_get_param,
.hw_init = a3xx_hw_init,
- .pm_suspend = msm_gpu_pm_suspend,
- .pm_resume = msm_gpu_pm_resume,
+ .pm_suspend = a3xx_gpu_pm_suspend,
+ .pm_resume = a3xx_gpu_pm_resume,
.recover = adreno_recover,
.last_fence = adreno_last_fence,
.submit = adreno_submit,
@@ -379,14 +382,18 @@ static const struct adreno_gpu_funcs funcs = {
#endif
};
+static const char *clk_names[] = {
+ "src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",
+};
+
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev, struct adreno_gem *gem,
struct workqueue_struct *wq, int reglog)
{
- struct adreno_gpu *adreno_gpu = NULL;
+ struct a3xx_gpu *a3xx_gpu = NULL;
struct msm_gpu *gpu;
struct platform_device *pdev = a3xx_pdev;
struct adreno_platform_config *config;
- int ret;
+ int i, ret;
if (!pdev) {
dev_err(dev->dev, "no a3xx device\n");
@@ -395,35 +402,63 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev, struct adreno_gem *gem,
config = pdev->dev.platform_data;
- adreno_gpu = kzalloc(sizeof(*adreno_gpu), GFP_KERNEL);
- if (!adreno_gpu) {
+ a3xx_gpu = kzalloc(sizeof(*a3xx_gpu), GFP_KERNEL);
+ if (!a3xx_gpu) {
ret = -ENOMEM;
goto fail;
}
- gpu = &adreno_gpu->base;
+ gpu = &a3xx_gpu->base.base;
get_device(&pdev->dev);
- adreno_gpu->pdev = pdev;
+ a3xx_gpu->base.pdev = pdev;
- gpu->fast_rate = config->fast_rate;
- gpu->slow_rate = config->slow_rate;
- gpu->bus_freq = config->bus_freq;
+ a3xx_gpu->fast_rate = config->fast_rate;
+ a3xx_gpu->slow_rate = config->slow_rate;
+ a3xx_gpu->bus_freq = config->bus_freq;
DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
- gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
+ a3xx_gpu->fast_rate, a3xx_gpu->slow_rate, a3xx_gpu->bus_freq);
+
+ /* Acquire clocks: */
+ BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(a3xx_gpu->grp_clks));
+
+ for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
+ a3xx_gpu->grp_clks[i] = devm_clk_get(&pdev->dev, clk_names[i]);
+ DBG("grp_clks[%s]: %p", clk_names[i], a3xx_gpu->grp_clks[i]);
+ if (IS_ERR(a3xx_gpu->grp_clks[i]))
+ a3xx_gpu->grp_clks[i] = NULL;
+ }
+
+ a3xx_gpu->ebi1_clk = devm_clk_get(&pdev->dev, "bus_clk");
+ DBG("ebi1_clk: %p", a3xx_gpu->ebi1_clk);
+ if (IS_ERR(a3xx_gpu->ebi1_clk))
+ a3xx_gpu->ebi1_clk = NULL;
+
+ /* Acquire regulators: */
+ a3xx_gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
+ DBG("gpu_reg: %p", a3xx_gpu->gpu_reg);
+ if (IS_ERR(a3xx_gpu->gpu_reg))
+ a3xx_gpu->gpu_reg = NULL;
+
+ a3xx_gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
+ DBG("gpu_cx: %p", a3xx_gpu->gpu_cx);
+ if (IS_ERR(a3xx_gpu->gpu_cx))
+ a3xx_gpu->gpu_cx = NULL;
+
+ a3xx_bs_init(a3xx_gpu, pdev);
adreno_reglog = reglog;
- ret = adreno_gpu_init(dev, pdev, adreno_gpu,
+ ret = adreno_gpu_init(dev, pdev, &a3xx_gpu->base,
&funcs, gem, wq, config->rev);
if (ret)
goto fail;
- return &adreno_gpu->base;
+ return &a3xx_gpu->base.base;
fail:
- if (adreno_gpu)
- a3xx_destroy(adreno_gpu);
+ if (a3xx_gpu)
+ a3xx_destroy(&a3xx_gpu->base);
return ERR_PTR(ret);
}