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path: root/drivers/gpu/drm/msm/msm_gpu.c
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Diffstat (limited to 'drivers/gpu/drm/msm/msm_gpu.c')
-rw-r--r--drivers/gpu/drm/msm/msm_gpu.c64
1 files changed, 58 insertions, 6 deletions
diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index 4b93c81..673bf1d 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -17,7 +17,6 @@
#include "msm_gpu.h"
#include "msm_gem.h"
-#include "adreno/adreno_gpu.h"
/*
* Cmdstream submission/retirement:
@@ -53,8 +52,9 @@ static void retire_worker(struct work_struct *work)
}
/* call from irq handler to schedule work to retire bo's */
-void msm_gpu_retire(struct msm_gpu *gpu)
+static void msm_gpu_retire(void *gem_priv)
{
+ struct msm_gpu *gpu = gem_priv;
struct msm_drm_private *priv = gpu->dev->dev_private;
queue_work(priv->wq, &gpu->retire_work);
}
@@ -98,6 +98,46 @@ int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
return ret;
}
+static struct drm_gem_object *
+gem_new(void *gem_priv, uint32_t size, uint32_t flags)
+{
+ struct msm_gpu *gpu = gem_priv;
+ return msm_gem_new(gpu->dev, size, flags);
+}
+
+static int
+gem_get_iova_locked(void *gem_priv, struct drm_gem_object *obj, uint32_t *iova)
+{
+ struct msm_gpu *gpu = gem_priv;
+ return msm_gem_get_iova_locked(obj, gpu->id, iova);
+}
+
+static int
+gem_get_iova(void *gem_priv, struct drm_gem_object *obj, uint32_t *iova)
+{
+ struct msm_gpu *gpu = gem_priv;
+ return msm_gem_get_iova(obj, gpu->id, iova);
+}
+
+static void
+gem_put_iova(void *gem_priv, struct drm_gem_object *obj)
+{
+ struct msm_gpu *gpu = gem_priv;
+ return msm_gem_put_iova(obj, gpu->id);
+}
+
+static void *
+gem_vaddr_locked(void *gem_priv, struct drm_gem_object *obj)
+{
+ return msm_gem_vaddr_locked(obj);
+}
+
+static void *
+gem_vaddr(void *gem_priv, struct drm_gem_object *obj)
+{
+ return msm_gem_vaddr(obj);
+}
+
/*
* Init/Cleanup:
*/
@@ -107,18 +147,30 @@ static const char *iommu_ports[] = {
"gfx3d1_user", "gfx3d1_priv",
};
-int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
- struct msm_gpu *gpu, const struct adreno_gpu_funcs *funcs,
- const char *ioname, const char *irqname, int ringsz)
+int msm_gpu_init(struct drm_device *drm, struct msm_gpu **pgpu)
{
+ struct msm_gpu *gpu = *pgpu;
int ret;
+ gpu = kzalloc(sizeof(*gpu), GFP_KERNEL);
+ if (!gpu)
+ return -ENOMEM;
+
gpu->dev = drm;
- gpu->funcs = funcs;
INIT_LIST_HEAD(&gpu->active_list);
INIT_WORK(&gpu->retire_work, retire_worker);
+ /* init GEM funcs for this device */
+ gpu->gem.priv = gpu;
+ gpu->gem.gem_new = gem_new;
+ gpu->gem.gem_get_iova = gem_get_iova;
+ gpu->gem.gem_get_iova_locked = gem_get_iova_locked;
+ gpu->gem.gem_put_iova = gem_put_iova;
+ gpu->gem.gem_vaddr = gem_vaddr;
+ gpu->gem.gem_vaddr_locked = gem_vaddr_locked;
+ gpu->gem.gem_retire = msm_gpu_retire;
+
/* Setup IOMMU.. eventually we will (I think) do this once per context
* and have separate page tables per context. For now, to keep things
* simple and to get something working, just use a single address space: