1 files changed, 1 insertions, 218 deletions

diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
index a319dc1f302b..f8152472ab91 100644
--- a/drivers/gpu/drm/msm/msm_gpu.c
+++ b/drivers/gpu/drm/msm/msm_gpu.c
@@ -20,189 +20,6 @@
 #include "adreno/adreno_gpu.h"
 
 /*
- * Power Management:
- */
-
-#ifdef CONFIG_MSM_BUS_SCALING
-#include <mach/board.h>
-#include <mach/kgsl.h>
-static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev)
-{
-	struct drm_device *dev = gpu->dev;
-	struct kgsl_device_platform_data *pdata = pdev->dev.platform_data;
-
-	if (!pdev) {
-		dev_err(dev->dev, "could not find dtv pdata\n");
-		return;
-	}
-
-	if (pdata->bus_scale_table) {
-		gpu->bsc = msm_bus_scale_register_client(pdata->bus_scale_table);
-		DBG("bus scale client: %08x", gpu->bsc);
-	}
-}
-
-static void bs_fini(struct msm_gpu *gpu)
-{
-	if (gpu->bsc) {
-		msm_bus_scale_unregister_client(gpu->bsc);
-		gpu->bsc = 0;
-	}
-}
-
-static void bs_set(struct msm_gpu *gpu, int idx)
-{
-	if (gpu->bsc) {
-		DBG("set bus scaling: %d", idx);
-		msm_bus_scale_client_update_request(gpu->bsc, idx);
-	}
-}
-#else
-static void bs_init(struct msm_gpu *gpu, struct platform_device *pdev) {}
-static void bs_fini(struct msm_gpu *gpu) {}
-static void bs_set(struct msm_gpu *gpu, int idx) {}
-#endif
-
-static int enable_pwrrail(struct msm_gpu *gpu)
-{
-	struct drm_device *dev = gpu->dev;
-	int ret = 0;
-
-	if (gpu->gpu_reg) {
-		ret = regulator_enable(gpu->gpu_reg);
-		if (ret) {
-			dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
-			return ret;
-		}
-	}
-
-	if (gpu->gpu_cx) {
-		ret = regulator_enable(gpu->gpu_cx);
-		if (ret) {
-			dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-static int disable_pwrrail(struct msm_gpu *gpu)
-{
-	if (gpu->gpu_cx)
-		regulator_disable(gpu->gpu_cx);
-	if (gpu->gpu_reg)
-		regulator_disable(gpu->gpu_reg);
-	return 0;
-}
-
-static int enable_clk(struct msm_gpu *gpu)
-{
-	struct clk *rate_clk = NULL;
-	int i;
-
-	/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
-	for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
-		if (gpu->grp_clks[i]) {
-			clk_prepare(gpu->grp_clks[i]);
-			rate_clk = gpu->grp_clks[i];
-		}
-	}
-
-	if (rate_clk && gpu->fast_rate)
-		clk_set_rate(rate_clk, gpu->fast_rate);
-
-	for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
-		if (gpu->grp_clks[i])
-			clk_enable(gpu->grp_clks[i]);
-
-	return 0;
-}
-
-static int disable_clk(struct msm_gpu *gpu)
-{
-	struct clk *rate_clk = NULL;
-	int i;
-
-	/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
-	for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
-		if (gpu->grp_clks[i]) {
-			clk_disable(gpu->grp_clks[i]);
-			rate_clk = gpu->grp_clks[i];
-		}
-	}
-
-	if (rate_clk && gpu->slow_rate)
-		clk_set_rate(rate_clk, gpu->slow_rate);
-
-	for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
-		if (gpu->grp_clks[i])
-			clk_unprepare(gpu->grp_clks[i]);
-
-	return 0;
-}
-
-static int enable_axi(struct msm_gpu *gpu)
-{
-	if (gpu->ebi1_clk)
-		clk_prepare_enable(gpu->ebi1_clk);
-	if (gpu->bus_freq)
-		bs_set(gpu, gpu->bus_freq);
-	return 0;
-}
-
-static int disable_axi(struct msm_gpu *gpu)
-{
-	if (gpu->ebi1_clk)
-		clk_disable_unprepare(gpu->ebi1_clk);
-	if (gpu->bus_freq)
-		bs_set(gpu, 0);
-	return 0;
-}
-
-int msm_gpu_pm_resume(struct adreno_gpu *gpu)
-{
-	int ret;
-
-	DBG("%s", adreno_get_name(gpu));
-
-	ret = enable_pwrrail(&gpu->base);
-	if (ret)
-		return ret;
-
-	ret = enable_clk(&gpu->base);
-	if (ret)
-		return ret;
-
-	ret = enable_axi(&gpu->base);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-int msm_gpu_pm_suspend(struct adreno_gpu *gpu)
-{
-	int ret;
-
-	DBG("%s", adreno_get_name(gpu));
-
-	ret = disable_axi(&gpu->base);
-	if (ret)
-		return ret;
-
-	ret = disable_clk(&gpu->base);
-	if (ret)
-		return ret;
-
-	ret = disable_pwrrail(&gpu->base);
-	if (ret)
-		return ret;
-
-	return 0;
-}
-
-/*
  * Cmdstream submission/retirement:
  */
 
@@ -285,15 +102,11 @@ int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
  * Init/Cleanup:
  */
 
-static const char *clk_names[] = {
-		"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",
-};
-
 int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 		struct msm_gpu *gpu, const struct adreno_gpu_funcs *funcs,
 		const char *ioname, const char *irqname, int ringsz)
 {
-	int i, ret;
+	int ret;
 
 	gpu->dev = drm;
 	gpu->funcs = funcs;
@@ -301,32 +114,6 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 	INIT_LIST_HEAD(&gpu->active_list);
 	INIT_WORK(&gpu->retire_work, retire_worker);
 
-	BUG_ON(ARRAY_SIZE(clk_names) != ARRAY_SIZE(gpu->grp_clks));
-
-	/* Acquire clocks: */
-	for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
-		gpu->grp_clks[i] = devm_clk_get(&pdev->dev, clk_names[i]);
-		DBG("grp_clks[%s]: %p", clk_names[i], gpu->grp_clks[i]);
-		if (IS_ERR(gpu->grp_clks[i]))
-			gpu->grp_clks[i] = NULL;
-	}
-
-	gpu->ebi1_clk = devm_clk_get(&pdev->dev, "bus_clk");
-	DBG("ebi1_clk: %p", gpu->ebi1_clk);
-	if (IS_ERR(gpu->ebi1_clk))
-		gpu->ebi1_clk = NULL;
-
-	/* Acquire regulators: */
-	gpu->gpu_reg = devm_regulator_get(&pdev->dev, "vdd");
-	DBG("gpu_reg: %p", gpu->gpu_reg);
-	if (IS_ERR(gpu->gpu_reg))
-		gpu->gpu_reg = NULL;
-
-	gpu->gpu_cx = devm_regulator_get(&pdev->dev, "vddcx");
-	DBG("gpu_cx: %p", gpu->gpu_cx);
-	if (IS_ERR(gpu->gpu_cx))
-		gpu->gpu_cx = NULL;
-
 	/* Setup IOMMU.. eventually we will (I think) do this once per context
 	 * and have separate page tables per context.  For now, to keep things
 	 * simple and to get something working, just use a single address space:
@@ -339,8 +126,6 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
 	}
 	gpu->id = msm_register_iommu(drm, gpu->iommu);
 
-	bs_init(gpu, pdev);
-
 	return 0;
 
 fail:
@@ -353,8 +138,6 @@ void msm_gpu_cleanup(struct msm_gpu *gpu)
 
 	WARN_ON(!list_empty(&gpu->active_list));
 
-	bs_fini(gpu);
-
 	if (gpu->iommu)
 		iommu_domain_free(gpu->iommu);
 }