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-rw-r--r--sound/soc/mediatek/common/mtk-afe-fe-dai.c22
-rw-r--r--sound/soc/mediatek/common/mtk-base-afe.h10
2 files changed, 27 insertions, 5 deletions
diff --git a/sound/soc/mediatek/common/mtk-afe-fe-dai.c b/sound/soc/mediatek/common/mtk-afe-fe-dai.c
index 3cb2adf420bb..baaa5881b1d4 100644
--- a/sound/soc/mediatek/common/mtk-afe-fe-dai.c
+++ b/sound/soc/mediatek/common/mtk-afe-fe-dai.c
@@ -139,7 +139,7 @@ int mtk_afe_fe_hw_params(struct snd_pcm_substream *substream,
substream->runtime->dma_area,
substream->runtime->dma_bytes);
- memset_io(substream->runtime->dma_area, 0,
+ memset_io((void __force __iomem *)substream->runtime->dma_area, 0,
substream->runtime->dma_bytes);
/* set addr */
@@ -433,11 +433,20 @@ int mtk_memif_set_addr(struct mtk_base_afe *afe, int id,
phys_buf_addr_upper_32);
}
- /* set MSB to 33-bit */
- if (memif->data->msb_reg >= 0)
+ /*
+ * set MSB to 33-bit, for memif address
+ * only for memif base address, if msb_end_reg exists
+ */
+ if (memif->data->msb_reg)
mtk_regmap_update_bits(afe->regmap, memif->data->msb_reg,
1, msb_at_bit33, memif->data->msb_shift);
+ /* set MSB to 33-bit, for memif end address */
+ if (memif->data->msb_end_reg)
+ mtk_regmap_update_bits(afe->regmap, memif->data->msb_end_reg,
+ 1, msb_at_bit33,
+ memif->data->msb_end_shift);
+
return 0;
}
EXPORT_SYMBOL_GPL(mtk_memif_set_addr);
@@ -464,6 +473,13 @@ int mtk_memif_set_channel(struct mtk_base_afe *afe,
else
mono = (channel == 1) ? 1 : 0;
+ /* for specific configuration of memif mono mode */
+ if (memif->data->int_odd_flag_reg)
+ mtk_regmap_update_bits(afe->regmap,
+ memif->data->int_odd_flag_reg,
+ 1, mono,
+ memif->data->int_odd_flag_shift);
+
return mtk_regmap_update_bits(afe->regmap, memif->data->mono_reg,
1, mono, memif->data->mono_shift);
}
diff --git a/sound/soc/mediatek/common/mtk-base-afe.h b/sound/soc/mediatek/common/mtk-base-afe.h
index a6f68c68581c..ef83e78c22a8 100644
--- a/sound/soc/mediatek/common/mtk-base-afe.h
+++ b/sound/soc/mediatek/common/mtk-base-afe.h
@@ -29,6 +29,8 @@ struct mtk_base_memif_data {
int quad_ch_reg;
int quad_ch_mask;
int quad_ch_shift;
+ int int_odd_flag_reg;
+ int int_odd_flag_shift;
int enable_reg;
int enable_shift;
int hd_reg;
@@ -37,10 +39,13 @@ struct mtk_base_memif_data {
int hd_align_mshift;
int msb_reg;
int msb_shift;
- int msb2_reg;
- int msb2_shift;
+ int msb_end_reg;
+ int msb_end_shift;
int agent_disable_reg;
int agent_disable_shift;
+ int ch_num_reg;
+ int ch_num_shift;
+ int ch_num_maskbit;
/* playback memif only */
int pbuf_reg;
int pbuf_mask;
@@ -62,6 +67,7 @@ struct mtk_base_irq_data {
int irq_en_shift;
int irq_clr_reg;
int irq_clr_shift;
+ int irq_status_shift;
};
struct device;