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* arm64: dts: qcom: sc7180: Update iommu property for simultaneous playbackV Sujith Kumar Reddy2021-04-191-1/+2
| | | | | | | | | | | Update iommu property in lpass cpu node for supporting simultaneous playback on headset and speaker. Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Link: https://lore.kernel.org/r/20210406163330.11996-1-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: pompom: Add "dmic_clk_en" + sound modelDouglas Anderson2021-04-191-0/+7
| | | | | | | | | | | | | | | | Match what's downstream for this board. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Cc: Ajit Pandey <ajitp@codeaurora.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Cc: Cheng-Yi Chiang <cychiang@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210315133924.v2.2.If218189eff613a6c48ba12d75fad992377d8f181@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: coachz: Add "dmic_clk_en"Douglas Anderson2021-04-192-13/+16
| | | | | | | | | | | | | | | | | | | This was present downstream. Add upstream too. NOTE: upstream I managed to get some sort of halfway state and got one pinctrl entry in the coachz-r1 device tree. Remove that as part of this since it's now in the dtsi. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Cc: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Cc: Ajit Pandey <ajitp@codeaurora.org> Cc: Judy Hsiao <judyhsiao@chromium.org> Cc: Cheng-Yi Chiang <cychiang@chromium.org> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210315133924.v2.1.I601a051cad7cfd0923e55b69ef7e5748910a6096@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: update usb qmp phy clock-cells propertyJonathan Marek2021-04-083-5/+6
| | | | | | | | | The top-level node doesn't provide any clocks, the subnode provides a single clock with of_clk_hw_simple_get. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20201123143705.14277-1-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8916: Add GICv2 hypervisor registers/interruptStephan Gerhold2021-04-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM Cortex-A53 CPU cores and QGIC2 interrupt controller (an implementation of the ARM GIC 2.0 specification) used in MSM8916 support virtualization, e.g. for KVM on Linux. However, so far it was not possible to make use of this functionality, because Qualcomm's proprietary "hyp" firmware blocks the EL2 mode of the CPU and only allows booting Linux in EL1. However, on devices without (firmware) secure boot there is no need to rely on all of Qualcomm's firmware. The "hyp" firmware on MSM8916 seems simple enough that it can be replaced with an open-source alternative created only based on trial and error - with some similar EL2/EL1 initialization code adapted from Linux and U-Boot. qhypstub [1] is such an open-source firmware for MSM8916 that can be used as drop-in replacement for Qualcomm's "hyp" firmware. It does not implement any hypervisor functionality. Instead, it allows booting Linux/KVM (or other hypervisors) in EL2. With Linux booting in EL2, KVM seems to be working just fine on MSM8916. However, so far it is not possible to make use of the virtualization features in the GICv2. To use KVM's VGICv2 code, the QGIC2 device tree node needs additional resources (according to binding documentation): - The CPU interface region (second reg) must be at least 8 KiB large to access the GICC_DIR register (mapped at 0x1000 offset) - Virtual control/CPU interface register base and size - Hypervisor maintenance interrupt Fortunately, the public APQ8016E TRM [2] provides the required information: - The CPU interface region (at 0x0B002000) actually has a size of 8 KiB - Virtual control/CPU interface register is at 0x0B001000/0x0B004000 - Hypervisor maintenance interrupt is "PPI #0" Note: This is a bit strange since almost all other ARM SoCs use GIC_PPI 9 for this. However, I have verified that this is indeed the interrupt that fires when bits are set in GICH_HCR. Add the additional resources to the QGIC2 device tree node in msm8916.dtsi. There is no functional difference when Linux is started in EL1 since the additional resources are ignored in that case. With these changes (and qhypstub), KVM seems to be fully working on the DragonBoard 410c (apq8016-sbc) and BQ Aquaris X5 (longcheer-l8910). [1]: https://github.com/msm8916-mainline/qhypstub [2]: https://developer.qualcomm.com/download/sd410/snapdragon-410e-technical-reference-manual.pdf Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20210407163648.4708-1-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sdm845-db845c: make firmware filenames follow linux-firmwareDmitry Baryshkov2021-04-061-2/+2
| | | | | | | | | Cange aDSP and cDSP firmware filenames to follow filenames merged into linux-firmware tree. Switch from split .mdt files to merged .mbn files. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210318201405.2244723-1-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845-xiaomi-beryllium: Add DSI and panel bitsSumit Semwal2021-04-051-0/+71
| | | | | | | | | | | | | Enabling the Display panel for beryllium requires DSI labibb regulators and panel dts nodes to be added. It is also required to keep some of the regulators as always-on. Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Link: https://lore.kernel.org/r/20210404194437.537011-1-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add Coresight supportSai Prakash Ranjan2021-04-051-0/+489
| | | | | | | | | | | | Add coresight components found on SC7280 SoC. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/de07324628f88900b72357f4ef7f0c7db7e3409d.1615832893.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add AOSS QMP nodeSai Prakash Ranjan2021-04-051-0/+14
| | | | | | | | Add a DT node for the AOSS QMP on SC7280 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/12f013a09989dbc3075bfb204653dc02d54ae8a1.1615832893.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add IPCC for SC7280 SoCSai Prakash Ranjan2021-04-051-0/+10
| | | | | | | | | | | | | Add the IPCC DT node which is used to send and receive IPC signals with remoteprocs for SC7280 SoC. Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Jassi Brar <jaswinder.singh@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/8374f407386209d2e7891763de3fa2450a14ad60.1615832893.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add device tree node for LLCCSai Prakash Ranjan2021-04-051-0/+7
| | | | | | | | | | | Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on SC7280 SoC. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/5bacaa8350e0d9553dccd623a15513590e795b47.1615832893.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Add support for OnePlus 5/5TJami Kettunen2021-04-054-0/+583
| | | | | | | | | | | | | | | | | | Add device trees for OnePlus 5 (cheeseburger) and 5T (dumpling) MSM8998 SoC smartphones with initial support included for: - UFS internal storage - USB peripheral mode - Display - Touch - Bluetooth - Hall effect sensor - Power and volume buttons - Capacitive keypad button backlight (on cheeseburger) Signed-off-by: Jami Kettunen <jamipkettunen@gmail.com> Link: https://lore.kernel.org/r/20210406010708.2376807-2-jamipkettunen@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8998: Disable MSS remoteproc by defaultJami Kettunen2021-04-053-0/+10
| | | | | | | | | This was already the case for ADSP and SLPI remoteprocs & doesn't affect existing boards where it has been re-enabled. Signed-off-by: Jami Kettunen <jamipkettunen@gmail.com> Link: https://lore.kernel.org/r/20210406010708.2376807-3-jamipkettunen@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Move rmtfs memory regionSujit Kautkar2021-04-042-3/+3
| | | | | | | | | | | Move rmtfs memory region so that it does not overlap with system RAM (kernel data) when KAsan is enabled. This puts rmtfs right after mba_mem which is not supposed to increase beyond 0x94600000 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Sujit Kautkar <sujitka@chromium.org> Link: https://lore.kernel.org/r/20210330014610.1451198-1-sujitka@chromium.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Add sound node for sc7180-trogdor-coachzSrinivasa Rao Mandadapu2021-04-041-0/+10
| | | | | | | | | | | | This is a trgodor variant, required to have sound node variable for coachz specific platform. Tested-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210314061054.19451-3-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180-trogdor: Add lpass dai link for I2S driverAjit Pandey2021-04-041-0/+58
| | | | | | | | | | | | | | | | | Add dai link for supporting lpass I2S driver, which is used for audio capture and playback. Add lpass-cpu node with pin controls and i2s primary and secondary dai-links. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ajit Pandey <ajitp@codeaurora.org> Signed-off-by: V Sujith Kumar Reddy <vsujithk@codeaurora.org> Signed-off-by: Srinivasa Rao Mandadapu <srivasam@codeaurora.org> Link: https://lore.kernel.org/r/20210314061054.19451-2-srivasam@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: use dp_phy to provide clocks to dispccDmitry Baryshkov2021-04-041-2/+2
| | | | | | | | | Plug dp_phy-provided clocks to display clock controller. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-8-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: switch usb1 qmp phy to USB3+DP modeDmitry Baryshkov2021-04-041-5/+18
| | | | | | | | | | USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree nodes accordingly. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210331151614.3810197-7-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: Add venus DT nodeBryan O'Donoghue2021-04-041-0/+59
| | | | | | | | | | | | | Add DT entries for the sm8250 venus encoder/decoder. Co-developed-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Jonathan Marek <jonathan@marek.ca> Co-developed-by: Dikshita Agarwal <dikshita@qti.qualcomm.com> Signed-off-by: Dikshita Agarwal <dikshita@qti.qualcomm.com> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210401174256.1810044-3-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: Add videocc DT nodejonathan@marek.ca2021-04-041-0/+14
| | | | | | | | | | This commit adds the videocc DTS node for sm8250. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210401174256.1810044-2-bryan.odonoghue@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: Add interconnectsVinod Koul2021-04-041-0/+78
| | | | | | | | Add interconnect nodes and add them for modem and cdsp nodes Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210401113252.3078466-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: Add support for PRNG EERobert Foss2021-04-041-0/+7
| | | | | | | | | | RNG (Random Number Generator) in SM8350 features PRNG EE (Execution Environment), hence add devicetree support for it. Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Robert Foss <robert.foss@linaro.org> Link: https://lore.kernel.org/r/20210401101536.1014560-1-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7280: Add RPMh regulators for sc7280-idpsatya priya2021-04-041-0/+212
| | | | | | | | | | | Add regulator devices for SC7280 as RPMh regulators. This ensures that consumers are able to modify the physical state of PMIC regulators. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: satya priya <skakit@codeaurora.org> Link: https://lore.kernel.org/r/1617192339-3760-4-git-send-email-skakit@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845: add required clocks on the gccDmitry Baryshkov2021-04-041-0/+12
| | | | | | | | | Specify input clocks to the SDM845's Global Clock Controller as required by the bindings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210402233944.273275-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: Add thermal zones and throttling supportRobert Foss2021-03-291-0/+826
| | | | | | | | | | | sm8350 has 29 thermal sensors split across two tsens controllers. Add the thermal zones to expose them and wireup the cpus to throttle their frequencies on crossing passive temperature thresholds. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210324124308.1265626-2-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8150: add i2c nodesCaleb Connolly2021-03-291-0/+521
| | | | | | | | | | Tested on the OnePlus 7 Pro (including DMA). Signed-off-by: Caleb Connolly <caleb@connolly.tech> Reviewed-by: Vinod Koul <vkoul@kernel.org> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@linaro.org> Link: https://lore.kernel.org/r/20210321174522.123036-3-caleb@connolly.tech Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8150: add other QUP nodes and iommusCaleb Connolly2021-03-291-0/+28
| | | | | | | | | | Add the first and third qupv3 nodes used to hook up peripherals on some devices, as well as the iommus properties for all of them. Signed-off-by: Caleb Connolly <caleb@connolly.tech> Link: https://lore.kernel.org/r/20210321174522.123036-2-caleb@connolly.tech Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: fix display nodesJonathan Marek2021-03-291-21/+6
| | | | | | | | | | | | | | | Apply these fixes to the newly added sm8250 display ndoes - Remove "notused" interconnect (which apparently was blindly copied from my old patches) - Use dispcc node example from dt-bindings, removing clocks which aren't documented or used by the driver and fixing the region size. Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes") Signed-off-by: Jonathan Marek <jonathan@marek.ca> [DB: compatibility changes split into separate patch] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210329120051.3401567-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: qrb5165-rb5: switch into using GPIO for SPI0 CSDmitry Baryshkov2021-03-181-2/+3
| | | | | | | | | | | | On the GENI SPI controller is is not very efficient if the chip select line is controlled by the QUP itself (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS") for the details). Configure SPI0 CS pin as a GPIO. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210210133458.1201066-5-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: add pinctrl for SPI using GPIO as a CSDmitry Baryshkov2021-03-181-0/+100
| | | | | | | | | | | | GENI SPI controller shows several issues if it manages the CS on its own (see 37dd4b777942 ("arm64: dts: qcom: sc7180: Provide pinconf for SPI to use GPIO for CS")) for the details. Provide pinctrl entries for SPI controllers using the same CS pin but in GPIO mode. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210210133458.1201066-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: further split of spi pinctrl configDmitry Baryshkov2021-03-182-81/+148
| | | | | | | | | | | Split "default" device tree nodes into common "data-clk" nodes and "cs" nodes which might differ from board to board depending on how the slave chips are wired. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210210133458.1201066-3-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: split spi pinctrl configDmitry Baryshkov2021-03-182-240/+66
| | | | | | | | | | | | As discussed on linux-arm-msm list, start splitting sm8250 pinctrl settings into generic and board-specific parts. The first part to receive such treatment is the spi, so split spi pinconf to the board device tree. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210210133458.1201066-2-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845-db845c: Enable ov8856 sensor and connect to ISPRobert Foss2021-03-161-2/+17
| | | | | | | | | Enable camss & ov8856 DT nodes. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Andrey Konovalov <andrey.konovalov@linaro.org> Link: https://lore.kernel.org/r/20210316171931.812748-23-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845-db845c: Configure regulators for camss nodeRobert Foss2021-03-161-0/+4
| | | | | | | | | Add regulator to camss device tree node. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Andrey Konovalov <andrey.konovalov@linaro.org> Link: https://lore.kernel.org/r/20210316171931.812748-22-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845: Add CAMSS ISP nodeRobert Foss2021-03-161-0/+135
| | | | | | | | | Add the camss dt node for sdm845. Signed-off-by: Robert Foss <robert.foss@linaro.org> Reviewed-by: Andrey Konovalov <andrey.konovalov@linaro.org> Link: https://lore.kernel.org/r/20210316171931.812748-21-robert.foss@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pm8150: Enable RTCBjorn Andersson2021-03-123-11/+1
| | | | | | | | | | | | The PM8150 comes with everything the RTC needs, so let's just leave it enabled instead of having to explicitly enable it for all boards. In effect this patch enables the RTC on the SM8150 MTP and the SM8250 HDK. Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20210106001004.4081508-1-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350-mtp: Add PMICsVinod Koul2021-03-121-0/+6
| | | | | | | | | SM8350-MTP features PM8350, PM8350B, PM8350C, PMK8350, PMR735A and PMR735B. PMICs Add the dtsi for these PMICs to MTP. Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-9-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pmr735B: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PMR735B along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-8-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pmr735a: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PMR735A along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-7-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pm8350c: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PM8350C along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-6-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pm8350b: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PM8350B along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-5-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pm8350: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PM8350 along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-4-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pmk8350: Add base dts fileVinod Koul2021-03-121-0/+25
| | | | | | | | Add base DTS file for PMK8350 along with GPIO node Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-3-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: Add spmi nodeVinod Koul2021-03-121-0/+18
| | | | | | | | Add SPMI node found in SM8350 SoC Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20210312052737.3558801-2-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: db845c: fix correct powerdown pin for WSA881xSrinivas Kandagatla2021-03-111-2/+2
| | | | | | | | | | | WSA881x powerdown pin is connected to GPIO1 not gpio2, so correct this. This was working so far due to a shift bug in gpio driver, however once that is fixed this will stop working, so fix this! Fixes: 89a32a4e769cc ("arm64: dts: qcom: db845c: add analog audio support") Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20210309102025.28405-1-srinivas.kandagatla@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Drop duplicate dp_hot_plug_det node in trogdorStephen Boyd2021-03-111-14/+0
| | | | | | | | | | | | | | | | | | | This moved from being trogdor specific to being part of the general sc7180.dtsi SoC file in commit 681a607ad21a ("arm64: dts: qcom: sc7180: Add DisplayPort HPD pin dt node"). Then we dropped the pinconf from the general sc7180.dtsi file in commit 8d079bf20410 ("arm64: dts: qcom: sc7180: Drop pinconf on dp_hot_plug_det") and added it back to the trogdor dts file in commit f772081f4883 ("arm64: dts: qcom: sc7180: Add "dp_hot_plug_det" pinconf for trogdor"). As part of this we managed to forget to drop the old copy in the trogdor dts. Let's do it now. Signed-off-by: Stephen Boyd <swboyd@chromium.org> [dianders: updated desc] Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20210311131008.1.I85fc8146c0ee47e261faa0c54dd621467b81952d@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'Shawn Guo2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC") Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-5-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: fix number of pins in 'gpio-ranges'Shawn Guo2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: 16951b490b20 ("arm64: dts: qcom: sm8250: Add TLMM pinctrl node") Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-4-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8150: fix number of pins in 'gpio-ranges'Shawn Guo2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: e13c6d144fa0 ("arm64: dts: qcom: sm8150: Add base dts file") Cc: Vinod Koul <vkoul@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-3-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845: fix number of pins in 'gpio-ranges'Shawn Guo2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | The last cell of 'gpio-ranges' should be number of GPIO pins, and in case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather than msm_pinctrl_soc_data.ngpio - 1. This fixes the problem that when the last GPIO pin in the range is configured with the following call sequence, it always fails with -EPROBE_DEFER. pinctrl_gpio_set_config() pinctrl_get_device_gpio_range() pinctrl_match_gpio_range() Fixes: bc2c806293c6 ("arm64: dts: qcom: sdm845: Add gpio-ranges to TLMM node") Cc: Evan Green <evgreen@chromium.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Link: https://lore.kernel.org/r/20210303033106.549-2-shawn.guo@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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