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* arm64: dts: qcom: Add Microsoft Lumia 950 (Talkman) device treeKonrad Dybcio2020-07-272-0/+40
| | | | | | | | | | | | | | | | | | | | | | Add device tree support for the Microsoft Lumia 950 smartphone. It is based on msm8992 and supports booting Linux via a custom EDK2 port. Currently it supports: * Screen console via EFIFB * Booting via EFI_STUB * SDHCI * I2C * PSCI core bringup Please note that there is an implementation of EL2 startup on this board, but it requires the user to resign from PSCI and use spin-table instead. This revision sticks with PSCI. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-14-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Add Xiaomi Libra (Mi 4C) device treeKonrad Dybcio2020-07-272-0/+365
| | | | | | | | | | | | | | | | This commit adds support for the Xiaomi Libra (Mi 4C) smartphone. It's based on the Qualcomm msm8992 SoC. It currently supports: * Screen console from bootloader * SDHCI * Regulator configuration * Serial console * I2C Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-13-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Add RPMCC nodeKonrad Dybcio2020-07-271-0/+5
| | | | | | | | This lets us use clocks provided by RPM. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-12-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Add PSCI support.Konrad Dybcio2020-07-271-0/+5
| | | | | | | | | This SoC's firmware does not fully support the PSCI spec, but it's good enough to bring the cores up. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-11-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Add PMU nodeKonrad Dybcio2020-07-271-0/+5
| | | | | | | | Add the PMU so we can get proper perf event support on this SoC. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-10-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Add BLSP2_UART2 and I2C nodesKonrad Dybcio2020-07-271-0/+153
| | | | | | | | | | | | Add support for I2C to enable support for peripherals such as touchscreens or sensors. Also add BLSP_UART2 interface. Please note that the naming scheme follows downstream and as abominable as it is, that's what we get. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-9-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Add SPMI PMIC arbiter deviceKonrad Dybcio2020-07-271-0/+16
| | | | | | | | | Add SPMI PMIC arbiter device to communicate with PMICs attached to SPMI bus. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-8-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Add a SCM nodeKonrad Dybcio2020-07-271-0/+6
| | | | | | Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Add a proper CPU mapKonrad Dybcio2020-07-271-7/+75
| | | | | | | | | This commit adds cpu nodes for all 6 cores present on this SoC and the cpu-map. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-6-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: bullhead: Move UART pinctrl to SoCKonrad Dybcio2020-07-271-9/+4
| | | | | | | | | | | This pinout is common for every 8992-based device and should therefore reside in the SoC device tree. Also convert addresses into phandles. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-5-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: bullhead: Add qcom,msm-idKonrad Dybcio2020-07-271-0/+1
| | | | | | | | | | | Add the property required for the bootloader to select the correct device tree blob. It has been removed from the SoC device tree as it should be set on a per-device basis. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Fix SDHCI1Konrad Dybcio2020-07-272-7/+15
| | | | | | | | | | | | | | | This commit ensures the correct IRQ type is set and disables the device by default. The mmc-hs400-1_8v property is also moved to Bullhead as it might not be present on all boards. The node has been renamed to sdhci@ instead of mmc@ and the phandle was changed to sdhc_1 to comply with the newer DTS style. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Modernize the DTS styleKonrad Dybcio2020-07-272-168/+168
| | | | | | | | | | | | | | | | | | Following changes have been made: - remove name, compatible and msm-id - wrap clocks in clocks{} - order nodes by name and by address - clock_gcc -> gcc - msmgpio -> tlmm - retire msm8992-pins.dtsi - add some of the missing pins - make comments C-style - make apcs a mailbox Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200625182118.131476-2-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Add support for Sony Xperia Z5 (SoMC Sumire-RoW)Konrad Dybcio2020-07-273-0/+249
| | | | | | | | | | | | | | | | | | | | Add device tree support for the Sony Xperia Z5 smartphone. It's based on Sony Kitakami platform (msm8994) and hence a Kitakami-common DTSI has been created so as to reduce clutter when remaining devices are added. The board currently supports * Serial * SDHCI * I2C * Regulator configuration * pstore log dump * GPIO keys Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-9-konradybcio@gmail.com [bjorn: Changed vendor identifier in board compatible from somc to sony] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Move msm8994-smd-rpm contents to lg-bullhead.Konrad Dybcio2020-07-273-315/+224
| | | | | | | | | | | | This was the only device using that dtsi, so no point keeping it separate AND with a confusing name (bullhead is based on msm8992 and the file contains regulator values for that specific board). Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-8-konradybcio@gmail.com [bjorn: Squashed with change that remove regulators from msm8992.dtsi] Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8994: Add support for SMD RPMKonrad Dybcio2020-07-271-0/+43
| | | | | | | | | Add support for SMD RPM, including pm8994 and pmi8994 regulators. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-7-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8992: Add a label to rpm-requestsKonrad Dybcio2020-07-271-1/+1
| | | | | | | | | This enables the node to be referenced directly from other DTs. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-4-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8994: Add SCM nodeKonrad Dybcio2020-07-271-0/+6
| | | | | | Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200624150107.76234-3-konradybcio@gmail.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845-db845c: Add hdmi bridge nodesBjorn Andersson2020-07-271-0/+118
| | | | | | | | | | | | Enable MDSS and DSI and add the LT9611 HDMI bridge. Also add the HDMI audio nodes. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Co-developed-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/20200727075532.1932134-1-vkoul@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: add sm8250 GPU nodesJonathan Marek2020-07-271-0/+142
| | | | | | | | This brings up the GPU. Tested on HDK865 by running vulkan CTS. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200709135251.643-15-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: add sm8150 GPU nodesJonathan Marek2020-07-271-0/+135
| | | | | | | | This brings up the GPU. Tested on HDK855 by running vulkan CTS. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Link: https://lore.kernel.org/r/20200709135251.643-14-jonathan@marek.ca Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Add opp-peak-kBps to GPU oppSharat Masetty2020-07-271-0/+7
| | | | | | | | | | | | Add opp-peak-kBps bindings to the GPU opp table, listing the peak GPU -> DDR bandwidth requirement for each opp level. This will be used to scale the DDR bandwidth along with the GPU frequency dynamically. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1594992579-20662-7-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Add interconnects property for GPUSharat Masetty2020-07-271-0/+3
| | | | | | | | | | This patch adds the interconnects property to the GPU node. This enables the GPU->DDR path bandwidth voting. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1594992579-20662-6-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: SDM845: Enable GPU DDR bw scalingSharat Masetty2020-07-271-0/+10
| | | | | | | | | | | | This patch adds the interconnects property for the gpu node and the opp-peak-kBps property to the opps of the gpu opp table. This should help enable DDR bandwidth scaling dynamically and proportionally to the GPU frequency. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org> Link: https://lore.kernel.org/r/1594992579-20662-5-git-send-email-akhilpo@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Add support for context losing replicatorSai Prakash Ranjan2020-07-271-0/+1
| | | | | | | | | | | Add "qcom,replicator-loses-context" property to the replicator in Always-on domain in SC7180 SoC to enable coresight replicator driver to handle this variation of replicator designs. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/5072d94849cfaee46748d26ac997212fb2d783c2.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Add iommus property to ETRSai Prakash Ranjan2020-07-271-0/+1
| | | | | | | | | | Define iommus property for Coresight ETR component in SC7180 SoC with the SID and mask to enable SMMU translation for this master. Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/2312c9a10e7251d69e31e4f51c0f1d70e6f2f2f5.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Add support to skip powering up of ETMSai Prakash Ranjan2020-07-271-0/+8
| | | | | | | | | | | | Add "qcom,skip-power-up" property to skip powering up ETM on SC7180 SoC to workaround a hardware errata where CPU watchdog counter is stopped when ETM power up bit is set (i.e., when TRCPDCR.PU = 1). Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/8c5ff297d8c89d9d451352f189baf26c8938842a.1591708204.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Add properties to qfprom for fuse blowingRavi Kumar Bokka2020-07-272-2/+12
| | | | | | | | | This patch adds properties to the qfprom node to enable fuse blowing. Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200710073439.v5.4.I70c17309f8b433e900656d7c53a2e6b61888bb68@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Add maximum speed property for DWC3 USB nodeSandeep Maheswaram2020-07-211-0/+1
| | | | | | | | | | Adding maximum speed property for DWC3 USB node which can be used for setting interconnect bandwidth. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1595317489-18432-3-git-send-email-sanm@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845: Support ETMv4 power managementSai Prakash Ranjan2020-07-211-0/+8
| | | | | | | | | | | Add "arm,coresight-loses-context-with-cpu" property to coresight ETM nodes to avoid failure of trace session because of losing context on entering deep idle states. Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Link: https://lore.kernel.org/r/20200721071343.2898-1-saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: pmi8998: Add nodes for LAB and IBB regulatorsNisha Kumari2020-07-181-0/+12
| | | | | | | | | | This patch adds devicetree nodes for LAB and IBB regulators. Signed-off-by: Nisha Kumari <nishakumari@codeaurora.org> [sumits: Updated for better compatible strings and names] Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org> Link: https://lore.kernel.org/r/20200622124110.20971-4-sumit.semwal@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sc7180: Add DSI and MDP OPP tables and power-domainsRajendra Nayak2020-07-171-0/+49
| | | | | | | | | | | Add the OPP tables for DSI and MDP based on the perf state/clk requirements, and add the power-domains property to specify the scalable power domain. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1594292674-15632-5-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sdm845: Add DSI and MDP OPP tables and power-domainsRajendra Nayak2020-07-171-0/+59
| | | | | | | | | | | | Add the OPP tables for DSI and MDP based on the perf state/clk requirements, and add the power-domains property to specify the scalable power domain. Tested-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Link: https://lore.kernel.org/r/1594292674-15632-4-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Move the fixed-perm property to SoC dtsiSibi Sankar2020-07-162-1/+1
| | | | | | | | | | | | All the platforms using SC7180 SoC are expected to have the wlan firmware memory statically mapped by the Trusted Firmware. Hence move back the qcom,msa-fixed-perm property to the SoC dtsi. Reviewed-by: Douglas Anderson <dianders@chromium.org> Fixes: 7d484566087c0 ("arm64: dts: qcom: sc7180: Add missing properties for Wifi node") Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200716191746.23196-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8916-samsung-a2015: Add accelerometer/magnetometerStephan Gerhold2020-07-153-0/+39
| | | | | | | | | | | | | | | | | A3U/A5U both use a Bosch BMC150 accelerometer/magnetometer combo. The chip provides two separate I2C devices for the accelerometer and magnetometer that are already supported by the bmc150-accel and bmc150-magn driver. The only difference between A3U/A5U is the way the sensor is mounted on the mainboard - set the mount-matrix in the device-specific device tree part to handle that difference. Co-developed-by: Michael Srba <michael.srba@seznam.cz> Signed-off-by: Michael Srba <michael.srba@seznam.cz> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200622151751.408995-5-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8916: Use higher I2C drive-strength only on DB410cStephan Gerhold2020-07-152-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | Commit c240f29e75e6 ("arm64: dts: set the default i2c pin drive strength to 16mA") changed the default drive-strength for I2C pins in msm8916-pins.dtsi to the maximum possible (16 mA). While this makes sense for apq8016-sbc (DB410c) where you can connect an arbitrary amount of I2C devices with level shifters etc, there is no need to use a higher drive strength for other MSM8916 devices. The minimum drive strength (2 mA) seems to be totally sufficient to have everything work there. With the short pinctrl nodes introduced earlier we can easily override the drive-strength only for apq8016-sbc now. Use that and change the default back to 2 mA. i2c1_default/i2c5_default are already using 2 mA because they were added separately later and are not used in apq8016-sbc. Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200622151751.408995-4-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: msm8916: Simplify pinctrl configurationStephan Gerhold2020-07-156-745/+426
| | | | | | | | | | | | | | | So far we have been separating pinctrl entries into pinmux/pinconf. It turns out it is also possible to combine them: The advantage is that the device tree is overall more concise because the "pins" to configure just need to be specified once, not separately for pinmux/pinconf. Using the simpler form only for new entries would be rather confusing. This commit makes all MSM8916 device trees use the simplfied form. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200622151751.408995-3-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: msm8916-samsung/longcheer: Move pinctrl/regulators to end of fileStephan Gerhold2020-07-152-104/+104
| | | | | | | | | | | | | It is helpful to be able to see all hardware components in one part of the device tree, without having to scroll over the large amount of regulator/pinctrl nodes. Keep those separated at the end of the file to make navigation a bit easier. This also makes it consistent with the order used in apq8016-sbc.dtsi. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200622151751.408995-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sm8250: Drop tcsr_mutex sysconBjorn Andersson2020-07-151-8/+3
| | | | | | | | | | Now that we don't need the intermediate syscon to represent the TCSR mutexes, update the dts to describe the TCSR mutex directly under /soc. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20200622075956.171058-5-bjorn.andersson@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Add missing properties for Wifi nodeRakesh Pillai2020-07-151-0/+3
| | | | | | | | | | | | | | | | | The wlan firmware memory is statically mapped in the Trusted Firmware, hence the wlan driver does not need to map/unmap this region dynamically. Hence add the property to indicate the wlan driver to not map/unamp the firmware memory region dynamically. Also add the chain1 voltage supply for wlan. Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org> Link: https://lore.kernel.org/r/1594615586-17055-1-git-send-email-pillair@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: Fix WiFi supplies on sc7180-idpDouglas Anderson2020-07-151-4/+4
| | | | | | | | | | | | | | | | | | | | The WiFi supplies that were added recently can't have done anything useful because they were missing the "-supply" suffix. Booting without the "-supply" suffix would give these messages: ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-0.8-cx-mx not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-1.8-xo not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-1.3-rfa not found, using dummy regulator ath10k_snoc 18800000.wifi: 18800000.wifi supply vdd-3.3-ch0 not found, using dummy regulator Let's add the "-supply" suffix. Tested-by: Rakesh Pillai <pillair@codeaurora.org> Reviewed-by: Rakesh Pillai <pillair@codeaurora.org> Fixes: 1e7594a38f37 ("arm64: dts: qcom: sc7180: Add WCN3990 WLAN module device node") Signed-off-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20200625131658.REPOST.1.I32960cd32bb84d6db4127c906d7e371fa29caebf@changeid Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sdm845: add Inline Crypto Engine registers and clockEric Biggers2020-07-141-4/+9
| | | | | | | | | | | | | | | | Add the vendor-specific registers and clock for Qualcomm ICE (Inline Crypto Engine) to the device tree node for the UFS host controller on sdm845, so that the ufs-qcom driver will be able to use inline crypto. Use a separate register range rather than extending the main UFS range because there's a gap between the two, and the ICE registers are vendor-specific. (Actually, the hardware claims that the ICE range also includes the array of standard crypto configuration registers; however, on this SoC the Linux kernel isn't permitted to access them directly.) Signed-off-by: Eric Biggers <ebiggers@google.com> Link: https://lore.kernel.org/r/20200710072013.177481-4-ebiggers@kernel.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sc7180: Add sdhc opps and power-domainsRajendra Nayak2020-07-131-0/+32
| | | | | | | | | | Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sc7180. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1593506712-24557-5-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sdm845: Add sdhc opps and power-domainsRajendra Nayak2020-07-131-0/+26
| | | | | | | | | | Add the power domain supporting performance state and the corresponding OPP tables for the sdhc device on sdm845. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1593506712-24557-4-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sc7180: Add OPP table for all qup devicesRajendra Nayak2020-07-131-0/+59
| | | | | | | | | | | | qup has a requirement to vote on the performance state of the CX domain in sc7180 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1593506712-24557-3-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sdm845: Add OPP table for all qup devicesRajendra Nayak2020-07-131-0/+83
| | | | | | | | | | | | | qup has a requirement to vote on the performance state of the CX domain in sdm845 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/1593506712-24557-2-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sc7180: Add qspi opps and power-domainsRajendra Nayak2020-07-131-0/+21
| | | | | | | | | | Add the power domain supporting performance state and the corresponding OPP tables for the qspi device on sc7180 Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1593769293-6354-4-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: sdm845: Add qspi opps and power-domainsRajendra Nayak2020-07-131-0/+26
| | | | | | | | | | Add the power domain supporting performance state and the corresponding OPP tables for the qspi device on sdm845 Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Link: https://lore.kernel.org/r/1593769293-6354-3-git-send-email-rnayak@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sdm845: Add cpu OPP tablesSibi Sankar2020-07-091-0/+285
| | | | | | | | | Add OPP tables required to scale DDR/L3 per freq-domain on SDM845 SoCs. Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200702204643.25785-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
* arm64: dts: qcom: sc7180: Drop the unused non-MSA SIDSibi Sankar2020-07-082-2/+2
| | | | | | | | | | | | | | | | | | | | Having a non-MSA (Modem Self-Authentication) SID bypassed breaks modem sandboxing i.e if a transaction were to originate from it, the hardware memory protections units (XPUs) would fail to flag them (any transaction originating from modem are historically termed as an MSA transaction). Drop the unused non-MSA modem SID on SC7180 SoCs and cheza so that SMMU continues to block them. Tested-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Reviewed-by: Douglas Anderson <dianders@chromium.org> Fixes: bec71ba243e95 ("arm64: dts: qcom: sc7180: Update Q6V5 MSS node") Fixes: 68aee4af5f620 ("arm64: dts: qcom: sdm845-cheza: Add iommus property") Cc: stable@vger.kernel.org Reported-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Link: https://lore.kernel.org/r/20200630081938.8131-1-sibis@codeaurora.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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