path: root/arch/avr32/mm/tlb.c
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* MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itselfRussell King2010-02-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: Stephen Rothwell <> Acked-by: Benjamin Herrenschmidt <> Signed-off-by: Russell King <>
* avr32: Clean up and optimize the TLB operationsHaavard Skinnemoen2008-07-021-88/+87
| | | | | | | | | | | | | | | | | | | This and the following patches aim to optimize the code dealing with page tables and TLB operations. Each patch reduces the time it takes to gzip a 16 MB file slightly, but I expect things like fork() and mmap() will improve somewhat more. This patch deals with the low-level TLB operations: * Remove unused _TLBEHI_I define * Use gcc builtins instead of inline assembly * Remove a few unnecessary pipeline flushes and nops * Introduce NR_TLB_ENTRIES define and use it instead of hardcoding it to 32 a few places throughout the code. * Use sysreg bitops instead of hardcoded shifts and masks * Make a few needlessly global functions static Signed-off-by: Haavard Skinnemoen <>
* avr32: proc: use non-racy method for /proc/tlb creationDenis V. Lunev2008-04-291-5/+1
| | | | | | | | | | | | Use proc_create() to make sure that ->proc_fops be setup before gluing PDE to main tree. Signed-off-by: Denis V. Lunev <> Cc: Haavard Skinnemoen <> Cc: Alexey Dobriyan <> Cc: "Eric W. Biederman" <> Signed-off-by: Andrew Morton <> Signed-off-by: Linus Torvalds <>
* [AVR32] constify function pointer tablesJan Engelhardt2008-01-251-1/+1
| | | | | Signed-off-by: Jan Engelhardt <> Signed-off-by: Haavard Skinnemoen <>
* [PATCH] mark struct file_operations const 2Arjan van de Ven2007-02-121-1/+1
| | | | | | | | | | | | Many struct file_operations in the kernel can be "const". Marking them const moves these to the .rodata section, which avoids false sharing with potential dirty data. In addition it'll catch accidental writes at compile time to these shared resources. [ sparc64 fix] Signed-off-by: Arjan van de Ven <> Signed-off-by: Andrew Morton <> Signed-off-by: Linus Torvalds <>
* [PATCH] AVR32: Use unsigned long flags for saving interrupt stateHaavard Skinnemoen2006-09-271-2/+4
| | | | | | Signed-off-by: Haavard Skinnemoen <> Signed-off-by: Andrew Morton <> Signed-off-by: Linus Torvalds <>
* [PATCH] avr32 architectureHaavard Skinnemoen2006-09-261-0/+378
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from Information about the AT32STK1000 development board can be found at including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [ Fix more pxx_page macro locations] [ fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <> Signed-off-by: Adrian Bunk <> Signed-off-by: Dave McCracken <> Signed-off-by: Andrew Morton <> Signed-off-by: Linus Torvalds <>