From ee4d9dc4e5bb841f7b3f681342b6d76b1c0037af Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Thu, 30 Apr 2020 12:46:17 +0000 Subject: arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core According to the documents, the i.MX8M-Mini features a GC320 and a GCNanoUltra GPU core. Etnaviv detects them as: etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 This seems to work fine more or less without any changes to the HWDB, which still might be needed in the future to correct some features, etc. [lst]: Added power domains and switched clock assignments to the new clock defines used for the composite clocks, instead of relying on the backwards compat defines. Signed-off-by: Frieder Schrempf Signed-off-by: Lucas Stach --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d8c53ffb5fff..6009e54266f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1139,6 +1139,37 @@ status = "disabled"; }; + gpu_3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + clock-names = "reg", "bus", "core", "shader"; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; + power-domains = <&pgc_gpu>; + }; + + gpu_2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU2D_ROOT>; + clock-names = "reg", "bus", "core"; + assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; + power-domains = <&pgc_gpu>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ -- cgit v1.2.3