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/*
* Copyright (C) 2013 Pengutronix
* Author: Lucas Stach <l.stach@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <adreno/a3xx_gpu.h>
/*
* Power Management:
*/
#ifdef CONFIG_MSM_BUS_SCALING
#include <mach/board.h>
#include <mach/kgsl.h>
void a3xx_bs_init(struct a3xx_gpu *gpu, struct platform_device *pdev)
{
struct drm_device *dev = gpu->dev;
struct kgsl_device_platform_data *pdata = pdev->dev.platform_data;
if (!pdev) {
dev_err(dev->dev, "could not find dtv pdata\n");
return;
}
if (pdata->bus_scale_table) {
gpu->bsc = msm_bus_scale_register_client(pdata->bus_scale_table);
DBG("bus scale client: %08x", gpu->bsc);
}
}
void a3xx_bs_fini(struct a3xx_gpu *gpu)
{
if (gpu->bsc) {
msm_bus_scale_unregister_client(gpu->bsc);
gpu->bsc = 0;
}
}
static void a3xx_bs_set(struct a3xx_gpu *gpu, int idx)
{
if (gpu->bsc) {
DBG("set bus scaling: %d", idx);
msm_bus_scale_client_update_request(gpu->bsc, idx);
}
}
#else
void a3xx_bs_init(struct a3xx_gpu *gpu, struct platform_device *pdev) {}
void a3xx_bs_fini(struct a3xx_gpu *gpu) {}
static void a3xx_bs_set(struct a3xx_gpu *gpu, int idx) {}
#endif
static int enable_pwrrail(struct a3xx_gpu *gpu)
{
struct drm_device *dev = gpu->base.drm;
int ret = 0;
if (gpu->gpu_reg) {
ret = regulator_enable(gpu->gpu_reg);
if (ret) {
dev_err(dev->dev, "failed to enable 'gpu_reg': %d\n", ret);
return ret;
}
}
if (gpu->gpu_cx) {
ret = regulator_enable(gpu->gpu_cx);
if (ret) {
dev_err(dev->dev, "failed to enable 'gpu_cx': %d\n", ret);
return ret;
}
}
return 0;
}
static int disable_pwrrail(struct a3xx_gpu *gpu)
{
if (gpu->gpu_cx)
regulator_disable(gpu->gpu_cx);
if (gpu->gpu_reg)
regulator_disable(gpu->gpu_reg);
return 0;
}
static int enable_clk(struct a3xx_gpu *gpu)
{
struct clk *rate_clk = NULL;
int i;
/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
if (gpu->grp_clks[i]) {
clk_prepare(gpu->grp_clks[i]);
rate_clk = gpu->grp_clks[i];
}
}
if (rate_clk && gpu->fast_rate)
clk_set_rate(rate_clk, gpu->fast_rate);
for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
if (gpu->grp_clks[i])
clk_enable(gpu->grp_clks[i]);
return 0;
}
static int disable_clk(struct a3xx_gpu *gpu)
{
struct clk *rate_clk = NULL;
int i;
/* NOTE: kgsl_pwrctrl_clk() ignores grp_clks[0].. */
for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--) {
if (gpu->grp_clks[i]) {
clk_disable(gpu->grp_clks[i]);
rate_clk = gpu->grp_clks[i];
}
}
if (rate_clk && gpu->slow_rate)
clk_set_rate(rate_clk, gpu->slow_rate);
for (i = ARRAY_SIZE(gpu->grp_clks) - 1; i > 0; i--)
if (gpu->grp_clks[i])
clk_unprepare(gpu->grp_clks[i]);
return 0;
}
static int enable_axi(struct a3xx_gpu *gpu)
{
if (gpu->ebi1_clk)
clk_prepare_enable(gpu->ebi1_clk);
if (gpu->bus_freq)
a3xx_bs_set(gpu, gpu->bus_freq);
return 0;
}
static int disable_axi(struct a3xx_gpu *gpu)
{
if (gpu->ebi1_clk)
clk_disable_unprepare(gpu->ebi1_clk);
if (gpu->bus_freq)
a3xx_bs_set(gpu, 0);
return 0;
}
int a3xx_gpu_pm_resume(struct adreno_gpu *gpu)
{
struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(gpu);
int ret;
DBG("%s", adreno_get_name(gpu));
ret = enable_pwrrail(a3xx_gpu);
if (ret)
return ret;
ret = enable_clk(a3xx_gpu);
if (ret)
return ret;
ret = enable_axi(a3xx_gpu);
if (ret)
return ret;
return 0;
}
int a3xx_gpu_pm_suspend(struct adreno_gpu *gpu)
{
struct a3xx_gpu *a3xx_gpu = to_a3xx_gpu(gpu);
int ret;
DBG("%s", adreno_get_name(gpu));
ret = disable_axi(a3xx_gpu);
if (ret)
return ret;
ret = disable_clk(a3xx_gpu);
if (ret)
return ret;
ret = disable_pwrrail(a3xx_gpu);
if (ret)
return ret;
return 0;
}
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