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/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MSM_GPU_H__
#define __MSM_GPU_H__

#include <linux/clk.h>
#include <linux/regulator/consumer.h>

#include "msm_drv.h"

/* So far, with hardware that I've seen to date, we can have:
 *  + zero, one, or two z180 2d cores
 *  + a3xx or a2xx 3d core, which share a common CP (the firmware
 *    for the CP seems to implement some different PM4 packet types
 *    but the basics of cmdstream submission are the same)
 *
 * Which means that the eventual complete "class" hierarchy, once
 * support for all past and present hw is in place, becomes:
 *  + msm_gpu
 *    + adreno_gpu
 *      + a3xx_gpu
 *      + a2xx_gpu
 *    + z180_gpu
 */

struct msm_gpu {
	struct drm_device *dev;
	struct adreno_gpu *gpu;
	const struct adreno_gpu_funcs *funcs;

	/* list of GEM active objects: */
	struct list_head active_list;

	/* worker for handling active-list retiring: */
	struct work_struct retire_work;

	void __iomem *mmio;
	int irq;

	struct iommu_domain *iommu;
	int id;

	/* Power Control: */
	struct regulator *gpu_reg, *gpu_cx;
	struct clk *ebi1_clk, *grp_clks[5];
	uint32_t fast_rate, slow_rate, bus_freq;
	uint32_t bsc;
};

int msm_gpu_pm_suspend(struct adreno_gpu *gpu);
int msm_gpu_pm_resume(struct adreno_gpu *gpu);

void msm_gpu_retire(struct msm_gpu *gpu);
struct msm_gem_submit;
int msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
		struct msm_file_private *ctx);

int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
		struct msm_gpu *gpu, const struct adreno_gpu_funcs *funcs,
		const char *ioname, const char *irqname, int ringsz);
void msm_gpu_cleanup(struct msm_gpu *gpu);

struct msm_gpu *a3xx_gpu_init(struct drm_device *dev,
		struct adreno_gem *gem, struct workqueue_struct *wq,
		int reglog);
void __init a3xx_register(void);
void __exit a3xx_unregister(void);

#endif /* __MSM_GPU_H__ */