HACK: etna: resolve from MULTI_TILED to TILED

Extremely unclean, but works for me. Don't ever show to
anyone. CLEAN THIS UP PROPERLY!

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

2 files changed, 76 insertions, 3 deletions

diff --git a/src/gallium/drivers/etna/etna_pipe.c b/src/gallium/drivers/etna/etna_pipe.c
index e51574326a..5104d6b478 100644
--- a/src/gallium/drivers/etna/etna_pipe.c
+++ b/src/gallium/drivers/etna/etna_pipe.c
@@ -40,6 +40,7 @@
 #include "etna_rasterizer.h"
 #include "etna_resource.h"
 #include "etna_shader.h"
+#include "etna_screen.h"
 #include "etna_surface.h"
 #include "etna_texture.h"
 #include "etna_transfer.h"
@@ -862,6 +863,56 @@ static void etna_pipe_destroy(struct pipe_context *pipe)
 /** Main draw function. Draw primitives from a vertex buffer object,
  * using optonally an index buffer.
  */
+
+static void do_resolve(struct etna_pipe_context *context)
+{
+   struct etna_surface *cbuf = etna_surface(context->framebuffer_s.cbufs[0]);
+   struct etna_resource *res = etna_resource(cbuf->base.texture);
+   struct etna_pipe_context *ectx = res->last_ctx;
+   int shadow_size;
+
+   if(context->framebuffer_s.nr_cbufs > 0 && cbuf->shadow) {
+      etna_set_state(context->ctx, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR);
+      etna_stall(context->ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
+
+#if 0
+   /* Set up color TS to source surface before blit, if needed */
+   uint32_t ts_mem_config = 0;
+   if(res->levels[0].ts_size) {
+      debug_printf("ts_size\n");
+      etna_set_state_multi(ectx->ctx, VIVS_TS_MEM_CONFIG, 4, (uint32_t[]) {
+      ectx->gpu3d.TS_MEM_CONFIG = VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | ts_mem_config,
+      ectx->gpu3d.TS_COLOR_STATUS_BASE = etna_bo_gpu_address(res->ts_bo) + res->levels[0].ts_offset,
+      ectx->gpu3d.TS_COLOR_SURFACE_BASE = etna_bo_gpu_address(res->bo) + res->levels[0].offset,
+      ectx->gpu3d.TS_COLOR_CLEAR_VALUE = res->levels[0].clear_value
+      });
+   }
+
+   ectx->dirty_bits |= ETNA_STATE_TS;
+#endif
+      shadow_size = util_format_get_nblocksy(cbuf->base.format, cbuf->level->padded_height) * util_format_get_stride(cbuf->base.format, cbuf->level->padded_width);
+      struct compiled_rs_state copy_to_screen;
+         etna_compile_rs_state(context->ctx, &copy_to_screen, &(struct rs_state){
+            .source_format = translate_rt_format(cbuf->shadow_format, false),
+            .source_tiling = cbuf->shadow_layout,
+            .source_addr[0] = etna_bo_gpu_address(cbuf->shadow),
+            .source_addr[1] =  etna_bo_gpu_address(cbuf->shadow) + shadow_size /2,
+            .source_stride = util_format_get_stride(cbuf->base.format, cbuf->level->padded_width),
+            .dest_format = translate_rt_format(cbuf->base.format, false),
+            .dest_tiling = cbuf->layout,
+            .dest_addr[0] = res->pipe_addr[0],
+            .dest_stride = util_format_get_stride(cbuf->base.format, cbuf->level->padded_width),
+            .downsample_x = 0,
+            .downsample_y = 0,
+            .swap_rb = 0,
+            .dither = {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
+            .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_DISABLED,
+            .width = cbuf->level->padded_width,
+            .height = cbuf->level->padded_height
+         });
+      etna_submit_rs_state(context->ctx, &copy_to_screen);
+   }
+}
 static void etna_pipe_draw_vbo(struct pipe_context *pipe,
                  const struct pipe_draw_info *info)
 {
@@ -895,6 +946,8 @@ static void etna_pipe_draw_vbo(struct pipe_context *pipe,
     {
         pipe->flush(pipe, NULL, 0);
     }
+
+    do_resolve(priv);
 }
 
 /** Create vertex element states, which define a layout for fetching
@@ -1017,9 +1070,11 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
                               const struct pipe_framebuffer_state *sv)
 {
     struct etna_pipe_context *priv = etna_pipe_context(pipe);
+    struct etna_screen *screen = etna_screen(pipe->screen);
     struct compiled_framebuffer_state *cs = &priv->framebuffer;
     int nr_samples_color = -1;
     int nr_samples_depth = -1;
+    int shadow_size;
 
     /* Set up TS as well. Warning: this state is used by both the RS and PE */
     uint32_t ts_mem_config = 0;
@@ -1051,8 +1106,22 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
         }
         else if (priv->ctx->conn->chip.pixel_pipes == 2)
         {
-            cs->PE_PIPE_COLOR_ADDR[0] = res->pipe_addr[0];
-            cs->PE_PIPE_COLOR_ADDR[1] = res->pipe_addr[1];
+           if (color_supertiled) {
+              cs->PE_PIPE_COLOR_ADDR[0] = res->pipe_addr[0];
+              cs->PE_PIPE_COLOR_ADDR[1] = res->pipe_addr[1];
+              cs->TS_COLOR_SURFACE_BASE = res->pipe_addr[0];
+           } else {
+              /* need a shadow buffer to resolve MULTI_TILED */
+              debug_printf("set shadow RT\n");
+              shadow_size = util_format_get_nblocksy(cbuf->base.format, cbuf->level->padded_height) * util_format_get_stride(cbuf->base.format, cbuf->level->padded_width);
+              cbuf->shadow = etna_bo_new(screen->dev, shadow_size, DRM_ETNA_GEM_TYPE_RT);
+              cbuf->shadow_layout = ETNA_LAYOUT_MULTI_TILED;
+              cbuf->shadow_format = cbuf->base.format;
+
+              cs->PE_PIPE_COLOR_ADDR[0] = etna_bo_gpu_address(cbuf->shadow);
+              cs->PE_PIPE_COLOR_ADDR[1] = etna_bo_gpu_address(cbuf->shadow) + shadow_size / 2;
+              cs->TS_COLOR_SURFACE_BASE = etna_bo_gpu_address(cbuf->shadow);
+           }
         }
         cs->PE_COLOR_STRIDE = cbuf->surf.stride;
         if(cbuf->surf.ts_size)
@@ -1061,7 +1130,6 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
             ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
             cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
             cs->TS_COLOR_STATUS_BASE = etna_bo_gpu_address(ts_bo) + cbuf->surf.ts_offset;
-            cs->TS_COLOR_SURFACE_BASE = res->pipe_addr[0];
         }
         /* MSAA */
         if(cbuf->base.texture->nr_samples > 1)
diff --git a/src/gallium/drivers/etna/etna_pipe.h b/src/gallium/drivers/etna/etna_pipe.h
index c9d59b1477..fb5769c1fd 100644
--- a/src/gallium/drivers/etna/etna_pipe.h
+++ b/src/gallium/drivers/etna/etna_pipe.h
@@ -100,6 +100,11 @@ struct etna_surface
     struct compiled_rs_state clear_command;
     /* Keep pointer to resource level, for fast clear */
     struct etna_resource_level *level;
+
+    bool needs_resolve;
+    struct etna_bo *shadow;
+    enum etna_surface_layout shadow_layout;
+    enum pipe_format shadow_format;
 };
 
 struct etna_sampler_view