sync etna driver to c209f5c

9 files changed, 65 insertions, 77 deletions

diff --git a/src/gallium/drivers/etna/etna_clear_blit.c b/src/gallium/drivers/etna/etna_clear_blit.c
index fe356ba731..13a1d9b9c2 100644
--- a/src/gallium/drivers/etna/etna_clear_blit.c
+++ b/src/gallium/drivers/etna/etna_clear_blit.c
@@ -77,10 +77,11 @@ void etna_rs_gen_clear_surface(struct compiled_rs_state *rs_state, struct etna_s
     /* use tiled clear if width is multiple of 16 */
     bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
                        (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
+    struct etna_bo *dest_bo = etna_resource(surf->base.texture)->bo;
     etna_compile_rs_state(rs_state, &(struct rs_state){
             .source_format = format,
             .dest_format = format,
-            .dest_addr = surf->surf.address,
+            .dest_addr = etna_bo_gpu_address(dest_bo) + surf->surf.offset,
             .dest_stride = surf->surf.stride,
             .dest_tiling = tiled_clear ? surf->layout : ETNA_LAYOUT_LINEAR,
             .dither = {0xffffffff, 0xffffffff},
@@ -111,13 +112,13 @@ static void etna_pipe_clear(struct pipe_context *pipe,
     if((buffers & PIPE_CLEAR_COLOR) && priv->framebuffer_s.nr_cbufs)
     {
         struct etna_surface *surf = etna_surface(priv->framebuffer_s.cbufs[0]);
-        if(surf->surf.ts_address)
+        if(surf->surf.ts_size)
             need_ts_flush = true;
     }
     if((buffers & PIPE_CLEAR_DEPTHSTENCIL) && priv->framebuffer_s.zsbuf != NULL)
     {
         struct etna_surface *surf = etna_surface(priv->framebuffer_s.zsbuf);
-        if(surf->surf.ts_address)
+        if(surf->surf.ts_size)
             need_ts_flush = true;
     }
     if(need_ts_flush)
@@ -133,7 +134,7 @@ static void etna_pipe_clear(struct pipe_context *pipe,
         {
             struct etna_surface *surf = etna_surface(priv->framebuffer_s.cbufs[idx]);
             uint32_t new_clear_value = translate_clear_color(surf->base.format, &color[idx]);
-            if(surf->surf.ts_address) /* TS: use precompiled clear command */
+            if(surf->surf.ts_size) /* TS: use precompiled clear command */
             {
                 /* Set new clear color */
                 priv->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
@@ -158,7 +159,7 @@ static void etna_pipe_clear(struct pipe_context *pipe,
     {
         struct etna_surface *surf = etna_surface(priv->framebuffer_s.zsbuf);
         uint32_t new_clear_value = translate_clear_depth_stencil(surf->base.format, depth, stencil);
-        if(surf->surf.ts_address) /* TS: use precompiled clear command */
+        if(surf->surf.ts_size) /* TS: use precompiled clear command */
         {
             /* Set new clear depth value */
             priv->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value;
diff --git a/src/gallium/drivers/etna/etna_internal.h b/src/gallium/drivers/etna/etna_internal.h
index 643914fc5a..e4b2ef249c 100644
--- a/src/gallium/drivers/etna/etna_internal.h
+++ b/src/gallium/drivers/etna/etna_internal.h
@@ -238,7 +238,6 @@ struct compiled_vertex_elements_state
 /* Compiled context->set_vertex_buffer result */
 struct compiled_set_vertex_buffer
 {
-    void *logical; /* CPU address of vertex buffer base */
     uint32_t FE_VERTEX_STREAM_CONTROL;
     uint32_t FE_VERTEX_STREAM_BASE_ADDR;
 };
@@ -246,7 +245,6 @@ struct compiled_set_vertex_buffer
 /* Compiled context->set_index_buffer result */
 struct compiled_set_index_buffer
 {
-    void *logical;
     uint32_t FE_INDEX_STREAM_CONTROL;
     uint32_t FE_INDEX_STREAM_BASE_ADDR;
 };
diff --git a/src/gallium/drivers/etna/etna_pipe.c b/src/gallium/drivers/etna/etna_pipe.c
index 358c686f0d..372b835e60 100644
--- a/src/gallium/drivers/etna/etna_pipe.c
+++ b/src/gallium/drivers/etna/etna_pipe.c
@@ -959,32 +959,34 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
                 (color_supertiled ? VIVS_PE_COLOR_FORMAT_SUPER_TILED : 0);
                 /* XXX VIVS_PE_COLOR_FORMAT_OVERWRITE and the rest comes from blend_state / depth_stencil_alpha */
                 /* merged with depth_stencil_alpha */
-        if((cbuf->surf.address & 63) || (((cbuf->surf.stride*4) & 63) && cbuf->surf.height > 4))
+        if((cbuf->surf.offset & 63) || (((cbuf->surf.stride*4) & 63) && cbuf->surf.height > 4))
         {
             /* XXX Must make temporary surface here.
              * Need the same mechanism on gc2000 when we want to do mipmap generation by
              * rendering to levels > 1 due to multitiled / tiled conversion.
              */
-            BUG("Alignment error, trying to render to %08x with tile stride %i",
-                    cbuf->surf.address, cbuf->surf.stride*4);
+            BUG("Alignment error, trying to render to offset %08x with tile stride %i",
+                    cbuf->surf.offset, cbuf->surf.stride*4);
         }
 
+        struct etna_bo *bo = etna_resource(cbuf->base.texture)->bo;
         if (priv->ctx->conn->chip.pixel_pipes == 1)
         {
-            cs->PE_COLOR_ADDR = cbuf->surf.address;
+            cs->PE_COLOR_ADDR = etna_bo_gpu_address(bo) + cbuf->surf.offset;
         }
         else if (priv->ctx->conn->chip.pixel_pipes == 2)
         {
-            cs->PE_PIPE_COLOR_ADDR[0] = cbuf->surf.address;
-            cs->PE_PIPE_COLOR_ADDR[1] = cbuf->surf.address;  /* TODO */
+            cs->PE_PIPE_COLOR_ADDR[0] = etna_bo_gpu_address(bo) + cbuf->surf.offset;
+            cs->PE_PIPE_COLOR_ADDR[1] = etna_bo_gpu_address(bo) + cbuf->surf.offset; /* TODO */
         }
         cs->PE_COLOR_STRIDE = cbuf->surf.stride;
-        if(cbuf->surf.ts_address)
+        if(cbuf->surf.ts_size)
         {
+            struct etna_bo *ts_bo = etna_resource(cbuf->base.texture)->ts_bo;
             ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR;
             cs->TS_COLOR_CLEAR_VALUE = cbuf->level->clear_value;
-            cs->TS_COLOR_STATUS_BASE = cbuf->surf.ts_address;
-            cs->TS_COLOR_SURFACE_BASE = cbuf->surf.address;
+            cs->TS_COLOR_STATUS_BASE = etna_bo_gpu_address(ts_bo) + cbuf->surf.ts_offset;
+            cs->TS_COLOR_SURFACE_BASE = etna_bo_gpu_address(bo) + cbuf->surf.offset;
         }
         /* MSAA */
         if(cbuf->base.texture->nr_samples > 1)
@@ -1009,24 +1011,26 @@ static void etna_pipe_set_framebuffer_state(struct pipe_context *pipe,
                 VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z;
                 /* VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH */
                 /* merged with depth_stencil_alpha */
+        struct etna_bo *bo = etna_resource(zsbuf->base.texture)->bo;
         if (priv->ctx->conn->chip.pixel_pipes == 1)
         {
-            cs->PE_DEPTH_ADDR = zsbuf->surf.address;
+            cs->PE_DEPTH_ADDR = etna_bo_gpu_address(bo) + zsbuf->surf.offset;
         }
         else if (priv->ctx->conn->chip.pixel_pipes == 2)
         {
-            cs->PE_PIPE_DEPTH_ADDR[0] = zsbuf->surf.address;
-            cs->PE_PIPE_DEPTH_ADDR[1] = zsbuf->surf.address;  /* TODO */
+            cs->PE_PIPE_DEPTH_ADDR[0] = etna_bo_gpu_address(bo) + zsbuf->surf.offset;
+            cs->PE_PIPE_DEPTH_ADDR[1] = etna_bo_gpu_address(bo) + zsbuf->surf.offset;  /* TODO */
         }
         cs->PE_DEPTH_STRIDE = zsbuf->surf.stride;
         cs->PE_HDEPTH_CONTROL = VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED;
         cs->PE_DEPTH_NORMALIZE = etna_f32_to_u32(exp2f(depth_bits) - 1.0f);
-        if(zsbuf->surf.ts_address)
+        if(zsbuf->surf.ts_size)
         {
+            struct etna_bo *ts_bo = etna_resource(zsbuf->base.texture)->ts_bo;
             ts_mem_config |= VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR;
             cs->TS_DEPTH_CLEAR_VALUE = zsbuf->level->clear_value;
-            cs->TS_DEPTH_STATUS_BASE = zsbuf->surf.ts_address;
-            cs->TS_DEPTH_SURFACE_BASE = zsbuf->surf.address;
+            cs->TS_DEPTH_STATUS_BASE = etna_bo_gpu_address(ts_bo) + zsbuf->surf.ts_offset;
+            cs->TS_DEPTH_SURFACE_BASE = etna_bo_gpu_address(bo) + zsbuf->surf.offset;
         }
         ts_mem_config |= (depth_bits == 16 ? VIVS_TS_MEM_CONFIG_DEPTH_16BPP : 0);
         /* MSAA */
@@ -1185,11 +1189,10 @@ static void etna_pipe_set_vertex_buffers( struct pipe_context *pipe,
         priv->vertex_buffer_s[slot].user_buffer = vbi->user_buffer;
         /* determine addresses */
         viv_addr_t gpu_addr = 0;
-        cs->logical = 0;
         if(vbi->buffer) /* GPU buffer */
         {
-            gpu_addr = etna_resource(vbi->buffer)->levels[0].address + vbi->buffer_offset;
-            cs->logical = etna_resource(vbi->buffer)->levels[0].logical + vbi->buffer_offset;
+            struct etna_bo *bo = etna_resource(vbi->buffer)->bo;
+            gpu_addr = etna_bo_gpu_address(bo) + vbi->buffer_offset;
         }
         /* compiled state */
         cs->FE_VERTEX_STREAM_CONTROL = FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(vbi->stride);
@@ -1209,7 +1212,6 @@ static void etna_pipe_set_index_buffer( struct pipe_context *pipe,
     if(ib == NULL)
     {
         pipe_resource_reference(&priv->index_buffer_s.buffer, NULL); /* update reference to buffer */
-        cs->logical = NULL;
         cs->FE_INDEX_STREAM_CONTROL = 0;
         cs->FE_INDEX_STREAM_BASE_ADDR = 0;
     } else
@@ -1220,10 +1222,10 @@ static void etna_pipe_set_index_buffer( struct pipe_context *pipe,
         priv->index_buffer_s.offset = ib->offset;
         priv->index_buffer_s.user_buffer = ib->user_buffer;
 
+        struct etna_bo *bo = etna_resource(ib->buffer)->bo;
         cs->FE_INDEX_STREAM_CONTROL =
                 translate_index_size(ib->index_size);
-        cs->FE_INDEX_STREAM_BASE_ADDR = etna_resource(ib->buffer)->levels[0].address + ib->offset;
-        cs->logical = etna_resource(ib->buffer)->levels[0].logical + ib->offset;
+        cs->FE_INDEX_STREAM_BASE_ADDR = etna_bo_gpu_address(bo) + ib->offset;
 
         etna_resource_touch(pipe, ib->buffer);
     }
diff --git a/src/gallium/drivers/etna/etna_pipe.h b/src/gallium/drivers/etna/etna_pipe.h
index fe231ff77a..dc13d7dbf0 100644
--- a/src/gallium/drivers/etna/etna_pipe.h
+++ b/src/gallium/drivers/etna/etna_pipe.h
@@ -66,9 +66,7 @@ struct etna_resource_level
    unsigned offset; /* offset into memory area */
    unsigned size; /* size of memory area */
 
-   uint32_t address; /* cached GPU pointers to LODs */
-   void *logical; /* cached CPU pointer */
-   uint32_t ts_address;
+   uint32_t ts_offset;
    uint32_t ts_size;
    uint32_t clear_value; /* clear value of resource level (mainly for TS) */
    uint32_t stride; /* VIVS_PE_(COLOR|DEPTH)_STRIDE */
diff --git a/src/gallium/drivers/etna/etna_resource.c b/src/gallium/drivers/etna/etna_resource.c
index 1f6dc538b0..6f07eef776 100644
--- a/src/gallium/drivers/etna/etna_resource.c
+++ b/src/gallium/drivers/etna/etna_resource.c
@@ -65,7 +65,7 @@ bool etna_screen_resource_alloc_ts(struct pipe_screen *screen, struct etna_resou
         return false;
     }
     resource->ts_bo = rt_ts;
-    resource->levels[0].ts_address = etna_bo_gpu_address(resource->ts_bo);
+    resource->levels[0].ts_offset = 0;
     resource->levels[0].ts_size = etna_bo_size(resource->ts_bo);
     /* It is important to initialize the TS, as random pattern
      * can result in crashes. Do this on the CPU as this only happens once
@@ -257,21 +257,6 @@ static struct pipe_resource * etna_screen_resource_create(struct pipe_screen *sc
         memset(map, 0, rt_size);
     }
 
-    /* Set up cached mipmap level addresses
-     * (this is pretty pointless, XXX remove it)
-     */
-    uint32_t gpu_address = etna_bo_gpu_address(resource->bo);
-    void *map = etna_bo_map(resource->bo);
-    for(unsigned ix=0; ix<=resource->base.last_level; ++ix)
-    {
-        struct etna_resource_level *mip = &resource->levels[ix];
-        mip->address = gpu_address + mip->offset;
-        mip->logical = map + mip->offset;
-        DBG_F(ETNA_DBG_RESOURCE_MSGS, "  %08x level %i: %ix%i (%i) stride=%i layer_stride=%i",
-                (int)mip->address, ix, (int)mip->width, (int)mip->height, (int)mip->size,
-                (int)mip->stride, (int)mip->layer_stride);
-    }
-
     return &resource->base;
 }
 
diff --git a/src/gallium/drivers/etna/etna_screen.c b/src/gallium/drivers/etna/etna_screen.c
index 2636e007e4..7d21d37512 100644
--- a/src/gallium/drivers/etna/etna_screen.c
+++ b/src/gallium/drivers/etna/etna_screen.c
@@ -448,22 +448,22 @@ static void etna_screen_flush_frontbuffer( struct pipe_screen *screen,
     etna_stall(ctx, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
 
     /* Set up color TS to source surface before blit, if needed */
-    if(rt_resource->levels[level].ts_address != ectx->gpu3d.TS_COLOR_STATUS_BASE)
+    uint32_t ts_mem_config = 0;
+    if(rt_resource->base.nr_samples > 1)
+        ts_mem_config |= VIVS_TS_MEM_CONFIG_MSAA | translate_msaa_format(rt_resource->base.format, false);
+    if(rt_resource->levels[level].ts_size)
     {
-        if(rt_resource->levels[level].ts_address)
-        {
-            etna_set_state_multi(ctx, VIVS_TS_MEM_CONFIG, 4, (uint32_t[]) {
-              ectx->gpu3d.TS_MEM_CONFIG = VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR, /* XXX |= VIVS_TS_MEM_CONFIG_MSAA | translate_msaa_format(cbuf->format) */
-              ectx->gpu3d.TS_COLOR_STATUS_BASE = rt_resource->levels[level].ts_address,
-              ectx->gpu3d.TS_COLOR_SURFACE_BASE = rt_resource->levels[level].address,
-              ectx->gpu3d.TS_COLOR_CLEAR_VALUE = rt_resource->levels[level].clear_value
-              });
-        } else {
-            etna_set_state(ctx, VIVS_TS_MEM_CONFIG, 0x00000000);
-            ectx->gpu3d.TS_MEM_CONFIG = 0;
-        }
-        ectx->dirty_bits |= ETNA_STATE_TS;
+        etna_set_state_multi(ctx, VIVS_TS_MEM_CONFIG, 4, (uint32_t[]) {
+          ectx->gpu3d.TS_MEM_CONFIG = VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | ts_mem_config,
+          ectx->gpu3d.TS_COLOR_STATUS_BASE = etna_bo_gpu_address(rt_resource->ts_bo) + rt_resource->levels[level].ts_offset,
+          ectx->gpu3d.TS_COLOR_SURFACE_BASE = etna_bo_gpu_address(rt_resource->bo) + rt_resource->levels[level].offset,
+          ectx->gpu3d.TS_COLOR_CLEAR_VALUE = rt_resource->levels[level].clear_value
+          });
+    } else {
+        etna_set_state(ctx, VIVS_TS_MEM_CONFIG,
+          ectx->gpu3d.TS_MEM_CONFIG = ts_mem_config);
     }
+    ectx->dirty_bits |= ETNA_STATE_TS;
 
     int msaa_xscale=1, msaa_yscale=1;
     if(!translate_samples_to_xyscale(resource->nr_samples, &msaa_xscale, &msaa_yscale, NULL))
@@ -474,7 +474,7 @@ static void etna_screen_flush_frontbuffer( struct pipe_screen *screen,
     etna_compile_rs_state(&copy_to_screen, &(struct rs_state){
                 .source_format = translate_rt_format(rt_resource->base.format, false),
                 .source_tiling = rt_resource->layout,
-                .source_addr = rt_resource->levels[level].address,
+                .source_addr = etna_bo_gpu_address(rt_resource->bo) + rt_resource->levels[level].offset,
                 .source_stride = rt_resource->levels[level].stride,
                 .dest_format = drawable->rs_format,
                 .dest_tiling = ETNA_LAYOUT_LINEAR,
@@ -491,7 +491,7 @@ static void etna_screen_flush_frontbuffer( struct pipe_screen *screen,
     etna_submit_rs_state(ctx, &copy_to_screen);
     DBG_F(ETNA_DBG_FRAME_MSGS,
             "Queued RS command to flush screen from %08x to %08x stride=%08x width=%i height=%i, ctx %p",
-            rt_resource->levels[0].address,
+            etna_bo_gpu_address(rt_resource->bo) + rt_resource->levels[level].offset,
             drawable->addr, drawable->stride,
             drawable->width, drawable->height, ctx);
     ectx->base.flush(&ectx->base, &drawable->fence, 0);
diff --git a/src/gallium/drivers/etna/etna_surface.c b/src/gallium/drivers/etna/etna_surface.c
index 73ad33d22b..6b07d402d2 100644
--- a/src/gallium/drivers/etna/etna_surface.c
+++ b/src/gallium/drivers/etna/etna_surface.c
@@ -81,18 +81,18 @@ static struct pipe_surface *etna_pipe_create_surface(struct pipe_context *pipe,
                                             /* underlying resource instead of surface */
     surf->surf = resource->levels[level]; /* Make copy of level to narrow down address to layer */
                                         /* XXX we don't really need a copy but it's convenient */
-    surf->surf.address += layer * surf->surf.layer_stride;
-    surf->surf.logical += layer * surf->surf.layer_stride;
+    surf->surf.offset += layer * surf->surf.layer_stride;
 
-    if(surf->surf.ts_address)
+    if(surf->surf.ts_size)
     {
-        /* This abuses the RS as a plain buffer memset().
+        /* This (ab)uses the RS as a plain buffer memset().
            Currently uses a fixed row size of 64 bytes. Some benchmarking with different sizes may be in order.
          */
+        struct etna_bo *ts_bo = etna_resource(surf->base.texture)->ts_bo;
         etna_compile_rs_state(&surf->clear_command, &(struct rs_state){
                 .source_format = RS_FORMAT_A8R8G8B8,
                 .dest_format = RS_FORMAT_A8R8G8B8,
-                .dest_addr = surf->surf.ts_address,
+                .dest_addr = etna_bo_gpu_address(ts_bo) + surf->surf.ts_offset,
                 .dest_stride = 0x40,
                 .dest_tiling = ETNA_LAYOUT_TILED,
                 .dither = {0xffffffff, 0xffffffff},
diff --git a/src/gallium/drivers/etna/etna_texture.c b/src/gallium/drivers/etna/etna_texture.c
index 58ac8ff2a2..59e4480e4c 100644
--- a/src/gallium/drivers/etna/etna_texture.c
+++ b/src/gallium/drivers/etna/etna_texture.c
@@ -135,7 +135,7 @@ static struct pipe_sampler_view *etna_pipe_create_sampler_view(struct pipe_conte
     /* Set up levels-of-detail */
     for(int lod=0; lod<=res->base.last_level; ++lod)
     {
-        cs->TE_SAMPLER_LOD_ADDR[lod] = res->levels[lod].address;
+        cs->TE_SAMPLER_LOD_ADDR[lod] = etna_bo_gpu_address(res->bo) + res->levels[lod].offset;
     }
     cs->min_lod = sv->base.u.tex.first_level << 5;
     cs->max_lod = MIN2(sv->base.u.tex.last_level, res->base.last_level) << 5;
diff --git a/src/gallium/drivers/etna/etna_transfer.c b/src/gallium/drivers/etna/etna_transfer.c
index b9ad9bd305..56631d42f4 100644
--- a/src/gallium/drivers/etna/etna_transfer.c
+++ b/src/gallium/drivers/etna/etna_transfer.c
@@ -111,11 +111,13 @@ static void *etna_pipe_transfer_map(struct pipe_context *pipe,
     ptrans->base.box = *box;
 
     struct etna_resource_level *res_level = &resource_priv->levels[level];
+    /* map buffer object */
+    void *mapped = etna_bo_map(resource_priv->bo) + res_level->offset;
     if(likely(ptrans->in_place))
     {
         ptrans->base.stride = res_level->stride;
         ptrans->base.layer_stride = res_level->layer_stride;
-        ptrans->buffer = res_level->logical + etna_compute_offset(resource->format, box, res_level->stride, res_level->layer_stride);
+        ptrans->buffer = mapped + etna_compute_offset(resource->format, box, res_level->stride, res_level->layer_stride);
     } else {
         unsigned divSizeX = util_format_get_blockwidth(format);
         unsigned divSizeY = util_format_get_blockheight(format);
@@ -138,7 +140,7 @@ static void *etna_pipe_transfer_map(struct pipe_context *pipe,
             {
                 if(resource_priv->layout == ETNA_LAYOUT_TILED && !util_format_is_compressed(resource_priv->base.format))
                 {
-                    etna_texture_untile(ptrans->buffer, res_level->logical,
+                    etna_texture_untile(ptrans->buffer, mapped,
                             ptrans->base.box.x, ptrans->base.box.y, res_level->stride,
                             ptrans->base.box.width, ptrans->base.box.height, ptrans->base.stride,
                             util_format_get_blocksize(resource_priv->base.format));
@@ -148,7 +150,7 @@ static void *etna_pipe_transfer_map(struct pipe_context *pipe,
                       ptrans->base.stride, ptrans->base.layer_stride,
                       0, 0, 0, /* dst x,y,z */
                       ptrans->base.box.width, ptrans->base.box.height, ptrans->base.box.depth,
-                      res_level->logical,
+                      mapped,
                       res_level->stride, res_level->layer_stride,
                       ptrans->base.box.x, ptrans->base.box.y, ptrans->base.box.z);
                 }
@@ -183,25 +185,27 @@ static void etna_pipe_transfer_unmap(struct pipe_context *pipe,
      */
     struct etna_resource *resource = etna_resource(ptrans->base.resource);
     assert(ptrans->base.level <= resource->base.last_level);
-    struct etna_resource_level *level = &resource->levels[ptrans->base.level];
 
     if(ptrans->base.usage & PIPE_TRANSFER_WRITE)
     {
         /* write back */
         if(unlikely(!ptrans->in_place))
         {
+            /* map buffer object */
+            struct etna_resource_level *res_level = &resource->levels[ptrans->base.level];
+            void *mapped = etna_bo_map(resource->bo) + res_level->offset;
             if(resource->layout == ETNA_LAYOUT_LINEAR || resource->layout == ETNA_LAYOUT_TILED)
             {
                 if(resource->layout == ETNA_LAYOUT_TILED && !util_format_is_compressed(resource->base.format))
                 {
-                    etna_texture_tile(level->logical, ptrans->buffer,
-                            ptrans->base.box.x, ptrans->base.box.y, level->stride,
+                    etna_texture_tile(mapped, ptrans->buffer,
+                            ptrans->base.box.x, ptrans->base.box.y, res_level->stride,
                             ptrans->base.box.width, ptrans->base.box.height, ptrans->base.stride,
                             util_format_get_blocksize(resource->base.format));
                 } else { /* non-tiled or compressed format */
-                    util_copy_box(level->logical,
+                    util_copy_box(mapped,
                       resource->base.format,
-                      level->stride, level->layer_stride,
+                      res_level->stride, res_level->layer_stride,
                       ptrans->base.box.x, ptrans->base.box.y, ptrans->base.box.z,
                       ptrans->base.box.width, ptrans->base.box.height, ptrans->base.box.depth,
                       ptrans->buffer,