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* etna: dehackify resolve pathHEADmasterLucas Stach2014-08-152-39/+64
| | | | | | Makes the RS resolve a lot less painful. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: implement flush_front_buffer as pipe blitLucas Stach2014-07-301-52/+16
| | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: rough cut at implementing RS blitLucas Stach2014-07-301-0/+79
| | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: use plain etna_resource to wrap framebufferLucas Stach2014-07-303-49/+105
| | | | | | | This moves framebuffer handling almost completely into MESA and doesn't rely on libetna anymore. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: add translate helpers for RS format conversionLucas Stach2014-07-301-0/+25
| | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: allow RGBA as RS formatLucas Stach2014-07-301-12/+26
| | | | | | While at it reformat a bit. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: don't store pipe addrLucas Stach2014-07-305-17/+29
| | | | | | | Compute them dynamically for each level. We will need this to render to different mipmap levels. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: make driver more self contained by including generated headersLucas Stach2014-07-3020-32/+4233
| | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* HACK allow NULL native windowLucas Stach2014-07-301-1/+3
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* HACK: etna: resolve from MULTI_TILED to TILEDLucas Stach2014-07-302-3/+76
| | | | | | | Extremely unclean, but works for me. Don't ever show to anyone. CLEAN THIS UP PROPERLY! Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: fix compile warningsChristian Gmeiner2014-07-301-1/+1
| | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* etna: do not upgrade textures (sampler views) to MULTI tiledChristian Gmeiner2014-07-301-1/+1
| | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* etna: wait for PE to finish before updating samplersLucas Stach2014-07-281-0/+3
| | | | | | | Otherwise we encounter visual corruption on frequent sampler updates. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* unclean: emit texture state to new sampler regsLucas Stach2014-07-282-0/+70
| | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: move to new sampler functionsLucas Stach2014-07-281-36/+47
| | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* etna: load of fixes to properly compile with mesa-10.2.4Lucas Stach2014-07-287-12/+8
| | | | Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
* update etna to 463f1e1Wladimir J. van der Laan2014-07-285-22/+46
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* update etna driver to 610025bWladimir J. van der Laan2014-07-284-8/+9
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* sync etna driver to c78f82fWladimir J. van der Laan2014-07-283-31/+17
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* fbdev_etna: use bo object for framebufferWladimir J. van der Laan2014-07-284-8/+11
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* sync etna driver to c209f5cWladimir J. van der Laan2014-07-289-77/+65
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* sync etna driver to 31f10deWladimir J. van der Laan2014-07-289-216/+65
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* fbdev: get rid of want_fenceWladimir J. van der Laan2014-07-284-7/+5
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* sync etna driver to 7a68324Wladimir J. van der Laan2014-07-289-75/+107
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* sync etna driver to cec463bWladimir J. van der Laan2014-07-283-13/+16
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* sync etna driver to 06c1bc8Wladimir J. van der Laan2014-07-281-1/+6
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* u_vbuf: use single vertex buffer if it's not possible to have multipleWladimir J. van der Laan2014-07-281-4/+23
| | | | | Put CONST, VERTEX and INSTANCE attributes into one vertex buffer if necessary due to hardware constraints.
* sync etna driver to a6f9e72Wladimir J. van der Laan2014-07-282-4/+3
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* sync etna driver to 468ff99Wladimir J. van der Laan2014-07-288-144/+62
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* sync etna driver to 296195cWladimir J. van der Laan2014-07-285-17/+80
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* sync etna driver to 6e4d4cbWladimir J. van der Laan2014-07-285-4/+22
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* sync etna driver to 23a0d9eWladimir J. van der Laan2014-07-2828-26/+88
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* add etna driver for Vivante GCxxxx embedded GPUsWladimir J. van der Laan2014-07-2857-80/+8814
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* Add release notes for 10.2.4Carl Worth2014-07-181-0/+125
| | | | Just prior to the release.
* Update VERSION to 10.2.4Carl Worth2014-07-181-1/+1
| | | | In preparation for the 10.2.4 release, of course.
* i965: Enable compressed multisample support (CMS) on Broadwell.Kenneth Graunke2014-07-171-8/+0
| | | | | | | | Everything is in place and appears to be working. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (cherry picked from commit 8cf289c3ef2fcaded5a89f9d7a600f60a5e8356e)
* i965: Add 2x MSAA support to the MCS allocation function.Kenneth Graunke2014-07-171-0/+1
| | | | | | | | 2x MSAA also uses 8 bits, just like 4x. More bits are unused. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> (cherry picked from commit db184d43b0573c00d911ef9e98fbaab26ebd6466)
* i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.Kenneth Graunke2014-07-171-0/+10
| | | | | | | | | | MCS buffers are never allocated on Broadwell, so this does nothing for now, but puts the infrastructure in place for when they do exist. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (cherry picked from commit a248b2a4ebb27832d6c8a40ce2b10134f8735b93)
* i965: Drop SINT workaround for CMS layout on Broadwell.Kenneth Graunke2014-07-171-3/+1
| | | | | | | | | | According to the documentation, we don't need this SINT workaround on Broadwell. (Or at least, it doesn't mention that we need it.) Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (cherry picked from commit e10311be9f61230de7f06e9fb30834835ba3677d)
* i965: Add plumbing for Broadwell's auxiliary surface support.Kenneth Graunke2014-07-171-7/+37
| | | | | | | | | | | | | | | Broadwell generalizes the MCS fields to allow for multiple kinds of auxiliary surfaces. This patch adds the plumbing to set those values, but doesn't yet hook any up. v2: (by Jordan Justen) Use mt for qpitch; pitch is tiles - 1. v3: Don't forget to subtract 1 from aux_mt->pitch. v4: Drop unnecessary aux_mt->offset (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (cherry picked from commit fd7718768929ff7fd1460bafc32f7b8be75a3140)
* i965: Add auxiliary surface field #defines for Broadwell.Jordan Justen2014-07-171-0/+10
| | | | | | | Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> (cherry picked from commit a46cb6a971b136f41e24739551f6d36ecc1694c0)
* i965/fs: Set correct number of regs_written for MCS fetches.Matt Turner2014-07-171-3/+3
| | | | | | | | regs_written is in units of virtual GRFs. Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit dfd117b8570a69a429e660c069997e78b181ab6d)
* i965: Generalize the pixel_x/y workaround for all UW types.Eric Anholt2014-07-171-4/+4
| | | | | | | | | | | | | | | | This is the only case where a fs_reg in brw_fs_visitor is used during optimization/code generation, and it meant that optimizations had to be careful to not move pixel_x/y's register number without updating it. Additionally, it turns out we had a couple of other UW values that weren't getting this treatment (like gl_SampleID), so this more general fix is probably a good idea (though I wasn't able to replicate problems with either pixel_[xy]'s values or gl_SampleID, even when telling the register allocator to reuse registers immediately) Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 66f5c8df067ed014c98ef7cf21591e9ea0b5b6bb)
* i965/fs: Use WE_all for gl_SampleID header register munging.Kenneth Graunke2014-07-171-5/+9
| | | | | | | | | | | This code should execute without regard to the currently executing channels. Asking for gl_SampleID inside control flow might break in strange ways. It appears to break even at the top of the program in SIMD16 mode occasionally as well. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 6dc9e4e22a19108057162d9d8f8c7d559545f8de)
* i965/fs: Don't use brw_imm_* unnecessarily.Matt Turner2014-07-172-5/+5
| | | | | | | | | | | | Using brw_imm_* creates a source with file=HW_REG, and the scheduler inserts barrier dependencies when it sees HW_REG. None of these are hardware-registers in the sense that they're special and scheduling shouldn't touch them. A few of the modified cases already have HW_REGs for other sources, so it won't allow extra flexibility in some cases. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit c938be8ad272a06bc0e91c4e718b61a0c5de400e) (This patch was cherry-picked to make the next commit apply cleanly.)
* i965/fs: Set force_uncompressed and force_sechalf on samplepos setup.Kenneth Graunke2014-07-171-6/+8
| | | | | | | | | | | | gen8_fs_generator uses these to decide whether to set the execution size to 8 or 16, so we incorrectly made both of these MOVs the full width in SIMD16 shaders. (It happened to work out on Gen4-7.) Setting them should also help inform optimization passes what's really going on, which could help avoid bugs. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org
* i965: Set execution size to 8 for instructions with force_sechalf set.Kenneth Graunke2014-07-171-1/+1
| | | | | | | | | | | | | | | | Both inst->force_uncompressed and inst->force_sechalf mean that the generated instruction should be uncompressed and have an execution size of 8. We don't require the visitor to set both flags - setting inst->force_sechalf by itself is supposed to be enough. On Gen4-7, guess_execution_size() demoted instructions to 8-wide based on the default compression state. On Gen8+, we instead set a default execution size, which worked great...except that we forgot to check inst->force_sechalf when deciding whether to use 8 or 16. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Cc: mesa-stable@lists.freedesktop.org (cherry picked from commit 1c62126612752f6eedb66f705cc3ff1e11beea5d)
* i965/vec4: Constant propagate into 2-src math instructions on Gen8.Matt Turner2014-07-171-2/+9
| | | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 7192207de18a7a7e127a8a5910626af96f001993)
* i965/fs: Constant propagate into 2-src math instructions on Gen8.Matt Turner2014-07-171-2/+9
| | | | | | | | total instructions in shared programs: 1878133 -> 1876986 (-0.06%) instructions in affected programs: 153007 -> 151860 (-0.75%) Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit 038eb649b30dfddaf40888ea28b5e88de3af2214)
* i965/fs: Make try_constant_propagate() static.Matt Turner2014-07-172-3/+2
| | | | | Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (cherry picked from commit aca4a951ea2bab855bcc2491a3b8996b54639ebd)
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