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authorMichael Grzeschik <m.grzeschik@pengutronix.de>2022-03-21 22:09:56 +0100
committerMichael Grzeschik <m.grzeschik@pengutronix.de>2022-03-21 22:15:53 +0100
commitdbf5834baf2f7565d74606f0de800516038d7725 (patch)
treeddafc7fb3240ccddd6e8dc9a501c29e7d54068e1
parent330bbad3592f5e5d3b635ac1aa6bc14bc35c34c4 (diff)
downloadbarebox-master.tar.gz
barebox-master.tar.xz
dwc2: align phy handling with kernelHEADmaster
With the linux kernel the phy will first be enabled and then initialised. Currently barebox does this vice versa. On stm32mp157c this leads to the following error: "WARNING: dwc2 49000000.usb-otg@49000000.of: dwc2_core_reset: Timeout! Waiting for Core Soft Reset" This is due to the phy not having the pll enabled in that case. Aligning the phy handling with the kernel, this issue is fixed. Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
-rw-r--r--drivers/usb/dwc2/dwc2.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/usb/dwc2/dwc2.c b/drivers/usb/dwc2/dwc2.c
index 1b5981c2d5..4e2c282d36 100644
--- a/drivers/usb/dwc2/dwc2.c
+++ b/drivers/usb/dwc2/dwc2.c
@@ -78,11 +78,11 @@ static int dwc2_probe(struct device_d *dev)
goto clk_disable;
}
- ret = phy_power_on(dwc2->phy);
+ ret = phy_init(dwc2->phy);
if (ret)
goto clk_disable;
- ret = phy_init(dwc2->phy);
+ ret = phy_power_on(dwc2->phy);
if (ret)
goto phy_power_off;