diff options
| author | Paul Fertser <fercerpav@gmail.com> | 2015-04-09 15:20:22 +0300 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-04-16 20:26:36 +0100 |
| commit | 68921d231655be696d6aad5ca7abe26cb5f17104 (patch) | |
| tree | 0f621c8618b16ec8e359224d6fd4fa3bc545d1ce | |
| parent | e7e13965782a114cca369a71382cd2dd2a7b8da0 (diff) | |
| download | openocd-68921d231655be696d6aad5ca7abe26cb5f17104.tar.gz openocd-68921d231655be696d6aad5ca7abe26cb5f17104.tar.xz | |
tcl/target/stm32f3: fix reset init for stlink
Use mmw to manipulate only selected bits of the word. msb and mwb verify the
memory location and may error on PLLRDY set as a result of PLLON written.
Change-Id: I9a4c1e58f002a1e5e99be1bd34aac27ba65d111d
Reported-by: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2702
Tested-by: jenkins
| -rw-r--r-- | tcl/target/stm32f3x.cfg | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg index f3c22af7..ca8e6e1d 100644 --- a/tcl/target/stm32f3x.cfg +++ b/tcl/target/stm32f3x.cfg @@ -104,11 +104,11 @@ proc stm32f3x_default_examine_end {} { proc stm32f3x_default_reset_init {} { # Configure PLL to boost clock to HSI x 8 (64 MHz) - mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] - mwh 0x40021002 0x0100 ;# RCC_CR[31:16] = PLLON - mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] - sleep 10 ;# Wait for PLL to lock - mww 0x40021004 0x00380402 ;# RCC_CFGR |= SW[1] + mww 0x40021004 0x00380400 ;# RCC_CFGR = PLLMUL[3:1] | PPRE1[2] + mmw 0x40021000 0x01000000 0 ;# RCC_CR |= PLLON + mww 0x40022000 0x00000012 ;# FLASH_ACR = PRFTBE | LATENCY[1] + sleep 10 ;# Wait for PLL to lock + mmw 0x40021004 0x00000002 0 ;# RCC_CFGR |= SW[1] # Boost JTAG frequency adapter_khz 8000 |