diff options
| author | Oleksij Rempel <linux@rempel-privat.de> | 2018-08-29 07:37:06 +0200 |
|---|---|---|
| committer | Oleksij Rempel <linux@rempel-privat.de> | 2018-08-29 07:37:06 +0200 |
| commit | e5cfb768f2c5e1a2cf7ac5bb2c3bddb8e0fdef07 (patch) | |
| tree | ca869ba9bbb2ffeff3cbc7c32c49f4624cf56948 | |
| download | elce-2018-openocd-e5cfb768f2c5e1a2cf7ac5bb2c3bddb8e0fdef07.tar.gz elce-2018-openocd-e5cfb768f2c5e1a2cf7ac5bb2c3bddb8e0fdef07.tar.xz | |
add bsdl files
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
| -rw-r--r-- | PIC32MX795F512L.bsdl | 554 | ||||
| -rw-r--r-- | STM32F302_F303_B_C_LQFP100.bsd | 572 |
2 files changed, 1126 insertions, 0 deletions
diff --git a/PIC32MX795F512L.bsdl b/PIC32MX795F512L.bsdl new file mode 100644 index 0000000..b9e066b --- /dev/null +++ b/PIC32MX795F512L.bsdl @@ -0,0 +1,554 @@ +-------------------------------------------------------------------------
+-- --
+-- Copyright Microchip Technology Inc. 2008. All rights reserved. --
+-- --
+-- --
+-- IMPORTANT NOTICE --
+-- --
+-- --
+-- Software License Agreement --
+-- --
+-- The software supplied herewith by Microchip Technology Incorporated --
+-- (the Company) for its PICmicro Microcontroller is intended and --
+-- supplied to you, the Company customer, for use solely and --
+-- exclusively on Microchip PICmicro Microcontroller products. The --
+-- software is owned by the Company and/or its supplier, and is --
+-- protected under applicable copyright laws. All rights are reserved. --
+-- Any use in violation of the foregoing restrictions may subject the --
+-- user to criminal sanctions under applicable laws, as well as to --
+-- civil liability for the breach of the terms and conditions of this --
+-- license. --
+-- --
+-- THIS SOFTWARE IS PROVIDED IN AN AS IS CONDITION. NO WARRANTIES, --
+-- WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED --
+-- TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
+-- PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, --
+-- IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR --
+-- CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. --
+-------------------------------------------------------------------------
+
+-- BSDL file
+
+-- File Name: PIC32MX795F512L.bsdl
+-- File Revision: Revision: 1.1
+-- Date created: Date: Tuesday, April 08, 2008
+-- Support:
+
+-- Device: PIC32MX795F512L
+-- rev 0001
+-- Package: 100 pin TQFP
+
+
+-- Notes:
+-- 1. The behavior of the Oscillator Boundary Scan cells are dependant
+-- on the Oscillator Fuse settings, and therefore caution must be used
+-- when controlling the the BSC's on RC12(PIN63) and RC15(PIN64).
+
+-- ***********************************************************************
+-- * PORT DEFINITIONS *
+-- ***********************************************************************
+ entity PIC32MX795F512L is
+
+ generic(PHYSICAL_PIN_MAP : string := "TQFP100");
+
+ port (
+ RB0 : inout bit;
+ RB1 : inout bit;
+ RB10 : inout bit;
+ RB11 : inout bit;
+ RB12 : inout bit;
+ RB13 : inout bit;
+ RB14 : inout bit;
+ RB15 : inout bit;
+ RB2 : inout bit;
+ RB3 : inout bit;
+ RB4 : inout bit;
+ RB5 : inout bit;
+ RB6 : inout bit;
+ RB7 : inout bit;
+ RB8 : inout bit;
+ RB9 : inout bit;
+ RD8 : inout bit;
+ RD9 : inout bit;
+ RD10 : inout bit;
+ RD11 : inout bit;
+ RD12 : inout bit;
+ RD0 : inout bit;
+ RD1 : inout bit;
+ RD2 : inout bit;
+ RD3 : inout bit;
+ RD4 : inout bit;
+ VREG : linkage bit;
+ RE8 : inout bit;
+ RE9 : inout bit;
+ RA14 : inout bit;
+ RA15 : inout bit;
+ MCLR : in bit;
+ RC12 : inout bit;
+ RC15 : inout bit;
+ RA2 : inout bit;
+ RA3 : inout bit;
+ RA6 : inout bit;
+ RA7 : inout bit;
+ RD13 : inout bit;
+ RD14 : inout bit;
+ RD15 : inout bit;
+ RD6 : inout bit;
+ RD7 : inout bit;
+ RF0 : inout bit;
+ RF1 : inout bit;
+ RG0 : inout bit;
+ RG1 : inout bit;
+ RG12 : inout bit;
+ RG13 : inout bit;
+ RG14 : inout bit;
+ RG15 : inout bit;
+ RE0 : inout bit;
+ RE1 : inout bit;
+ RE2 : inout bit;
+ RE3 : inout bit;
+ RE4 : inout bit;
+ RE5 : inout bit;
+ RE6 : inout bit;
+ RE7 : inout bit;
+ RD5 : inout bit;
+ RG6 : inout bit;
+ RG7 : inout bit;
+ RF8 : inout bit;
+ RG8 : inout bit;
+ RC13 : inout bit;
+ RC14 : inout bit;
+ RG9 : inout bit;
+ RC1 : inout bit;
+ RC2 : inout bit;
+ RC3 : inout bit;
+ RC4 : inout bit;
+ RF2 : inout bit;
+ RF3 : inout bit;
+ RF12 : inout bit;
+ RF13 : inout bit;
+ RF4 : inout bit;
+ RF5 : inout bit;
+ VBUS : linkage bit;
+ RA9 : inout bit;
+ RA10 : inout bit;
+ USBDM : inout bit;
+ USBDP : inout bit;
+ TDI : in bit;
+ TMS : in bit;
+ TCK : in bit;
+ TDO : out bit;
+ VUSB : linkage bit;
+ VSS1 : linkage bit;
+ VSS2 : linkage bit;
+ VSS3 : linkage bit;
+ VSS4 : linkage bit;
+ VSS5 : linkage bit;
+ AVSS : linkage bit;
+ VDDCORE : linkage bit;
+ AVDD : linkage bit;
+ VDD1 : linkage bit;
+ VDD2 : linkage bit;
+ VDD3 : linkage bit;
+ VDD4 : linkage bit;
+ VDD5 : linkage bit
+ );
+
+ use STD_1149_1_2001.all; -- Get IEEE 1149.1-2001 attributes and definitions
+
+ attribute COMPONENT_CONFORMANCE of PIC32MX795F512L : entity is "STD_1149_1_2001";
+
+ attribute PIN_MAP of PIC32MX795F512L : entity is PHYSICAL_PIN_MAP;
+
+ constant TQFP100 : PIN_MAP_STRING :=
+ " RG15 : 1 ," &
+ " VDD1 : 2 ," &
+ " RE5 : 3 ," &
+ " RE6 : 4 ," &
+ " RE7 : 5 ," &
+ " RC1 : 6 ," &
+ " RC2 : 7 ," &
+ " RC3 : 8 ," &
+ " RC4 : 9 ," &
+ " RG6 : 10 ," &
+ " RG7 : 11 ," &
+ " RG8 : 12 ," &
+ " MCLR : 13 ," &
+ " RG9 : 14 ," &
+ " VSS2 : 15 ," &
+ " VDD2 : 16 ," &
+ " TMS : 17 ," &
+ " RE8 : 18 ," &
+ " RE9 : 19 ," &
+ " RB5 : 20 ," &
+ " RB4 : 21 ," &
+ " RB3 : 22 ," &
+ " RB2 : 23 ," &
+ " RB1 : 24 ," &
+ " RB0 : 25 ," &
+ " RB6 : 26 ," &
+ " RB7 : 27 ," &
+ " RA9 : 28 ," &
+ " RA10 : 29 ," &
+ " AVDD : 30 ," &
+ " AVSS : 31 ," &
+ " RB8 : 32 ," &
+ " RB9 : 33 ," &
+ " RB10 : 34 ," &
+ " RB11 : 35 ," &
+ " VSS3 : 36 ," &
+ " VDD3 : 37 ," &
+ " TCK : 38 ," &
+ " RF13 : 39 ," &
+ " RF12 : 40 ," &
+ " RB12 : 41 ," &
+ " RB13 : 42 ," &
+ " RB14 : 43 ," &
+ " RB15 : 44 ," &
+ " VSS4 : 45 ," &
+ " VDD4 : 46 ," &
+ " RD14 : 47 ," &
+ " RD15 : 48 ," &
+ " RF4 : 49 ," &
+ " RF5 : 50 ," &
+ " RF3 : 51 ," &
+ " RF2 : 52 ," &
+ " RF8 : 53 ," &
+ " VBUS : 54 ," &
+ " VUSB : 55 ," &
+ " USBDM : 56 ," &
+ " USBDP : 57 ," &
+ " RA2 : 58 ," &
+ " RA3 : 59 ," &
+ " TDI : 60 ," &
+ " TDO : 61 ," &
+ " VDD5 : 62 ," &
+ " RC12 : 63 ," &
+ " RC15 : 64 ," &
+ " VSS5 : 65 ," &
+ " RA14 : 66 ," &
+ " RA15 : 67 ," &
+ " RD8 : 68 ," &
+ " RD9 : 69 ," &
+ " RD10 : 70 ," &
+ " RD11 : 71 ," &
+ " RD0 : 72 ," &
+ " RC13 : 73 ," &
+ " RC14 : 74 ," &
+ " VSS1 : 75 ," &
+ " RD1 : 76 ," &
+ " RD2 : 77 ," &
+ " RD3 : 78 ," &
+ " RD12 : 79 ," &
+ " RD13 : 80 ," &
+ " RD4 : 81 ," &
+ " RD5 : 82 ," &
+ " RD6 : 83 ," &
+ " RD7 : 84 ," &
+ " VDDCORE : 85 ," &
+ " VREG : 86 ," &
+ " RF0 : 87 ," &
+ " RF1 : 88 ," &
+ " RG1 : 89 ," &
+ " RG0 : 90 ," &
+ " RA6 : 91 ," &
+ " RA7 : 92 ," &
+ " RE0 : 93 ," &
+ " RE1 : 94 ," &
+ " RG14 : 95 ," &
+ " RG12 : 96 ," &
+ " RG13 : 97 ," &
+ " RE2 : 98 ," &
+ " RE3 : 99 ," &
+ " RE4 : 100 ";
+
+-- *********************************************************************
+-- * IEEE 1149.1 TAP PORTS *
+-- *********************************************************************
+
+ attribute TAP_SCAN_IN of TDI : signal is true;
+ attribute TAP_SCAN_MODE of TMS : signal is true;
+ attribute TAP_SCAN_OUT of TDO : signal is true;
+ attribute TAP_SCAN_CLOCK of TCK : signal is (10.00e+06,BOTH);
+
+-- *********************************************************************
+-- * INSTRUCTIONS AND REGISTER ACCESS *
+-- *********************************************************************
+
+ attribute INSTRUCTION_LENGTH of PIC32MX795F512L : entity is 5;
+ attribute INSTRUCTION_OPCODE of PIC32MX795F512L : entity is
+ "extest (00110)," &
+ "bypass (11111)," &
+ "sample (00010)," &
+ "preload (00010)," &
+ "highz (00000)," &
+ "idcode (00001)," &
+ "swtap_chip (00100)," &
+ "swtap (00101)," &
+ "mchp_cmd (00111)," &
+ "mchp_scan (01000)" ;
+
+ attribute INSTRUCTION_CAPTURE of PIC32MX795F512L : entity is "00001";
+
+
+ attribute IDCODE_REGISTER of PIC32MX795F512L : entity is
+ "0000" & -- Version Number
+ "0100001100000111" & -- Part Number
+ "00000101001" & -- Manufacturer ID
+ "1"; -- Required by IEEE
+
+ attribute REGISTER_ACCESS of PIC32MX795F512L : entity is
+ "BOUNDARY (extest, sample, preload), " &
+ "DEVICE_ID (idcode), " &
+ "BYPASS (bypass, highz, swtap_chip, swtap), " &
+ "MCHP_CMD_REG[8] (mchp_cmd), " &
+ "MCHP_SCAN_REG[8] (mchp_scan) " ;
+
+-- *********************************************************************
+-- * BOUNDARY SCAN CELL INFORMATION *
+-- *********************************************************************
+
+ attribute BOUNDARY_LENGTH of PIC32MX795F512L : entity is 237;
+ attribute BOUNDARY_REGISTER of PIC32MX795F512L : entity is
+ --- num cell port function safe [ccell disval rslt]
+ "0 ( BC_4, RE4, input, X)," &
+ "1 ( BC_1, RE4, output3, X, 2, 0, Z)," &
+ "2 ( BC_2, *, control, 0)," &
+ "3 ( BC_4, RE3, input, X)," &
+ "4 ( BC_1, RE3, output3, X, 5, 0, Z)," &
+ "5 ( BC_2, *, control, 0)," &
+ "6 ( BC_4, RE2, input, X)," &
+ "7 ( BC_1, RE2, output3, X, 8, 0, Z)," &
+ "8 ( BC_2, *, control, 0)," &
+ "9 ( BC_4, RG13, input, X)," &
+ "10 ( BC_1, RG13, output3, X, 11, 0, Z)," &
+ "11 ( BC_2, *, control, 0)," &
+ "12 ( BC_4, RG12, input, X)," &
+ "13 ( BC_1, RG12, output3, X, 14, 0, Z)," &
+ "14 ( BC_2, *, control, 0)," &
+ "15 ( BC_4, RG14, input, X)," &
+ "16 ( BC_1, RG14, output3, X, 17, 0, Z)," &
+ "17 ( BC_2, *, control, 0)," &
+ "18 ( BC_4, RE1, input, X)," &
+ "19 ( BC_1, RE1, output3, X, 20, 0, Z)," &
+ "20 ( BC_2, *, control, 0)," &
+ "21 ( BC_4, RE0, input, X)," &
+ "22 ( BC_1, RE0, output3, X, 23, 0, Z)," &
+ "23 ( BC_2, *, control, 0)," &
+ "24 ( BC_4, RA7, input, X)," &
+ "25 ( BC_1, RA7, output3, X, 26, 0, Z)," &
+ "26 ( BC_2, *, control, 0)," &
+ "27 ( BC_4, RA6, input, X)," &
+ "28 ( BC_1, RA6, output3, X, 29, 0, Z)," &
+ "29 ( BC_2, *, control, 0)," &
+ "30 ( BC_4, RG0, input, X)," &
+ "31 ( BC_1, RG0, output3, X, 32, 0, Z)," &
+ "32 ( BC_2, *, control, 0)," &
+ "33 ( BC_4, RG1, input, X)," &
+ "34 ( BC_1, RG1, output3, X, 35, 0, Z)," &
+ "35 ( BC_2, *, control, 0)," &
+ "36 ( BC_4, RF1, input, X)," &
+ "37 ( BC_1, RF1, output3, X, 38, 0, Z)," &
+ "38 ( BC_2, *, control, 0)," &
+ "39 ( BC_4, RF0, input, X)," &
+ "40 ( BC_1, RF0, output3, X, 41, 0, Z)," &
+ "41 ( BC_2, *, control, 0)," &
+ "42 ( BC_4, RD7, input, X)," &
+ "43 ( BC_1, RD7, output3, X, 44, 0, Z)," &
+ "44 ( BC_2, *, control, 0)," &
+ "45 ( BC_4, RD6, input, X)," &
+ "46 ( BC_1, RD6, output3, X, 47, 0, Z)," &
+ "47 ( BC_2, *, control, 0)," &
+ "48 ( BC_4, RD5, input, X)," &
+ "49 ( BC_1, RD5, output3, X, 50, 0, Z)," &
+ "50 ( BC_2, *, control, 0)," &
+ "51 ( BC_4, RD4, input, X)," &
+ "52 ( BC_1, RD4, output3, X, 53, 0, Z)," &
+ "53 ( BC_2, *, control, 0)," &
+ "54 ( BC_4, RD13, input, X)," &
+ "55 ( BC_1, RD13, output3, X, 56, 0, Z)," &
+ "56 ( BC_2, *, control, 0)," &
+ "57 ( BC_4, RD12, input, X)," &
+ "58 ( BC_1, RD12, output3, X, 59, 0, Z)," &
+ "59 ( BC_2, *, control, 0)," &
+ "60 ( BC_4, RD3, input, X)," &
+ "61 ( BC_1, RD3, output3, X, 62, 0, Z)," &
+ "62 ( BC_2, *, control, 0)," &
+ "63 ( BC_4, RD2, input, X)," &
+ "64 ( BC_1, RD2, output3, X, 65, 0, Z)," &
+ "65 ( BC_2, *, control, 0)," &
+ "66 ( BC_4, RD1, input, X)," &
+ "67 ( BC_1, RD1, output3, X, 68, 0, Z)," &
+ "68 ( BC_2, *, control, 0)," &
+ "69 ( BC_4, RC14, input, X)," &
+ "70 ( BC_1, RC14, output3, X, 71, 0, Z)," &
+ "71 ( BC_2, *, control, 0)," &
+ "72 ( BC_4, RC13, input, X)," &
+ "73 ( BC_1, RC13, output3, X, 74, 0, Z)," &
+ "74 ( BC_2, *, control, 0)," &
+ "75 ( BC_4, RD0, input, X)," &
+ "76 ( BC_1, RD0, output3, X, 77, 0, Z)," &
+ "77 ( BC_2, *, control, 0)," &
+ "78 ( BC_4, RD11, input, X)," &
+ "79 ( BC_1, RD11, output3, X, 80, 0, Z)," &
+ "80 ( BC_2, *, control, 0)," &
+ "81 ( BC_4, RD10, input, X)," &
+ "82 ( BC_1, RD10, output3, X, 83, 0, Z)," &
+ "83 ( BC_2, *, control, 0)," &
+ "84 ( BC_4, RD9, input, X)," &
+ "85 ( BC_1, RD9, output3, X, 86, 0, Z)," &
+ "86 ( BC_2, *, control, 0)," &
+ "87 ( BC_4, RD8, input, X)," &
+ "88 ( BC_1, RD8, output3, X, 89, 0, Z)," &
+ "89 ( BC_2, *, control, 0)," &
+ "90 ( BC_4, RA15, input, X)," &
+ "91 ( BC_1, RA15, output3, X, 92, 0, Z)," &
+ "92 ( BC_2, *, control, 0)," &
+ "93 ( BC_4, RA14, input, X)," &
+ "94 ( BC_1, RA14, output3, X, 95, 0, Z)," &
+ "95 ( BC_2, *, control, 0)," &
+ "96 ( BC_4, RC15, input, X)," &
+ "97 ( BC_1, RC15, output3, X, 98, 0, Z)," &
+ "98 ( BC_2, *, control, 0)," &
+ "99 ( BC_4, RC12, input, X)," &
+ "100 ( BC_1, RC12, output3, X, 101, 0, Z)," &
+ "101 ( BC_2, *, control, 0)," &
+ "102 ( BC_4, RA3, input, X)," &
+ "103 ( BC_1, RA3, output3, X, 104, 0, Z)," &
+ "104 ( BC_2, *, control, 0)," &
+ "105 ( BC_4, RA2, input, X)," &
+ "106 ( BC_1, RA2, output3, X, 107, 0, Z)," &
+ "107 ( BC_2, *, control, 0)," &
+ "108 ( BC_4, USBDP, input, X)," &
+ "109 ( BC_1, USBDP, output3, X, 110, 0, Z)," &
+ "110 ( BC_2, *, control, 0)," &
+ "111 ( BC_4, USBDM, input, X)," &
+ "112 ( BC_1, USBDM, output3, X, 110, 0, Z)," &
+ "113 ( BC_4, RF8, input, X)," &
+ "114 ( BC_1, RF8, output3, X, 115, 0, Z)," &
+ "115 ( BC_2, *, control, 0)," &
+ "116 ( BC_4, RF2, input, X)," &
+ "117 ( BC_1, RF2, output3, X, 118, 0, Z)," &
+ "118 ( BC_2, *, control, 0)," &
+ "119 ( BC_4, RF3, input, X)," &
+ "120 ( BC_1, RF3, output3, X, 121, 0, Z)," &
+ "121 ( BC_2, *, control, 0)," &
+ "122 ( BC_4, RF5, input, X)," &
+ "123 ( BC_1, RF5, output3, X, 124, 0, Z)," &
+ "124 ( BC_2, *, control, 0)," &
+ "125 ( BC_4, RF4, input, X)," &
+ "126 ( BC_1, RF4, output3, X, 127, 0, Z)," &
+ "127 ( BC_2, *, control, 0)," &
+ "128 ( BC_4, RD15, input, X)," &
+ "129 ( BC_1, RD15, output3, X, 130, 0, Z)," &
+ "130 ( BC_2, *, control, 0)," &
+ "131 ( BC_4, RD14, input, X)," &
+ "132 ( BC_1, RD14, output3, X, 133, 0, Z)," &
+ "133 ( BC_2, *, control, 0)," &
+ "134 ( BC_4, RB15, input, X)," &
+ "135 ( BC_1, RB15, output3, X, 136, 0, Z)," &
+ "136 ( BC_2, *, control, 0)," &
+ "137 ( BC_4, RB14, input, X)," &
+ "138 ( BC_1, RB14, output3, X, 139, 0, Z)," &
+ "139 ( BC_2, *, control, 0)," &
+ "140 ( BC_4, RB13, input, X)," &
+ "141 ( BC_1, RB13, output3, X, 142, 0, Z)," &
+ "142 ( BC_2, *, control, 0)," &
+ "143 ( BC_4, RB12, input, X)," &
+ "144 ( BC_1, RB12, output3, X, 145, 0, Z)," &
+ "145 ( BC_2, *, control, 0)," &
+ "146 ( BC_4, RF12, input, X)," &
+ "147 ( BC_1, RF12, output3, X, 148, 0, Z)," &
+ "148 ( BC_2, *, control, 0)," &
+ "149 ( BC_4, RF13, input, X)," &
+ "150 ( BC_1, RF13, output3, X, 151, 0, Z)," &
+ "151 ( BC_2, *, control, 0)," &
+ "152 ( BC_4, RB11, input, X)," &
+ "153 ( BC_1, RB11, output3, X, 154, 0, Z)," &
+ "154 ( BC_2, *, control, 0)," &
+ "155 ( BC_4, RB10, input, X)," &
+ "156 ( BC_1, RB10, output3, X, 157, 0, Z)," &
+ "157 ( BC_2, *, control, 0)," &
+ "158 ( BC_4, RB9, input, X)," &
+ "159 ( BC_1, RB9, output3, X, 160, 0, Z)," &
+ "160 ( BC_2, *, control, 0)," &
+ "161 ( BC_4, RB8, input, X)," &
+ "162 ( BC_1, RB8, output3, X, 163, 0, Z)," &
+ "163 ( BC_2, *, control, 0)," &
+ "164 ( BC_4, RA10, input, X)," &
+ "165 ( BC_1, RA10, output3, X, 166, 0, Z)," &
+ "166 ( BC_2, *, control, 0)," &
+ "167 ( BC_4, RA9, input, X)," &
+ "168 ( BC_1, RA9, output3, X, 169, 0, Z)," &
+ "169 ( BC_2, *, control, 0)," &
+ "170 ( BC_4, RB7, input, X)," &
+ "171 ( BC_1, RB7, output3, X, 172, 0, Z)," &
+ "172 ( BC_2, *, control, 0)," &
+ "173 ( BC_4, RB6, input, X)," &
+ "174 ( BC_1, RB6, output3, X, 175, 0, Z)," &
+ "175 ( BC_2, *, control, 0)," &
+ "176 ( BC_4, RB0, input, X)," &
+ "177 ( BC_1, RB0, output3, X, 178, 0, Z)," &
+ "178 ( BC_2, *, control, 0)," &
+ "179 ( BC_4, RB1, input, X)," &
+ "180 ( BC_1, RB1, output3, X, 181, 0, Z)," &
+ "181 ( BC_2, *, control, 0)," &
+ "182 ( BC_4, RB2, input, X)," &
+ "183 ( BC_1, RB2, output3, X, 184, 0, Z)," &
+ "184 ( BC_2, *, control, 0)," &
+ "185 ( BC_4, RB3, input, X)," &
+ "186 ( BC_1, RB3, output3, X, 187, 0, Z)," &
+ "187 ( BC_2, *, control, 0)," &
+ "188 ( BC_4, RB4, input, X)," &
+ "189 ( BC_1, RB4, output3, X, 190, 0, Z)," &
+ "190 ( BC_2, *, control, 0)," &
+ "191 ( BC_4, RB5, input, X)," &
+ "192 ( BC_1, RB5, output3, X, 193, 0, Z)," &
+ "193 ( BC_2, *, control, 0)," &
+ "194 ( BC_4, RE9, input, X)," &
+ "195 ( BC_1, RE9, output3, X, 196, 0, Z)," &
+ "196 ( BC_2, *, control, 0)," &
+ "197 ( BC_4, RE8, input, X)," &
+ "198 ( BC_1, RE8, output3, X, 199, 0, Z)," &
+ "199 ( BC_2, *, control, 0)," &
+ "200 ( BC_4, RG9, input, X)," &
+ "201 ( BC_1, RG9, output3, X, 202, 0, Z)," &
+ "202 ( BC_2, *, control, 0)," &
+ "203 ( BC_4, MCLR, input, X)," &
+ "204 ( BC_4, RG8, input, X)," &
+ "205 ( BC_1, RG8, output3, X, 206, 0, Z)," &
+ "206 ( BC_2, *, control, 0)," &
+ "207 ( BC_4, RG7, input, X)," &
+ "208 ( BC_1, RG7, output3, X, 209, 0, Z)," &
+ "209 ( BC_2, *, control, 0)," &
+ "210 ( BC_4, RG6, input, X)," &
+ "211 ( BC_1, RG6, output3, X, 212, 0, Z)," &
+ "212 ( BC_2, *, control, 0)," &
+ "213 ( BC_4, RC4, input, X)," &
+ "214 ( BC_1, RC4, output3, X, 215, 0, Z)," &
+ "215 ( BC_2, *, control, 0)," &
+ "216 ( BC_4, RC3, input, X)," &
+ "217 ( BC_1, RC3, output3, X, 218, 0, Z)," &
+ "218 ( BC_2, *, control, 0)," &
+ "219 ( BC_4, RC2, input, X)," &
+ "220 ( BC_1, RC2, output3, X, 221, 0, Z)," &
+ "221 ( BC_2, *, control, 0)," &
+ "222 ( BC_4, RC1, input, X)," &
+ "223 ( BC_1, RC1, output3, X, 224, 0, Z)," &
+ "224 ( BC_2, *, control, 0)," &
+ "225 ( BC_4, RE7, input, X)," &
+ "226 ( BC_1, RE7, output3, X, 227, 0, Z)," &
+ "227 ( BC_2, *, control, 0)," &
+ "228 ( BC_4, RE6, input, X)," &
+ "229 ( BC_1, RE6, output3, X, 230, 0, Z)," &
+ "230 ( BC_2, *, control, 0)," &
+ "231 ( BC_4, RE5, input, X)," &
+ "232 ( BC_1, RE5, output3, X, 233, 0, Z)," &
+ "233 ( BC_2, *, control, 0)," &
+ "234 ( BC_4, RG15, input, X)," &
+ "235 ( BC_1, RG15, output3, X, 236, 0, Z)," &
+ "236 ( BC_2, *, control, 0)";
+
+ end PIC32MX795F512L;
+
+
diff --git a/STM32F302_F303_B_C_LQFP100.bsd b/STM32F302_F303_B_C_LQFP100.bsd new file mode 100644 index 0000000..a48783e --- /dev/null +++ b/STM32F302_F303_B_C_LQFP100.bsd @@ -0,0 +1,572 @@ +-- ****************** (C) COPYRIGHT 2015 STMicroelectronics **************************
+-- * File Name : STM32F302_F303_B_C_LQFP100.bsd *
+-- * Author : STMicroelectronics www.st.com *
+-- * Version : V1.0 *
+-- * Date : 13-August-2015 *
+-- * Description : Boundary Scan Description Language (BSDL) file for the *
+-- * STM32F302_F303_B_C_LQFP100 Microcontrollers. *
+-- ***********************************************************************************
+-- * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS *
+-- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.*
+-- * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, *
+-- * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE *
+-- * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING *
+-- * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. *
+-- ***********************************************************************************
+-- * This BSDL file has been syntaxed checked and validated by: *
+-- * GOEPEL SyntaxChecker Version 3.1.2 *
+-- ***********************************************************************************
+
+
+ entity STM32F302_F303_B_C_LQFP100 is
+ -- This section identifies the default device package selected.
+ generic (PHYSICAL_PIN_MAP: string:= "LQFP100_PACKAGE");
+ -- This section declares all the ports in the design.
+ port (
+ BOOT0 : in bit;
+ JTDI : in bit;
+ JTMS : in bit;
+ JTCK : in bit;
+ JTRST : in bit;
+ JTDO : out bit;
+ NRST : in bit; -- modification to add COMPLIANCE_PATTERNS
+ PA0 : inout bit;
+ PA1 : inout bit;
+ PA2 : inout bit;
+ PA3 : inout bit;
+ PF4 : inout bit;
+ PA4 : inout bit;
+ PA5 : inout bit;
+ PA6 : inout bit;
+ PA7 : inout bit;
+ PA8 : inout bit;
+ PA9 : inout bit;
+ PA10 : inout bit;
+ PA11 : inout bit;
+ PA12 : inout bit;
+ PB0 : inout bit;
+ PB1 : inout bit;
+ PB2 : inout bit;
+ PB5 : inout bit;
+ PB6 : inout bit;
+ PB7 : inout bit;
+ PB8 : inout bit;
+ PB9 : inout bit;
+ PB10 : inout bit;
+ PB11 : inout bit;
+ PB12 : inout bit;
+ PB13 : inout bit;
+ PB14 : inout bit;
+ PB15 : inout bit;
+ PC0 : inout bit;
+ PC1 : inout bit;
+ PC2 : inout bit;
+ PC3 : inout bit;
+ PC4 : inout bit;
+ PC5 : inout bit;
+ PC6 : inout bit;
+ PC7 : inout bit;
+ PC8 : inout bit;
+ PC9 : inout bit;
+ PC10 : inout bit;
+ PC11 : inout bit;
+ PC12 : inout bit;
+ PC13 : inout bit;
+ PC14_OSC32IN : inout bit;
+ PC15_OSC32OUT : inout bit;
+ PD0 : inout bit;
+ PD1 : inout bit;
+ PD2 : inout bit;
+ PD3 : inout bit;
+ PD4 : inout bit;
+ PD5 : inout bit;
+ PD6 : inout bit;
+ PD7 : inout bit;
+ PD8 : inout bit;
+ PD9 : inout bit;
+ PD10 : inout bit;
+ PD11 : inout bit;
+ PD12 : inout bit;
+ PD13 : inout bit;
+ PD14 : inout bit;
+ PD15 : inout bit;
+ PE0 : inout bit;
+ PE1 : inout bit;
+ PE2 : inout bit;
+ PE3 : inout bit;
+ PE4 : inout bit;
+ PE5 : inout bit;
+ PE6 : inout bit;
+ PE7 : inout bit;
+ PE8 : inout bit;
+ PE9 : inout bit;
+ PE10 : inout bit;
+ PE11 : inout bit;
+ PE12 : inout bit;
+ PE13 : inout bit;
+ PE14 : inout bit;
+ PE15 : inout bit;
+ PF0_OSCIN : inout bit;
+ PF1_OSCOUT : inout bit;
+ PF2 : inout bit;
+ PF6 : inout bit;
+ PF9 : inout bit;
+ PF10 : inout bit;
+ VDDA : linkage bit;
+ VSSA : linkage bit;
+ VREF_PLUS : linkage bit;
+ VBAT : linkage bit;
+ VDD : linkage bit_vector(1 to 4);
+ VSS : linkage bit_vector(1 to 3)
+);
+----------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+ use STD_1149_1_2001.all;
+
+ attribute COMPONENT_CONFORMANCE of STM32F302_F303_B_C_LQFP100: entity is "STD_1149_1_2001";
+
+ attribute PIN_MAP of STM32F302_F303_B_C_LQFP100 : entity is PHYSICAL_PIN_MAP;
+
+-- This section specifies the pin map for each port. This information is extracted from the
+-- port-to-pin map file that was read in using the "read_pin_map" command.
+
+ constant LQFP100_PACKAGE: PIN_MAP_STRING :=
+ "BOOT0 : 94," &
+ "JTDI : 77," &
+ "JTMS : 72," &
+ "JTCK : 76," &
+ "JTRST : 90," &
+ "JTDO : 89," &
+ "NRST : 14," &
+ "PA0 : 23," &
+ "PA1 : 24," &
+ "PA2 : 25," &
+ "PA3 : 26," &
+ "PF4 : 27," &
+ "PA4 : 29," &
+ "PA5 : 30," &
+ "PA6 : 31," &
+ "PA7 : 32," &
+ "PA8 : 67," &
+ "PA9 : 68," &
+ "PA10 : 69," &
+ "PA11 : 70," &
+ "PA12 : 71," &
+ "PB0 : 35," &
+ "PB1 : 36," &
+ "PB2 : 37," &
+ "PB5 : 91," &
+ "PB6 : 92," &
+ "PB7 : 93," &
+ "PB8 : 95," &
+ "PB9 : 96," &
+ "PB10 : 47," &
+ "PB11 : 48," &
+ "PB12 : 51," &
+ "PB13 : 52," &
+ "PB14 : 53," &
+ "PB15 : 54," &
+ "PC0 : 15," &
+ "PC1 : 16," &
+ "PC2 : 17," &
+ "PC3 : 18," &
+ "PF2 : 19," &
+ "PC4 : 33," &
+ "PC5 : 34," &
+ "PC6 : 63," &
+ "PC7 : 64," &
+ "PC8 : 65," &
+ "PC9 : 66," &
+ "PC10 : 78," &
+ "PC11 : 79," &
+ "PC12 : 80," &
+ "PC13 : 7," &
+ "PC14_OSC32IN : 8," &
+ "PC15_OSC32OUT : 9," &
+ "PD0 : 81," &
+ "PD1 : 82," &
+ "PD2 : 83," &
+ "PD3 : 84," &
+ "PD4 : 85," &
+ "PD5 : 86," &
+ "PD6 : 87," &
+ "PD7 : 88," &
+ "PD8 : 55," &
+ "PD9 : 56," &
+ "PD10 : 57," &
+ "PD11 : 58," &
+ "PD12 : 59," &
+ "PD13 : 60," &
+ "PD14 : 61," &
+ "PD15 : 62," &
+ "PE0 : 97," &
+ "PE1 : 98," &
+ "PE2 : 1," &
+ "PE3 : 2," &
+ "PE4 : 3," &
+ "PE5 : 4," &
+ "PE6 : 5," &
+ "PE7 : 38," &
+ "PE8 : 39," &
+ "PE9 : 40," &
+ "PE10 : 41," &
+ "PE11 : 42," &
+ "PE12 : 43," &
+ "PE13 : 44," &
+ "PE14 : 45," &
+ "PE15 : 46," &
+ "PF0_OSCIN : 12," &
+ "PF1_OSCOUT : 13," &
+ "PF6 : 73," &
+ "PF9 : 10," &
+ "PF10 : 11," &
+ "VDDA : 22," &
+ "VSSA : 20," &
+ "VREF_PLUS : 21," &
+ "VBAT : 6," &
+ "VDD : (28, 50, 75, 100)," &
+ "VSS : (49, 74, 99)" ;
+
+-- This section specifies the TAP ports. For the TAP TCK port, the parameters in the brackets are:
+-- First Field : Maximum TCK frequency.
+-- Second Field: Allowable states TCK may be stopped in.
+
+ attribute TAP_SCAN_CLOCK of JTCK : signal is (10.0e6, BOTH);
+ attribute TAP_SCAN_IN of JTDI : signal is true;
+ attribute TAP_SCAN_MODE of JTMS : signal is true;
+ attribute TAP_SCAN_OUT of JTDO : signal is true;
+ attribute TAP_SCAN_RESET of JTRST : signal is true;
+
+-- Specifies the compliance enable patterns for the design. It lists a set of
+-- design ports and the values that they should be set to, in order to enable
+-- compliance to IEEE Std 1149.1
+
+
+ attribute COMPLIANCE_PATTERNS of STM32F302_F303_B_C_LQFP100: entity is
+ "(NRST) (0)";
+
+
+-- Specifies the number of bits in the instruction register.
+
+ attribute INSTRUCTION_LENGTH of STM32F302_F303_B_C_LQFP100: entity is 5;
+
+-- Specifies the boundary-scan instructions implemented in the design and their opcodes.
+
+ attribute INSTRUCTION_OPCODE of STM32F302_F303_B_C_LQFP100: entity is
+ "BYPASS (11111)," &
+ "EXTEST (00000)," &
+ "SAMPLE (00010)," &
+ "PRELOAD (00010)," &
+ "IDCODE (00001)";
+
+-- Specifies the bit pattern that is loaded into the instruction register when the TAP controller
+-- passes through the Capture-IR state. The standard mandates that the two LSBs must be "01". The
+-- remaining bits are design specific.
+
+ attribute INSTRUCTION_CAPTURE of STM32F302_F303_B_C_LQFP100: entity is "XXX01";
+
+-- Specifies the bit pattern that is loaded into the DEVICE_ID register during the IDCODE
+-- instruction when the TAP controller passes through the Capture-DR state.
+
+ attribute IDCODE_REGISTER of STM32F302_F303_B_C_LQFP100: entity is
+ "XXXX" & -- 4-bit version number
+ "0110010000100010" & -- 16-bit part number
+ "00000100000" & -- 11-bit identity of the manufacturer
+ "1"; -- Required by IEEE Std 1149.1
+
+ -- This section specifies the test data register placed between TDI and TDO for each implemented
+-- instruction.
+
+ attribute REGISTER_ACCESS of STM32F302_F303_B_C_LQFP100: entity is
+ "BYPASS (BYPASS)," &
+ "BOUNDARY (EXTEST, SAMPLE, PRELOAD)," &
+ "DEVICE_ID (IDCODE)";
+
+-- Specifies the length of the boundary scan register.
+
+ attribute BOUNDARY_LENGTH of STM32F302_F303_B_C_LQFP100: entity is 250;
+
+-- The following list specifies the characteristics of each cell in the boundary scan register from
+-- TDI to TDO. The following is a description of the label fields:
+-- num : Is the cell number.
+-- cell : Is the cell type as defined by the standard.
+-- port : Is the design port name. Control cells do not have a port name.
+-- function: Is the function of the cell as defined by the standard. Is one of input, output2,
+-- output3, bidir, control or controlr.
+-- safe : Specifies the value that the BSR cell should be loaded with for safe operation
+-- when the software might otherwise choose a random value.
+-- ccell : The control cell number. Specifies the control cell that drives the output enable
+-- for this port.
+-- disval : Specifies the value that is loaded into the control cell to disable the output
+-- enable for the corresponding port.
+-- rslt : Resulting state. Shows the state of the driver when it is disabled.
+
+ attribute BOUNDARY_REGISTER of STM32F302_F303_B_C_LQFP100: entity is
+--
+-- num cell port function safe [ccell disval rslt]
+--
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+ "249 (BC_1, *, CONTROL, 1), " &
+ "248 (BC_1, PE2, OUTPUT3, X, 249, 1, Z), " &
+ "247 (BC_4, PE2, INPUT, X), " &
+ "246 (BC_1, *, CONTROL, 1), " &
+ "245 (BC_1, PE3, OUTPUT3, X, 246, 1, Z), " &
+ "244 (BC_4, PE3, INPUT, X), " &
+ "243 (BC_1, *, CONTROL, 1), " &
+ "242 (BC_1, PE4, OUTPUT3, X, 243, 1, Z), " &
+ "241 (BC_4, PE4, INPUT, X), " &
+ "240 (BC_1, *, CONTROL, 1), " &
+ "239 (BC_1, PE5, OUTPUT3, X, 240, 1, Z), " &
+ "238 (BC_4, PE5, INPUT, X), " &
+ "237 (BC_1, *, CONTROL, 1), " &
+ "236 (BC_1, PE6, OUTPUT3, X, 237, 1, Z), " &
+ "235 (BC_4, PE6, INPUT, X), " &
+ "234 (BC_1, *, CONTROL, 1), " &
+ "233 (BC_1, PC13, OUTPUT3, X, 234, 1, Z), " &
+ "232 (BC_4, PC13, INPUT, X), " &
+ "231 (BC_1, *, CONTROL, 1), " &
+ "230 (BC_1, PC14_OSC32IN, OUTPUT3, X, 231, 1, Z), " &
+ "229 (BC_4, PC14_OSC32IN, INPUT, X), " &
+ "228 (BC_1, *, CONTROL, 1), " &
+ "227 (BC_1, PC15_OSC32OUT, OUTPUT3, X, 228, 1, Z), " &
+ "226 (BC_4, PC15_OSC32OUT, INPUT, X), " &
+ "225 (BC_1, *, CONTROL, 1), " &
+ "224 (BC_1, PF9, OUTPUT3, X, 225, 1, Z), " &
+ "223 (BC_4, PF9, INPUT, X), " &
+ "222 (BC_1, *, CONTROL, 1), " &
+ "221 (BC_1, PF10, OUTPUT3, X, 222, 1, Z), " &
+ "220 (BC_4, PF10, INPUT, X), " &
+ "219 (BC_1, *, CONTROL, 1), " &
+ "218 (BC_1, PF0_OSCIN, OUTPUT3, X, 219, 1, Z), " &
+ "217 (BC_4, PF0_OSCIN, INPUT, X), " &
+ "216 (BC_1, *, CONTROL, 1), " &
+ "215 (BC_1, PF1_OSCOUT, OUTPUT3, X, 216, 1, Z), " &
+ "214 (BC_4, PF1_OSCOUT, INPUT, X), " &
+ "213 (BC_1, *, CONTROL, 1), " &
+ "212 (BC_1, PC0, OUTPUT3, X, 213, 1, Z), " &
+ "211 (BC_4, PC0, INPUT, X), " &
+ "210 (BC_1, *, CONTROL, 1), " &
+ "209 (BC_1, PC1, OUTPUT3, X, 210, 1, Z), " &
+ "208 (BC_4, PC1, INPUT, X), " &
+ "207 (BC_1, *, CONTROL, 1), " &
+ "206 (BC_1, PC2, OUTPUT3, X, 207, 1, Z), " &
+ "205 (BC_4, PC2, INPUT, X), " &
+ "204 (BC_1, *, CONTROL, 1), " &
+ "203 (BC_1, PC3, OUTPUT3, X, 204, 1, Z), " &
+ "202 (BC_4, PC3, INPUT, X), " &
+ "201 (BC_1, *, CONTROL, 1), " &
+ "200 (BC_1, PF2, OUTPUT3, X, 201, 1, Z), " &
+ "199 (BC_4, PF2, INPUT, X), " &
+ "198 (BC_1, *, CONTROL, 1), " &
+ "197 (BC_1, PA0, OUTPUT3, X, 198, 1, Z), " &
+ "196 (BC_4, PA0, INPUT, X), " &
+ "195 (BC_1, *, CONTROL, 1), " &
+ "194 (BC_1, PA1, OUTPUT3, X, 195, 1, Z), " &
+ "193 (BC_4, PA1, INPUT, X), " &
+ "192 (BC_1, *, CONTROL, 1), " &
+ "191 (BC_1, PA2, OUTPUT3, X, 192, 1, Z), " &
+ "190 (BC_4, PA2, INPUT, X), " &
+ "189 (BC_1, *, CONTROL, 1), " &
+ "188 (BC_1, PA3, OUTPUT3, X, 189, 1, Z), " &
+ "187 (BC_4, PA3, INPUT, X), " &
+ "186 (BC_1, *, CONTROL, 1), " &
+ "185 (BC_1, PF4, OUTPUT3, X, 186, 1, Z), " &
+ "184 (BC_4, PF4, INPUT, X), " &
+ "183 (BC_1, *, CONTROL, 1), " &
+ "182 (BC_1, PA4, OUTPUT3, X, 183, 1, Z), " &
+ "181 (BC_4, PA4, INPUT, X), " &
+ "180 (BC_1, *, CONTROL, 1), " &
+ "179 (BC_1, PA5, OUTPUT3, X, 180, 1, Z), " &
+ "178 (BC_4, PA5, INPUT, X), " &
+ "177 (BC_1, *, CONTROL, 1), " &
+ "176 (BC_1, PA6, OUTPUT3, X, 177, 1, Z), " &
+ "175 (BC_4, PA6, INPUT, X), " &
+ "174 (BC_1, *, CONTROL, 1), " &
+ "173 (BC_1, PA7, OUTPUT3, X, 174, 1, Z), " &
+ "172 (BC_4, PA7, INPUT, X), " &
+ "171 (BC_1, *, CONTROL, 1), " &
+ "170 (BC_1, PC4, OUTPUT3, X, 171, 1, Z), " &
+ "169 (BC_4, PC4, INPUT, X), " &
+ "168 (BC_1, *, CONTROL, 1), " &
+ "167 (BC_1, PC5, OUTPUT3, X, 168, 1, Z), " &
+ "166 (BC_4, PC5, INPUT, X), " &
+ "165 (BC_1, *, CONTROL, 1), " &
+ "164 (BC_1, PB0, OUTPUT3, X, 165, 1, Z), " &
+ "163 (BC_4, PB0, INPUT, X), " &
+ "162 (BC_1, *, CONTROL, 1), " &
+ "161 (BC_1, PB1, OUTPUT3, X, 162, 1, Z), " &
+ "160 (BC_4, PB1, INPUT, X), " &
+ "159 (BC_1, *, CONTROL, 1), " &
+ "158 (BC_1, PB2, OUTPUT3, X, 159, 1, Z), " &
+ "157 (BC_4, PB2, INPUT, X), " &
+ "156 (BC_1, *, CONTROL, 1), " &
+ "155 (BC_1, PE7, OUTPUT3, X, 156, 1, Z), " &
+ "154 (BC_4, PE7, INPUT, X), " &
+ "153 (BC_1, *, CONTROL, 1), " &
+ "152 (BC_1, PE8, OUTPUT3, X, 153, 1, Z), " &
+ "151 (BC_4, PE8, INPUT, X), " &
+ "150 (BC_1, *, CONTROL, 1), " &
+ "149 (BC_1, PE9, OUTPUT3, X, 150, 1, Z), " &
+ "148 (BC_4, PE9, INPUT, X), " &
+ "147 (BC_1, *, CONTROL, 1), " &
+ "146 (BC_1, PE10, OUTPUT3, X, 147, 1, Z), " &
+ "145 (BC_4, PE10, INPUT, X), " &
+ "144 (BC_1, *, CONTROL, 1), " &
+ "143 (BC_1, PE11, OUTPUT3, X, 144, 1, Z), " &
+ "142 (BC_4, PE11, INPUT, X), " &
+ "141 (BC_1, *, CONTROL, 1), " &
+ "140 (BC_1, PE12, OUTPUT3, X, 141, 1, Z), " &
+ "139 (BC_4, PE12, INPUT, X), " &
+ "138 (BC_1, *, CONTROL, 1), " &
+ "137 (BC_1, PE13, OUTPUT3, X, 138, 1, Z), " &
+ "136 (BC_4, PE13, INPUT, X), " &
+ "135 (BC_1, *, CONTROL, 1), " &
+ "134 (BC_1, PE14, OUTPUT3, X, 135, 1, Z), " &
+ "133 (BC_4, PE14, INPUT, X), " &
+ "132 (BC_1, *, CONTROL, 1), " &
+ "131 (BC_1, PE15, OUTPUT3, X, 132, 1, Z), " &
+ "130 (BC_4, PE15, INPUT, X), " &
+ "129 (BC_1, *, CONTROL, 1), " &
+ "128 (BC_1, PB10, OUTPUT3, X, 129, 1, Z), " &
+ "127 (BC_4, PB10, INPUT, X), " &
+ "126 (BC_1, *, CONTROL, 1), " &
+ "125 (BC_1, PB11, OUTPUT3, X, 126, 1, Z), " &
+ "124 (BC_4, PB11, INPUT, X), " &
+ "123 (BC_1, *, internal, 0 )," &
+ "122 (BC_1, *, internal, 0 )," &
+ "121 (BC_1, *, internal, 0 )," &
+ "120 (BC_1, *, CONTROL, 1), " &
+ "119 (BC_1, PB12, OUTPUT3, X, 120, 1, Z), " &
+ "118 (BC_4, PB12, INPUT, X), " &
+ "117 (BC_1, *, CONTROL, 1), " &
+ "116 (BC_1, PB13, OUTPUT3, X, 117, 1, Z), " &
+ "115 (BC_4, PB13, INPUT, X), " &
+ "114 (BC_1, *, CONTROL, 1), " &
+ "113 (BC_1, PB14, OUTPUT3, X, 114, 1, Z), " &
+ "112 (BC_4, PB14, INPUT, X), " &
+ "111 (BC_1, *, CONTROL, 1), " &
+ "110 (BC_1, PB15, OUTPUT3, X, 111, 1, Z), " &
+ "109 (BC_4, PB15, INPUT, X), " &
+ "108 (BC_1, *, CONTROL, 1), " &
+ "107 (BC_1, PD8, OUTPUT3, X, 108, 1, Z), " &
+ "106 (BC_4, PD8, INPUT, X), " &
+ "105 (BC_1, *, CONTROL, 1), " &
+ "104 (BC_1, PD9, OUTPUT3, X, 105, 1, Z), " &
+ "103 (BC_4, PD9, INPUT, X), " &
+ "102 (BC_1, *, CONTROL, 1), " &
+ "101 (BC_1, PD10, OUTPUT3, X, 102, 1, Z), " &
+ "100 (BC_4, PD10, INPUT, X), " &
+ "99 (BC_1, *, CONTROL, 1), " &
+ "98 (BC_1, PD11, OUTPUT3, X, 99, 1, Z), " &
+ "97 (BC_4, PD11, INPUT, X), " &
+ "96 (BC_1, *, CONTROL, 1), " &
+ "95 (BC_1, PD12, OUTPUT3, X, 96, 1, Z), " &
+ "94 (BC_4, PD12, INPUT, X), " &
+ "93 (BC_1, *, CONTROL, 1), " &
+ "92 (BC_1, PD13, OUTPUT3, X, 93, 1, Z), " &
+ "91 (BC_4, PD13, INPUT, X), " &
+ "90 (BC_1, *, CONTROL, 1), " &
+ "89 (BC_1, PD14, OUTPUT3, X, 90, 1, Z), " &
+ "88 (BC_4, PD14, INPUT, X), " &
+ "87 (BC_1, *, CONTROL, 1), " &
+ "86 (BC_1, PD15, OUTPUT3, X, 87, 1, Z), " &
+ "85 (BC_4, PD15, INPUT, X), " &
+ "84 (BC_1, *, CONTROL, 1), " &
+ "83 (BC_1, PC6, OUTPUT3, X, 84, 1, Z), " &
+ "82 (BC_4, PC6, INPUT, X), " &
+ "81 (BC_1, *, CONTROL, 1), " &
+ "80 (BC_1, PC7, OUTPUT3, X, 81, 1, Z), " &
+ "79 (BC_4, PC7, INPUT, X), " &
+ "78 (BC_1, *, CONTROL, 1), " &
+ "77 (BC_1, PC8, OUTPUT3, X, 78, 1, Z), " &
+ "76 (BC_4, PC8, INPUT, X), " &
+ "75 (BC_1, *, CONTROL, 1), " &
+ "74 (BC_1, PC9, OUTPUT3, X, 75, 1, Z), " &
+ "73 (BC_4, PC9, INPUT, X), " &
+ "72 (BC_1, *, CONTROL, 1), " &
+ "71 (BC_1, PA8, OUTPUT3, X, 72, 1, Z), " &
+ "70 (BC_4, PA8, INPUT, X), " &
+ "69 (BC_1, *, CONTROL, 1), " &
+ "68 (BC_1, PA9, OUTPUT3, X, 69, 1, Z), " &
+ "67 (BC_4, PA9, INPUT, X), " &
+ "66 (BC_1, *, CONTROL, 1), " &
+ "65 (BC_1, PA10, OUTPUT3, X, 66, 1, Z), " &
+ "64 (BC_4, PA10, INPUT, X), " &
+ "63 (BC_1, *, CONTROL, 1), " &
+ "62 (BC_1, PA11, OUTPUT3, X, 63, 1, Z), " &
+ "61 (BC_4, PA11, INPUT, X), " &
+ "60 (BC_1, *, CONTROL, 1), " &
+ "59 (BC_1, PA12, OUTPUT3, X, 60, 1, Z), " &
+ "58 (BC_4, PA12, INPUT, X), " &
+ "57 (BC_1, *, CONTROL, 1), " &
+ "56 (BC_1, PF6, OUTPUT3, X, 57, 1, Z), " &
+ "55 (BC_4, PF6, INPUT, X), " &
+ "54 (BC_1, *, CONTROL, 1), " &
+ "53 (BC_1, PC10, OUTPUT3, X, 54, 1, Z), " &
+ "52 (BC_4, PC10, INPUT, X), " &
+ "51 (BC_1, *, CONTROL, 1), " &
+ "50 (BC_1, PC11, OUTPUT3, X, 51, 1, Z), " &
+ "49 (BC_4, PC11, INPUT, X), " &
+ "48 (BC_1, *, CONTROL, 1), " &
+ "47 (BC_1, PC12, OUTPUT3, X, 48, 1, Z), " &
+ "46 (BC_4, PC12, INPUT, X), " &
+ "45 (BC_1, *, CONTROL, 1), " &
+ "44 (BC_1, PD0, OUTPUT3, X, 45, 1, Z), " &
+ "43 (BC_4, PD0, INPUT, X), " &
+ "42 (BC_1, *, CONTROL, 1), " &
+ "41 (BC_1, PD1, OUTPUT3, X, 42, 1, Z), " &
+ "40 (BC_4, PD1, INPUT, X), " &
+ "39 (BC_1, *, CONTROL, 1), " &
+ "38 (BC_1, PD2, OUTPUT3, X, 39, 1, Z), " &
+ "37 (BC_4, PD2, INPUT, X), " &
+ "36 (BC_1, *, CONTROL, 1), " &
+ "35 (BC_1, PD3, OUTPUT3, X, 36, 1, Z), " &
+ "34 (BC_4, PD3, INPUT, X), " &
+ "33 (BC_1, *, CONTROL, 1), " &
+ "32 (BC_1, PD4, OUTPUT3, X, 33, 1, Z), " &
+ "31 (BC_4, PD4, INPUT, X), " &
+ "30 (BC_1, *, CONTROL, 1), " &
+ "29 (BC_1, PD5, OUTPUT3, X, 30, 1, Z), " &
+ "28 (BC_4, PD5, INPUT, X), " &
+ "27 (BC_1, *, CONTROL, 1), " &
+ "26 (BC_1, PD6, OUTPUT3, X, 27, 1, Z), " &
+ "25 (BC_4, PD6, INPUT, X), " &
+ "24 (BC_1, *, CONTROL, 1), " &
+ "23 (BC_1, PD7, OUTPUT3, X, 24, 1, Z), " &
+ "22 (BC_4, PD7, INPUT, X), " &
+ "21 (BC_1, *, CONTROL, 1), " &
+ "20 (BC_1, PB5, OUTPUT3, X, 21, 1, Z), " &
+ "19 (BC_4, PB5, INPUT, X), " &
+ "18 (BC_1, *, CONTROL, 1), " &
+ "17 (BC_1, PB6, OUTPUT3, X, 18, 1, Z), " &
+ "16 (BC_4, PB6, INPUT, X), " &
+ "15 (BC_1, *, CONTROL, 1), " &
+ "14 (BC_1, PB7, OUTPUT3, X, 15, 1, Z), " &
+ "13 (BC_4, PB7, INPUT, X), " &
+ "12 (BC_4, BOOT0, INPUT, X), " &
+ "11 (BC_1, *, CONTROL, 1), " &
+ "10 (BC_1, PB8, OUTPUT3, X, 11, 1, Z), " &
+ "9 (BC_4, PB8, INPUT, X), " &
+ "8 (BC_1, *, CONTROL, 1), " &
+ "7 (BC_1, PB9, OUTPUT3, X, 8, 1, Z), " &
+ "6 (BC_4, PB9, INPUT, X), " &
+ "5 (BC_1, *, CONTROL, 1), " &
+ "4 (BC_1, PE0, OUTPUT3, X, 5, 1, Z), " &
+ "3 (BC_4, PE0, INPUT, X), " &
+ "2 (BC_1, *, CONTROL, 1), " &
+ "1 (BC_1, PE1, OUTPUT3, X, 2, 1, Z), " &
+ "0 (BC_4, PE1, INPUT, X)";
+
+--------------------------------------------------------------------------------
+--------------------------------------------------------------------------------
+ attribute DESIGN_WARNING of STM32F302_F303_B_C_LQFP100: entity is
+ "Device configuration can effect boundary scan behavior. " &
+ "Keep the NRST pin low to ensure default boundary scan operation " &
+ "as described in this file." ;
+
+end STM32F302_F303_B_C_LQFP100;
+
+-- ******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE********
+
+
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