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| author | Oleksij Rempel <linux@rempel-privat.de> | 2017-09-01 11:30:11 +0200 |
|---|---|---|
| committer | Oleksij Rempel <o.rempel@pengutronix.de> | 2018-05-28 19:21:16 +0200 |
| commit | 4b49ec2faeb08462e6226273ab7ccbe04c6488f5 (patch) | |
| tree | 952e1129828fbe2dcf024cb4d14b342047f462c0 | |
| parent | 9be5ae17316df89a055741d79e8a5b4401e36f60 (diff) | |
| download | linux-4b49ec2faeb08462e6226273ab7ccbe04c6488f5.tar.gz linux-4b49ec2faeb08462e6226273ab7ccbe04c6488f5.tar.xz | |
add imx7d-m4-phyboard-zeta.dts
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
| -rw-r--r-- | arch/arm/boot/dts/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts | 54 |
2 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4d2560ab3e16..c2531c109cab 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -551,6 +551,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-sht11.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-warp.dtb +dtb-$(CONFIG_SOC_IMX7D_CM4) += \ + imx7d-m4-phyboard-zeta.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts b/arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts new file mode 100644 index 000000000000..f11b257ce758 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2015 PHYTEC America, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "imx7d-m4.dtsi" + +/ { + model = "Phytec i.MX7D Cortex M4 phyCORE"; + compatible = "fsl,imx7d-m4"; + + chosen { + stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x18000000 0x04000000>; + }; + + clk24m: clk24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clk24m"; + }; + + clk240m: clk240m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <240000000>; + clock-output-names = "clk240m"; + }; +}; + +&cpu0 { + clocks = <&clk240m>; +}; + +&gpt2 { + clocks = <&clk24m>, <&clk24m>; + clock-names = "ipg", "per"; + status = "okay"; +}; + +&uart1 { + clocks = <&clk24m>, <&clk24m>; + clock-names = "ipg", "per"; + status = "okay"; +}; |