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author | Oleksij Rempel <o.rempel@pengutronix.de> | 2018-05-30 09:39:50 +0200 |
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committer | Oleksij Rempel <o.rempel@pengutronix.de> | 2018-06-14 09:03:21 +0200 |
commit | c037b6a243f4f7b1feeb066ab406e524440b1a14 (patch) | |
tree | ba7ad8e7f7617103f4a3fdf5effa828a1527fc58 | |
parent | 52a50427312b46a0b143dbcacfd282fa77b14741 (diff) | |
download | linux-c037b6a243f4f7b1feeb066ab406e524440b1a14.tar.gz linux-c037b6a243f4f7b1feeb066ab406e524440b1a14.tar.xz |
dt-bindings: mailbox: provide imx-mailbox documentation
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
-rw-r--r-- | Documentation/devicetree/bindings/mailbox/imx-mailbox.txt | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt b/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt new file mode 100644 index 000000000000..a45604b33039 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt @@ -0,0 +1,35 @@ +i.MX Messaging Unit +=================== + +The i.MX Messaging Unit (MU) contains two register sets: "A" and "B". In most cases +they are accessible from all Processor Units. On one hand, at least for mailbox functionality, +it makes no difference which application or processor is using which set of the MU. On +other hand, the register sets for each of the MU parts are not identical. + +Required properties: +- compatible : Shell be one of: + "fsl,imx7s-mu-a" and "fsl,imx7s-mu-b" for i.MX7S or i.MX7D +- reg : physical base address of the mailbox and length of + memory mapped region. +- #mbox-cells: Common mailbox binding property to identify the number + of cells required for the mailbox specifier. Should be 1. +- interrupts : interrupt number. The interrupt specifier format + depends on the interrupt controller parent. +- clocks : phandle to the input clock. + +Example: + mu0a: mu@30aa0000 { + compatible = "fsl,imx7s-mu-a"; + reg = <0x30aa0000 0x28>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + #mbox-cells = <1>; + }; + + mu0b: mu@30ab0000 { + compatible = "fsl,imx7s-mu-b"; + reg = <0x30ab0000 0x28>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + #mbox-cells = <1>; + }; |