m Documentation/devicetree/bindings/mailbox/imx-mailbox.txt

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>

1 files changed, 9 insertions, 9 deletions

diff --git a/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt b/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt
index a45604b33039..1577b86f1206 100644
--- a/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt
+++ b/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt
@@ -1,24 +1,24 @@
 i.MX Messaging Unit
 ===================
 
-The i.MX Messaging Unit (MU) contains two register sets: "A" and "B". In most cases
-they are accessible from all Processor Units. On one hand, at least for mailbox functionality,
-it makes no difference which application or processor is using which set of the MU. On
-other hand, the register sets for each of the MU parts are not identical.
+The i.MX Messaging Unit (MU) contains two register sets: "A" and "B". In most
+cases they are accessible from all Processor Units. On one hand, at least for
+mailbox functionality, it makes no difference which application or processor is
+using which set of the MU. On other hand, the register sets for each of the MU
+parts are not identical.
 
 Required properties:
 - compatible :	Shell be one of:
                     "fsl,imx7s-mu-a" and "fsl,imx7s-mu-b" for i.MX7S or i.MX7D
-- reg : 	physical base address of the mailbox and length of
+- reg :		physical base address of the mailbox and length of
 		memory mapped region.
 - #mbox-cells:	Common mailbox binding property to identify the number
 		of cells required for the mailbox specifier. Should be 1.
-- interrupts :	interrupt number. The interrupt specifier format
-		depends on the interrupt controller parent.
+- interrupts :	The interrupt number
 - clocks     :  phandle to the input clock.
 
 Example:
-	mu0a: mu@30aa0000 {
+	mu0a: mailbox@30aa0000 {
 		compatible = "fsl,imx7s-mu-a";
 		reg = <0x30aa0000 0x28>;
 		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
@@ -26,7 +26,7 @@ Example:
 		#mbox-cells = <1>;
 	};
 
-	mu0b: mu@30ab0000 {
+	mu0b: mailbox@30ab0000 {
 		compatible = "fsl,imx7s-mu-b";
 		reg = <0x30ab0000 0x28>;
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;