diff options
| author | Jan Luebbe <jlu@pengutronix.de> | 2013-07-20 19:51:10 +0200 |
|---|---|---|
| committer | Jan Luebbe <jlu@pengutronix.de> | 2013-07-20 19:51:58 +0200 |
| commit | e878fa19dcb109a3d89e6063a211fb6c4257bbf0 (patch) | |
| tree | d509fb01494209b66030e85aa5e96a2deadbf6b5 | |
| parent | a8106e82041f2d471d5ceeee76c463d38147e8db (diff) | |
| download | platform-pengutronix-beaglebone-e878fa19dcb109a3d89e6063a211fb6c4257bbf0.tar.gz platform-pengutronix-beaglebone-e878fa19dcb109a3d89e6063a211fb6c4257bbf0.tar.xz | |
barebox: add support for the beaglebone black
Signed-off-by: Jan Luebbe <jlu@pengutronix.de>
30 files changed, 2269 insertions, 428 deletions
diff --git a/barebox-defaultenv/boot/sd b/barebox-defaultenv/boot/sd index ecd8e49..4346720 100644 --- a/barebox-defaultenv/boot/sd +++ b/barebox-defaultenv/boot/sd @@ -5,8 +5,8 @@ if [ "$1" = menu ]; then exit fi -global.bootm.image=/boot/uImage -global.bootm.oftree=/boot/oftree +global.bootm.image="/boot/uImage" +global.bootm.oftree="/boot/oftree-${global.board.variant}" #global.bootm.initrd=<path to initrd> global.linux.bootargs.dyn.root="root=/dev/mmcblk0p2 rootfstype=ext4 rootwait rw" diff --git a/barebox.config b/barebox.config index a2cb3d3..294bba1 100644 --- a/barebox.config +++ b/barebox.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Barebox/arm 2013.04.0 Configuration +# Barebox/arm 2013.07.0 Configuration # CONFIG_ARM=y CONFIG_ARM_LINUX=y @@ -8,12 +8,14 @@ CONFIG_ARM_LINUX=y # # System Type # +# CONFIG_BUILTIN_DTB is not set # CONFIG_ARCH_AT91 is not set # CONFIG_ARCH_BCM2835 is not set # CONFIG_ARCH_CLPS711X is not set # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_HIGHBANK is not set # CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_MXS is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_NOMADIK is not set @@ -25,6 +27,7 @@ CONFIG_ARCH_OMAP=y # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_ZYNQ is not set # # Processor Type @@ -52,6 +55,8 @@ CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0=y # CONFIG_OMAP_BUILD_SPI is not set CONFIG_MACH_BEAGLEBONE=y # CONFIG_MACH_PCM051 is not set +# CONFIG_OMAP_UART1 is not set +CONFIG_OMAP_UART3=y CONFIG_AEABI=y # CONFIG_THUMB2_BAREBOX is not set # CONFIG_ARM_BOARD_APPEND_ATAG is not set @@ -103,9 +108,10 @@ CONFIG_STACK_SIZE=0x8000 CONFIG_MALLOC_SIZE=0x1000000 # CONFIG_BROKEN is not set # CONFIG_EXPERIMENTAL is not set -CONFIG_MALLOC_DLMALLOC=y -# CONFIG_MALLOC_TLSF is not set +# CONFIG_MALLOC_DLMALLOC is not set +CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y +# CONFIG_RELOCATABLE is not set CONFIG_PROMPT="barebox> " CONFIG_BAUDRATE=115200 CONFIG_LONGHELP=y @@ -218,6 +224,12 @@ CONFIG_CMD_ECHO_E=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MEMINFO=y CONFIG_CMD_IOMEM=y +CONFIG_CMD_MD=y +CONFIG_CMD_MW=y +CONFIG_CMD_MM=y +CONFIG_CMD_MEMCMP=y +CONFIG_CMD_MEMCPY=y +CONFIG_CMD_MEMSET=y CONFIG_CMD_CRC=y CONFIG_CMD_CRC_CMP=y CONFIG_CMD_DIGEST=y @@ -248,7 +260,6 @@ CONFIG_FLEXIBLE_BOOTARGS=y CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y -# CONFIG_CMD_OFTREE_PROBE is not set # CONFIG_CMD_OF_PROPERTY is not set # CONFIG_CMD_OF_NODE is not set @@ -273,6 +284,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_UNCOMPRESS=y CONFIG_CMD_I2C=y CONFIG_CMD_MIITOOL=y +# CONFIG_CMD_DETECT is not set CONFIG_NET=y CONFIG_NET_DHCP=y CONFIG_NET_NFS=y @@ -283,6 +295,11 @@ CONFIG_NET_RESOLV=y # # Drivers # +CONFIG_OFTREE=y +CONFIG_OFTREE_MEM_GENERIC=y +CONFIG_DTC=y +CONFIG_OFDEVICE=y +CONFIG_OF_NET=y # # serial drivers @@ -290,6 +307,7 @@ CONFIG_NET_RESOLV=y # CONFIG_DRIVER_SERIAL_ARM_DCC is not set CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +# CONFIG_DRIVER_SERIAL_CADENCE is not set CONFIG_PHYLIB=y # @@ -316,13 +334,12 @@ CONFIG_DRIVER_NET_CPSW=y # # CONFIG_SPI is not set CONFIG_I2C=y -CONFIG_I2C_ALGOBIT=y # # I2C Hardware Bus support # -CONFIG_I2C_GPIO=y -# CONFIG_I2C_OMAP is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_OMAP=y # CONFIG_MTD is not set CONFIG_DISK=y CONFIG_DISK_WRITE=y @@ -347,6 +364,7 @@ CONFIG_MCI=y CONFIG_MCI_STARTUP=y CONFIG_MCI_INFO=y CONFIG_MCI_WRITE=y +# CONFIG_MCI_MMC_BOOT_PARTITIONS is not set # # --- MCI host drivers --- @@ -362,6 +380,7 @@ CONFIG_MCI_OMAP_HSMMC=y # CONFIG_MFD_MC34708 is not set # CONFIG_MFD_MC9SDZ60 is not set # CONFIG_MFD_STMPE is not set +# CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TWL4030 is not set # CONFIG_MFD_TWL6030 is not set # CONFIG_MISC_DEVICES is not set @@ -388,10 +407,20 @@ CONFIG_GPIOLIB=y # # GPIO # -CONFIG_OFDEVICE=y +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_IMX is not set # CONFIG_W1 is not set # +# Pin controllers +# +# CONFIG_PINCTRL is not set +# CONFIG_PINCTRL_IMX_IOMUX_V1 is not set +# CONFIG_PINCTRL_IMX_IOMUX_V2 is not set +# CONFIG_PINCTRL_IMX_IOMUX_V3 is not set +# CONFIG_PINCTRL_TEGRA20 is not set + +# # Filesystem support # CONFIG_FS=y @@ -416,8 +445,6 @@ CONFIG_UNCOMPRESS=y # CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_PROCESS_ESCAPE_SEQUENCE=y # CONFIG_LZO_DECOMPRESS is not set -CONFIG_FDT=y -CONFIG_OFTREE=y CONFIG_QSORT=y # diff --git a/barebox_mlo.config b/barebox_mlo.config index c24720a..2d87086 100644 --- a/barebox_mlo.config +++ b/barebox_mlo.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Barebox/arm 2013.04.0 Configuration +# Barebox/arm 2013.07.0 Configuration # CONFIG_ARM=y @@ -13,6 +13,7 @@ CONFIG_ARM=y # CONFIG_ARCH_EP93XX is not set # CONFIG_ARCH_HIGHBANK is not set # CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_MVEBU is not set # CONFIG_ARCH_MXS is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_NOMADIK is not set @@ -24,6 +25,7 @@ CONFIG_ARCH_OMAP=y # CONFIG_ARCH_VERSATILE is not set # CONFIG_ARCH_VEXPRESS is not set # CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_ZYNQ is not set # # Processor Type @@ -46,11 +48,13 @@ CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xffffffff # CONFIG_ARCH_OMAP4 is not set CONFIG_ARCH_AM33XX=y CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0=y -# CONFIG_OMAP_GPMC is not set +CONFIG_OMAP_GPMC=y CONFIG_OMAP_BUILD_IFT=y # CONFIG_OMAP_BUILD_SPI is not set CONFIG_MACH_BEAGLEBONE=y # CONFIG_MACH_PCM051 is not set +# CONFIG_OMAP_UART1 is not set +CONFIG_OMAP_UART3=y CONFIG_ARM_ASM_UNIFIED=y CONFIG_AEABI=y CONFIG_THUMB2_BAREBOX=y @@ -75,9 +79,9 @@ CONFIG_FILETYPE=y # # General Settings # -CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION="-mlo" CONFIG_LOCALVERSION_AUTO=y -# CONFIG_BANNER is not set +CONFIG_BANNER=y # CONFIG_MEMINFO is not set CONFIG_ENVIRONMENT_VARIABLES=y @@ -92,14 +96,15 @@ CONFIG_MMU_EARLY=y CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y CONFIG_TEXT_BASE=0x402F0400 CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0xffffffff -CONFIG_STACK_SIZE=0x1600 +CONFIG_STACK_SIZE=0x2000 CONFIG_MALLOC_SIZE=0x1000000 # CONFIG_BROKEN is not set # CONFIG_EXPERIMENTAL is not set -CONFIG_MALLOC_DLMALLOC=y -# CONFIG_MALLOC_TLSF is not set +# CONFIG_MALLOC_DLMALLOC is not set +CONFIG_MALLOC_TLSF=y # CONFIG_MALLOC_DUMMY is not set # CONFIG_KALLSYMS is not set +# CONFIG_RELOCATABLE is not set CONFIG_PROMPT="MLO>" CONFIG_BAUDRATE=115200 CONFIG_SIMPLE_READLINE=y @@ -144,6 +149,7 @@ CONFIG_HAS_DEBUG_LL=y # # Drivers # +# CONFIG_OFDEVICE is not set # # serial drivers @@ -151,6 +157,7 @@ CONFIG_HAS_DEBUG_LL=y # CONFIG_DRIVER_SERIAL_ARM_DCC is not set CONFIG_DRIVER_SERIAL_NS16550=y CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y +# CONFIG_DRIVER_SERIAL_CADENCE is not set # # SPI drivers @@ -180,6 +187,7 @@ CONFIG_MCI=y # CONFIG_MCI_STARTUP=y CONFIG_MCI_WRITE=y +# CONFIG_MCI_MMC_BOOT_PARTITIONS is not set # # --- MCI host drivers --- @@ -189,6 +197,7 @@ CONFIG_MCI_OMAP_HSMMC=y # # MFD # +# CONFIG_MFD_SYSCON is not set # CONFIG_MISC_DEVICES is not set # CONFIG_LED is not set @@ -211,9 +220,19 @@ CONFIG_GPIOLIB=y # # GPIO # +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_IMX is not set # CONFIG_W1 is not set # +# Pin controllers +# +# CONFIG_PINCTRL_IMX_IOMUX_V1 is not set +# CONFIG_PINCTRL_IMX_IOMUX_V2 is not set +# CONFIG_PINCTRL_IMX_IOMUX_V3 is not set +# CONFIG_PINCTRL_TEGRA20 is not set + +# # Filesystem support # CONFIG_FS=y diff --git a/config/images/boot-mlo-vfat.config b/config/images/boot-mlo-vfat.config index 6a52246..ca5f180 100644 --- a/config/images/boot-mlo-vfat.config +++ b/config/images/boot-mlo-vfat.config @@ -3,7 +3,8 @@ image @IMAGE@ { file MLO { image = "MLO"} file barebox.bin { image = "barebox-image" } file barebox.env { image = "barebox-default-environment" } - file oftree { image = "am335x-bone.dtb" } + file oftree-bone { image = "am335x-bone.dtb" } + file oftree-boneblack { image = "am335x-boneblack.dtb" } file uImage { image = "linuximage" } } name = boot-mlo diff --git a/patches/barebox-2013.04.0/0001-arm-start-improve-memory-layout-calculation.patch b/patches/barebox-2013.04.0/0001-arm-start-improve-memory-layout-calculation.patch deleted file mode 100644 index 8c6854d..0000000 --- a/patches/barebox-2013.04.0/0001-arm-start-improve-memory-layout-calculation.patch +++ /dev/null @@ -1,95 +0,0 @@ -From d7df89aff4ba68d8bb57cbf6145c5cd5f201f704 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Fri, 15 Mar 2013 12:40:55 +0100 -Subject: [PATCH 1/8] arm: start: improve memory layout calculation - -On AM335x a barebox MLO is placed at the base of the usable SRAM range. -When running without SDRAM, we should be able to pass the SRAM range -to barebox_arm_entry. - -First we check if the ends of the memory range lie in the barebox image -and reduce the range in these cases. Then we check if the image splits -the memory range in two and choose to use the larger one. - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/cpu/start.c | 48 +++++++++++++++++++++++++++++++----------------- - 1 file changed, 31 insertions(+), 17 deletions(-) - -diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c -index cd34d9c..fa148c2 100644 ---- a/arch/arm/cpu/start.c -+++ b/arch/arm/cpu/start.c -@@ -34,38 +34,52 @@ unsigned long arm_stack_top; - static noinline __noreturn void __start(uint32_t membase, uint32_t memsize, - uint32_t boarddata) - { -- unsigned long endmem = membase + memsize; -+ unsigned long memend; - unsigned long malloc_start, malloc_end; - - setup_c(); - -- arm_stack_top = endmem; -- endmem -= STACK_SIZE; /* Stack */ -+ if ((unsigned long)_text <= membase && -+ (unsigned long)_end > membase) { /* membase is in barebox */ -+ memsize -= (unsigned long)_end - membase; -+ membase = (unsigned long)_end; -+ } -+ -+ if ((unsigned long)_text < membase + memsize && -+ (unsigned long)_end >= membase + memsize) { /* membase + memsize is in barebox */ -+ memsize = (unsigned long)_text - membase; -+ } -+ -+ if ((unsigned long)_text > membase && -+ (unsigned long)_end < membase + memsize) { /* barebox splits or memory range */ -+ unsigned long lowsize = (unsigned long)_text - membase; -+ unsigned long highsize = membase + memsize - (unsigned long)_end; -+ /* use larger range */ -+ if (lowsize > highsize) { -+ memsize = lowsize; -+ } else { -+ membase = (unsigned long)_end; -+ memsize = highsize; -+ } -+ } -+ -+ arm_stack_top = membase + memsize; -+ memend = membase + memsize - STACK_SIZE; /* Stack */ - - if (IS_ENABLED(CONFIG_MMU_EARLY)) { - -- endmem &= ~0x3fff; -- endmem -= SZ_16K; /* ttb */ -+ memend &= ~0x3fff; -+ memend -= SZ_16K; /* ttb */ - - if (!IS_ENABLED(CONFIG_PBL_IMAGE)) -- mmu_early_enable(membase, memsize, endmem); -+ mmu_early_enable(membase, memsize, memend); - } - -- if ((unsigned long)_text > membase + memsize || -- (unsigned long)_text < membase) -- /* -- * barebox is either outside SDRAM or in another -- * memory bank, so we can use the whole bank for -- * malloc. -- */ -- malloc_end = endmem; -- else -- malloc_end = (unsigned long)_text; -- - /* - * Maximum malloc space is the Kconfig value if given - * or 64MB. - */ -+ malloc_end = memend; - if (MALLOC_SIZE > 0) { - malloc_start = malloc_end - MALLOC_SIZE; - if (malloc_start < membase) --- -1.8.2.rc2 - diff --git a/patches/barebox-2013.04.0/0004-am33xx-add-defines-for-GPIOs.patch b/patches/barebox-2013.04.0/0004-am33xx-add-defines-for-GPIOs.patch deleted file mode 100644 index baf47c6..0000000 --- a/patches/barebox-2013.04.0/0004-am33xx-add-defines-for-GPIOs.patch +++ /dev/null @@ -1,45 +0,0 @@ -From 7d2dfe2ceead859a63404199799bb765873de4cb Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 31 Mar 2013 01:54:28 +0100 -Subject: [PATCH 4/8] am33xx: add defines for GPIOs - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/mach-omap/include/mach/am33xx-clock.h | 2 ++ - arch/arm/mach-omap/include/mach/am33xx-silicon.h | 6 ++++++ - 2 files changed, 8 insertions(+) - -diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h -index 39c107f..cbee641 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-clock.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h -@@ -139,7 +139,9 @@ - #define CM_PER_CPGMAC0_CLKCTRL (CM_PER + 0x14) /* Ethernet */ - #define CM_PER_CPSW_CLKSTCTRL (CM_PER + 0x144)/* Ethernet */ - #define CM_PER_OCMCRAM_CLKCTRL (CM_PER + 0x2C) /* OCMC RAM */ -+#define CM_PER_GPIO1_CLKCTRL (CM_PER + 0xAC) /* GPIO1 */ - #define CM_PER_GPIO2_CLKCTRL (CM_PER + 0xB0) /* GPIO2 */ -+#define CM_PER_GPIO3_CLKCTRL (CM_PER + 0xB4) /* GPIO3 */ - #define CM_PER_UART3_CLKCTRL (CM_PER + 0x74) /* UART3 */ - #define CM_PER_I2C1_CLKCTRL (CM_PER + 0x48) /* I2C1 */ - #define CM_PER_I2C2_CLKCTRL (CM_PER + 0x44) /* I2C2 */ -diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h -index e69d345..9edf4ca 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h -@@ -29,6 +29,12 @@ - #define AM33XX_UART1_BASE (AM33XX_L4_PER_BASE + 0x22000) - #define AM33XX_UART2_BASE (AM33XX_L4_PER_BASE + 0x24000) - -+/* GPIO */ -+#define AM33XX_GPIO0_BASE (AM33XX_L4_WKUP_BASE + 0x207000 + 0x100) -+#define AM33XX_GPIO1_BASE (AM33XX_L4_PER_BASE + 0x4C000 + 0x100) -+#define AM33XX_GPIO2_BASE (AM33XX_L4_PER_BASE + 0x1AC000 + 0x100) -+#define AM33XX_GPIO3_BASE (AM33XX_L4_PER_BASE + 0x1AE000 + 0x100) -+ - /* EMFI Registers */ - #define AM33XX_EMFI0_BASE 0x4C000000 - --- -1.8.2.rc2 - diff --git a/patches/barebox-2013.04.0/0005-WIP-GPIO-for-am33xx.patch b/patches/barebox-2013.04.0/0005-WIP-GPIO-for-am33xx.patch deleted file mode 100644 index e6dc7f6..0000000 --- a/patches/barebox-2013.04.0/0005-WIP-GPIO-for-am33xx.patch +++ /dev/null @@ -1,101 +0,0 @@ -From 278fb30cf0ce864e15505330238e891d88b3f965 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 31 Mar 2013 12:27:43 +0200 -Subject: [PATCH 5/8] WIP: GPIO for am33xx - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/mach-omap/am33xx_generic.c | 28 ++++++++++++++++++++++++++++ - arch/arm/mach-omap/am33xx_mux.c | 11 +++++++++++ - arch/arm/mach-omap/include/mach/am33xx-mux.h | 1 + - 3 files changed, 40 insertions(+) - -diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c -index d3014c2..bf03fcd 100644 ---- a/arch/arm/mach-omap/am33xx_generic.c -+++ b/arch/arm/mach-omap/am33xx_generic.c -@@ -19,8 +19,10 @@ - */ - - #include <common.h> -+#include <init.h> - #include <io.h> - #include <net.h> -+#include <driver.h> - #include <mach/am33xx-silicon.h> - #include <mach/am33xx-clock.h> - #include <mach/sys_info.h> -@@ -122,3 +124,29 @@ int am33xx_register_ethaddr(int eth_id, int mac_id) - - return -ENODEV; - } -+ -+static int am33xx_gpio_init(void) -+{ -+ /* GPIO 1-3 */ -+#define PRCM_MOD_EN 0x2 -+ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO1_CLKCTRL); -+ while (__raw_readl(CM_PER_GPIO1_CLKCTRL) != PRCM_MOD_EN); -+ -+ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO2_CLKCTRL); -+ while (__raw_readl(CM_PER_GPIO2_CLKCTRL) != PRCM_MOD_EN); -+ -+ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO3_CLKCTRL); -+ while (__raw_readl(CM_PER_GPIO3_CLKCTRL) != PRCM_MOD_EN); -+ -+ add_generic_device("omap-gpio", 0, NULL, AM33XX_GPIO0_BASE, -+ 0xf00, IORESOURCE_MEM, NULL); -+ add_generic_device("omap-gpio", 1, NULL, AM33XX_GPIO1_BASE, -+ 0xf00, IORESOURCE_MEM, NULL); -+ add_generic_device("omap-gpio", 2, NULL, AM33XX_GPIO2_BASE, -+ 0xf00, IORESOURCE_MEM, NULL); -+ add_generic_device("omap-gpio", 3, NULL, AM33XX_GPIO3_BASE, -+ 0xf00, IORESOURCE_MEM, NULL); -+ -+ return 0; -+} -+coredevice_initcall(am33xx_gpio_init); -diff --git a/arch/arm/mach-omap/am33xx_mux.c b/arch/arm/mach-omap/am33xx_mux.c -index 3d7f245..e3a700d 100644 ---- a/arch/arm/mach-omap/am33xx_mux.c -+++ b/arch/arm/mach-omap/am33xx_mux.c -@@ -291,6 +291,12 @@ static const __maybe_unused struct module_pin_mux i2c0_pin_mux[] = { - {-1}, - }; - -+static const __maybe_unused struct module_pin_mux i2c0_pin_mux_gpio[] = { -+ {OFFSET(i2c0_sda), (MODE(7) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ -+ {OFFSET(i2c0_scl), (MODE(7) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ -+ {-1}, -+}; -+ - static const __maybe_unused struct module_pin_mux i2c1_pin_mux[] = { - {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ - {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ -@@ -490,6 +496,11 @@ void enable_i2c0_pin_mux(void) - configure_module_pin_mux(i2c0_pin_mux); - } - -+void enable_i2c0_pin_mux_gpio(void) -+{ -+ configure_module_pin_mux(i2c0_pin_mux_gpio); -+} -+ - void enable_i2c1_pin_mux(void) - { - configure_module_pin_mux(i2c1_pin_mux); -diff --git a/arch/arm/mach-omap/include/mach/am33xx-mux.h b/arch/arm/mach-omap/include/mach/am33xx-mux.h -index 6078b3a..f4318c2 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-mux.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-mux.h -@@ -15,6 +15,7 @@ - - extern void enable_mii1_pin_mux(void); - extern void enable_i2c0_pin_mux(void); -+extern void enable_i2c0_pin_mux_gpio(void); - extern void enable_i2c1_pin_mux(void); - extern void enable_i2c2_pin_mux(void); - extern void enable_uart0_pin_mux(void); --- -1.8.2.rc2 - diff --git a/patches/barebox-2013.04.0/0006-beaglebone-enable-i2c.patch b/patches/barebox-2013.04.0/0006-beaglebone-enable-i2c.patch deleted file mode 100644 index cf46a83..0000000 --- a/patches/barebox-2013.04.0/0006-beaglebone-enable-i2c.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 8d2caf59e024d664d3c06757d727aecfb618b74e Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 31 Mar 2013 12:27:14 +0200 -Subject: [PATCH 6/8] beaglebone: enable i2c - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/boards/beaglebone/board.c | 20 +++++++++++++++++++- - 1 file changed, 19 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c -index e4b8b0a..42dbebf 100644 ---- a/arch/arm/boards/beaglebone/board.c -+++ b/arch/arm/boards/beaglebone/board.c -@@ -42,6 +42,7 @@ - #include <mach/gpmc.h> - #include <mach/ehci.h> - #include <i2c/i2c.h> -+#include <i2c/i2c-gpio.h> - #include <linux/err.h> - #include <linux/phy.h> - #include <usb/ehci.h> -@@ -100,16 +101,33 @@ static void beaglebone_eth_init(void) - am33xx_add_cpsw(&cpsw_data); - } - -+static struct i2c_board_info i2c_devices[] = { -+ { -+ I2C_BOARD_INFO("24c256", 0x50) -+ }, -+}; -+ -+static struct i2c_gpio_platform_data i2c_gpio_data = { -+ .sda_pin = 32*3 + 5, -+ .sda_is_open_drain = 0, -+ .scl_pin = 32*3 + 6, -+ .scl_is_open_drain = 0, -+ .udelay = 5, /* ~100 kHz */ -+}; -+ - static int beaglebone_devices_init(void) - { - am33xx_add_mmc0(NULL); - -- enable_i2c0_pin_mux(); - beaglebone_eth_init(); - - armlinux_set_bootparams((void *)0x80000100); - armlinux_set_architecture(MACH_TYPE_BEAGLEBONE); - -+ enable_i2c0_pin_mux_gpio(); -+ i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); -+ add_generic_device_res("i2c-gpio", 0, NULL, 0, &i2c_gpio_data); -+ - return 0; - } - device_initcall(beaglebone_devices_init); --- -1.8.2.rc2 - diff --git a/patches/barebox-2013.04.0/0007-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch b/patches/barebox-2013.04.0/0007-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch deleted file mode 100644 index b04e09e..0000000 --- a/patches/barebox-2013.04.0/0007-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch +++ /dev/null @@ -1,32 +0,0 @@ -From ff05523fb89a2b50e670d40e00301ea4dc62515a Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 31 Mar 2013 12:28:01 +0200 -Subject: [PATCH 7/8] WIP: beaglebone: add simple script to change usb current - limit - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/boards/beaglebone/env/init/usb-limit-1300 | 11 +++++++++++ - 1 file changed, 11 insertions(+) - create mode 100644 arch/arm/boards/beaglebone/env/init/usb-limit-1300 - -diff --git a/arch/arm/boards/beaglebone/env/init/usb-limit-1300 b/arch/arm/boards/beaglebone/env/init/usb-limit-1300 -new file mode 100644 -index 0000000..b5a97eb ---- /dev/null -+++ b/arch/arm/boards/beaglebone/env/init/usb-limit-1300 -@@ -0,0 +1,11 @@ -+#!/bin/sh -+ -+ENABLED=0 -+ -+if [ $ENABLED -eq 0 ]; then -+ echo "edit /env/init/usb-limit-1300 to change the USB current limit" -+else -+ echo -n "changing USB current limit to 1300 mA... " -+ i2c_write -b 0 -a 0x24 -r 0x01 0x3e -+ echo "done" -+fi --- -1.8.2.rc2 - diff --git a/patches/barebox-2013.04.0/0008-defaultenv-2-init-display-prompt-after-running-env-i.patch b/patches/barebox-2013.04.0/0008-defaultenv-2-init-display-prompt-after-running-env-i.patch deleted file mode 100644 index 69d1f64..0000000 --- a/patches/barebox-2013.04.0/0008-defaultenv-2-init-display-prompt-after-running-env-i.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 376025ea1243bd1c81f51b0c37cea30507ef3098 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Mon, 8 Apr 2013 18:03:21 +0200 -Subject: [PATCH 8/8] defaultenv-2: init: display prompt after running - /env/init/* - -This allows init scripts to print messages to the console without messing -up the timeout prompt. - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - defaultenv-2/base/bin/init | 12 ++++++------ - 1 file changed, 6 insertions(+), 6 deletions(-) - -diff --git a/defaultenv-2/base/bin/init b/defaultenv-2/base/bin/init -index e4a7fee..a47ca47 100644 ---- a/defaultenv-2/base/bin/init -+++ b/defaultenv-2/base/bin/init -@@ -16,12 +16,6 @@ global editcmd=sedit - /env/config-board - /env/config - --if [ -e /env/menu ]; then -- echo -e -n "\nHit m for menu or any other key to stop autoboot: " --else -- echo -e -n "\nHit any key to stop autoboot: " --fi -- - # allow to stop the boot before execute the /env/init/* - # but without waiting - timeout -s -a -v key 0 -@@ -34,6 +28,12 @@ for i in /env/init/*; do - . $i - done - -+if [ -e /env/menu ]; then -+ echo -e -n "\nHit m for menu or any other key to stop autoboot: " -+else -+ echo -e -n "\nHit any key to stop autoboot: " -+fi -+ - timeout -a $global.autoboot_timeout -v key - autoboot="$?" - --- -1.8.2.rc2 - diff --git a/patches/barebox-2013.04.0/series b/patches/barebox-2013.04.0/series deleted file mode 100644 index c576a1a..0000000 --- a/patches/barebox-2013.04.0/series +++ /dev/null @@ -1,8 +0,0 @@ -0001-arm-start-improve-memory-layout-calculation.patch -0002-beaglebone-fix-booting.patch -0003-beaglebone-env-use-config-board-instead-of-config.patch -0004-am33xx-add-defines-for-GPIOs.patch -0005-WIP-GPIO-for-am33xx.patch -0006-beaglebone-enable-i2c.patch -0007-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch -0008-defaultenv-2-init-display-prompt-after-running-env-i.patch diff --git a/patches/barebox-2013.07.0/0001-scripts-genenv-remove-empty-files-from-tempdir.patch b/patches/barebox-2013.07.0/0001-scripts-genenv-remove-empty-files-from-tempdir.patch new file mode 100644 index 0000000..3643c08 --- /dev/null +++ b/patches/barebox-2013.07.0/0001-scripts-genenv-remove-empty-files-from-tempdir.patch @@ -0,0 +1,29 @@ +From 8544d430c081371152796a0de45fa8edef1bf594 Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Tue, 28 May 2013 09:43:29 +0200 +Subject: [PATCH 01/17] scripts: genenv: remove empty files from tempdir + +This allows leaving out default files from the environment by overriding +them with empty files in the board or BSP. + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + scripts/genenv | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/scripts/genenv b/scripts/genenv +index 374db6d..3e91062 100755 +--- a/scripts/genenv ++++ b/scripts/genenv +@@ -24,7 +24,7 @@ for i in $*; do + done + ) + +-find $tempdir -name '.svn' -o -name '*~' | xargs --no-run-if-empty rm -r ++find $tempdir -name '.svn' -o -name '*~' -o -size 0 | xargs --no-run-if-empty rm -r + + $objtree/scripts/bareboxenv -s $tempdir $target + +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0002-scripts-Makefile-do-not-use-obj-variables-for-usersp.patch b/patches/barebox-2013.07.0/0002-scripts-Makefile-do-not-use-obj-variables-for-usersp.patch new file mode 100644 index 0000000..b9811ad --- /dev/null +++ b/patches/barebox-2013.07.0/0002-scripts-Makefile-do-not-use-obj-variables-for-usersp.patch @@ -0,0 +1,30 @@ +From cd780d60b41f5b743e7c4518364053a9c266f17d Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Tue, 28 May 2013 11:04:12 +0200 +Subject: [PATCH 02/17] scripts: Makefile: do not use obj-* variables for + userspace tools + +When using obj-?, it erroneously tries to link a built-in.o. Instead +use the extra-? variable. + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + scripts/Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/scripts/Makefile b/scripts/Makefile +index 307dc3d..eaf12d9 100644 +--- a/scripts/Makefile ++++ b/scripts/Makefile +@@ -32,7 +32,7 @@ subdir- += basic kconfig setupmbr + quiet_cmd_csingle = CC $@ + cmd_csingle = $(CC) -Wp,-MD,$(depfile) $(CFLAGS) -o $@ $< + +-obj-$(CONFIG_BAREBOXENV_TARGET) += bareboxenv-target ++extra-$(CONFIG_BAREBOXENV_TARGET) += bareboxenv-target + + scripts/bareboxenv-target: scripts/bareboxenv.c FORCE + $(call if_changed_dep,csingle) +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0003-console-fix-console-without-CONFIG_PARAMETER.patch b/patches/barebox-2013.07.0/0003-console-fix-console-without-CONFIG_PARAMETER.patch new file mode 100644 index 0000000..e0a0076 --- /dev/null +++ b/patches/barebox-2013.07.0/0003-console-fix-console-without-CONFIG_PARAMETER.patch @@ -0,0 +1,35 @@ +From 08c73dea817bc6c589e3ef4fae11fccdd562c81c Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Mon, 15 Apr 2013 18:17:30 +0200 +Subject: [PATCH 03/17] console: fix console without CONFIG_PARAMETER + +If CONFIG_PARAMETER is not set, dev_set_param() does not call the setter +function. Call it directly instead in this case. + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + common/console.c | 8 ++++++-- + 1 file changed, 6 insertions(+), 2 deletions(-) + +diff --git a/common/console.c b/common/console.c +index a0a06f6..b2d70f5 100644 +--- a/common/console.c ++++ b/common/console.c +@@ -163,8 +163,12 @@ int console_register(struct console_device *newcdev) + + list_add_tail(&newcdev->list, &console_list); + +- if (activate) +- dev_set_param(dev, "active", "ioe"); ++ if (activate) { ++ if (IS_ENABLED(CONFIG_PARAMETER)) ++ dev_set_param(dev, "active", "ioe"); ++ else ++ console_std_set(dev, NULL, "ioe"); ++ } + + return 0; + } +-- +1.7.10.4 + diff --git a/patches/barebox-2013.04.0/0002-beaglebone-fix-booting.patch b/patches/barebox-2013.07.0/0004-beaglebone-fix-booting.patch index 1c87406..fb5d09c 100644 --- a/patches/barebox-2013.04.0/0002-beaglebone-fix-booting.patch +++ b/patches/barebox-2013.07.0/0004-beaglebone-fix-booting.patch @@ -1,15 +1,15 @@ -From a88084a1d16c0d792be410f196d1e2e537c21d0c Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jluebbe@debian.org> -Date: Sat, 30 Mar 2013 21:20:09 +0100 -Subject: [PATCH 2/8] beaglebone: fix booting +From 3c44683c4f806eedf920704b768f178221e652e1 Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Sun, 14 Jul 2013 13:21:00 +0200 +Subject: [PATCH 04/17] beaglebone: fix booting Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- - arch/arm/boards/beaglebone/lowlevel.c | 14 ++++++++++++-- - 1 file changed, 12 insertions(+), 2 deletions(-) + arch/arm/boards/beaglebone/lowlevel.c | 17 ++++++++++++++--- + 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c -index 76ac90b..229968e 100644 +index 28959ff..2a8e677 100644 --- a/arch/arm/boards/beaglebone/lowlevel.c +++ b/arch/arm/boards/beaglebone/lowlevel.c @@ -1,6 +1,7 @@ @@ -25,17 +25,17 @@ index 76ac90b..229968e 100644 beaglebone_config_ddr(); + /* Enable pin mux */ -+ enable_uart0_pin_mux(); ++ am33xx_enable_uart0_pin_mux(); + /* UART softreset */ uart_base = AM33XX_UART0_BASE; -@@ -242,11 +246,17 @@ static int beaglebone_board_init(void) +@@ -242,17 +246,24 @@ static int beaglebone_board_init(void) if (!in_sdram) beaglebone_sram_init(); - /* Enable pin mux */ -- enable_uart0_pin_mux(); +- am33xx_enable_uart0_pin_mux(); + return 0; +} + @@ -48,8 +48,16 @@ index 76ac90b..229968e 100644 } +mem_initcall(beaglebone_sram_mem_init); - void __naked barebox_arm_reset_vector(void) +-void __naked barebox_arm_reset_vector(void) ++void __bare_init __naked barebox_arm_reset_vector(void) { + arm_cpu_lowlevel_init(); + + beaglebone_board_init(); + + barebox_arm_entry(0x80000000, SZ_256M, 0); ++ /* barebox_arm_entry(0x402F0400, 0x4030CE00-0x402F0400, 0); */ /* for SRAM */ + } -- -1.8.2.rc2 +1.7.10.4 diff --git a/patches/barebox-2013.04.0/0003-beaglebone-env-use-config-board-instead-of-config.patch b/patches/barebox-2013.07.0/0005-beaglebone-env-use-config-board-instead-of-config.patch index 473d099..e9e2db1 100644 --- a/patches/barebox-2013.04.0/0003-beaglebone-env-use-config-board-instead-of-config.patch +++ b/patches/barebox-2013.07.0/0005-beaglebone-env-use-config-board-instead-of-config.patch @@ -1,12 +1,12 @@ -From 6e87252630465a45259599cfef0c4e245220e3ba Mon Sep 17 00:00:00 2001 +From d4a3d4e53d37d64a7c2490b103356b18cf0999be Mon Sep 17 00:00:00 2001 From: Jan Luebbe <jlu@pengutronix.de> Date: Mon, 8 Apr 2013 18:05:35 +0200 -Subject: [PATCH 3/8] beaglebone: env: use config-board instead of config +Subject: [PATCH 05/17] beaglebone: env: use config-board instead of config Signed-off-by: Jan Luebbe <jlu@pengutronix.de> --- - arch/arm/boards/beaglebone/env/config | 21 --------------------- - arch/arm/boards/beaglebone/env/config-board | 7 +++++++ + arch/arm/boards/beaglebone/env/config | 21 --------------------- + arch/arm/boards/beaglebone/env/config-board | 7 +++++++ 2 files changed, 7 insertions(+), 21 deletions(-) delete mode 100644 arch/arm/boards/beaglebone/env/config create mode 100644 arch/arm/boards/beaglebone/env/config-board @@ -52,5 +52,5 @@ index 0000000..f9a2db7 +global.hostname=beaglebone +global.linux.bootargs.base="console=ttyO0,115200n8" -- -1.8.2.rc2 +1.7.10.4 diff --git a/patches/barebox-2013.07.0/0006-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch b/patches/barebox-2013.07.0/0006-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch new file mode 100644 index 0000000..7f346d1 --- /dev/null +++ b/patches/barebox-2013.07.0/0006-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch @@ -0,0 +1,26 @@ +From 6bf54b3d1cc8b5506781fc3e754e38a65371e9b1 Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Sun, 31 Mar 2013 12:28:01 +0200 +Subject: [PATCH 06/17] WIP: beaglebone: add simple script to change usb + current limit + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + arch/arm/boards/beaglebone/env/init/usb-limit-1300 | 5 +++++ + 1 file changed, 5 insertions(+) + create mode 100644 arch/arm/boards/beaglebone/env/init/usb-limit-1300 + +diff --git a/arch/arm/boards/beaglebone/env/init/usb-limit-1300 b/arch/arm/boards/beaglebone/env/init/usb-limit-1300 +new file mode 100644 +index 0000000..56313bf +--- /dev/null ++++ b/arch/arm/boards/beaglebone/env/init/usb-limit-1300 +@@ -0,0 +1,5 @@ ++#!/bin/sh ++ ++echo -n "changing USB current limit to 1300 mA... " ++i2c_write -b 0 -a 0x24 -r 0x01 0x3e ++echo "done" +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0007-ARM-AM33xx-Add-gpio-support.patch b/patches/barebox-2013.07.0/0007-ARM-AM33xx-Add-gpio-support.patch new file mode 100644 index 0000000..4740391 --- /dev/null +++ b/patches/barebox-2013.07.0/0007-ARM-AM33xx-Add-gpio-support.patch @@ -0,0 +1,41 @@ +From af8dbd7d41f9a57791b2bd04c277728ad3ea5138 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> +Date: Tue, 9 Jul 2013 11:23:13 +0200 +Subject: [PATCH 07/17] ARM: AM33xx: Add gpio support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Register GPIO banks for AM33xx boards. + +Signed-off-by: Teresa Gámez <t.gamez@phytec.de> +Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> +--- + arch/arm/mach-omap/am33xx_generic.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c +index 96432c9..3ab16b0 100644 +--- a/arch/arm/mach-omap/am33xx_generic.c ++++ b/arch/arm/mach-omap/am33xx_generic.c +@@ -126,3 +126,17 @@ int am33xx_register_ethaddr(int eth_id, int mac_id) + + return -ENODEV; + } ++ ++static int am33xx_gpio_init(void) ++{ ++ add_generic_device("omap-gpio", 0, NULL, AM33XX_GPIO0_BASE, ++ 0xf00, IORESOURCE_MEM, NULL); ++ add_generic_device("omap-gpio", 1, NULL, AM33XX_GPIO1_BASE, ++ 0xf00, IORESOURCE_MEM, NULL); ++ add_generic_device("omap-gpio", 2, NULL, AM33XX_GPIO2_BASE, ++ 0xf00, IORESOURCE_MEM, NULL); ++ add_generic_device("omap-gpio", 3, NULL, AM33XX_GPIO3_BASE, ++ 0xf00, IORESOURCE_MEM, NULL); ++ return 0; ++} ++coredevice_initcall(am33xx_gpio_init); +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0008-ARM-AM33xx-Enable-clock-for-all-GPIO-banks.patch b/patches/barebox-2013.07.0/0008-ARM-AM33xx-Enable-clock-for-all-GPIO-banks.patch new file mode 100644 index 0000000..654c58f --- /dev/null +++ b/patches/barebox-2013.07.0/0008-ARM-AM33xx-Enable-clock-for-all-GPIO-banks.patch @@ -0,0 +1,40 @@ +From b284ba947ff3626063aabd0e5bb9ec16aba8e145 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> +Date: Tue, 9 Jul 2013 11:23:17 +0200 +Subject: [PATCH 08/17] ARM: AM33xx: Enable clock for all GPIO banks +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Teresa Gámez <t.gamez@phytec.de> +Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> +--- + arch/arm/mach-omap/am33xx_clock.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c +index 4451d62..e4d9d77 100644 +--- a/arch/arm/mach-omap/am33xx_clock.c ++++ b/arch/arm/mach-omap/am33xx_clock.c +@@ -53,6 +53,18 @@ static void interface_clocks_enable(void) + /* GPIO0 */ + __raw_writel(PRCM_MOD_EN, CM_WKUP_GPIO0_CLKCTRL); + while (__raw_readl(CM_WKUP_GPIO0_CLKCTRL) != PRCM_MOD_EN); ++ ++ /* GPIO1 */ ++ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO1_CLKCTRL); ++ while (__raw_readl(CM_PER_GPIO1_CLKCTRL) != PRCM_MOD_EN); ++ ++ /* GPIO2 */ ++ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO2_CLKCTRL); ++ while (__raw_readl(CM_PER_GPIO2_CLKCTRL) != PRCM_MOD_EN); ++ ++ /* GPIO3 */ ++ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO3_CLKCTRL); ++ while (__raw_readl(CM_PER_GPIO3_CLKCTRL) != PRCM_MOD_EN); + } + + static void power_domain_transition_enable(void) +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0009-ARM-AM33xx-Make-mpu-pll-configurable-by-lowlevel-boa.patch b/patches/barebox-2013.07.0/0009-ARM-AM33xx-Make-mpu-pll-configurable-by-lowlevel-boa.patch new file mode 100644 index 0000000..76ebeae --- /dev/null +++ b/patches/barebox-2013.07.0/0009-ARM-AM33xx-Make-mpu-pll-configurable-by-lowlevel-boa.patch @@ -0,0 +1,62 @@ +From 16f580940c592e26d9e816be330509e16a2741da Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> +Date: Tue, 9 Jul 2013 11:23:19 +0200 +Subject: [PATCH 09/17] ARM: AM33xx: Make mpu pll configurable by lowlevel + board code +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Signed-off-by: Teresa Gámez <t.gamez@phytec.de> +Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> +--- + arch/arm/boards/beaglebone/lowlevel.c | 2 +- + arch/arm/mach-omap/am33xx_clock.c | 4 ++-- + arch/arm/mach-omap/include/mach/am33xx-clock.h | 2 +- + 3 files changed, 4 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c +index 2a8e677..ebbd960 100644 +--- a/arch/arm/boards/beaglebone/lowlevel.c ++++ b/arch/arm/boards/beaglebone/lowlevel.c +@@ -198,7 +198,7 @@ void beaglebone_sram_init(void) + u32 regVal, uart_base; + + /* Setup the PLLs and the clocks for the peripherals */ +- pll_init(); ++ pll_init(MPUPLL_M_500); + + beaglebone_config_ddr(); + +diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c +index e4d9d77..9928e9f 100644 +--- a/arch/arm/mach-omap/am33xx_clock.c ++++ b/arch/arm/mach-omap/am33xx_clock.c +@@ -294,9 +294,9 @@ void enable_ddr_clocks(void) + /* + * Configure the PLL/PRCM for necessary peripherals + */ +-void pll_init() ++void pll_init(int mpupll_M) + { +- mpu_pll_config(MPUPLL_M_500); ++ mpu_pll_config(mpupll_M); + core_pll_config(); + per_pll_config(); + ddr_pll_config(); +diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h +index 3d1f074..968509e 100644 +--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h ++++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h +@@ -187,7 +187,7 @@ + + #define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL + +-extern void pll_init(void); ++extern void pll_init(int mpupll_M); + extern void enable_ddr_clocks(void); + + #endif /* endif _AM33XX_CLOCKS_H_ */ +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0010-arm-omap-store-boot-source-info-from-ROM-loader.patch b/patches/barebox-2013.07.0/0010-arm-omap-store-boot-source-info-from-ROM-loader.patch new file mode 100644 index 0000000..3edcb3a --- /dev/null +++ b/patches/barebox-2013.07.0/0010-arm-omap-store-boot-source-info-from-ROM-loader.patch @@ -0,0 +1,481 @@ +From 989eded334449152f1a3a162dd20939a7c9de388 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> +Date: Tue, 9 Jul 2013 11:23:20 +0200 +Subject: [PATCH 10/17] arm: omap: store boot source info from ROM loader +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The ROM loader passes the address of a buffer to the MLO in +register 0. Store this data so we can find the boot source later. +On the same way the bootinformation are passed to the barebox, +then. It has to be enshured that r0 contains always the +buffer or the boot source detection will not work. + +Applied this on all OMAPs. This patch is based on work of +Jan Luebbe <jlu@pengutronix.de>. + +Compile tested on all OMAP boards. +Tested on pcm049, phyCARD-A-L1 and pcm051. + +Signed-off-by: Teresa Gámez <t.gamez@phytec.de> +Tested-by: Christoph Fritz <chf.fritz@googlemail.com> +Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> +--- + arch/arm/boards/archosg9/lowlevel.c | 5 ++++- + arch/arm/boards/beagle/lowlevel.c | 6 +++++- + arch/arm/boards/beaglebone/lowlevel.c | 5 ++++- + arch/arm/boards/omap343xdsp/lowlevel.c | 6 +++++- + arch/arm/boards/omap3evm/lowlevel.c | 5 ++++- + arch/arm/boards/panda/lowlevel.c | 6 +++++- + arch/arm/boards/pcm049/lowlevel.c | 6 +++++- + arch/arm/boards/phycard-a-l1/lowlevel.c | 5 ++++- + arch/arm/boards/phycard-a-xl2/lowlevel.c | 6 +++++- + arch/arm/mach-omap/Makefile | 4 ++-- + arch/arm/mach-omap/am33xx_generic.c | 18 +++++++++++++++++- + arch/arm/mach-omap/include/mach/generic.h | 3 +++ + arch/arm/mach-omap/omap3_generic.c | 16 +++++++++++++--- + arch/arm/mach-omap/omap4_generic.c | 18 +++++++++++++----- + arch/arm/mach-omap/omap_bootinfo.S | 25 +++++++++++++++++++++++++ + arch/arm/mach-omap/xload.c | 8 ++++++-- + 16 files changed, 120 insertions(+), 22 deletions(-) + create mode 100644 arch/arm/mach-omap/omap_bootinfo.S + +diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c +index 0334693..d443a60 100644 +--- a/arch/arm/boards/archosg9/lowlevel.c ++++ b/arch/arm/boards/archosg9/lowlevel.c +@@ -14,6 +14,7 @@ + #include <io.h> + #include <init.h> + #include <sizes.h> ++#include <mach/generic.h> + #include <mach/omap4-mux.h> + #include <mach/omap4-silicon.h> + #include <mach/omap4-clock.h> +@@ -65,8 +66,10 @@ static noinline void archosg9_init_lowlevel(void) + omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); + } + +-void __naked __bare_init barebox_arm_reset_vector(void) ++void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + if (get_pc() > 0x80000000) +diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c +index d0fd066..ef7e3c0 100644 +--- a/arch/arm/boards/beagle/lowlevel.c ++++ b/arch/arm/boards/beagle/lowlevel.c +@@ -1,8 +1,10 @@ ++#include <init.h> + #include <io.h> + #include <sizes.h> + #include <asm/barebox-arm-head.h> + #include <asm/barebox-arm.h> + #include <mach/control.h> ++#include <mach/generic.h> + #include <mach/omap3-silicon.h> + #include <mach/omap3-mux.h> + #include <mach/sdrc.h> +@@ -178,8 +180,10 @@ static int beagle_board_init(void) + return 0; + } + +-void __naked barebox_arm_reset_vector(void) ++void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + beagle_board_init(); +diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c +index ebbd960..59d9ff1 100644 +--- a/arch/arm/boards/beaglebone/lowlevel.c ++++ b/arch/arm/boards/beaglebone/lowlevel.c +@@ -6,6 +6,7 @@ + #include <asm/barebox-arm.h> + #include <mach/am33xx-silicon.h> + #include <mach/am33xx-clock.h> ++#include <mach/generic.h> + #include <mach/sdrc.h> + #include <mach/sys_info.h> + #include <mach/syslib.h> +@@ -258,8 +259,10 @@ static int beaglebone_sram_mem_init(void) + } + mem_initcall(beaglebone_sram_mem_init); + +-void __bare_init __naked barebox_arm_reset_vector(void) ++void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + beaglebone_board_init(); +diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c +index ed675ad..61b7f99 100644 +--- a/arch/arm/boards/omap343xdsp/lowlevel.c ++++ b/arch/arm/boards/omap343xdsp/lowlevel.c +@@ -1,8 +1,10 @@ + #include <common.h> ++#include <init.h> + #include <io.h> + #include <sizes.h> + #include <asm/barebox-arm-head.h> + #include <asm/barebox-arm.h> ++#include <mach/generic.h> + #include <mach/omap3-mux.h> + #include <mach/sdrc.h> + #include <mach/control.h> +@@ -545,8 +547,10 @@ static int sdp343x_board_init(void) + return 0; + } + +-void __naked barebox_arm_reset_vector(void) ++void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + sdp343x_board_init(); +diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c +index 2d9e130..ea92835 100644 +--- a/arch/arm/boards/omap3evm/lowlevel.c ++++ b/arch/arm/boards/omap3evm/lowlevel.c +@@ -3,6 +3,7 @@ + #include <sizes.h> + #include <asm/barebox-arm-head.h> + #include <asm/barebox-arm.h> ++#include <mach/generic.h> + #include <mach/omap3-mux.h> + #include <mach/sdrc.h> + #include <mach/control.h> +@@ -159,8 +160,10 @@ static int omap3_evm_board_init(void) + return 0; + } + +-void __naked barebox_arm_reset_vector(void) ++void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + omap3_evm_board_init(); +diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c +index ed1dc6f..76ef83b 100644 +--- a/arch/arm/boards/panda/lowlevel.c ++++ b/arch/arm/boards/panda/lowlevel.c +@@ -17,8 +17,10 @@ + * + */ + #include <common.h> ++#include <init.h> + #include <io.h> + #include <sizes.h> ++#include <mach/generic.h> + #include <mach/omap4-mux.h> + #include <mach/omap4-silicon.h> + #include <mach/omap4-clock.h> +@@ -73,8 +75,10 @@ static void noinline panda_init_lowlevel(void) + omap4_scale_vcores(TPS62361_VSEL0_GPIO); + } + +-void barebox_arm_reset_vector(void) ++void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + if (get_pc() > 0x80000000) +diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c +index 8bcecb1..e409ad8 100644 +--- a/arch/arm/boards/pcm049/lowlevel.c ++++ b/arch/arm/boards/pcm049/lowlevel.c +@@ -17,8 +17,10 @@ + * + */ + #include <common.h> ++#include <init.h> + #include <io.h> + #include <sizes.h> ++#include <mach/generic.h> + #include <mach/omap4-mux.h> + #include <mach/omap4-silicon.h> + #include <mach/omap4-clock.h> +@@ -102,8 +104,10 @@ static void noinline pcm049_init_lowlevel(void) + sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */ + } + +-void barebox_arm_reset_vector(void) ++void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + if (get_pc() > 0x80000000) +diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c +index 30379d8..7855040 100644 +--- a/arch/arm/boards/phycard-a-l1/lowlevel.c ++++ b/arch/arm/boards/phycard-a-l1/lowlevel.c +@@ -5,6 +5,7 @@ + #include <asm/barebox-arm-head.h> + #include <asm/barebox-arm.h> + #include <mach/omap3-mux.h> ++#include <mach/generic.h> + #include <mach/sdrc.h> + #include <mach/control.h> + #include <mach/syslib.h> +@@ -250,8 +251,10 @@ static int pcaal1_board_init(void) + return 0; + } + +-void __naked barebox_arm_reset_vector(void) ++void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + pcaal1_board_init(); +diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c +index 07505ff..5e68334 100644 +--- a/arch/arm/boards/phycard-a-xl2/lowlevel.c ++++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c +@@ -17,8 +17,10 @@ + * + */ + #include <common.h> ++#include <init.h> + #include <io.h> + #include <sizes.h> ++#include <mach/generic.h> + #include <mach/omap4-mux.h> + #include <mach/omap4-silicon.h> + #include <mach/omap4-clock.h> +@@ -83,8 +85,10 @@ static noinline void pcaaxl2_init_lowlevel(void) + sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ + } + +-void barebox_arm_reset_vector(void) ++void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) + { ++ omap_save_bootinfo(); ++ + arm_cpu_lowlevel_init(); + + if (get_pc() > 0x80000000) +diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile +index 973068d..d42de48 100644 +--- a/arch/arm/mach-omap/Makefile ++++ b/arch/arm/mach-omap/Makefile +@@ -15,8 +15,8 @@ + # GNU General Public License for more details. + # + # +-obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o +-pbl-$(CONFIG_ARCH_OMAP) += syslib.o ++obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_bootinfo.o ++pbl-$(CONFIG_ARCH_OMAP) += syslib.o omap_bootinfo.o + obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o + obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o + obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o +diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c +index 3ab16b0..45fefb4 100644 +--- a/arch/arm/mach-omap/am33xx_generic.c ++++ b/arch/arm/mach-omap/am33xx_generic.c +@@ -25,6 +25,7 @@ + #include <net.h> + #include <mach/am33xx-silicon.h> + #include <mach/am33xx-clock.h> ++#include <mach/generic.h> + #include <mach/sys_info.h> + #include <mach/am33xx-generic.h> + +@@ -97,7 +98,22 @@ u32 running_in_sdram(void) + + static int am33xx_bootsource(void) + { +- bootsource_set(BOOTSOURCE_MMC); /* only MMC for now */ ++ enum bootsource src; ++ ++ switch (omap_bootinfo[2] & 0xFF) { ++ case 0x05: ++ src = BOOTSOURCE_NAND; ++ break; ++ case 0x08: ++ src = BOOTSOURCE_MMC; ++ break; ++ case 0x0b: ++ src = BOOTSOURCE_SPI; ++ break; ++ default: ++ src = BOOTSOURCE_UNKNOWN; ++ } ++ bootsource_set(src); + bootsource_set_instance(0); + return 0; + } +diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h +index 5a10a54..f1a3efe 100644 +--- a/arch/arm/mach-omap/include/mach/generic.h ++++ b/arch/arm/mach-omap/include/mach/generic.h +@@ -27,4 +27,7 @@ + #define cpu_is_omap4xxx() (0) + #endif + ++extern uint32_t omap_bootinfo[3]; ++void omap_save_bootinfo(void); ++ + #endif +diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c +index f144813..8b661ff 100644 +--- a/arch/arm/mach-omap/omap3_generic.c ++++ b/arch/arm/mach-omap/omap3_generic.c +@@ -33,6 +33,7 @@ + #include <io.h> + #include <mach/omap3-silicon.h> + #include <mach/gpmc.h> ++#include <mach/generic.h> + #include <mach/sdrc.h> + #include <mach/control.h> + #include <mach/omap3-smx.h> +@@ -468,12 +469,21 @@ void omap3_core_init(void) + static int omap3_bootsource(void) + { + enum bootsource src = BOOTSOURCE_UNKNOWN; +- u32 bootsrc = readl(OMAP3_TRACING_VECTOR1); + +- if (bootsrc & (1 << 2)) ++ switch (omap_bootinfo[1] & 0xFF) { ++ case 0x02: + src = BOOTSOURCE_NAND; +- if (bootsrc & (1 << 6)) ++ break; ++ case 0x06: + src = BOOTSOURCE_MMC; ++ break; ++ case 0x11: ++ src = BOOTSOURCE_USB; ++ break; ++ default: ++ src = BOOTSOURCE_UNKNOWN; ++ } ++ + bootsource_set(src); + bootsource_set_instance(0); + +diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c +index 7d71fdc..4e98205 100644 +--- a/arch/arm/mach-omap/omap4_generic.c ++++ b/arch/arm/mach-omap/omap4_generic.c +@@ -6,6 +6,7 @@ + #include <mach/omap4-silicon.h> + #include <mach/omap4-mux.h> + #include <mach/syslib.h> ++#include <mach/generic.h> + #include <mach/gpmc.h> + #include <mach/gpio.h> + #include <mach/omap4_rom_usb.h> +@@ -504,14 +505,21 @@ static int omap_vector_init(void) + static int omap4_bootsource(void) + { + enum bootsource src = BOOTSOURCE_UNKNOWN; +- u32 bootsrc = readl(OMAP4_TRACING_VECTOR3); + +- if (bootsrc & (1 << 5)) +- src = BOOTSOURCE_MMC; +- else if (bootsrc & (1 << 3)) ++ switch (omap_bootinfo[2] & 0xFF) { ++ case 0x03: + src = BOOTSOURCE_NAND; +- else if (bootsrc & (1<<20)) ++ break; ++ case 0x05: ++ src = BOOTSOURCE_MMC; ++ break; ++ case 0x20: + src = BOOTSOURCE_USB; ++ break; ++ default: ++ src = BOOTSOURCE_UNKNOWN; ++ } ++ + bootsource_set(src); + bootsource_set_instance(0); + +diff --git a/arch/arm/mach-omap/omap_bootinfo.S b/arch/arm/mach-omap/omap_bootinfo.S +new file mode 100644 +index 0000000..ffd0a3d +--- /dev/null ++++ b/arch/arm/mach-omap/omap_bootinfo.S +@@ -0,0 +1,25 @@ ++#include <config.h> ++#include <linux/linkage.h> ++#include <asm/assembler.h> ++ ++.section ".text_bare_init","ax" ++.globl omap_bootinfo ++omap_bootinfo: ++ .word 0x0 ++ .word 0x0 ++ .word 0x0 ++ ++.section ".text_bare_init","ax" ++ENTRY(omap_save_bootinfo) ++ /* ++ * save data from rom boot loader ++ */ ++ adr r2, omap_bootinfo ++ ldr r1, [r0, #0x00] ++ str r1, [r2, #0x00] ++ ldr r1, [r0, #0x04] ++ str r1, [r2, #0x04] ++ ldr r1, [r0, #0x08] ++ str r1, [r2, #0x08] ++ mov pc, lr ++ENDPROC(omap_save_bootinfo) +diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c +index 3cce3f2..3dbdef5 100644 +--- a/arch/arm/mach-omap/xload.c ++++ b/arch/arm/mach-omap/xload.c +@@ -9,6 +9,7 @@ + #include <fcntl.h> + #include <sizes.h> + #include <filetype.h> ++#include <mach/generic.h> + + static void *read_image_head(const char *name) + { +@@ -163,7 +164,8 @@ static void *omap4_xload_boot_usb(void){ + */ + static __noreturn int omap_xload(void) + { +- int (*func)(void) = NULL; ++ int (*func)(void *) = NULL; ++ uint32_t *arg; + + switch (bootsource_get()) + { +@@ -198,8 +200,10 @@ static __noreturn int omap_xload(void) + while (1); + } + ++ arg = (uint32_t *)&omap_bootinfo; ++ + shutdown_barebox(); +- func(); ++ func(arg); + + while (1); + } +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0011-i2c-omap-cleanup-cpu_is-functions.patch b/patches/barebox-2013.07.0/0011-i2c-omap-cleanup-cpu_is-functions.patch new file mode 100644 index 0000000..3212c33 --- /dev/null +++ b/patches/barebox-2013.07.0/0011-i2c-omap-cleanup-cpu_is-functions.patch @@ -0,0 +1,247 @@ +From b7912f1e3d3ddebbb544e0808df65010e10efad6 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> +Date: Thu, 20 Jun 2013 14:50:28 +0200 +Subject: [PATCH 11/17] i2c-omap: cleanup cpu_is functions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +cpu_is_omap2430() is set when CONFIG_ARCH_OMAP is enabled. +This fits for all OMAP/AM33xx boards supported in barebox. +Cleaned up all conditions that use the cpu_is_omap2430(). +Also removed some unused defines. + +Signed-off-by: Teresa Gámez <t.gamez@phytec.de> +Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> +--- + drivers/i2c/busses/i2c-omap.c | 159 +++++++++++++++-------------------------- + 1 file changed, 57 insertions(+), 102 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c +index 503443f..ecb33ea 100644 +--- a/drivers/i2c/busses/i2c-omap.c ++++ b/drivers/i2c/busses/i2c-omap.c +@@ -24,10 +24,6 @@ + * GNU General Public License for more details. + */ + +- +-/* #include <linux/delay.h> */ +- +- + #include <clock.h> + #include <common.h> + #include <driver.h> +@@ -44,12 +40,6 @@ + #include <mach/generic.h> + #include <mach/omap3-clock.h> + +-#define OMAP_I2C_SIZE 0x3f +-#define OMAP1_I2C_BASE 0xfffb3800 +-#define OMAP2_I2C_BASE1 0x48070000 +-#define OMAP2_I2C_BASE2 0x48072000 +-#define OMAP2_I2C_BASE3 0x48060000 +- + /* This will be the driver name */ + #define DRIVER_NAME "i2c-omap" + +@@ -141,7 +131,6 @@ + #define SYSC_IDLEMODE_SMART 0x2 + #define SYSC_CLOCKACTIVITY_FCLK 0x2 + +- + struct omap_i2c_struct { + void *base; + u8 *regs; +@@ -352,63 +341,51 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap) + } + omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0); + +- /* omap1 handling is missing here */ +- +- if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap4xxx()) { +- +- /* +- * HSI2C controller internal clk rate should be 19.2 Mhz for +- * HS and for all modes on 2430. On 34xx we can use lower rate +- * to get longer filter period for better noise suppression. +- * The filter is iclk (fclk for HS) period. +- */ +- if (i2c_omap->speed > 400 || cpu_is_omap2430()) +- internal_clk = 19200; +- else if (i2c_omap->speed > 100) +- internal_clk = 9600; +- else +- internal_clk = 4000; +- fclk_rate = 96000000 / 1000; +- +- /* Compute prescaler divisor */ +- psc = fclk_rate / internal_clk; +- psc = psc - 1; +- +- /* If configured for High Speed */ +- if (i2c_omap->speed > 400) { +- unsigned long scl; +- +- /* For first phase of HS mode */ +- scl = internal_clk / 400; +- fsscll = scl - (scl / 3) - 7; +- fssclh = (scl / 3) - 5; +- +- /* For second phase of HS mode */ +- scl = fclk_rate / i2c_omap->speed; +- hsscll = scl - (scl / 3) - 7; +- hssclh = (scl / 3) - 5; +- } else if (i2c_omap->speed > 100) { +- unsigned long scl; +- +- /* Fast mode */ +- scl = internal_clk / i2c_omap->speed; +- fsscll = scl - (scl / 3) - 7; +- fssclh = (scl / 3) - 5; +- } else { +- /* Standard mode */ +- fsscll = internal_clk / (i2c_omap->speed * 2) - 7; +- fssclh = internal_clk / (i2c_omap->speed * 2) - 5; +- } +- scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; +- sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; ++ /* ++ * HSI2C controller internal clk rate should be 19.2 Mhz for ++ * HS and for all modes on 2430. On 34xx we can use lower rate ++ * to get longer filter period for better noise suppression. ++ * The filter is iclk (fclk for HS) period. ++ */ ++ if (i2c_omap->speed > 400) ++ internal_clk = 19200; ++ else if (i2c_omap->speed > 100) ++ internal_clk = 9600; ++ else ++ internal_clk = 4000; ++ fclk_rate = 96000000 / 1000; ++ ++ /* Compute prescaler divisor */ ++ psc = fclk_rate / internal_clk; ++ psc = psc - 1; ++ ++ /* If configured for High Speed */ ++ if (i2c_omap->speed > 400) { ++ unsigned long scl; ++ ++ /* For first phase of HS mode */ ++ scl = internal_clk / 400; ++ fsscll = scl - (scl / 3) - 7; ++ fssclh = (scl / 3) - 5; ++ ++ /* For second phase of HS mode */ ++ scl = fclk_rate / i2c_omap->speed; ++ hsscll = scl - (scl / 3) - 7; ++ hssclh = (scl / 3) - 5; ++ } else if (i2c_omap->speed > 100) { ++ unsigned long scl; ++ ++ /* Fast mode */ ++ scl = internal_clk / i2c_omap->speed; ++ fsscll = scl - (scl / 3) - 7; ++ fssclh = (scl / 3) - 5; + } else { +- /* Program desired operating rate */ +- fclk_rate /= (psc + 1) * 1000; +- if (psc > 2) +- psc = 2; +- scll = fclk_rate / (i2c_omap->speed * 2) - 7 + psc; +- sclh = fclk_rate / (i2c_omap->speed * 2) - 7 + psc; ++ /* Standard mode */ ++ fsscll = internal_clk / (i2c_omap->speed * 2) - 7; ++ fssclh = internal_clk / (i2c_omap->speed * 2) - 5; + } ++ scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; ++ sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; + + /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ + omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, psc); +@@ -525,15 +502,6 @@ complete: + if (dev->buf_len) { + *dev->buf++ = w; + dev->buf_len--; +- /* Data reg from 2430 is 8 bit wide */ +- if (!cpu_is_omap2430() && +- !cpu_is_omap34xx() && +- !cpu_is_omap4xxx()) { +- if (dev->buf_len) { +- *dev->buf++ = w >> 8; +- dev->buf_len--; +- } +- } + } else { + if (stat & OMAP_I2C_STAT_RRDY) + dev_err(&dev->adapter.dev, +@@ -566,15 +534,6 @@ complete: + if (dev->buf_len) { + w = *dev->buf++; + dev->buf_len--; +- /* Data reg from 2430 is 8 bit wide */ +- if (!cpu_is_omap2430() && +- !cpu_is_omap34xx() && +- !cpu_is_omap4xxx()) { +- if (dev->buf_len) { +- w |= *dev->buf++ << 8; +- dev->buf_len--; +- } +- } + } else { + if (stat & OMAP_I2C_STAT_XRDY) + dev_err(&dev->adapter.dev, +@@ -776,6 +735,7 @@ i2c_omap_probe(struct device_d *pdev) + /* struct i2c_platform_data *pdata; */ + int r; + u32 speed = 0; ++ u16 s; + + i2c_omap = kzalloc(sizeof(struct omap_i2c_struct), GFP_KERNEL); + if (!i2c_omap) { +@@ -802,28 +762,23 @@ i2c_omap_probe(struct device_d *pdev) + omap_i2c_unidle(i2c_omap); + + i2c_omap->rev = omap_i2c_read_reg(i2c_omap, OMAP_I2C_REV_REG) & 0xff; +- /* i2c_omap->base = OMAP2_I2C_BASE3; */ +- +- if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap4xxx()) { +- u16 s; + +- /* Set up the fifo size - Get total size */ +- s = (omap_i2c_read_reg(i2c_omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; +- i2c_omap->fifo_size = 0x8 << s; ++ /* Set up the fifo size - Get total size */ ++ s = (omap_i2c_read_reg(i2c_omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; ++ i2c_omap->fifo_size = 0x8 << s; + +- /* +- * Set up notification threshold as half the total available +- * size. This is to ensure that we can handle the status on int +- * call back latencies. +- */ ++ /* ++ * Set up notification threshold as half the total available ++ * size. This is to ensure that we can handle the status on int ++ * call back latencies. ++ */ + +- i2c_omap->fifo_size = (i2c_omap->fifo_size / 2); ++ i2c_omap->fifo_size = (i2c_omap->fifo_size / 2); + +- if (i2c_omap->rev >= OMAP_I2C_REV_ON_4430) +- i2c_omap->b_hw = 0; /* Disable hardware fixes */ +- else +- i2c_omap->b_hw = 1; /* Enable hardware fixes */ +- } ++ if (i2c_omap->rev >= OMAP_I2C_REV_ON_4430) ++ i2c_omap->b_hw = 0; /* Disable hardware fixes */ ++ else ++ i2c_omap->b_hw = 1; /* Enable hardware fixes */ + + /* reset ASAP, clearing any IRQs */ + omap_i2c_init(i2c_omap); +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0012-ARM-AM33xx-Add-i2c-support-for-AM33xx.patch b/patches/barebox-2013.07.0/0012-ARM-AM33xx-Add-i2c-support-for-AM33xx.patch new file mode 100644 index 0000000..05801aa --- /dev/null +++ b/patches/barebox-2013.07.0/0012-ARM-AM33xx-Add-i2c-support-for-AM33xx.patch @@ -0,0 +1,138 @@ +From 6289d04745fe4282a5a255318bed673e73b29bd8 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> +Date: Thu, 20 Jun 2013 14:50:29 +0200 +Subject: [PATCH 12/17] ARM: AM33xx: Add i2c support for AM33xx +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Added device register functions and cpu_is_am33xx() +function. +Adapted the i2c-omap driver. AM335x has a lower +clock rate and the timeout of polling the isr function +had to be increased. + +Based on a patch from Shravan Kumar <shravan.k@phytec.in>. + +Signed-off-by: Teresa Gámez <t.gamez@phytec.de> +Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> +--- + arch/arm/mach-omap/include/mach/am33xx-devices.h | 15 +++++++++++++++ + arch/arm/mach-omap/include/mach/am33xx-silicon.h | 5 +++++ + arch/arm/mach-omap/include/mach/generic.h | 6 ++++++ + drivers/i2c/busses/i2c-omap.c | 14 +++++++++----- + 4 files changed, 35 insertions(+), 5 deletions(-) + +diff --git a/arch/arm/mach-omap/include/mach/am33xx-devices.h b/arch/arm/mach-omap/include/mach/am33xx-devices.h +index fe9fba9..edf8982 100644 +--- a/arch/arm/mach-omap/include/mach/am33xx-devices.h ++++ b/arch/arm/mach-omap/include/mach/am33xx-devices.h +@@ -37,4 +37,19 @@ static inline struct device_d *am33xx_add_cpsw(struct cpsw_platform_data *cpsw_d + AM335X_CPSW_BASE, SZ_32K, IORESOURCE_MEM, cpsw_data); + } + ++static inline struct device_d *am33xx_add_i2c0(void *pdata) ++{ ++ return omap_add_i2c(0, AM33XX_I2C0_BASE, pdata); ++} ++ ++static inline struct device_d *am33xx_add_i2c1(void *pdata) ++{ ++ return omap_add_i2c(1, AM33XX_I2C1_BASE, pdata); ++} ++ ++static inline struct device_d *am33xx_add_i2c2(void *pdata) ++{ ++ return omap_add_i2c(2, AM33XX_I2C2_BASE, pdata); ++} ++ + #endif /* __MACH_OMAP3_DEVICES_H */ +diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h +index 9edf4ca..9cf3e73 100644 +--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h ++++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h +@@ -41,6 +41,11 @@ + #define AM33XX_DRAM_ADDR_SPACE_START 0x80000000 + #define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000 + ++/* I2C */ ++#define AM33XX_I2C0_BASE (AM33XX_L4_WKUP_BASE + 0x20B000) ++#define AM33XX_I2C1_BASE (AM33XX_L4_PER_BASE + 0x02A000) ++#define AM33XX_I2C2_BASE (AM33XX_L4_PER_BASE + 0x19C000) ++ + /* GPMC */ + #define AM33XX_GPMC_BASE 0x50000000 + +diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h +index f1a3efe..9c474e2 100644 +--- a/arch/arm/mach-omap/include/mach/generic.h ++++ b/arch/arm/mach-omap/include/mach/generic.h +@@ -27,6 +27,12 @@ + #define cpu_is_omap4xxx() (0) + #endif + ++#ifdef CONFIG_ARCH_AM33XX ++#define cpu_is_am33xx() (1) ++#else ++#define cpu_is_am33xx() (0) ++#endif ++ + extern uint32_t omap_bootinfo[3]; + void omap_save_bootinfo(void); + +diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c +index ecb33ea..19d54ee 100644 +--- a/drivers/i2c/busses/i2c-omap.c ++++ b/drivers/i2c/busses/i2c-omap.c +@@ -245,7 +245,7 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_struct *i2c_omap, int reg) + + static void omap_i2c_unidle(struct omap_i2c_struct *i2c_omap) + { +- if (cpu_is_omap34xx()) { ++ if (cpu_is_omap34xx() || cpu_is_am33xx()) { + omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0); + omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, i2c_omap->pscstate); + omap_i2c_write_reg(i2c_omap, OMAP_I2C_SCLL_REG, i2c_omap->scllstate); +@@ -353,7 +353,11 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap) + internal_clk = 9600; + else + internal_clk = 4000; +- fclk_rate = 96000000 / 1000; ++ ++ if (cpu_is_am33xx()) ++ fclk_rate = 48000; ++ else ++ fclk_rate = 96000; + + /* Compute prescaler divisor */ + psc = fclk_rate / internal_clk; +@@ -410,7 +414,7 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap) + OMAP_I2C_IE_AL) | ((i2c_omap->fifo_size) ? + (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); + omap_i2c_write_reg(i2c_omap, OMAP_I2C_IE_REG, i2c_omap->iestate); +- if (cpu_is_omap34xx()) { ++ if (cpu_is_omap34xx() || cpu_is_am33xx()) { + i2c_omap->pscstate = psc; + i2c_omap->scllstate = scll; + i2c_omap->sclhstate = sclh; +@@ -665,7 +669,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adapter, + ret = omap_i2c_isr(i2c_omap); + while (ret){ + ret = omap_i2c_isr(i2c_omap); +- if (is_timeout(start, MSECOND)) { ++ if (is_timeout(start, 50 * MSECOND)) { + dev_err(&adapter->dev, + "timed out on polling for " + "open i2c message handling\n"); +@@ -743,7 +747,7 @@ i2c_omap_probe(struct device_d *pdev) + goto err_free_mem; + } + +- if (cpu_is_omap4xxx()) { ++ if (cpu_is_omap4xxx() || cpu_is_am33xx()) { + i2c_omap->regs = (u8 *)omap4_reg_map; + i2c_omap->reg_shift = 0; + } else { +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0013-beaglebone-configure-I2C-EEPROM.patch b/patches/barebox-2013.07.0/0013-beaglebone-configure-I2C-EEPROM.patch new file mode 100644 index 0000000..9d43570 --- /dev/null +++ b/patches/barebox-2013.07.0/0013-beaglebone-configure-I2C-EEPROM.patch @@ -0,0 +1,38 @@ +From c8c5086b65d13a7f59414db2f52c5381c4279bb5 Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Sun, 14 Jul 2013 14:13:02 +0200 +Subject: [PATCH 13/17] beaglebone: configure I2C EEPROM + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + arch/arm/boards/beaglebone/board.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c +index b3f39ea..ccb7004 100644 +--- a/arch/arm/boards/beaglebone/board.c ++++ b/arch/arm/boards/beaglebone/board.c +@@ -97,11 +97,20 @@ static void beaglebone_eth_init(void) + am33xx_add_cpsw(&cpsw_data); + } + ++static struct i2c_board_info i2c0_devices[] = { ++ { ++ I2C_BOARD_INFO("24c256", 0x50) ++ }, ++}; ++ + static int beaglebone_devices_init(void) + { + am33xx_add_mmc0(NULL); + + am33xx_enable_i2c0_pin_mux(); ++ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); ++ am33xx_add_i2c0(NULL); ++ + beaglebone_eth_init(); + + armlinux_set_bootparams((void *)0x80000100); +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0014-arm-cpuinfo-display-the-core-name-and-version.patch b/patches/barebox-2013.07.0/0014-arm-cpuinfo-display-the-core-name-and-version.patch new file mode 100644 index 0000000..bda2c18 --- /dev/null +++ b/patches/barebox-2013.07.0/0014-arm-cpuinfo-display-the-core-name-and-version.patch @@ -0,0 +1,64 @@ +From 2eb44063bbe56d7e9e1fe2cd11e3f6addf60e248 Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Sun, 14 Jul 2013 15:45:03 +0200 +Subject: [PATCH 14/17] arm: cpuinfo: display the core name and version + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + arch/arm/cpu/cpuinfo.c | 33 +++++++++++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c +index 8aea4b4..260d47b 100644 +--- a/arch/arm/cpu/cpuinfo.c ++++ b/arch/arm/cpu/cpuinfo.c +@@ -31,6 +31,12 @@ + #define CPU_ARCH_ARMv6 8 + #define CPU_ARCH_ARMv7 9 + ++#define ARM_CPU_PART_CORTEX_A5 0xC050 ++#define ARM_CPU_PART_CORTEX_A7 0xC070 ++#define ARM_CPU_PART_CORTEX_A8 0xC080 ++#define ARM_CPU_PART_CORTEX_A9 0xC090 ++#define ARM_CPU_PART_CORTEX_A15 0xC0F0 ++ + static void decode_cache(unsigned long size) + { + int linelen = 1 << ((size & 0x3) + 3); +@@ -154,6 +160,33 @@ static int do_cpuinfo(int argc, char *argv[]) + printf("implementer: %s\narchitecture: %s\n", + implementer, architecture); + ++ if (cpu_arch == CPU_ARCH_ARMv7) { ++ unsigned int major, minor; ++ char *part; ++ major = (mainid >> 20) & 0xf; ++ minor = mainid & 0xf; ++ switch (mainid & 0xfff0) { ++ case ARM_CPU_PART_CORTEX_A5: ++ part = "Cortex-A5"; ++ break; ++ case ARM_CPU_PART_CORTEX_A7: ++ part = "Cortex-A7"; ++ break; ++ case ARM_CPU_PART_CORTEX_A8: ++ part = "Cortex-A8"; ++ break; ++ case ARM_CPU_PART_CORTEX_A9: ++ part = "Cortex-A9"; ++ break; ++ case ARM_CPU_PART_CORTEX_A15: ++ part = "Cortex-A15"; ++ break; ++ default: ++ part = "unknown"; ++ } ++ printf("core: %s r%up%u\n", part, major, minor); ++ } ++ + if (cache & (1 << 24)) { + /* separate I/D cache */ + printf("I-cache: "); +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0015-am33xx-implement-cpu-revision-decoding.patch b/patches/barebox-2013.07.0/0015-am33xx-implement-cpu-revision-decoding.patch new file mode 100644 index 0000000..c4154e9 --- /dev/null +++ b/patches/barebox-2013.07.0/0015-am33xx-implement-cpu-revision-decoding.patch @@ -0,0 +1,113 @@ +From 6e2126a736cb0aea390a941bbb1e735fab045def Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Sun, 14 Jul 2013 16:42:46 +0200 +Subject: [PATCH 15/17] am33xx: implement cpu revision decoding + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + arch/arm/mach-omap/am33xx_generic.c | 34 +++++++++++++++++++++- + arch/arm/mach-omap/include/mach/am33xx-silicon.h | 1 + + arch/arm/mach-omap/include/mach/sys_info.h | 10 +++++-- + 3 files changed, 42 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c +index 45fefb4..18661d7 100644 +--- a/arch/arm/mach-omap/am33xx_generic.c ++++ b/arch/arm/mach-omap/am33xx_generic.c +@@ -1,6 +1,6 @@ + /* + * (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH +- * (C) Copyright 2012 Jan Luebbe <j.luebbe@pengutronix.de> ++ * (C) Copyright 2012-2013 Jan Luebbe <j.luebbe@pengutronix.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as +@@ -37,6 +37,38 @@ void __noreturn reset_cpu(unsigned long addr) + } + + /** ++ * @brief Extract the AM33xx ES revision ++ * ++ * The significance of the CPU revision depends upon the cpu type. ++ * Latest known revision is considered default. ++ * ++ * @return silicon version ++ */ ++u32 get_cpu_rev(void) ++{ ++ u32 version, retval; ++ ++ version = (readl(AM33XX_IDCODE_REG) >> 28) & 0xF; ++ ++ switch (version) { ++ case 0: ++ retval = AM335X_ES1_0; ++ break; ++ case 1: ++ retval = AM335X_ES2_0; ++ break; ++ case 2: ++ /* ++ * Fall through the default case. ++ */ ++ default: ++ retval = AM335X_ES2_1; ++ } ++ ++ return retval; ++} ++ ++/** + * @brief Get the upper address of current execution + * + * we can use this to figure out if we are running in SRAM / +diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h +index 9cf3e73..06035c4 100644 +--- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h ++++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h +@@ -65,6 +65,7 @@ + + /* CTRL */ + #define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000) ++#define AM33XX_IDCODE_REG (AM33XX_CTRL_BASE + 0x600) + + /* Watchdog Timer */ + #define AM33XX_WDT_BASE 0x44E35000 +diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h +index 4d9b138..fce5895 100644 +--- a/arch/arm/mach-omap/include/mach/sys_info.h ++++ b/arch/arm/mach-omap/include/mach/sys_info.h +@@ -40,6 +40,7 @@ + #define CPU_1710 0x1710 + #define CPU_2420 0x2420 + #define CPU_2430 0x2430 ++#define CPU_3350 0x3350 + #define CPU_3430 0x3430 + #define CPU_3630 0x3630 + +@@ -54,6 +55,10 @@ + #define OMAP34XX_ES3 cpu_revision(CPU_3430, 3) + #define OMAP34XX_ES3_1 cpu_revision(CPU_3430, 4) + ++#define AM335X_ES1_0 cpu_revision(CPU_3350, 0) ++#define AM335X_ES2_0 cpu_revision(CPU_3350, 1) ++#define AM335X_ES2_1 cpu_revision(CPU_3350, 2) ++ + #define OMAP36XX_ES1 cpu_revision(CPU_3630, 0) + #define OMAP36XX_ES1_1 cpu_revision(CPU_3630, 1) + #define OMAP36XX_ES1_2 cpu_revision(CPU_3630, 2) +@@ -76,8 +81,9 @@ + /** + * Hawkeye definitions to identify silicon families + */ +-#define OMAP_HAWKEYE_34XX 0xB7AE +-#define OMAP_HAWKEYE_36XX 0xB891 ++#define OMAP_HAWKEYE_34XX 0xB7AE /* OMAP34xx */ ++#define OMAP_HAWKEYE_36XX 0xB891 /* OMAP36xx */ ++#define OMAP_HAWKEYE_335X 0xB944 /* AM335x */ + + /** These are implemented by the System specific code in omapX-generic.c */ + u32 get_cpu_type(void); +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0016-beaglebone-split-out-DDR2-init-for-BB-White.patch b/patches/barebox-2013.07.0/0016-beaglebone-split-out-DDR2-init-for-BB-White.patch new file mode 100644 index 0000000..a74892c --- /dev/null +++ b/patches/barebox-2013.07.0/0016-beaglebone-split-out-DDR2-init-for-BB-White.patch @@ -0,0 +1,417 @@ +From 425a24f42a726b6dc30d23c474dcacbb719820c5 Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Sun, 14 Jul 2013 18:22:51 +0200 +Subject: [PATCH 16/17] beaglebone: split out DDR2 init for BB White + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + arch/arm/boards/beaglebone/Makefile | 2 +- + arch/arm/boards/beaglebone/ddr.h | 1 + + arch/arm/boards/beaglebone/ddr2.c | 178 +++++++++++++++++++++++++++++++++ + arch/arm/boards/beaglebone/lowlevel.c | 175 +------------------------------- + 4 files changed, 184 insertions(+), 172 deletions(-) + create mode 100644 arch/arm/boards/beaglebone/ddr.h + create mode 100644 arch/arm/boards/beaglebone/ddr2.c + +diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile +index 092c31d..7ec0c8b 100644 +--- a/arch/arm/boards/beaglebone/Makefile ++++ b/arch/arm/boards/beaglebone/Makefile +@@ -1,2 +1,2 @@ +-lwl-y += lowlevel.o ++lwl-y += lowlevel.o ddr2.o + obj-y += board.o +diff --git a/arch/arm/boards/beaglebone/ddr.h b/arch/arm/boards/beaglebone/ddr.h +new file mode 100644 +index 0000000..d2f0c95 +--- /dev/null ++++ b/arch/arm/boards/beaglebone/ddr.h +@@ -0,0 +1 @@ ++void beaglebone_config_ddr2(void); +diff --git a/arch/arm/boards/beaglebone/ddr2.c b/arch/arm/boards/beaglebone/ddr2.c +new file mode 100644 +index 0000000..42a099d +--- /dev/null ++++ b/arch/arm/boards/beaglebone/ddr2.c +@@ -0,0 +1,178 @@ ++#include <init.h> ++#include <sizes.h> ++#include <io.h> ++#include <asm/armlinux.h> ++#include <asm/barebox-arm-head.h> ++#include <asm/barebox-arm.h> ++#include <mach/am33xx-silicon.h> ++#include <mach/am33xx-clock.h> ++ ++/* AM335X EMIF Register values */ ++#define EMIF_SDMGT 0x80000000 ++#define EMIF_SDRAM 0x00004650 ++#define EMIF_PHYCFG 0x2 ++#define DDR_PHY_RESET (0x1 << 10) ++#define DDR_FUNCTIONAL_MODE_EN 0x1 ++#define DDR_PHY_READY (0x1 << 2) ++#define VTP_CTRL_READY (0x1 << 5) ++#define VTP_CTRL_ENABLE (0x1 << 6) ++#define VTP_CTRL_LOCK_EN (0x1 << 4) ++#define VTP_CTRL_START_EN (0x1) ++#define DDR2_RATIO 0x80 /* for mDDR */ ++#define CMD_FORCE 0x00 /* common #def */ ++#define CMD_DELAY 0x00 ++ ++#define EMIF_READ_LATENCY 0x05 ++#define EMIF_TIM1 0x0666B3D6 ++#define EMIF_TIM2 0x143731DA ++#define EMIF_TIM3 0x00000347 ++#define EMIF_SDCFG 0x43805332 ++#define EMIF_SDREF 0x0000081a ++#define DDR2_DLL_LOCK_DIFF 0x0 ++#define DDR2_RD_DQS 0x12 ++#define DDR2_PHY_FIFO_WE 0x80 ++ ++#define DDR2_INVERT_CLKOUT 0x00 ++#define DDR2_WR_DQS 0x00 ++#define DDR2_PHY_WRLVL 0x00 ++#define DDR2_PHY_GATELVL 0x00 ++#define DDR2_PHY_WR_DATA 0x40 ++#define PHY_RANK0_DELAY 0x01 ++#define PHY_DLL_LOCK_DIFF 0x0 ++#define DDR_IOCTRL_VALUE 0x18B ++ ++static void beaglebone_data_macro_config_ddr2(int dataMacroNum) ++{ ++ u32 BaseAddrOffset = 0x00; ++ ++ if (dataMacroNum == 1) ++ BaseAddrOffset = 0xA4; ++ ++ __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) ++ |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), ++ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_RD_DQS>>2, ++ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); ++ __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) ++ |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), ++ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_WR_DQS>>2, ++ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); ++ __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) ++ |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), ++ (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_PHY_WRLVL>>2, ++ (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset)); ++ __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) ++ |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), ++ (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_PHY_GATELVL>>2, ++ (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset)); ++ __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) ++ |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), ++ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_PHY_FIFO_WE>>2, ++ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset)); ++ __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) ++ |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), ++ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_PHY_WR_DATA>>2, ++ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset)); ++ __raw_writel(PHY_DLL_LOCK_DIFF, ++ (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); ++} ++ ++static void beaglebone_cmd_macro_config_ddr2(void) ++{ ++ __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); ++ __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); ++ __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); ++ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); ++ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); ++ ++ __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); ++ __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); ++ __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); ++ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); ++ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); ++ ++ __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); ++ __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); ++ __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); ++ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); ++ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); ++} ++ ++static void beaglebone_config_vtp_ddr2(void) ++{ ++ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, ++ AM33XX_VTP0_CTRL_REG); ++ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), ++ AM33XX_VTP0_CTRL_REG); ++ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, ++ AM33XX_VTP0_CTRL_REG); ++ ++ /* Poll for READY */ ++ while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); ++} ++ ++static void beaglebone_config_emif_ddr2(void) ++{ ++ u32 i; ++ ++ /*Program EMIF0 CFG Registers*/ ++ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); ++ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); ++ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); ++ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); ++ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); ++ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); ++ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); ++ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); ++ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); ++ ++ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); ++ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); ++ ++ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); ++ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ ++ __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); ++ __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); ++ ++ for (i = 0; i < 5000; i++) { ++ ++ } ++ ++ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); ++ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ ++ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); ++ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); ++ ++ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); ++ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); ++} ++ ++void beaglebone_config_ddr2(void) ++{ ++ enable_ddr_clocks(); ++ ++ beaglebone_config_vtp_ddr2(); ++ ++ beaglebone_cmd_macro_config_ddr2(); ++ beaglebone_data_macro_config_ddr2(0); ++ beaglebone_data_macro_config_ddr2(1); ++ ++ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); ++ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); ++ ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); ++ ++ __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); ++ __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); ++ ++ beaglebone_config_emif_ddr2(); ++} +diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c +index 59d9ff1..282b471 100644 +--- a/arch/arm/boards/beaglebone/lowlevel.c ++++ b/arch/arm/boards/beaglebone/lowlevel.c +@@ -13,6 +13,8 @@ + #include <mach/am33xx-mux.h> + #include <mach/wdt.h> + ++#include "ddr.h" ++ + /* UART Defines */ + #define UART_SYSCFG_OFFSET (0x54) + #define UART_SYSSTS_OFFSET (0x58) +@@ -21,176 +23,6 @@ + #define UART_CLK_RUNNING_MASK 0x1 + #define UART_SMART_IDLE_EN (0x1 << 0x3) + +-/* AM335X EMIF Register values */ +-#define EMIF_SDMGT 0x80000000 +-#define EMIF_SDRAM 0x00004650 +-#define EMIF_PHYCFG 0x2 +-#define DDR_PHY_RESET (0x1 << 10) +-#define DDR_FUNCTIONAL_MODE_EN 0x1 +-#define DDR_PHY_READY (0x1 << 2) +-#define VTP_CTRL_READY (0x1 << 5) +-#define VTP_CTRL_ENABLE (0x1 << 6) +-#define VTP_CTRL_LOCK_EN (0x1 << 4) +-#define VTP_CTRL_START_EN (0x1) +-#define DDR2_RATIO 0x80 /* for mDDR */ +-#define CMD_FORCE 0x00 /* common #def */ +-#define CMD_DELAY 0x00 +- +-#define EMIF_READ_LATENCY 0x05 +-#define EMIF_TIM1 0x0666B3D6 +-#define EMIF_TIM2 0x143731DA +-#define EMIF_TIM3 0x00000347 +-#define EMIF_SDCFG 0x43805332 +-#define EMIF_SDREF 0x0000081a +-#define DDR2_DLL_LOCK_DIFF 0x0 +-#define DDR2_RD_DQS 0x12 +-#define DDR2_PHY_FIFO_WE 0x80 +- +-#define DDR2_INVERT_CLKOUT 0x00 +-#define DDR2_WR_DQS 0x00 +-#define DDR2_PHY_WRLVL 0x00 +-#define DDR2_PHY_GATELVL 0x00 +-#define DDR2_PHY_WR_DATA 0x40 +-#define PHY_RANK0_DELAY 0x01 +-#define PHY_DLL_LOCK_DIFF 0x0 +-#define DDR_IOCTRL_VALUE 0x18B +- +-static void beaglebone_data_macro_config(int dataMacroNum) +-{ +- u32 BaseAddrOffset = 0x00; +- +- if (dataMacroNum == 1) +- BaseAddrOffset = 0xA4; +- +- __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) +- |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), +- (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); +- __raw_writel(DDR2_RD_DQS>>2, +- (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); +- __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) +- |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), +- (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); +- __raw_writel(DDR2_WR_DQS>>2, +- (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); +- __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) +- |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), +- (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset)); +- __raw_writel(DDR2_PHY_WRLVL>>2, +- (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset)); +- __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) +- |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), +- (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset)); +- __raw_writel(DDR2_PHY_GATELVL>>2, +- (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset)); +- __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) +- |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), +- (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); +- __raw_writel(DDR2_PHY_FIFO_WE>>2, +- (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset)); +- __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) +- |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), +- (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); +- __raw_writel(DDR2_PHY_WR_DATA>>2, +- (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset)); +- __raw_writel(PHY_DLL_LOCK_DIFF, +- (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); +-} +- +-static void beaglebone_cmd_macro_config(void) +-{ +- __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); +- __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); +- __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); +- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); +- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); +- +- __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); +- __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); +- __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); +- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); +- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); +- +- __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); +- __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); +- __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); +- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); +- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); +-} +- +-static void beaglebone_config_vtp(void) +-{ +- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, +- AM33XX_VTP0_CTRL_REG); +- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), +- AM33XX_VTP0_CTRL_REG); +- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, +- AM33XX_VTP0_CTRL_REG); +- +- /* Poll for READY */ +- while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); +-} +- +-static void beaglebone_config_emif_ddr2(void) +-{ +- u32 i; +- +- /*Program EMIF0 CFG Registers*/ +- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); +- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); +- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); +- __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); +- __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); +- __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); +- __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); +- __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); +- __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); +- +- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); +- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); +- +- /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); +- __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ +- __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); +- __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); +- +- for (i = 0; i < 5000; i++) { +- +- } +- +- /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); +- __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ +- __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); +- __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); +- +- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); +- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); +-} +- +-static void beaglebone_config_ddr(void) +-{ +- enable_ddr_clocks(); +- +- beaglebone_config_vtp(); +- +- beaglebone_cmd_macro_config(); +- beaglebone_data_macro_config(0); +- beaglebone_data_macro_config(1); +- +- __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); +- __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); +- +- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); +- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); +- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); +- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); +- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); +- +- __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); +- __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); +- +- beaglebone_config_emif_ddr2(); +-} +- + /* + * early system init of muxing and clocks. + */ +@@ -201,7 +33,8 @@ void beaglebone_sram_init(void) + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(MPUPLL_M_500); + +- beaglebone_config_ddr(); ++ if (get_cpu_rev() == AM335X_ES1_0) ++ beaglebone_config_ddr2(); + + /* Enable pin mux */ + am33xx_enable_uart0_pin_mux(); +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/0017-beaglebone-add-support-for-beaglebone-black-with-DDR.patch b/patches/barebox-2013.07.0/0017-beaglebone-add-support-for-beaglebone-black-with-DDR.patch new file mode 100644 index 0000000..aa5edbf --- /dev/null +++ b/patches/barebox-2013.07.0/0017-beaglebone-add-support-for-beaglebone-black-with-DDR.patch @@ -0,0 +1,396 @@ +From d8b67830c302eb2cf3d396f1828534850f136771 Mon Sep 17 00:00:00 2001 +From: Jan Luebbe <jlu@pengutronix.de> +Date: Sun, 14 Jul 2013 19:25:39 +0200 +Subject: [PATCH 17/17] beaglebone: add support for beaglebone black with DDR3 + RAM + +Also allow configuration of the DDR PLL from board code + +Signed-off-by: Jan Luebbe <jlu@pengutronix.de> +--- + arch/arm/boards/beaglebone/Makefile | 2 +- + arch/arm/boards/beaglebone/board.c | 47 ++++++- + arch/arm/boards/beaglebone/ddr.h | 1 + + arch/arm/boards/beaglebone/ddr3.c | 155 ++++++++++++++++++++++ + arch/arm/boards/beaglebone/lowlevel.c | 11 +- + arch/arm/mach-omap/am33xx_clock.c | 9 +- + arch/arm/mach-omap/include/mach/am33xx-clock.h | 5 +- + arch/arm/mach-omap/include/mach/am33xx-devices.h | 6 + + 8 files changed, 222 insertions(+), 14 deletions(-) + create mode 100644 arch/arm/boards/beaglebone/ddr3.c + +diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile +index 7ec0c8b..eb2ffec 100644 +--- a/arch/arm/boards/beaglebone/Makefile ++++ b/arch/arm/boards/beaglebone/Makefile +@@ -1,2 +1,2 @@ +-lwl-y += lowlevel.o ddr2.o ++lwl-y += lowlevel.o ddr2.o ddr3.o + obj-y += board.o +diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c +index ccb7004..a01fe1b 100644 +--- a/arch/arm/boards/beaglebone/board.c ++++ b/arch/arm/boards/beaglebone/board.c +@@ -26,6 +26,8 @@ + #include <init.h> + #include <driver.h> + #include <envfs.h> ++#include <environment.h> ++#include <globalvar.h> + #include <sizes.h> + #include <io.h> + #include <ns16550.h> +@@ -68,7 +70,11 @@ console_initcall(beaglebone_console_init); + + static int beaglebone_mem_init(void) + { +- omap_add_ram0(SZ_256M); ++ if (get_cpu_rev() == AM335X_ES1_0) { /* white */ ++ omap_add_ram0(SZ_256M); ++ } else { /* black */ ++ omap_add_ram0(SZ_512M); ++ } + + return 0; + } +@@ -103,19 +109,56 @@ static struct i2c_board_info i2c0_devices[] = { + }, + }; + ++static const __maybe_unused struct module_pin_mux mmc1_pin_mux[] = { ++ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */ ++ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */ ++ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */ ++ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */ ++ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE)}, /* MMC1_DAT4 */ ++ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE)}, /* MMC1_DAT5 */ ++ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE)}, /* MMC1_DAT6 */ ++ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE)}, /* MMC1_DAT7 */ ++ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ ++ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ ++ {-1}, ++}; ++ + static int beaglebone_devices_init(void) + { ++ bool black = get_cpu_rev() != AM335X_ES1_0; ++ ++ am33xx_enable_mmc0_pin_mux(); + am33xx_add_mmc0(NULL); + ++ if (black) { ++ configure_module_pin_mux(mmc1_pin_mux); ++ am33xx_add_mmc1(NULL); ++ } ++ + am33xx_enable_i2c0_pin_mux(); + i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); + am33xx_add_i2c0(NULL); + + beaglebone_eth_init(); + ++ return 0; ++} ++device_initcall(beaglebone_devices_init); ++ ++static int beaglebone_env_init(void) ++{ ++ bool black = get_cpu_rev() != AM335X_ES1_0; ++ ++#if defined(CONFIG_GLOBALVAR) ++ globalvar_add_simple("board.variant"); ++ setenv("global.board.variant", black ? "boneblack" : "bone"); ++#endif ++ ++ printf("detected 'BeageBone %s'\n", black ? "Black" : "White"); ++ + armlinux_set_bootparams((void *)0x80000100); + armlinux_set_architecture(MACH_TYPE_BEAGLEBONE); + + return 0; + } +-device_initcall(beaglebone_devices_init); ++late_initcall(beaglebone_env_init); +diff --git a/arch/arm/boards/beaglebone/ddr.h b/arch/arm/boards/beaglebone/ddr.h +index d2f0c95..46c2504 100644 +--- a/arch/arm/boards/beaglebone/ddr.h ++++ b/arch/arm/boards/beaglebone/ddr.h +@@ -1 +1,2 @@ + void beaglebone_config_ddr2(void); ++void beaglebone_config_ddr3(void); +diff --git a/arch/arm/boards/beaglebone/ddr3.c b/arch/arm/boards/beaglebone/ddr3.c +new file mode 100644 +index 0000000..643a94d +--- /dev/null ++++ b/arch/arm/boards/beaglebone/ddr3.c +@@ -0,0 +1,155 @@ ++#include <init.h> ++#include <sizes.h> ++#include <io.h> ++#include <asm/armlinux.h> ++#include <asm/barebox-arm-head.h> ++#include <asm/barebox-arm.h> ++#include <mach/am33xx-silicon.h> ++#include <mach/am33xx-clock.h> ++ ++/* AM335X EMIF Register values */ ++#define EMIF_SDMGT 0x80000000 ++#define EMIF_SDRAM 0x00004650 ++#define EMIF_PHYCFG 0x2 ++#define DDR_PHY_RESET (0x1 << 10) ++#define DDR_FUNCTIONAL_MODE_EN 0x1 ++#define DDR_PHY_READY (0x1 << 2) ++#define VTP_CTRL_READY (0x1 << 5) ++#define VTP_CTRL_ENABLE (0x1 << 6) ++#define VTP_CTRL_LOCK_EN (0x1 << 4) ++#define VTP_CTRL_START_EN (0x1) ++#define DDR2_RATIO 0x80 /* for mDDR */ ++#define CMD_FORCE 0x00 /* common #def */ ++#define CMD_DELAY 0x00 ++ ++#define EMIF_READ_LATENCY 0x100007 ++#define EMIF_TIM1 0x0AAAD4DB ++#define EMIF_TIM2 0x266B7FDA ++#define EMIF_TIM3 0x501F867F ++#define EMIF_SDCFG 0x61C05332 ++#define EMIF_SDREF 0xC30 ++#define ZQ_CFG 0x50074BE4 ++#define DDR2_DLL_LOCK_DIFF 0x1 ++#define DDR2_RD_DQS 0x38 ++#define DDR2_WR_DQS 0x44 ++#define DDR2_PHY_FIFO_WE 0x94 ++#define DDR2_PHY_WR_DATA 0x7D ++ ++#define DDR2_INVERT_CLKOUT 0x0 ++#define PHY_RANK0_DELAY 0x01 ++#define PHY_DLL_LOCK_DIFF 0x0 ++#define DDR_IOCTRL_VALUE 0x18B ++ ++static void beaglebone_data_macro_config_ddr3(int dataMacroNum) ++{ ++ u32 BaseAddrOffset = 0x00; ++ ++ if (dataMacroNum == 1) ++ BaseAddrOffset = 0xA4; ++ ++ __raw_writel(DDR2_RD_DQS, ++ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_WR_DQS, ++ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_PHY_FIFO_WE, ++ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(DDR2_PHY_WR_DATA, ++ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); ++ __raw_writel(PHY_DLL_LOCK_DIFF, ++ (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); ++} ++ ++static void beaglebone_cmd_macro_config_ddr3(void) ++{ ++ __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); ++ __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); ++ __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); ++ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); ++ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); ++ ++ __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); ++ __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); ++ __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); ++ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); ++ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); ++ ++ __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); ++ __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); ++ __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); ++ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); ++ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); ++} ++ ++static void beaglebone_config_vtp_ddr3(void) ++{ ++ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, ++ AM33XX_VTP0_CTRL_REG); ++ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), ++ AM33XX_VTP0_CTRL_REG); ++ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, ++ AM33XX_VTP0_CTRL_REG); ++ ++ /* Poll for READY */ ++ while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); ++} ++ ++static void beaglebone_config_emif_ddr3(void) ++{ ++ u32 i; ++ ++ /*Program EMIF0 CFG Registers*/ ++ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); ++ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); ++ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); ++ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); ++ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); ++ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); ++ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); ++ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); ++ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); ++ ++ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); ++ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); ++ ++ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); ++ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ ++ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); ++ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); ++ ++ for (i = 0; i < 5000; i++) { ++ ++ } ++ ++ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); ++ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ ++ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); ++ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); ++ ++ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); ++ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); ++} ++ ++void beaglebone_config_ddr3(void) ++{ ++ enable_ddr_clocks(); ++ ++ beaglebone_config_vtp_ddr3(); ++ ++ beaglebone_cmd_macro_config_ddr3(); ++ beaglebone_data_macro_config_ddr3(0); ++ beaglebone_data_macro_config_ddr3(1); ++ ++ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); ++ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); ++ ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); ++ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); ++ ++ __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); ++ __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); ++ ++ beaglebone_config_emif_ddr3(); ++} +diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c +index 282b471..c1e11a1 100644 +--- a/arch/arm/boards/beaglebone/lowlevel.c ++++ b/arch/arm/boards/beaglebone/lowlevel.c +@@ -31,10 +31,13 @@ void beaglebone_sram_init(void) + u32 regVal, uart_base; + + /* Setup the PLLs and the clocks for the peripherals */ +- pll_init(MPUPLL_M_500); +- +- if (get_cpu_rev() == AM335X_ES1_0) ++ if (get_cpu_rev() == AM335X_ES1_0) { /* white */ ++ pll_init(MPUPLL_M_500, DDRPLL_M_266); + beaglebone_config_ddr2(); ++ } else { /* black */ ++ pll_init(MPUPLL_M_500, DDRPLL_M_400); ++ beaglebone_config_ddr3(); ++ } + + /* Enable pin mux */ + am33xx_enable_uart0_pin_mux(); +@@ -100,6 +103,6 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) + + beaglebone_board_init(); + +- barebox_arm_entry(0x80000000, SZ_256M, 0); ++ barebox_arm_entry(0x80000000, SZ_256M, 0); /* real RAM setup comes later */ + /* barebox_arm_entry(0x402F0400, 0x4030CE00-0x402F0400, 0); */ /* for SRAM */ + } +diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c +index 9928e9f..e0ba197 100644 +--- a/arch/arm/mach-omap/am33xx_clock.c ++++ b/arch/arm/mach-omap/am33xx_clock.c +@@ -248,7 +248,7 @@ static void per_pll_config(void) + while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1); + } + +-static void ddr_pll_config(void) ++static void ddr_pll_config(int ddrpll_M) + { + u32 clkmode, clksel, div_m2; + +@@ -263,7 +263,7 @@ static void ddr_pll_config(void) + while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100); + + clksel = clksel & (~0x7ffff); +- clksel = clksel | ((DDRPLL_M << 0x8) | DDRPLL_N); ++ clksel = clksel | ((ddrpll_M << 0x8) | DDRPLL_N); + __raw_writel(clksel, CM_CLKSEL_DPLL_DDR); + + div_m2 = div_m2 & 0xFFFFFFE0; +@@ -288,18 +288,17 @@ void enable_ddr_clocks(void) + PRCM_L3_GCLK_ACTIVITY)); + /* Poll if module is functional */ + while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN); +- + } + + /* + * Configure the PLL/PRCM for necessary peripherals + */ +-void pll_init(int mpupll_M) ++void pll_init(int mpupll_M, int ddrpll_M) + { + mpu_pll_config(mpupll_M); + core_pll_config(); + per_pll_config(); +- ddr_pll_config(); ++ ddr_pll_config(ddrpll_M); + /* Enable the required interconnect clocks */ + interface_clocks_enable(); + /* Enable power domain transition */ +diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h +index 968509e..3f86d14 100644 +--- a/arch/arm/mach-omap/include/mach/am33xx-clock.h ++++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h +@@ -53,7 +53,8 @@ + + /* DDR Freq is 266 MHZ for now*/ + /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ +-#define DDRPLL_M 266 ++#define DDRPLL_M_266 266 ++#define DDRPLL_M_400 400 + #define DDRPLL_N (OSC - 1) + #define DDRPLL_M2 1 + +@@ -187,7 +188,7 @@ + + #define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL + +-extern void pll_init(int mpupll_M); ++extern void pll_init(int mpupll_M, int ddrpll_M); + extern void enable_ddr_clocks(void); + + #endif /* endif _AM33XX_CLOCKS_H_ */ +diff --git a/arch/arm/mach-omap/include/mach/am33xx-devices.h b/arch/arm/mach-omap/include/mach/am33xx-devices.h +index edf8982..1d13d3d 100644 +--- a/arch/arm/mach-omap/include/mach/am33xx-devices.h ++++ b/arch/arm/mach-omap/include/mach/am33xx-devices.h +@@ -31,6 +31,12 @@ static inline struct device_d *am33xx_add_mmc0(struct omap_hsmmc_platform_data * + AM33XX_MMCHS0_BASE, SZ_4K, IORESOURCE_MEM, pdata); + } + ++static inline struct device_d *am33xx_add_mmc1(struct omap_hsmmc_platform_data *pdata) ++{ ++ return add_generic_device("omap4-hsmmc", 1, NULL, ++ AM33XX_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata); ++} ++ + static inline struct device_d *am33xx_add_cpsw(struct cpsw_platform_data *cpsw_data) + { + return add_generic_device("cpsw", 0, NULL, +-- +1.7.10.4 + diff --git a/patches/barebox-2013.07.0/series b/patches/barebox-2013.07.0/series new file mode 100644 index 0000000..042cb61 --- /dev/null +++ b/patches/barebox-2013.07.0/series @@ -0,0 +1,17 @@ +0001-scripts-genenv-remove-empty-files-from-tempdir.patch +0002-scripts-Makefile-do-not-use-obj-variables-for-usersp.patch +0003-console-fix-console-without-CONFIG_PARAMETER.patch +0004-beaglebone-fix-booting.patch +0005-beaglebone-env-use-config-board-instead-of-config.patch +0006-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch +0007-ARM-AM33xx-Add-gpio-support.patch +0008-ARM-AM33xx-Enable-clock-for-all-GPIO-banks.patch +0009-ARM-AM33xx-Make-mpu-pll-configurable-by-lowlevel-boa.patch +0010-arm-omap-store-boot-source-info-from-ROM-loader.patch +0011-i2c-omap-cleanup-cpu_is-functions.patch +0012-ARM-AM33xx-Add-i2c-support-for-AM33xx.patch +0013-beaglebone-configure-I2C-EEPROM.patch +0014-arm-cpuinfo-display-the-core-name-and-version.patch +0015-am33xx-implement-cpu-revision-decoding.patch +0016-beaglebone-split-out-DDR2-init-for-BB-White.patch +0017-beaglebone-add-support-for-beaglebone-black-with-DDR.patch diff --git a/platformconfig b/platformconfig index a5dcac9..c6d5d76 100644 --- a/platformconfig +++ b/platformconfig @@ -125,7 +125,7 @@ PTXCONF_KERNEL_CONFIG="kernelconfig" PTXCONF_KERNEL_EXTRA_MAKEVARS="CONFIG_DEBUG_SECTION_MISMATCH=y" PTXCONF_DTC=y # PTXCONF_DTC_INSTALL_OFTREE is not set -PTXCONF_DTC_OFTREE_DTS="${KERNEL_DIR}/arch/arm/boot/dts/am335x-bone.dts" +PTXCONF_DTC_OFTREE_DTS="${KERNEL_DIR}/arch/arm/boot/dts/am335x-bone.dts ${KERNEL_DIR}/arch/arm/boot/dts/am335x-boneblack.dts" PTXCONF_DTC_KERNEL=y PTXCONF_DTC_EXTRA_ARGS="-@" @@ -146,8 +146,8 @@ PTXCONF_CONSOLE_SPEED="115200" # PTXCONF_AT91BOOTSTRAP2 is not set PTXCONF_BAREBOX_ARCH_STRING="arm" PTXCONF_BAREBOX=y -PTXCONF_BAREBOX_VERSION="2013.04.0" -PTXCONF_BAREBOX_MD5="eef5e25a3d2855e99aa1bc04862841db" +PTXCONF_BAREBOX_VERSION="2013.07.0" +PTXCONF_BAREBOX_MD5="6e60845aa3ebfe4ccc1d834508d8c8c8" PTXCONF_BAREBOX_CONFIG="barebox.config" PTXCONF_BAREBOX_EXTRA_ENV=y PTXCONF_BAREBOX_EXTRA_ENV_PATH="${PTXDIST_PLATFORMCONFIGDIR}/barebox-defaultenv" |