From 5a36bd3c8444a9d5699fe77189c1f5ab4d7e4d72 Mon Sep 17 00:00:00 2001 From: Jan Luebbe Date: Sun, 2 Sep 2012 16:24:17 +0200 Subject: beagleboneti: add plaform Signed-off-by: Jan Luebbe --- barebox.config | 346 + barebox_mlo.config | 228 + config/images/boot-mlo-vfat.config | 10 + config/images/sd.config | 15 + kernelconfig-3.2.16 | 3563 + .../0000-barebox-v2012.07.0-to-master.patch | 12305 +++ ...aglebone-add-support-for-AM335x-and-board.patch | 3688 + patches/barebox-2012.07.0/series | 2 + patches/linux-3.2.16/0000-arago-beaglebone.patch | 79756 +++++++++++++++++++ patches/linux-3.2.16/series | 1 + .../0000-v2011.09-arago-beaglebone.patch | 16912 ++++ ...only-do-in-kernel-dhcp-when-using-NFS-use.patch | 35 + ...boot-kernel-from-boot-in-ext2-3-filesyste.patch | 27 + .../0003-am335x_evm-set-bootdelay-to-1.patch | 26 + ...-make-MMC-rootfs-RO-on-boot-so-fsck-works.patch | 26 + ...ge-mmc_load_uimage-to-load-at-a-fixed-add.patch | 49 + ...vm-Fix-bone-pmic-shut-down-over-USB-power.patch | 82 + .../0007-am335x_evm-switch-to-ext4.patch | 26 + ...-evm-turn-d-cache-on-globally-turn-it-off.patch | 46 + ...35x-evm-enable-i2c2-pinmux-for-beaglebone.patch | 63 + ...ddr_defs-change-DDR-timings-for-15x15-EVM.patch | 30 + .../0011-ext2load-increase-read-speed.patch | 74 + ...fix-ext2load-and-specify-partition-for-bo.patch | 28 + ...evm-load-uImage-from-boot-instead-of-VFAT.patch | 35 + .../0014-ext4fs-ls-load-support.patch | 2362 + .../0015-am335x-switch-to-ext4-mode.patch | 51 + patches/u-boot-2011.09/series | 16 + platformconfig | 224 + platforms/image-boot-mlo.in | 12 + platforms/image-sd.in | 10 + rules/image-sd.make | 34 + 31 files changed, 120082 insertions(+) create mode 100644 barebox.config create mode 100644 barebox_mlo.config create mode 100644 config/images/boot-mlo-vfat.config create mode 100644 config/images/sd.config create mode 100644 kernelconfig-3.2.16 create mode 100644 patches/barebox-2012.07.0/0000-barebox-v2012.07.0-to-master.patch create mode 100644 patches/barebox-2012.07.0/0001-WIP-beaglebone-add-support-for-AM335x-and-board.patch create mode 100644 patches/barebox-2012.07.0/series create mode 100644 patches/linux-3.2.16/0000-arago-beaglebone.patch create mode 100644 patches/linux-3.2.16/series create mode 100644 patches/u-boot-2011.09/0000-v2011.09-arago-beaglebone.patch create mode 100644 patches/u-boot-2011.09/0001-am335x_evm-only-do-in-kernel-dhcp-when-using-NFS-use.patch create mode 100644 patches/u-boot-2011.09/0002-am335x_evm-boot-kernel-from-boot-in-ext2-3-filesyste.patch create mode 100644 patches/u-boot-2011.09/0003-am335x_evm-set-bootdelay-to-1.patch create mode 100644 patches/u-boot-2011.09/0004-am335x-evm-make-MMC-rootfs-RO-on-boot-so-fsck-works.patch create mode 100644 patches/u-boot-2011.09/0005-am335x-Change-mmc_load_uimage-to-load-at-a-fixed-add.patch create mode 100644 patches/u-boot-2011.09/0006-am335x-evm-Fix-bone-pmic-shut-down-over-USB-power.patch create mode 100644 patches/u-boot-2011.09/0007-am335x_evm-switch-to-ext4.patch create mode 100644 patches/u-boot-2011.09/0008-HACK-am335x-evm-turn-d-cache-on-globally-turn-it-off.patch create mode 100644 patches/u-boot-2011.09/0009-am335x-evm-enable-i2c2-pinmux-for-beaglebone.patch create mode 100644 patches/u-boot-2011.09/0010-ddr_defs-change-DDR-timings-for-15x15-EVM.patch create mode 100644 patches/u-boot-2011.09/0011-ext2load-increase-read-speed.patch create mode 100644 patches/u-boot-2011.09/0012-am335x-evm-fix-ext2load-and-specify-partition-for-bo.patch create mode 100644 patches/u-boot-2011.09/0013-am335x-evm-load-uImage-from-boot-instead-of-VFAT.patch create mode 100644 patches/u-boot-2011.09/0014-ext4fs-ls-load-support.patch create mode 100644 patches/u-boot-2011.09/0015-am335x-switch-to-ext4-mode.patch create mode 100644 patches/u-boot-2011.09/series create mode 100644 platformconfig create mode 100644 platforms/image-boot-mlo.in create mode 100644 platforms/image-sd.in create mode 100644 rules/image-sd.make diff --git a/barebox.config b/barebox.config new file mode 100644 index 0000000..2e5e08f --- /dev/null +++ b/barebox.config @@ -0,0 +1,346 @@ +# +# Automatically generated file; DO NOT EDIT. +# Barebox/arm 2012.07.0 Configuration +# +# CONFIG_BOARD_LINKER_SCRIPT is not set +CONFIG_GENERIC_LINKER_SCRIPT=y +CONFIG_ARM=y +CONFIG_ARM_LINUX=y + +# +# System Type +# +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +CONFIG_ARCH_OMAP=y +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_S3C24xx is not set +# CONFIG_ARCH_S5PCxx is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_TEGRA is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y + +# +# processor features +# +# CONFIG_BOOT_ENDIANNESS_SWITCH is not set +CONFIG_BOARDINFO="Texas Instrument's Beagle Bone" + +# +# OMAP Features +# +CONFIG_OMAP3_LOWLEVEL_INIT=y +CONFIG_ARCH_OMAP3=y +# CONFIG_ARCH_OMAP4 is not set +CONFIG_OMAP_CLOCK_ALL=y +CONFIG_OMAP_CLOCK_SOURCE_S32K=y +# CONFIG_OMAP3_CLOCK_CONFIG is not set +# CONFIG_OMAP_GPMC is not set +# CONFIG_OMAP_BUILD_IFT is not set +# CONFIG_MACH_OMAP343xSDP is not set +# CONFIG_MACH_BEAGLE is not set +CONFIG_MACH_BEAGLEBONE=y +# CONFIG_MACH_OMAP3EVM is not set +# CONFIG_MACH_PCAAL1 is not set +CONFIG_AEABI=y +# CONFIG_THUMB2_BAREBOX is not set + +# +# Arm specific settings +# +CONFIG_CMD_ARM_CPUINFO=y +# CONFIG_CMD_ARM_MMUINFO is not set +# CONFIG_CPU_V7_DCACHE_SKIP is not set +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_ARM_EXCEPTIONS=y +CONFIG_ARM_UNWIND=y +CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG" +CONFIG_HAS_KALLSYMS=y +CONFIG_HAS_MODULES=y +CONFIG_CMD_MEMORY=y +CONFIG_ENV_HANDLING=y +CONFIG_GENERIC_GPIO=y +CONFIG_BLOCK=y +CONFIG_BLOCK_WRITE=y +CONFIG_HAVE_NOSHELL=y +CONFIG_FILETYPE=y +CONFIG_BINFMT=y +CONFIG_GLOBALVAR=y + +# +# General Settings +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BANNER=y +CONFIG_ENVIRONMENT_VARIABLES=y + +# +# memory layout +# +CONFIG_MMU=y +CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y +CONFIG_TEXT_BASE=0x81000000 +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xffffffff +CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0xffffffff +CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y +CONFIG_MEMORY_LAYOUT_DEFAULT=y +# CONFIG_MEMORY_LAYOUT_FIXED is not set +CONFIG_STACK_SIZE=0x8000 +CONFIG_MALLOC_SIZE=0x400000 +# CONFIG_BROKEN is not set +# CONFIG_EXPERIMENTAL is not set +CONFIG_MALLOC_DLMALLOC=y +# CONFIG_MALLOC_TLSF is not set +CONFIG_KALLSYMS=y +CONFIG_ARCH_HAS_LOWLEVEL_INIT=y +CONFIG_PROMPT="barebox> " +CONFIG_BAUDRATE=115200 +CONFIG_LONGHELP=y +CONFIG_CBSIZE=1024 +CONFIG_MAXARGS=16 +CONFIG_SHELL_HUSH=y +# CONFIG_SHELL_SIMPLE is not set +# CONFIG_SHELL_NONE is not set +CONFIG_GLOB=y +CONFIG_GLOB_SORT=y +CONFIG_PROMPT_HUSH_PS2="> " +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_HUSH_GETOPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +# CONFIG_PASSWORD is not set +CONFIG_DYNAMIC_CRC_TABLE=y +CONFIG_ERRNO_MESSAGES=y +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_FULL=y +CONFIG_CONSOLE_ACTIVATE_FIRST=y +CONFIG_PARTITION=y +CONFIG_PARTITION_DISK=y +CONFIG_PARTITION_DISK_DOS=y +CONFIG_DEFAULT_ENVIRONMENT=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +# CONFIG_DEFAULT_ENVIRONMENT_GENERIC is not set +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/beaglebone/env" +# CONFIG_BAREBOXENV_TARGET is not set +# CONFIG_POLLER is not set + +# +# Debugging +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_FLASH_NOISE is not set +# CONFIG_ENABLE_PARTITION_NOISE is not set +# CONFIG_ENABLE_DEVICE_NOISE is not set +# CONFIG_DEBUG_LL is not set +CONFIG_HAS_DEBUG_LL=y +CONFIG_COMMAND_SUPPORT=y +# CONFIG_HAS_POWEROFF is not set + +# +# commands +# + +# +# scripting +# +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +# CONFIG_CMD_MSLEEP is not set +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TRUE=y +CONFIG_CMD_FALSE=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +# CONFIG_CMD_LOGIN is not set +# CONFIG_CMD_PASSWD is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_GLOBAL=y + +# +# file commands +# +CONFIG_CMD_LS=y +CONFIG_CMD_RM=y +CONFIG_CMD_CAT=y +CONFIG_CMD_MKDIR=y +CONFIG_CMD_RMDIR=y +CONFIG_CMD_CP=y +CONFIG_CMD_PWD=y +CONFIG_CMD_CD=y +CONFIG_CMD_MOUNT=y +CONFIG_CMD_UMOUNT=y +CONFIG_CMD_AUTOMOUNT=y +CONFIG_CMD_BASENAME=y +CONFIG_CMD_DIRNAME=y + +# +# console +# +CONFIG_CMD_CLEAR=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ECHO_E=y + +# +# memory +# +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADY is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_IOMEM is not set +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +# CONFIG_CMD_MD5SUM is not set +# CONFIG_CMD_SHA1SUM is not set +# CONFIG_CMD_SHA256SUM is not set +# CONFIG_CMD_SHA224SUM is not set +# CONFIG_CMD_MTEST is not set + +# +# flash +# +# CONFIG_CMD_FLASH is not set + +# +# booting +# +CONFIG_CMD_BOOTM=y +CONFIG_CMD_BOOTM_SHOW_TYPE=y +CONFIG_CMD_BOOTM_VERBOSE=y +CONFIG_CMD_BOOTM_INITRD=y +CONFIG_CMD_BOOTM_OFTREE=y +CONFIG_CMD_BOOTM_OFTREE_UIMAGE=y +# CONFIG_CMD_BOOTM_AIMAGE is not set +CONFIG_CMD_UIMAGE=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_BOOTU=y +CONFIG_FLEXIBLE_BOOTARGS=y +CONFIG_CMD_RESET=y +CONFIG_CMD_GO=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_TEST=y +CONFIG_CMD_VERSION=y +CONFIG_CMD_HELP=y +CONFIG_CMD_MAGICVAR=y +CONFIG_CMD_MAGICVAR_HELP=y +CONFIG_CMD_DEVINFO=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_UNCOMPRESS=y +# CONFIG_NET is not set + +# +# Drivers +# + +# +# serial drivers +# +# CONFIG_DRIVER_SERIAL_ARM_DCC is not set +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y + +# +# SPI drivers +# +# CONFIG_SPI is not set +# CONFIG_I2C is not set + +# +# flash drivers +# +# CONFIG_DRIVER_CFI is not set +# CONFIG_MTD is not set +CONFIG_DISK=y +CONFIG_DISK_WRITE=y + +# +# drive types +# +# CONFIG_DISK_ATA is not set + +# +# interface types +# +# CONFIG_DISK_INTF_PLATFORM_IDE is not set +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set +# CONFIG_VIDEO is not set +CONFIG_MCI=y + +# +# --- Feature list --- +# +CONFIG_MCI_STARTUP=y +CONFIG_MCI_INFO=y +CONFIG_MCI_WRITE=y + +# +# --- MCI host drivers --- +# +CONFIG_MCI_OMAP_HSMMC=y + +# +# MFD +# +# CONFIG_LED is not set + +# +# EEPROM support +# + +# +# Input device support +# +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_WATCHDOG is not set +# CONFIG_PWM is not set + +# +# DMA support +# + +# +# Filesystem support +# +CONFIG_FS_AUTOMOUNT=y +# CONFIG_FS_CRAMFS is not set +CONFIG_FS_RAMFS=y +CONFIG_FS_DEVFS=y +# CONFIG_FS_NFS is not set +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y + +# +# Library routines +# +CONFIG_PARAMETER=y +CONFIG_UNCOMPRESS=y +# CONFIG_ZLIB is not set +# CONFIG_BZLIB is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_PROCESS_ESCAPE_SEQUENCE=y +# CONFIG_LZO_DECOMPRESS is not set +CONFIG_FDT=y +CONFIG_OFTREE=y +CONFIG_QSORT=y +CONFIG_CRC32=y +# CONFIG_DIGEST is not set diff --git a/barebox_mlo.config b/barebox_mlo.config new file mode 100644 index 0000000..b83ffb1 --- /dev/null +++ b/barebox_mlo.config @@ -0,0 +1,228 @@ +# +# Automatically generated file; DO NOT EDIT. +# Barebox/arm 2012.07.0 Configuration +# +# CONFIG_BOARD_LINKER_SCRIPT is not set +CONFIG_GENERIC_LINKER_SCRIPT=y +CONFIG_ARM=y + +# +# System Type +# +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +CONFIG_ARCH_OMAP=y +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_S3C24xx is not set +# CONFIG_ARCH_S5PCxx is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_TEGRA is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_V7=y +CONFIG_CPU_32v7=y + +# +# processor features +# +# CONFIG_BOOT_ENDIANNESS_SWITCH is not set +CONFIG_BOARDINFO="Texas Instrument's Beagle Bone" + +# +# OMAP Features +# +CONFIG_OMAP3_LOWLEVEL_INIT=y +CONFIG_ARCH_OMAP3=y +# CONFIG_ARCH_OMAP4 is not set +CONFIG_OMAP_CLOCK_ALL=y +CONFIG_OMAP_CLOCK_SOURCE_S32K=y +# CONFIG_OMAP3_CLOCK_CONFIG is not set +# CONFIG_OMAP_GPMC is not set +CONFIG_OMAP_BUILD_IFT=y +# CONFIG_MACH_OMAP343xSDP is not set +# CONFIG_MACH_BEAGLE is not set +CONFIG_MACH_BEAGLEBONE=y +# CONFIG_MACH_OMAP3EVM is not set +# CONFIG_MACH_PCAAL1 is not set +CONFIG_ARM_ASM_UNIFIED=y +CONFIG_AEABI=y +CONFIG_THUMB2_BAREBOX=y + +# +# Arm specific settings +# +# CONFIG_CMD_ARM_CPUINFO is not set +# CONFIG_CMD_ARM_MMUINFO is not set +# CONFIG_CPU_V7_DCACHE_SKIP is not set +# CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS is not set +CONFIG_ARM_EXCEPTIONS=y +# CONFIG_ARM_UNWIND is not set +CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG" +CONFIG_HAS_KALLSYMS=y +CONFIG_HAS_MODULES=y +CONFIG_GENERIC_GPIO=y +CONFIG_BLOCK=y +CONFIG_BLOCK_WRITE=y +CONFIG_HAVE_NOSHELL=y + +# +# General Settings +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_BANNER=y +CONFIG_ENVIRONMENT_VARIABLES=y + +# +# memory layout +# +CONFIG_MMU=y +CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y +CONFIG_TEXT_BASE=0x402F0400 +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xffffffff +CONFIG_BAREBOX_MAX_BARE_INIT_SIZE=0xffffffff +CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y +# CONFIG_MEMORY_LAYOUT_DEFAULT is not set +CONFIG_MEMORY_LAYOUT_FIXED=y +CONFIG_STACK_BASE=0x4030B800 +CONFIG_STACK_SIZE=0x1600 +CONFIG_MALLOC_BASE=0x8F000000 +CONFIG_MALLOC_SIZE=0x1000000 +# CONFIG_BROKEN is not set +# CONFIG_EXPERIMENTAL is not set +CONFIG_MALLOC_DLMALLOC=y +# CONFIG_MALLOC_TLSF is not set +# CONFIG_MALLOC_DUMMY is not set +# CONFIG_KALLSYMS is not set +CONFIG_ARCH_HAS_LOWLEVEL_INIT=y +CONFIG_PROMPT="MLO>" +CONFIG_BAUDRATE=115200 +CONFIG_SIMPLE_READLINE=y +CONFIG_LONGHELP=y +CONFIG_CBSIZE=1024 +CONFIG_MAXARGS=16 +# CONFIG_SHELL_HUSH is not set +# CONFIG_SHELL_SIMPLE is not set +CONFIG_SHELL_NONE=y +# CONFIG_CMDLINE_EDITING is not set +# CONFIG_PASSWORD is not set +# CONFIG_ERRNO_MESSAGES is not set +# CONFIG_TIMESTAMP is not set +CONFIG_CONSOLE_FULL=y +CONFIG_CONSOLE_ACTIVATE_FIRST=y +CONFIG_PARTITION=y +CONFIG_PARTITION_DISK=y +CONFIG_PARTITION_DISK_DOS=y +# CONFIG_DEFAULT_ENVIRONMENT is not set +# CONFIG_BAREBOXENV_TARGET is not set +# CONFIG_POLLER is not set + +# +# Debugging +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_ENABLE_FLASH_NOISE is not set +# CONFIG_ENABLE_PARTITION_NOISE is not set +# CONFIG_ENABLE_DEVICE_NOISE is not set +# CONFIG_DEBUG_LL is not set +CONFIG_HAS_DEBUG_LL=y +# CONFIG_HAS_POWEROFF is not set +# CONFIG_NET is not set + +# +# Drivers +# + +# +# serial drivers +# +# CONFIG_DRIVER_SERIAL_ARM_DCC is not set +CONFIG_DRIVER_SERIAL_NS16550=y +CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y + +# +# SPI drivers +# +# CONFIG_SPI is not set +# CONFIG_I2C is not set + +# +# flash drivers +# +# CONFIG_DRIVER_CFI is not set +# CONFIG_MTD is not set +CONFIG_DISK=y +CONFIG_DISK_WRITE=y + +# +# drive types +# +# CONFIG_DISK_ATA is not set + +# +# interface types +# +# CONFIG_DISK_INTF_PLATFORM_IDE is not set +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set +# CONFIG_VIDEO is not set +CONFIG_MCI=y + +# +# --- Feature list --- +# +CONFIG_MCI_STARTUP=y +CONFIG_MCI_WRITE=y + +# +# --- MCI host drivers --- +# +CONFIG_MCI_OMAP_HSMMC=y + +# +# MFD +# +# CONFIG_LED is not set + +# +# EEPROM support +# + +# +# Input device support +# +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_WATCHDOG is not set +# CONFIG_PWM is not set + +# +# DMA support +# + +# +# Filesystem support +# +# CONFIG_FS_CRAMFS is not set +# CONFIG_FS_RAMFS is not set +# CONFIG_FS_DEVFS is not set +# CONFIG_FS_NFS is not set +CONFIG_FS_FAT=y +# CONFIG_FS_FAT_WRITE is not set +CONFIG_FS_FAT_LFN=y + +# +# Library routines +# +# CONFIG_ZLIB is not set +# CONFIG_BZLIB is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +# CONFIG_PROCESS_ESCAPE_SEQUENCE is not set +# CONFIG_LZO_DECOMPRESS is not set +# CONFIG_DIGEST is not set diff --git a/config/images/boot-mlo-vfat.config b/config/images/boot-mlo-vfat.config new file mode 100644 index 0000000..3b5f9b5 --- /dev/null +++ b/config/images/boot-mlo-vfat.config @@ -0,0 +1,10 @@ +image @IMAGE@ { + vfat { + file MLO { image = "MLO"} + file barebox.bin { image = "barebox-image" } + file barebox.env { image = "barebox-default-environment" } + file uImage { image = "linuximage" } + } + name = boot-mlo + size = 10M +} diff --git a/config/images/sd.config b/config/images/sd.config new file mode 100644 index 0000000..1b914c5 --- /dev/null +++ b/config/images/sd.config @@ -0,0 +1,15 @@ +image @IMAGE@ { + hdimage { + align = 1M + } + size = 512M + partition boot { + image = boot-mlo.vfat + partition-type = 0x0C + bootable = true + } + partition root { + image = root.ext2 + partition-type = 0x83 + } +} diff --git a/kernelconfig-3.2.16 b/kernelconfig-3.2.16 new file mode 100644 index 0000000..649ee4c --- /dev/null +++ b/kernelconfig-3.2.16 @@ -0,0 +1,3563 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.2.16 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_HAVE_PWM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_SCHED_CLOCK=y +CONFIG_GENERIC_GPIO=y +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_KTIME_SCALAR=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_HAVE_IRQ_WORK=y +CONFIG_IRQ_WORK=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_KERNEL_LZO=y +CONFIG_DEFAULT_HOSTNAME="beaglebone" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_FHANDLE=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_HAVE_SPARSE_IRQ=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_SPARSE_IRQ=y + +# +# RCU Subsystem +# +CONFIG_TINY_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +# CONFIG_RCU_TRACE is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +# CONFIG_CPUSETS is not set +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +# CONFIG_CGROUP_MEM_RES_CTLR is not set +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +# CONFIG_RELAY is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_PERF_COUNTERS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_COMPAT_BRK=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBDAF=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_BSGLIB is not set +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_THROTTLING=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_CFQ_GROUP_IOSCHED=y +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_INLINE_SPIN_TRYLOCK is not set +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK is not set +# CONFIG_INLINE_SPIN_LOCK_BH is not set +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +# CONFIG_INLINE_SPIN_UNLOCK is not set +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_READ_TRYLOCK is not set +# CONFIG_INLINE_READ_LOCK is not set +# CONFIG_INLINE_READ_LOCK_BH is not set +# CONFIG_INLINE_READ_LOCK_IRQ is not set +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +# CONFIG_INLINE_READ_UNLOCK is not set +# CONFIG_INLINE_READ_UNLOCK_BH is not set +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +# CONFIG_INLINE_WRITE_TRYLOCK is not set +# CONFIG_INLINE_WRITE_LOCK is not set +# CONFIG_INLINE_WRITE_LOCK_BH is not set +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +# CONFIG_INLINE_WRITE_UNLOCK is not set +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +# CONFIG_MUTEX_SPIN_ON_OWNER is not set +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_BCMRING is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_CNS3XXX is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_PRIMA2 is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_MXS is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_PICOXCELL is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_TCC_926 is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_DAVINCI is not set +CONFIG_ARCH_OMAP=y +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_VT8500 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set + +# +# TI OMAP Common Features +# +# CONFIG_ARCH_OMAP1 is not set +CONFIG_ARCH_OMAP2PLUS=y + +# +# OMAP Feature Selections +# +# CONFIG_OMAP_SMARTREFLEX is not set +# CONFIG_OMAP_RESET_CLOCKS is not set +CONFIG_OMAP_MUX=y +CONFIG_OMAP_MUX_DEBUG=y +CONFIG_OMAP_MUX_WARNINGS=y +CONFIG_OMAP_MCBSP=y +CONFIG_OMAP_MBOX_FWK=y +CONFIG_OMAP_MBOX_KFIFO_SIZE=256 +# CONFIG_OMAP_32K_TIMER is not set +# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set +CONFIG_OMAP_DM_TIMER=y +CONFIG_OMAP_PM_NOOP=y +CONFIG_MACH_OMAP_GENERIC=y + +# +# TI OMAP2/3/4 Specific Features +# +CONFIG_ARCH_OMAP2PLUS_TYPICAL=y +# CONFIG_ARCH_OMAP2 is not set +CONFIG_ARCH_OMAP3=y +# CONFIG_ARCH_OMAP4 is not set +# CONFIG_SOC_OMAP3430 is not set +CONFIG_SOC_OMAPTI81XX=y +CONFIG_SOC_OMAPAM33XX=y +CONFIG_OMAP_PACKAGE_CBB=y + +# +# OMAP Board Type +# +CONFIG_MACH_OMAP3_BEAGLE=y +# CONFIG_MACH_DEVKIT8000 is not set +# CONFIG_MACH_OMAP_LDP is not set +# CONFIG_MACH_OMAP3530_LV_SOM is not set +# CONFIG_MACH_OMAP3_TORPEDO is not set +# CONFIG_MACH_ENCORE is not set +# CONFIG_MACH_OVERO is not set +# CONFIG_MACH_OMAP3EVM is not set +# CONFIG_MACH_OMAP3517EVM is not set +# CONFIG_MACH_CRANEBOARD is not set +# CONFIG_MACH_OMAP3_PANDORA is not set +# CONFIG_MACH_OMAP3_TOUCHBOOK is not set +# CONFIG_MACH_OMAP_3430SDP is not set +# CONFIG_MACH_NOKIA_RM680 is not set +# CONFIG_MACH_NOKIA_RX51 is not set +# CONFIG_MACH_OMAP_ZOOM2 is not set +# CONFIG_MACH_OMAP_ZOOM3 is not set +# CONFIG_MACH_CM_T35 is not set +# CONFIG_MACH_CM_T3517 is not set +# CONFIG_MACH_IGEP0020 is not set +# CONFIG_MACH_IGEP0030 is not set +# CONFIG_MACH_SBC3530 is not set +# CONFIG_MACH_OMAP_3630SDP is not set +CONFIG_MACH_TI8168EVM=y +CONFIG_MACH_TI8148EVM=y +CONFIG_MACH_AM335XEVM=y +CONFIG_MACH_AM335XIAEVM=y +# CONFIG_OMAP3_EMU is not set +# CONFIG_OMAP3_SDRC_AC_TIMING is not set +CONFIG_OMAP3_EDMA=y + +# +# System MMU +# + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +# CONFIG_SWP_EMULATE is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_ARM_ERRATA_430973=y +# CONFIG_ARM_ERRATA_458693 is not set +# CONFIG_ARM_ERRATA_460075 is not set +# CONFIG_ARM_ERRATA_720789 is not set +# CONFIG_ARM_ERRATA_743622 is not set +# CONFIG_ARM_ERRATA_751472 is not set +# CONFIG_ARM_ERRATA_754322 is not set + +# +# Bus support +# +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ=100 +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +# CONFIG_HIGHMEM is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_COMPACTION is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_NEED_PER_CPU_KM=y +# CONFIG_CLEANCACHE is not set +CONFIG_FORCE_MAX_ZONEORDER=11 +# CONFIG_LEDS is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +# CONFIG_SECCOMP is not set +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_DEPRECATED_PARAM_STRUCT is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE=" debug " +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_STAT_DETAILS=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + +# +# ARM CPU frequency scaling drivers +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +CONFIG_BINFMT_MISC=y + +# +# Power management options +# +# CONFIG_SUSPEND is not set +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_OPP=y +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +CONFIG_CPU_PM=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=y +CONFIG_XFRM_SUB_POLICY=y +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_IPCOMP=m +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +CONFIG_IP_MROUTE=y +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=m +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET6_TUNNEL=m +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +# CONFIG_NETFILTER_XT_MARK is not set + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set +# CONFIG_NETFILTER_XT_TARGET_LED is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TEE is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set + +# +# Xtables matches +# +# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CPU is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=m +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +# CONFIG_IP_NF_FILTER is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_RAW is not set +CONFIG_IP_NF_ARPTABLES=m +# CONFIG_IP_NF_ARPFILTER is not set +# CONFIG_IP_NF_ARP_MANGLE is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV6 is not set +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=m +CONFIG_GARP=m +CONFIG_BRIDGE=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_GVRP=y +# CONFIG_DECNET is not set +CONFIG_LLC=m +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set + +# +# Classification +# +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=m +CONFIG_CAN_GW=m + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=m +CONFIG_CAN_SLCAN=m +CONFIG_CAN_DEV=y +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_TI_HECC=m +CONFIG_CAN_MCP251X=y +# CONFIG_CAN_SJA1000 is not set +# CONFIG_CAN_C_CAN is not set +CONFIG_CAN_D_CAN=y +CONFIG_CAN_D_CAN_PLATFORM=y + +# +# CAN USB interfaces +# +CONFIG_CAN_EMS_USB=m +CONFIG_CAN_ESD_USB2=m +# CONFIG_CAN_SOFTING is not set +CONFIG_CAN_DEBUG_DEVICES=y +CONFIG_IRDA=m + +# +# IrDA protocols +# +CONFIG_IRLAN=m +CONFIG_IRNET=m +CONFIG_IRCOMM=m +# CONFIG_IRDA_ULTRA is not set + +# +# IrDA options +# +# CONFIG_IRDA_CACHE_LAST_LSAP is not set +# CONFIG_IRDA_FAST_RR is not set +# CONFIG_IRDA_DEBUG is not set + +# +# Infrared-port device drivers +# + +# +# SIR device drivers +# +CONFIG_IRTTY_SIR=m + +# +# Dongle support +# +# CONFIG_DONGLE is not set +CONFIG_KINGSUN_DONGLE=m +CONFIG_KSDAZZLE_DONGLE=m +CONFIG_KS959_DONGLE=m + +# +# FIR device drivers +# +CONFIG_USB_IRDA=m +CONFIG_SIGMATEL_FIR=m +CONFIG_MCS_FIR=m +CONFIG_BT=m +CONFIG_BT_L2CAP=y +CONFIG_BT_SCO=y +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBFUSB=m +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_BT_ATH3K is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_EXT=y +CONFIG_WEXT_CORE=y +CONFIG_WEXT_PROC=y +CONFIG_WEXT_SPY=y +CONFIG_WEXT_PRIV=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +CONFIG_CFG80211_WEXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_LIB80211=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +CONFIG_MAC80211_RC_PID=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set +CONFIG_MAC80211_RC_DEFAULT="pid" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_WIMAX=m +CONFIG_WIMAX_DEBUG_LEVEL=8 +CONFIG_RFKILL=m +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_REGULATOR=m +CONFIG_RFKILL_GPIO=m +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y +CONFIG_NFC=m +CONFIG_NFC_NCI=m + +# +# Near Field Communication (NFC) devices +# +CONFIG_PN544_NFC=m +CONFIG_NFC_PN533=m + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y + +# +# CBUS support +# +# CONFIG_CBUS is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +# CONFIG_MTD is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_DEVICE=y +CONFIG_OF_GPIO=y +CONFIG_OF_I2C=y +CONFIG_OF_NET=y +CONFIG_OF_SPI=y +CONFIG_OF_MDIO=y +CONFIG_PARPORT=m +# CONFIG_PARPORT_PC is not set +# CONFIG_PARPORT_GSC is not set +# CONFIG_PARPORT_AX88796 is not set +CONFIG_PARPORT_1284=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_DRBD is not set +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=2 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +CONFIG_CDROM_PKTCDVD_WCACHE=y +CONFIG_ATA_OVER_ETH=m +# CONFIG_MG_DISK is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_SENSORS_LIS3LV02D is not set +CONFIG_MISC_DEVICES=y +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +CONFIG_BMP085=m +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +# CONFIG_EEPROM_AT25 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_IWMC3200TOP is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_SCH=y +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_ISCSI_BOOT_SYSFS is not set +# CONFIG_LIBFC is not set +# CONFIG_LIBFCOE is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=m +CONFIG_MD_LINEAR=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID456=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_FAULTY=m +CONFIG_BLK_DEV_DM=m +# CONFIG_DM_DEBUG is not set +CONFIG_DM_CRYPT=m +CONFIG_DM_SNAPSHOT=m +# CONFIG_DM_THIN_PROVISIONING is not set +CONFIG_DM_MIRROR=m +CONFIG_DM_RAID=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_ZERO=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +# CONFIG_DM_DELAY is not set +CONFIG_DM_UEVENT=y +CONFIG_DM_FLAKEY=m +# CONFIG_TARGET_CORE is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +CONFIG_BONDING=m +CONFIG_DUMMY=m +CONFIG_EQUALIZER=m +CONFIG_MII=y +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +CONFIG_NETCONSOLE=m +CONFIG_NETPOLL=y +# CONFIG_NETPOLL_TRAP is not set +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_TUN=m +# CONFIG_VETH is not set +# CONFIG_VIRTIO_NET is not set + +# +# CAIF transport drivers +# +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DE600 is not set +# CONFIG_DE620 is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_8390=y +# CONFIG_AX88796 is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SMSC=y +CONFIG_SMC91X=y +# CONFIG_SMC911X is not set +CONFIG_SMSC911X=y +# CONFIG_SMSC911X_ARCH_HOOKS is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_DAVINCI_EMAC is not set +CONFIG_TI_DAVINCI_MDIO=y +CONFIG_TI_DAVINCI_CPDMA=y +CONFIG_TI_CPSW=y +# CONFIG_TLK110_WORKAROUND is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +CONFIG_SMSC_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_PLIP is not set +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOE=m +CONFIG_PPTP=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_SLIP=m +CONFIG_SLHC=m +# CONFIG_SLIP_COMPRESSED is not set +CONFIG_SLIP_SMART=y +# CONFIG_SLIP_MODE_SLIP6 is not set + +# +# USB Network Adapters +# +CONFIG_USB_CATC=y +CONFIG_USB_KAWETH=y +CONFIG_USB_PEGASUS=y +CONFIG_USB_RTL8150=y +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=y +CONFIG_USB_NET_DM9601=y +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_CDC_SUBSET=y +CONFIG_USB_ALI_M5632=y +CONFIG_USB_AN2720=y +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +CONFIG_USB_EPSON2888=y +CONFIG_USB_KC2190=y +CONFIG_USB_NET_ZAURUS=y +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_HSO=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_IPHETH=m +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_VL600=m +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +CONFIG_AT76C50X_USB=m +CONFIG_USB_ZD1201=m +CONFIG_USB_NET_RNDIS_WLAN=m +CONFIG_RTL8187=m +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_ATH_COMMON is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +CONFIG_BRCMUTIL=m +CONFIG_BRCMFMAC=m +# CONFIG_BRCMDBG is not set +# CONFIG_HOSTAP is not set +# CONFIG_IWM is not set +CONFIG_LIBERTAS=m +CONFIG_LIBERTAS_USB=m +CONFIG_LIBERTAS_SDIO=m +# CONFIG_LIBERTAS_SPI is not set +CONFIG_LIBERTAS_DEBUG=y +# CONFIG_LIBERTAS_MESH is not set +CONFIG_P54_COMMON=m +CONFIG_P54_USB=m +# CONFIG_P54_SPI is not set +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RT2800_LIB=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RTL8192CU=m +CONFIG_RTLWIFI=m +CONFIG_RTL8192C_COMMON=m +# CONFIG_WL1251 is not set +CONFIG_WL12XX_MENU=m +CONFIG_WL12XX=m +CONFIG_WL12XX_SPI=m +CONFIG_WL12XX_SDIO=m +# CONFIG_WL12XX_SDIO_TEST is not set +CONFIG_WL12XX_PLATFORM_DATA=y +CONFIG_ZD1211RW=m +# CONFIG_ZD1211RW_DEBUG is not set +# CONFIG_MWIFIEX is not set + +# +# WiMAX Wireless Broadband devices +# +CONFIG_WIMAX_I2400M=m +CONFIG_WIMAX_I2400M_USB=m +# CONFIG_WIMAX_I2400M_SDIO is not set +CONFIG_WIMAX_I2400M_DEBUG_LEVEL=8 +# CONFIG_WAN is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=m +CONFIG_INPUT_POLLDEV=m +# CONFIG_INPUT_SPARSEKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +CONFIG_KEYBOARD_TWL4030=y +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=y +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +CONFIG_TOUCHSCREEN_TI_TSCADC=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +CONFIG_TOUCHSCREEN_TSC_SERIO=m +CONFIG_TOUCHSCREEN_TSC2005=m +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_AD714X_I2C=m +CONFIG_INPUT_AD714X_SPI=m +CONFIG_INPUT_BMA150=m +CONFIG_INPUT_MMA8450=m +CONFIG_INPUT_MPU3050=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KXTJ9=m +# CONFIG_INPUT_KXTJ9_POLLED_MODE is not set +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_YEALINK=m +CONFIG_INPUT_CM109=m +CONFIG_INPUT_TWL4030_PWRBUTTON=y +CONFIG_INPUT_TWL4030_VIBRA=m +CONFIG_INPUT_TWL6040_VIBRA=m +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_PCF8574=m +# CONFIG_INPUT_PWM_BEEPER is not set +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_ADXL34X=m +CONFIG_INPUT_ADXL34X_I2C=m +CONFIG_INPUT_ADXL34X_SPI=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CMA3000_I2C=m + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PARKBD is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +CONFIG_DEVKMEM=y + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +# CONFIG_SERIAL_8250_DW is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX3107 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_OF_PLATFORM is not set +CONFIG_SERIAL_OMAP=y +CONFIG_SERIAL_OMAP_CONSOLE=y +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_PRINTER=m +# CONFIG_LP_CONSOLE is not set +# CONFIG_PPDEV is not set +# CONFIG_HVC_DCC is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_VIRTIO is not set +# CONFIG_R3964 is not set +CONFIG_RAW_DRIVER=m +CONFIG_MAX_RAW_DEVS=256 +# CONFIG_TCG_TPM is not set +# CONFIG_RAMOOPS is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_ALGOBIT=m + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +CONFIG_I2C_OMAP=y +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=m +# CONFIG_SPI_BUTTERFLY is not set +CONFIG_SPI_GPIO=m +# CONFIG_SPI_LM70_LLP is not set +# CONFIG_SPI_OC_TINY is not set +CONFIG_SPI_OMAP24XX=y +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set + +# +# PPS generators support +# + +# +# PTP clock support +# + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_DEBUG_GPIO=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_IT8761E is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +CONFIG_GPIO_TWL4030=y +# CONFIG_GPIO_ADP5588 is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# +CONFIG_GENERIC_PWM=y +CONFIG_DAVINCI_EHRPWM=y +CONFIG_ECAP_PWM=y +CONFIG_W1=y +CONFIG_W1_CON=y + +# +# 1-wire Bus Masters +# +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=y +# CONFIG_HDQ_MASTER_OMAP is not set + +# +# 1-wire Slaves +# +CONFIG_W1_SLAVE_THERM=y +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_DS2408=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2760=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_BQ27000=m +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_BQ20Z75 is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_TWL4030 is not set +# CONFIG_CHARGER_GPIO is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=m +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4261=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_MAX1111=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6642=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +CONFIG_PMBUS=m +CONFIG_SENSORS_PMBUS=m +# CONFIG_SENSORS_ADM1275 is not set +# CONFIG_SENSORS_LM25066 is not set +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_MAX16064 is not set +# CONFIG_SENSORS_MAX34440 is not set +# CONFIG_SENSORS_MAX8688 is not set +# CONFIG_SENSORS_UCD9000 is not set +# CONFIG_SENSORS_UCD9200 is not set +CONFIG_SENSORS_ZL6100=m +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SMM665=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_EMC1403=m +CONFIG_SENSORS_EMC2103=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SCH56XX_COMMON=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_ADS1015=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +CONFIG_SENSORS_W83795=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83627EHF=m +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +CONFIG_OMAP_WATCHDOG=y +CONFIG_TWL4030_WATCHDOG=y +# CONFIG_MAX63XX_WATCHDOG is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +CONFIG_MFD_TPS65217=y +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +CONFIG_TWL4030_CORE=y +# CONFIG_TWL4030_MADC is not set +CONFIG_TWL4030_POWER=y +CONFIG_MFD_TWL4030_AUDIO=y +# CONFIG_TWL6030_PWM is not set +CONFIG_TWL6040_CORE=y +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13XXX is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_AAT2870_CORE is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +CONFIG_REGULATOR_DUMMY=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y +CONFIG_REGULATOR_USERSPACE_CONSUMER=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_BQ24022 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +CONFIG_REGULATOR_TWL4030=y +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +CONFIG_REGULATOR_TPS65023=y +CONFIG_REGULATOR_TPS6507X=y +CONFIG_REGULATOR_TPS65217=y +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CONTROLLER=y +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2_COMMON=y +# CONFIG_VIDEO_V4L2_SUBDEV_API is not set +CONFIG_DVB_CORE=m +CONFIG_DVB_NET=y +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +CONFIG_RC_CORE=y +CONFIG_LIRC=y +CONFIG_RC_MAP=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_RC5_SZ_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_LIRC_CODEC=y +CONFIG_RC_ATI_REMOTE=m +# CONFIG_IR_IMON is not set +# CONFIG_IR_MCEUSB is not set +# CONFIG_IR_REDRAT3 is not set +# CONFIG_IR_STREAMZAP is not set +# CONFIG_RC_LOOPBACK is not set +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_TUNER=m +CONFIG_MEDIA_TUNER_CUSTOMISE=y + +# +# Customize TV tuners +# +CONFIG_MEDIA_TUNER_SIMPLE=m +CONFIG_MEDIA_TUNER_TDA8290=m +CONFIG_MEDIA_TUNER_TDA827X=m +CONFIG_MEDIA_TUNER_TDA18271=m +CONFIG_MEDIA_TUNER_TDA9887=m +CONFIG_MEDIA_TUNER_TEA5761=m +CONFIG_MEDIA_TUNER_TEA5767=m +CONFIG_MEDIA_TUNER_MT20XX=m +CONFIG_MEDIA_TUNER_MT2060=m +CONFIG_MEDIA_TUNER_MT2266=m +CONFIG_MEDIA_TUNER_MT2131=m +CONFIG_MEDIA_TUNER_QT1010=m +CONFIG_MEDIA_TUNER_XC2028=m +CONFIG_MEDIA_TUNER_XC5000=m +CONFIG_MEDIA_TUNER_XC4000=m +CONFIG_MEDIA_TUNER_MXL5005S=m +CONFIG_MEDIA_TUNER_MXL5007T=m +CONFIG_MEDIA_TUNER_MC44S803=m +CONFIG_MEDIA_TUNER_MAX2165=m +CONFIG_MEDIA_TUNER_TDA18218=m +CONFIG_MEDIA_TUNER_TDA18212=m +CONFIG_VIDEO_V4L2=y +CONFIG_VIDEOBUF_GEN=m +CONFIG_VIDEOBUF_VMALLOC=m +CONFIG_VIDEOBUF_DVB=m +CONFIG_VIDEO_TVEEPROM=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEOBUF2_CORE=m +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set +CONFIG_VIDEO_IR_I2C=y + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +CONFIG_VIDEO_MSP3400=m +# CONFIG_VIDEO_CS5345 is not set +CONFIG_VIDEO_CS53L32A=m +# CONFIG_VIDEO_TLV320AIC23B is not set +CONFIG_VIDEO_WM8775=m +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_SAA7110 is not set +CONFIG_VIDEO_SAA711X=m +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +CONFIG_VIDEO_CX25840=m + +# +# MPEG video encoders +# +CONFIG_VIDEO_CX2341X=m + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SR030PC30 is not set + +# +# Flash devices +# +# CONFIG_VIDEO_ADP1653 is not set + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set +CONFIG_VIDEO_VIVI=m +# CONFIG_VIDEO_VPFE_CAPTURE is not set +# CONFIG_VIDEO_OMAP2_VOUT is not set +# CONFIG_VIDEO_BWQCAM is not set +# CONFIG_VIDEO_CQCAM is not set +# CONFIG_VIDEO_W9966 is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_AU0828 is not set +# CONFIG_SOC_CAMERA is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=y +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +CONFIG_USB_M5602=m +CONFIG_USB_STV06XX=m +CONFIG_USB_GL860=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_PVRUSB2_DVB=y +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX_RC=y +CONFIG_VIDEO_TLG2300=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +# CONFIG_VIDEO_TM6000 is not set +CONFIG_VIDEO_USBVISION=m +CONFIG_USB_ET61X251=m +CONFIG_USB_SN9C102=m +CONFIG_USB_PWC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_ZR364XX=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +CONFIG_RADIO_ADAPTERS=y +# CONFIG_I2C_SI4713 is not set +# CONFIG_RADIO_SI4713 is not set +# CONFIG_USB_DSBR is not set +# CONFIG_RADIO_SI470X is not set +# CONFIG_USB_MR800 is not set +# CONFIG_RADIO_TEA5764 is not set +# CONFIG_RADIO_SAA7706H is not set +# CONFIG_RADIO_TEF6862 is not set +# CONFIG_RADIO_WL1273 is not set + +# +# Texas Instruments WL128x FM driver (ST based) +# +# CONFIG_RADIO_WL128X is not set +CONFIG_DVB_MAX_ADAPTERS=8 +# CONFIG_DVB_DYNAMIC_MINORS is not set +CONFIG_DVB_CAPTURE_DRIVERS=y +# CONFIG_TTPCI_EEPROM is not set + +# +# Supported USB Adapters +# +# CONFIG_DVB_USB is not set +# CONFIG_SMS_SIANO_MDTV is not set + +# +# Supported FlexCopII (B2C2) Adapters +# +# CONFIG_DVB_B2C2_FLEXCOP is not set + +# +# Supported DVB Frontends +# +CONFIG_DVB_FE_CUSTOMISE=y + +# +# Customise DVB Frontends +# + +# +# Multistandard (satellite) frontends +# +CONFIG_DVB_STB0899=m +CONFIG_DVB_STB6100=m +CONFIG_DVB_STV090x=m +CONFIG_DVB_STV6110x=m + +# +# Multistandard (cable + terrestrial) frontends +# +CONFIG_DVB_DRXK=m +CONFIG_DVB_TDA18271C2DD=m + +# +# DVB-S (satellite) frontends +# +CONFIG_DVB_CX24110=m +CONFIG_DVB_CX24123=m +CONFIG_DVB_MT312=m +CONFIG_DVB_ZL10036=m +CONFIG_DVB_ZL10039=m +CONFIG_DVB_S5H1420=m +CONFIG_DVB_STV0288=m +CONFIG_DVB_STB6000=m +CONFIG_DVB_STV0299=m +CONFIG_DVB_STV6110=m +CONFIG_DVB_STV0900=m +CONFIG_DVB_TDA8083=m +CONFIG_DVB_TDA10086=m +CONFIG_DVB_TDA8261=m +CONFIG_DVB_VES1X93=m +CONFIG_DVB_TUNER_ITD1000=m +CONFIG_DVB_TUNER_CX24113=m +CONFIG_DVB_TDA826X=m +CONFIG_DVB_TUA6100=m +CONFIG_DVB_CX24116=m +CONFIG_DVB_SI21XX=m +CONFIG_DVB_DS3000=m +CONFIG_DVB_MB86A16=m +CONFIG_DVB_TDA10071=m + +# +# DVB-T (terrestrial) frontends +# +CONFIG_DVB_SP8870=m +CONFIG_DVB_SP887X=m +CONFIG_DVB_CX22700=m +CONFIG_DVB_CX22702=m +CONFIG_DVB_S5H1432=m +CONFIG_DVB_DRXD=m +CONFIG_DVB_L64781=m +CONFIG_DVB_TDA1004X=m +CONFIG_DVB_NXT6000=m +CONFIG_DVB_MT352=m +CONFIG_DVB_ZL10353=m +CONFIG_DVB_DIB3000MB=m +CONFIG_DVB_DIB3000MC=m +CONFIG_DVB_DIB7000M=m +CONFIG_DVB_DIB7000P=m +CONFIG_DVB_DIB9000=m +CONFIG_DVB_TDA10048=m +CONFIG_DVB_AF9013=m +CONFIG_DVB_EC100=m +CONFIG_DVB_STV0367=m +CONFIG_DVB_CXD2820R=m + +# +# DVB-C (cable) frontends +# +CONFIG_DVB_VES1820=m +CONFIG_DVB_TDA10021=m +CONFIG_DVB_TDA10023=m +CONFIG_DVB_STV0297=m + +# +# ATSC (North American/Korean Terrestrial/Cable DTV) frontends +# +CONFIG_DVB_NXT200X=m +CONFIG_DVB_OR51211=m +CONFIG_DVB_OR51132=m +CONFIG_DVB_BCM3510=m +CONFIG_DVB_LGDT330X=m +CONFIG_DVB_LGDT3305=m +CONFIG_DVB_S5H1409=m +CONFIG_DVB_AU8522=m +CONFIG_DVB_S5H1411=m + +# +# ISDB-T (terrestrial) frontends +# +CONFIG_DVB_S921=m +CONFIG_DVB_DIB8000=m +CONFIG_DVB_MB86A20S=m + +# +# Digital terrestrial only tuners/PLL +# +CONFIG_DVB_PLL=m +CONFIG_DVB_TUNER_DIB0070=m +CONFIG_DVB_TUNER_DIB0090=m + +# +# SEC control devices for DVB-S +# +CONFIG_DVB_LNBP21=m +CONFIG_DVB_LNBP22=m +CONFIG_DVB_ISL6405=m +CONFIG_DVB_ISL6421=m +CONFIG_DVB_ISL6423=m +CONFIG_DVB_A8293=m +CONFIG_DVB_LGS8GL5=m +CONFIG_DVB_LGS8GXX=m +CONFIG_DVB_ATBM8830=m +CONFIG_DVB_TDA665x=m +CONFIG_DVB_IX2505V=m +CONFIG_DVB_IT913X_FE=m + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_DRM=m +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_FOREIGN_ENDIAN=y +CONFIG_FB_BOTH_ENDIAN=y +# CONFIG_FB_BIG_ENDIAN is not set +# CONFIG_FB_LITTLE_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +# CONFIG_FB_WMT_GE_ROPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_TMIO is not set +CONFIG_FB_SMSCUFX=m +CONFIG_FB_UDL=m +CONFIG_FB_DA8XX=y +CONFIG_FB_DA8XX_CONSISTENT_DMA_SIZE=5 +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_FB_ST7735=y +# CONFIG_FB_OMAP_BOOTLOADER_INIT is not set +CONFIG_OMAP2_VRAM=y +CONFIG_OMAP2_VRFB=y +CONFIG_OMAP2_DSS=m +CONFIG_OMAP2_VRAM_SIZE=0 +CONFIG_OMAP2_DSS_DEBUG_SUPPORT=y +# CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS is not set +CONFIG_OMAP2_DSS_DPI=y +CONFIG_OMAP2_DSS_RFBI=y +CONFIG_OMAP2_DSS_VENC=y +CONFIG_OMAP2_DSS_SDI=y +CONFIG_OMAP2_DSS_DSI=y +# CONFIG_OMAP2_DSS_FAKE_VSYNC is not set +CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0 +CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y +CONFIG_FB_OMAP2=m +CONFIG_FB_OMAP2_DEBUG_SUPPORT=y +CONFIG_FB_OMAP2_NUM_FBS=3 + +# +# OMAP2/3 Display Device Drivers +# +CONFIG_PANEL_GENERIC_DPI=m +CONFIG_PANEL_DVI=m +# CONFIG_PANEL_LGPHILIPS_LB035Q02 is not set +CONFIG_PANEL_SHARP_LS037V7DW01=m +CONFIG_PANEL_NEC_NL8048HL11_01B=m +CONFIG_PANEL_PICODLP=m +CONFIG_PANEL_TAAL=m +CONFIG_PANEL_TPO_TD043MTEA1=m +CONFIG_PANEL_ACX565AKM=m +CONFIG_PANEL_N8X0=m +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=y +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_TLC59108 is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=y +CONFIG_SND_RAWMIDI=y +CONFIG_SND_JACK=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_SEQUENCER_OSS is not set +CONFIG_SND_HRTIMER=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_RAWMIDI_SEQ=m +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_ALOOP is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_MTS64 is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_PORTMAN2X4 is not set +CONFIG_SND_ARM=y +CONFIG_SND_SPI=y +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=y +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_SOC=y +# CONFIG_SND_SOC_CACHE_LZO is not set +CONFIG_SND_AM33XX_SOC=y +CONFIG_SND_DAVINCI_SOC_MCASP=m +CONFIG_SND_AM335X_SOC_EVM=m +# CONFIG_SND_OMAP_SOC is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_TLV320AIC3X=m +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_QUANTA is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_EHCI_HCD is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_U132_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set +CONFIG_USB_MUSB_HDRC=y + +# +# Platform Glue Layer +# +# CONFIG_USB_MUSB_TUSB6010_GLUE is not set +# CONFIG_USB_MUSB_OMAP2PLUS_GLUE is not set +# CONFIG_USB_MUSB_AM35X_GLUE is not set +CONFIG_USB_MUSB_TI81XX_GLUE=y +# CONFIG_USB_MUSB_DAVINCI is not set +# CONFIG_USB_MUSB_DA8XX is not set +# CONFIG_USB_MUSB_TUSB6010 is not set +# CONFIG_USB_MUSB_OMAP2PLUS is not set +# CONFIG_USB_MUSB_AM35X is not set +CONFIG_USB_MUSB_TI81XX=y +# CONFIG_USB_MUSB_BLACKFIN is not set +# CONFIG_USB_MUSB_UX500 is not set +CONFIG_MUSB_PIO_ONLY=y +# CONFIG_USB_INVENTRA_DMA is not set +# CONFIG_USB_TI_CPPI_DMA is not set +# CONFIG_USB_TI_CPPI41_DMA is not set +# CONFIG_USB_TUSB_OMAP_DMA is not set +# CONFIG_USB_UX500_DMA is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +CONFIG_USB_UAS=y +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_USS720 is not set +CONFIG_USB_SERIAL=m +CONFIG_USB_EZUSB=y +# CONFIG_USB_SERIAL_GENERIC is not set +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +# CONFIG_USB_SERIAL_WHITEHEAT is not set +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_FUNSOFT=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KEYSPAN=m +# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set +# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +CONFIG_USB_SERIAL_MOS7720=m +# CONFIG_USB_SERIAL_MOS7715_PARPORT is not set +CONFIG_USB_SERIAL_MOS7840=m +CONFIG_USB_SERIAL_MOTOROLA=m +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_HP4X=m +CONFIG_USB_SERIAL_SAFE=m +# CONFIG_USB_SERIAL_SAFE_PADDED is not set +CONFIG_USB_SERIAL_SIEMENS_MPI=m +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_WWAN=m +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m +CONFIG_USB_SERIAL_ZIO=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_DEBUG=m + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +CONFIG_USB_LEGOTOWER=m +CONFIG_USB_LCD=m +CONFIG_USB_LED=m +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_SISUSBVGA=m +CONFIG_USB_SISUSBVGA_CON=y +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +CONFIG_USB_TEST=m +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_OMAP is not set +# CONFIG_USB_R8A66597 is not set +CONFIG_USB_GADGET_MUSB_HDRC=y +# CONFIG_USB_M66592 is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_ZERO=m +CONFIG_USB_AUDIO=m +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_FUNCTIONFS=m +# CONFIG_USB_FUNCTIONFS_ETH is not set +CONFIG_USB_FUNCTIONFS_RNDIS=y +# CONFIG_USB_FUNCTIONFS_GENERIC is not set +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_USB_MIDI_GADGET=m +CONFIG_USB_G_PRINTER=m +CONFIG_USB_CDC_COMPOSITE=m +# CONFIG_USB_G_ACM_MS is not set +CONFIG_USB_G_MULTI=m +CONFIG_USB_G_MULTI_RNDIS=y +# CONFIG_USB_G_MULTI_CDC is not set +CONFIG_USB_G_HID=m +CONFIG_USB_G_DBGP=m +CONFIG_USB_G_DBGP_PRINTK=y +# CONFIG_USB_G_DBGP_SERIAL is not set +CONFIG_USB_G_WEBCAM=m + +# +# OTG and related infrastructure +# +CONFIG_USB_OTG_UTILS=y +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ULPI is not set +# CONFIG_TWL4030_USB is not set +# CONFIG_TWL6030_USB is not set +CONFIG_NOP_USB_XCEIV=y +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_OMAP is not set +CONFIG_MMC_OMAP_HS=y +# CONFIG_MMC_SPI is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_PWM is not set +CONFIG_LEDS_REGULATOR=y +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_RENESAS_TPU is not set +CONFIG_LEDS_TRIGGERS=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +CONFIG_RTC_DRV_TWL4030=y +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_OMAP=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=m +CONFIG_UIO_PDRV=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_PRUSS=m +CONFIG_VIRTIO=m +CONFIG_VIRTIO_RING=m + +# +# Virtio drivers +# +# CONFIG_VIRTIO_BALLOON is not set +CONFIG_VIRTIO_MMIO=m +CONFIG_STAGING=y +# CONFIG_USBIP_CORE is not set +CONFIG_W35UND=m +CONFIG_PRISM2_USB=m +# CONFIG_ECHO is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_PANEL is not set +CONFIG_R8712U=m +CONFIG_RTS5139=m +# CONFIG_RTS5139_DEBUG is not set +# CONFIG_TRANZPORT is not set +# CONFIG_POHMELFS is not set +# CONFIG_LINE6_USB is not set +CONFIG_USB_SERIAL_QUATECH2=m +CONFIG_USB_SERIAL_QUATECH_USB2=m +# CONFIG_VT6656 is not set +CONFIG_IIO=y +CONFIG_IIO_BUFFER=y +CONFIG_IIO_SW_RING=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_IIO_TRIGGER=y +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_KXSD9 is not set +# CONFIG_LIS3L02DQ is not set +# CONFIG_SCA3000 is not set + +# +# Analog to digital converters +# +# CONFIG_AD7291 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD799X is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +CONFIG_AD7192=m +# CONFIG_ADT7310 is not set +# CONFIG_ADT7410 is not set +CONFIG_AD7280=m +# CONFIG_MAX1363 is not set + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +CONFIG_AD7746=m + +# +# Digital to analog converters +# +CONFIG_AD5064=m +CONFIG_AD5360=m +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5686 is not set +# CONFIG_MAX517 is not set + +# +# Direct Digital Synthesis +# +# CONFIG_AD5930 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADXRS450 is not set + +# +# Network Analyzer, Impedance Converters +# +CONFIG_AD5933=m + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set + +# +# Light sensors +# +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_TSL2583 is not set + +# +# Magnetometer sensors +# +# CONFIG_SENSORS_AK8975 is not set +# CONFIG_SENSORS_HMC5843 is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +CONFIG_AD2S1200=m +# CONFIG_AD2S1210 is not set + +# +# Triggers - standalone +# +# CONFIG_IIO_PERIODIC_RTC_TRIGGER is not set +# CONFIG_IIO_GPIO_TRIGGER is not set +# CONFIG_IIO_SYSFS_TRIGGER is not set +CONFIG_IIO_DUMMY_EVGEN=m +CONFIG_IIO_SIMPLE_DUMMY=m +CONFIG_IIO_SIMPLE_DUMMY_EVENTS=y +CONFIG_IIO_SIMPLE_DUMMY_BUFFER=y +# CONFIG_XVMALLOC is not set +# CONFIG_ZRAM is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_TIDSPBRIDGE is not set +CONFIG_USB_ENESTORAGE=m +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set +CONFIG_CLKDEV_LOOKUP=y + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_MMIO=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y +CONFIG_OMAP_IOMMU=y +CONFIG_OMAP_IOVMM=y +CONFIG_OMAP_IOMMU_DEBUG=y +# CONFIG_VIRT_DRIVERS is not set +CONFIG_PM_DEVFREQ=y + +# +# DEVFREQ Governors +# +# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_USERSPACE=y + +# +# DEVFREQ Drivers +# + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +# CONFIG_EXT4_FS_SECURITY is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +CONFIG_JFS_FS=m +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set +CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS_LOCKING_DLM is not set +CONFIG_BTRFS_FS=m +# CONFIG_BTRFS_FS_POSIX_ACL is not set +CONFIG_NILFS2_FS=m +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_FANOTIFY=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=m +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=m +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_LOGFS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFS_USE_NEW_IDMAPPER is not set +CONFIG_NFSD=m +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=m +CONFIG_CIFS_STATS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_WEAK_PW_HASH=y +# CONFIG_CIFS_UPCALL is not set +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_ACL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +CONFIG_SCHEDSTATS=y +CONFIG_TIMER_STATS=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_LKDTM is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_RING_BUFFER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_ASYNC_RAID6_TEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +CONFIG_ARM_UNWIND=y +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_JTAG_ENABLE=y + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_XOR_BLOCKS=m +CONFIG_ASYNC_CORE=m +CONFIG_ASYNC_MEMCPY=m +CONFIG_ASYNC_XOR=m +CONFIG_ASYNC_PQ=m +CONFIG_ASYNC_RAID6_RECOV=m +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_GHASH is not set +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_MICHAEL_MIC=y +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_OMAP_SHAM is not set +# CONFIG_CRYPTO_DEV_OMAP_AES is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_RAID6_PQ=m +CONFIG_BITREVERSE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set diff --git a/patches/barebox-2012.07.0/0000-barebox-v2012.07.0-to-master.patch b/patches/barebox-2012.07.0/0000-barebox-v2012.07.0-to-master.patch new file mode 100644 index 0000000..4519124 --- /dev/null +++ b/patches/barebox-2012.07.0/0000-barebox-v2012.07.0-to-master.patch @@ -0,0 +1,12305 @@ +diff --git a/.gitignore b/.gitignore +index df0ed2c..fd429fa 100644 +--- a/.gitignore ++++ b/.gitignore +@@ -65,3 +65,4 @@ cscope.* + *.patch + scripts/gen_netx_image + scripts/s5p_cksum ++scripts/bareboxenv-target +diff --git a/Makefile b/Makefile +index 63da477..ebcf9bf 100644 +--- a/Makefile ++++ b/Makefile +@@ -540,7 +540,7 @@ quiet_cmd_check_file_size = CHKSIZE $@ + max_size=`printf "%d" $2`; \ + if [ $$size -gt $$max_size ] ; \ + then \ +- echo "$@ size $$size > of the maximum size $$max_size"; \ ++ echo "$@ size $$size > of the maximum size $$max_size" >&2; \ + exit 1 ; \ + fi; + +@@ -1003,6 +1003,7 @@ CLEAN_DIRS += $(MODVERDIR) + CLEAN_FILES += barebox System.map include/generated/barebox_default_env.h \ + .tmp_version .tmp_barebox* barebox.bin barebox.map barebox.S \ + .tmp_kallsyms* barebox_default_env* barebox.ldr \ ++ scripts/bareboxenv-target \ + Doxyfile.version barebox.srec barebox.s5p + + # Directories & files removed with 'make mrproper' +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 3eada5b..af4cb59 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -135,7 +135,15 @@ config CMD_ARM_CPUINFO + default y + help + Say yes here to get a cpuinfo command to show some +- information about the cp15 registers ++ CPU information using the cp15 registers ++ ++config CMD_ARM_MMUINFO ++ bool "mmuinfo command" ++ depends on CPU_V7 ++ default n ++ help ++ Say yes here to get a mmuinfo command to show some ++ MMU and cache information using the cp15 registers + + config CPU_V7_DCACHE_SKIP + bool "Skip DCache Invalidate" +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index bd684dc..1225df7 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -136,6 +136,7 @@ board-$(CONFIG_MACH_TQMA53) := tqma53 + board-$(CONFIG_MACH_TX51) := karo-tx51 + board-$(CONFIG_MACH_MX6Q_ARM2) := freescale-mx6-arm2 + board-$(CONFIG_MACH_TOSHIBA_AC100) := toshiba-ac100 ++board-$(CONFIG_MACH_CCMX51) := ccxmx51 + + machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) + +diff --git a/arch/arm/boards/a9m2410/a9m2410.c b/arch/arm/boards/a9m2410/a9m2410.c +index eaafdbd..e2044a9 100644 +--- a/arch/arm/boards/a9m2410/a9m2410.c ++++ b/arch/arm/boards/a9m2410/a9m2410.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -109,8 +110,7 @@ static int a9m2410_devices_init(void) + writel(reg, S3C_MISCCR); + + /* ----------- the devices the boot loader should work with -------- */ +- add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE, +- 0, IORESOURCE_MEM, &nand_info); ++ s3c24xx_add_nand(&nand_info); + /* + * SMSC 91C111 network controller on the baseboard + * connected to CS line 1 and interrupt line +@@ -145,8 +145,7 @@ void __bare_init nand_boot(void) + + static int a9m2410_console_init(void) + { +- add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE, +- S3C_UART1_SIZE, IORESOURCE_MEM, NULL); ++ s3c24xx_add_uart1(); + return 0; + } + +diff --git a/arch/arm/boards/a9m2440/a9m2440.c b/arch/arm/boards/a9m2440/a9m2440.c +index 1d20248..8975c15 100644 +--- a/arch/arm/boards/a9m2440/a9m2440.c ++++ b/arch/arm/boards/a9m2440/a9m2440.c +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -129,8 +130,7 @@ static int a9m2440_devices_init(void) + writel(reg, S3C_MISCCR); + + /* ----------- the devices the boot loader should work with -------- */ +- add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE, 0, +- IORESOURCE_MEM, &nand_info); ++ s3c24xx_add_nand(&nand_info); + /* + * cs8900 network controller onboard + * Connected to CS line 5 + A24 and interrupt line EINT9, +@@ -164,8 +164,7 @@ void __bare_init nand_boot(void) + + static int a9m2440_console_init(void) + { +- add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE, +- S3C_UART1_SIZE, IORESOURCE_MEM, NULL); ++ s3c24xx_add_uart1(); + return 0; + } + +diff --git a/arch/arm/boards/ccxmx51/Makefile b/arch/arm/boards/ccxmx51/Makefile +new file mode 100644 +index 0000000..249927e +--- /dev/null ++++ b/arch/arm/boards/ccxmx51/Makefile +@@ -0,0 +1,2 @@ ++obj-y += flash_header.o ccxmx51.o ++obj-$(CONFIG_MACH_CCMX51_BASEBOARD) += ccxmx51js.o +diff --git a/arch/arm/boards/ccxmx51/ccxmx51.c b/arch/arm/boards/ccxmx51/ccxmx51.c +new file mode 100644 +index 0000000..f494174 +--- /dev/null ++++ b/arch/arm/boards/ccxmx51/ccxmx51.c +@@ -0,0 +1,489 @@ ++/* ++ * (C) Copyright 2009-2010 Digi International, Inc. ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * (c) 2011 Eukrea Electromatique, Eric Bénard ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ccxmx51.h" ++ ++static struct ccxmx51_ident ccxmx51_ids[] = { ++/* 0x00 */ { "Unknown", 0, 0, 0, 0, 0 }, ++/* 0x01 */ { "Not supported", 0, 0, 0, 0, 0 }, ++/* 0x02 */ { "i.MX515@800MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 1 }, ++/* 0x03 */ { "i.MX515@800MHz, PHY, Ext. Eth, Accel", SZ_512M, 0, 1, 1, 0 }, ++/* 0x04 */ { "i.MX515@600MHz, Wireless, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 1 }, ++/* 0x05 */ { "i.MX515@600MHz, PHY, Ext. Eth, Accel", SZ_512M, 1, 1, 1, 0 }, ++/* 0x06 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 }, ++/* 0x07 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 }, ++/* 0x08 */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_256M, 0, 1, 0, 1 }, ++/* 0x09 */ { "i.MX515@800MHz, PHY, Accel", SZ_256M, 0, 1, 0, 0 }, ++/* 0x0a */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_256M, 1, 1, 0, 1 }, ++/* 0x0b */ { "i.MX515@600MHz, PHY, Accel", SZ_256M, 1, 1, 0, 0 }, ++/* 0x0c */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_128M, 0, 1, 0, 1 }, ++/* 0x0d */ { "i.MX512@800MHz", SZ_128M, 0, 0, 0, 0 }, ++/* 0x0e */ { "i.MX515@800MHz, Wireless, PHY, Accel", SZ_512M, 0, 1, 0, 1 }, ++/* 0x0f */ { "i.MX515@600MHz, PHY, Accel", SZ_128M, 1, 1, 0, 0 }, ++/* 0x10 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_128M, 1, 1, 0, 1 }, ++/* 0x11 */ { "i.MX515@800MHz, PHY, Accel", SZ_128M, 0, 1, 0, 0 }, ++/* 0x12 */ { "i.MX515@600MHz, Wireless, PHY, Accel", SZ_512M, 1, 1, 0, 1 }, ++/* 0x13 */ { "i.MX515@800MHz, PHY, Accel", SZ_512M, 0, 1, 0, 0 }, ++}; ++ ++struct ccxmx51_ident *ccxmx51_id; ++ ++struct imx_nand_platform_data nand_info = { ++ .width = 1, ++ .hw_ecc = 1, ++ .flash_bbt = 1, ++}; ++ ++#ifdef CONFIG_DRIVER_NET_FEC_IMX ++static struct fec_platform_data fec_info = { ++ .xcv_type = MII100, ++ .phy_addr = 7, ++}; ++#endif ++ ++static iomux_v3_cfg_t ccxmx51_pads[] = { ++ /* UART1 */ ++ MX51_PAD_UART1_RXD__UART1_RXD, ++ MX51_PAD_UART1_TXD__UART1_TXD, ++ /* UART2 */ ++ MX51_PAD_UART2_RXD__UART2_RXD, ++ MX51_PAD_UART2_TXD__UART2_TXD, ++ /* UART3 */ ++ MX51_PAD_UART3_RXD__UART3_RXD, ++ MX51_PAD_UART3_TXD__UART3_TXD, ++ /* I2C2 */ ++ MX51_PAD_GPIO1_2__I2C2_SCL, ++ MX51_PAD_GPIO1_3__I2C2_SDA, ++ /* eCSPI1 */ ++ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, ++ MX51_PAD_CSPI1_MISO__ECSPI1_MISO, ++ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, ++ MX51_PAD_CSPI1_RDY__ECSPI1_RDY, ++ MX51_PAD_CSPI1_SS0__ECSPI1_SS0, ++ MX51_PAD_CSPI1_SS1__ECSPI1_SS1, ++ /* FEC */ ++ MX51_PAD_DISP2_DAT14__FEC_RDATA0, ++ MX51_PAD_DI2_DISP_CLK__FEC_RDATA1, ++ MX51_PAD_DI_GP4__FEC_RDATA2, ++ MX51_PAD_DISP2_DAT0__FEC_RDATA3, ++ MX51_PAD_DISP2_DAT15__FEC_TDATA0, ++ MX51_PAD_DISP2_DAT6__FEC_TDATA1, ++ MX51_PAD_DISP2_DAT7__FEC_TDATA2, ++ MX51_PAD_DISP2_DAT8__FEC_TDATA3, ++ MX51_PAD_DISP2_DAT9__FEC_TX_EN, ++ MX51_PAD_DISP2_DAT10__FEC_COL, ++ MX51_PAD_DISP2_DAT11__FEC_RX_CLK, ++ MX51_PAD_DISP2_DAT12__FEC_RX_DV, ++ MX51_PAD_DISP2_DAT13__FEC_TX_CLK, ++ MX51_PAD_DI2_PIN2__FEC_MDC, ++ MX51_PAD_DI2_PIN4__FEC_CRS, ++ MX51_PAD_DI2_PIN3__FEC_MDIO, ++ MX51_PAD_DI_GP3__FEC_TX_ER, ++ MX51_PAD_DISP2_DAT1__FEC_RX_ER, ++ /* WEIM */ ++ MX51_PAD_EIM_DA0__EIM_DA0, ++ MX51_PAD_EIM_DA1__EIM_DA1, ++ MX51_PAD_EIM_DA2__EIM_DA2, ++ MX51_PAD_EIM_DA3__EIM_DA3, ++ MX51_PAD_EIM_DA4__EIM_DA4, ++ MX51_PAD_EIM_DA5__EIM_DA5, ++ MX51_PAD_EIM_DA6__EIM_DA6, ++ MX51_PAD_EIM_DA7__EIM_DA7, ++ MX51_PAD_EIM_D16__EIM_D16, ++ MX51_PAD_EIM_D17__EIM_D17, ++ MX51_PAD_EIM_D18__EIM_D18, ++ MX51_PAD_EIM_D19__EIM_D19, ++ MX51_PAD_EIM_D20__EIM_D20, ++ MX51_PAD_EIM_D21__EIM_D21, ++ MX51_PAD_EIM_D22__EIM_D22, ++ MX51_PAD_EIM_D23__EIM_D23, ++ MX51_PAD_EIM_D24__EIM_D24, ++ MX51_PAD_EIM_D25__EIM_D25, ++ MX51_PAD_EIM_D26__EIM_D26, ++ MX51_PAD_EIM_D27__EIM_D27, ++ MX51_PAD_EIM_D28__EIM_D28, ++ MX51_PAD_EIM_D29__EIM_D29, ++ MX51_PAD_EIM_D30__EIM_D30, ++ MX51_PAD_EIM_D31__EIM_D31, ++ MX51_PAD_EIM_OE__EIM_OE, ++ MX51_PAD_EIM_CS5__EIM_CS5, ++ /* NAND */ ++ MX51_PAD_NANDF_D0__NANDF_D0, ++ MX51_PAD_NANDF_D1__NANDF_D1, ++ MX51_PAD_NANDF_D2__NANDF_D2, ++ MX51_PAD_NANDF_D3__NANDF_D3, ++ MX51_PAD_NANDF_D4__NANDF_D4, ++ MX51_PAD_NANDF_D5__NANDF_D5, ++ MX51_PAD_NANDF_D6__NANDF_D6, ++ MX51_PAD_NANDF_D7__NANDF_D7, ++ MX51_PAD_NANDF_ALE__NANDF_ALE, ++ MX51_PAD_NANDF_CLE__NANDF_CLE, ++ MX51_PAD_NANDF_RE_B__NANDF_RE_B, ++ MX51_PAD_NANDF_WE_B__NANDF_WE_B, ++ MX51_PAD_NANDF_WP_B__NANDF_WP_B, ++ MX51_PAD_NANDF_CS0__NANDF_CS0, ++ MX51_PAD_NANDF_RB0__NANDF_RB0, ++ /* LAN9221 IRQ (GPIO1.9) */ ++ MX51_PAD_GPIO1_9__GPIO1_9, ++ /* MC13892 IRQ (GPIO1.5) */ ++ MX51_PAD_GPIO1_5__GPIO1_5, ++ /* MMA7455LR IRQ1 (GPIO1.7) */ ++ MX51_PAD_GPIO1_7__GPIO1_7, ++ /* MMA7455LR IRQ2 (GPIO1.6) */ ++ MX51_PAD_GPIO1_6__GPIO1_6, ++}; ++ ++#define CCXMX51_ECSPI1_CS0 IMX_GPIO_NR(4, 24) ++#define CCXMX51_ECSPI1_CS1 IMX_GPIO_NR(4, 25) ++ ++static int ecspi_0_cs[] = { CCXMX51_ECSPI1_CS0, CCXMX51_ECSPI1_CS1, }; ++ ++static struct spi_imx_master ecspi_0_data = { ++ .chipselect = ecspi_0_cs, ++ .num_chipselect = ARRAY_SIZE(ecspi_0_cs), ++}; ++ ++static const struct spi_board_info ccxmx51_spi_board_info[] = { ++ { ++ .name = "mc13xxx-spi", ++ .max_speed_hz = 6000000, ++ .bus_num = 0, ++ .chip_select = 0, ++ }, ++}; ++ ++static int ccxmx51_mem_init(void) ++{ ++ /* Add minimal SDRAM first */ ++ arm_add_mem_device("ram0", MX51_CSD0_BASE_ADDR, SZ_128M); ++ ++ return 0; ++} ++mem_initcall(ccxmx51_mem_init); ++ ++static void ccxmx51_otghost_init(void) ++{ ++#define MX51_USBOTHER_REGS_OFFSET 0x800 ++#define MX51_USBCTRL_OFFSET 0x0 ++#define MX51_USB_PHY_CTR_FUNC_OFFSET 0x8 ++#define MX51_USB_PHY_CTR_FUNC2_OFFSET 0xc ++#define MX51_USB_UTMI_PHYCTRL1_PLLDIV_MASK 0x3 ++#define MX51_USB_PLL_DIV_19_2_MHZ 0x00 ++#define MX51_USB_PLL_DIV_24_MHZ 0x01 ++#define MX51_USB_PLL_DIV_26_MHZ 0x02 ++#define MX51_USB_PLL_DIV_27_MHZ 0x03 ++#define MX51_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) ++#define MX51_OTG_UCTRL_OWIE_BIT (1 << 27) ++#define MX51_OTG_UCTRL_OPM_BIT (1 << 24) ++ ++#define USBOTHER_BASE (MX51_OTG_BASE_ADDR + MX51_USBOTHER_REGS_OFFSET) ++ ++ u32 reg; ++ ++ /* Set sysclock to 24 MHz */ ++ reg = readl(USBOTHER_BASE + MX51_USB_PHY_CTR_FUNC2_OFFSET); ++ reg &= ~MX51_USB_UTMI_PHYCTRL1_PLLDIV_MASK; ++ reg |= MX51_USB_PLL_DIV_24_MHZ; ++ writel(reg, USBOTHER_BASE + MX51_USB_PHY_CTR_FUNC2_OFFSET); ++ ++ /* OC is not used */ ++ reg = readl(USBOTHER_BASE + MX51_USB_PHY_CTR_FUNC_OFFSET); ++ reg |= MX51_OTG_PHYCTRL_OC_DIS_BIT; ++ writel(reg, USBOTHER_BASE + MX51_USB_PHY_CTR_FUNC_OFFSET); ++ ++ /* Power pins enable */ ++ reg = readl(USBOTHER_BASE + MX51_USBCTRL_OFFSET); ++ reg |= MX51_OTG_UCTRL_OWIE_BIT | MX51_OTG_UCTRL_OPM_BIT; ++ writel(reg, USBOTHER_BASE + MX51_USBCTRL_OFFSET); ++ ++ /* Setup PORTSC */ ++ reg = readl(MX51_OTG_BASE_ADDR + 0x184); ++ reg &= ~(3 << 30); ++ reg |= 1 << 28; ++ writel(reg, MX51_OTG_BASE_ADDR + 0x184); ++ ++ mdelay(10); ++ ++ add_generic_usb_ehci_device(0, MX51_OTG_BASE_ADDR, NULL); ++} ++ ++static int ccxmx51_power_init(void) ++{ ++ struct mc13xxx *mc13xxx_dev; ++ u32 val; ++ ++ mc13xxx_dev = mc13xxx_get(); ++ if (!mc13xxx_dev) ++ return -ENODEV; ++ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val); ++ /* Reset devices by clearing GP01-GPO4 */ ++ val &= ~((1 << 21) | (3 << 12) | (3 << 10) | (3 << 8) | (3 << 6)); ++ /* Switching off the PWGT1SPIEN */ ++ val |= (1 << 15); ++ /* Switching on the PWGT2SPIEN */ ++ val &= ~(1 << 16); ++ /* Enable short circuit protection */ ++ val |= (1 << 0); ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_MISC, val); ++ ++ /* Allow charger to charge (4.2V and 560mA) */ ++ val = 0x238033; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_CHARGE, val); ++ ++ /* Set core voltage (SW1) to 1.1V */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_0, &val); ++ val &= ~0x00001f; ++ val |= 0x000014; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_0, val); ++ ++ if (imx_silicon_revision() < IMX_CHIP_REV_3_0) { ++ /* Setup VCC (SW2) to 1.25 */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_1, &val); ++ val &= ~0x00001f; ++ val |= 0x00001a; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_1, val); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.25 */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_2, &val); ++ val &= ~0x00001f; ++ val |= 0x00001a; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val); ++ } else { ++ /* Setup VCC (SW2) to 1.225 */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_1, &val); ++ val &= ~0x00001f; ++ val |= 0x000019; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_1, val); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.2 */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_2, &val); ++ val &= ~0x00001f; ++ val |= 0x000018; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_2, val); ++ } ++ ++ if (mc13xxx_dev->revision <= MC13892_REVISION_2_0) { ++ /* Set switchers in PWM mode for Atlas 2.0 and lower */ ++ /* Setup the switcher mode for SW1 & SW2*/ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val); ++ val &= ~0x003c0f; ++ val |= 0x001405; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_4, val); ++ ++ /* Setup the switcher mode for SW3 & SW4 */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_5, &val); ++ val &= ~0x000f0f; ++ val |= 0x000505; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_5, val); ++ } else { ++ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ ++ /* Setup the switcher mode for SW1 & SW2*/ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_4, &val); ++ val &= ~0x003c0f; ++ val |= 0x002008; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_4, val); ++ ++ /* Setup the switcher mode for SW3 & SW4 */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SW_5, &val); ++ val &= ~0x000f0f; ++ val |= 0x000808; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SW_5, val); ++ } ++ ++ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SETTING_1, &val); ++ val &= ~0x0001fc; ++ val |= 0x0001f4; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SETTING_1, val); ++ ++ /* Configure VGEN3 and VCAM regulators to use external PNP */ ++ val = 0x000208; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_MODE_1, val); ++ udelay(200); ++ ++ /* Set VGEN3 to 1.8V */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_SETTING_0, &val); ++ val &= ~(1 << 14); ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_SETTING_0, val); ++ ++ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ ++ val = 0x049249; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_MODE_1, val); ++ ++ /* Enable USB1 charger */ ++ val = 0x000409; ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_USB1, val); ++ ++ /* Set VCOIN to 3.0V and Enable It */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_CTL0, &val); ++ val &= ~(7 << 20); ++ val |= (4 << 20) | (1 << 23); ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_CTL0, val); ++ /* Keeps VSRTC and CLK32KMCU */ ++ val |= (1 << 4); ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_CTL0, val); ++ ++ /* De-assert reset of external devices on GP01, GPO2, GPO3 and GPO4 */ ++ mc13xxx_reg_read(mc13xxx_dev, MC13892_REG_POWER_MISC, &val); ++ /* GPO1 - External */ ++ /* GP02 - LAN9221 */ ++ /* GP03 - FEC */ ++ /* GP04 - Wireless */ ++ if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X) && ccxmx51_id->eth0) ++ val |= (1 << 8); ++ if (IS_ENABLED(CONFIG_DRIVER_NET_FEC_IMX) && ccxmx51_id->eth1) ++ val |= (1 << 10); ++ if (ccxmx51_id->wless) ++ val |= (1 << 12); ++ mc13xxx_reg_write(mc13xxx_dev, MC13892_REG_POWER_MISC, val); ++ ++ udelay(100); ++ ++ return 0; ++} ++ ++static int ccxmx51_devices_init(void) ++{ ++ u8 hwid[6]; ++ int pwr; ++ char manloc; ++ ++ if ((imx_iim_read(1, 9, hwid, sizeof(hwid)) != sizeof(hwid)) || (hwid[0] < 0x02) || (hwid[0] >= ARRAY_SIZE(ccxmx51_ids))) ++ memset(hwid, 0x00, sizeof(hwid)); ++ ++ ccxmx51_id = &ccxmx51_ids[hwid[0]]; ++ printf("Module Variant: %s (0x%02x)\n", ccxmx51_id->id_string, hwid[0]); ++ ++ if (hwid[0]) { ++ printf("Module HW Rev : %02x\n", hwid[1]); ++ switch (hwid[2] & 0xc0) { ++ case 0x00: ++ manloc = 'B'; ++ break; ++ case 0x40: ++ manloc = 'W'; ++ break; ++ case 0x80: ++ manloc = 'S'; ++ break; ++ default: ++ manloc = 'N'; ++ break; ++ } ++ printf("Module Serial : %c%d\n", manloc, ((hwid[2] & 0x3f) << 24) | (hwid[3] << 16) | (hwid[4] << 8) | hwid[5]); ++ if ((ccxmx51_id->mem_sz - SZ_128M) > 0) ++ arm_add_mem_device("ram1", MX51_CSD0_BASE_ADDR + SZ_128M, ccxmx51_id->mem_sz - SZ_128M); ++ } ++ ++ imx51_add_uart1(); ++ imx51_add_uart2(); ++ ++ spi_register_board_info(ccxmx51_spi_board_info, ARRAY_SIZE(ccxmx51_spi_board_info)); ++ imx51_add_spi0(&ecspi_0_data); ++ ++ pwr = ccxmx51_power_init(); ++ console_flush(); ++ imx51_init_lowlevel((ccxmx51_id->industrial || pwr) ? 600 : 800); ++ clock_notifier_call_chain(); ++ if (pwr) ++ printf("Could not setup PMIC. Clocks not adjusted.\n"); ++ ++ imx51_add_i2c1(NULL); ++ ++ imx51_add_nand(&nand_info); ++ devfs_add_partition("nand0", 0x00000, 0x80000, DEVFS_PARTITION_FIXED, "self_raw"); ++ dev_add_bb_dev("self_raw", "self0"); ++ devfs_add_partition("nand0", 0x80000, 0x40000, DEVFS_PARTITION_FIXED, "env_raw"); ++ dev_add_bb_dev("env_raw", "env0"); ++ ++#ifdef CONFIG_DRIVER_NET_FEC_IMX ++ if (ccxmx51_id->eth0 && !pwr) { ++ imx51_add_fec(&fec_info); ++ eth_register_ethaddr(0, hwid); ++ } ++#endif ++ ++#ifdef CONFIG_DRIVER_NET_SMC911X ++ if (ccxmx51_id->eth1 && !pwr) { ++ /* Configure the WEIM CS5 timming, bus width, etc */ ++ /* 16 bit on DATA[31..16], not multiplexed, async */ ++ writel(0x00420081, MX51_WEIM_BASE_ADDR + WEIM_CSxGCR1(5)); ++ /* ADH has not effect on non muxed bus */ ++ writel(0, MX51_WEIM_BASE_ADDR + WEIM_CSxGCR2(5)); ++ /* RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0 */ ++ writel(0x32260000, MX51_WEIM_BASE_ADDR + WEIM_CSxRCR1(5)); ++ /* APR=0 */ ++ writel(0, MX51_WEIM_BASE_ADDR + WEIM_CSxRCR2(5)); ++ /* WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0 */ ++ writel(0x72080f00, MX51_WEIM_BASE_ADDR + WEIM_CSxWCR1(5)); ++ ++ /* LAN9221 network controller */ ++ add_generic_device("smc911x", 1, NULL, MX51_CS5_BASE_ADDR, SZ_4K, IORESOURCE_MEM, NULL); ++ } ++#endif ++ ++ ccxmx51_otghost_init(); ++ ++ armlinux_set_bootparams((void *)(MX51_CSD0_BASE_ADDR + 0x100)); ++ ++ armlinux_set_architecture(ccxmx51_id->wless ? MACH_TYPE_CCWMX51 : MACH_TYPE_CCMX51); ++ ++ return 0; ++} ++device_initcall(ccxmx51_devices_init); ++ ++static int ccxmx51_console_init(void) ++{ ++ mxc_iomux_v3_setup_multiple_pads(ccxmx51_pads, ARRAY_SIZE(ccxmx51_pads)); ++ ++ imx51_add_uart0(); ++ ++ return 0; ++} ++console_initcall(ccxmx51_console_init); +diff --git a/arch/arm/boards/ccxmx51/ccxmx51.dox b/arch/arm/boards/ccxmx51/ccxmx51.dox +new file mode 100644 +index 0000000..cc28e8d +--- /dev/null ++++ b/arch/arm/boards/ccxmx51/ccxmx51.dox +@@ -0,0 +1,7 @@ ++/** @page ccxmx51 Digi ConnectCore board ++ ++This boards is based on a Freescale i.MX51 CPU. The board is shipped with: ++- Up to 8 GB NAND Flash. ++- Up to 512 MB DDR2 RAM. ++ ++*/ +diff --git a/arch/arm/boards/ccxmx51/ccxmx51.h b/arch/arm/boards/ccxmx51/ccxmx51.h +new file mode 100644 +index 0000000..3feacac +--- /dev/null ++++ b/arch/arm/boards/ccxmx51/ccxmx51.h +@@ -0,0 +1,35 @@ ++/* ++ * Copyright 2010 Digi International Inc. All Rights Reserved. ++ */ ++ ++/* ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++#ifndef _CCXMX51_H_ ++#define _CCXMX51_H_ ++ ++struct ccxmx51_hwid { ++ u8 variant; ++ u8 version; ++ u32 sn; ++ char mloc; ++}; ++ ++struct ccxmx51_ident { ++ const char *id_string; ++ const int mem_sz; ++ const char industrial; ++ const char eth0; ++ const char eth1; ++ const char wless; ++}; ++ ++extern struct ccxmx51_ident *ccxmx51_id; ++ ++#endif /* _CCXMX51_H_ */ +diff --git a/arch/arm/boards/ccxmx51/ccxmx51js.c b/arch/arm/boards/ccxmx51/ccxmx51js.c +new file mode 100644 +index 0000000..f04615d +--- /dev/null ++++ b/arch/arm/boards/ccxmx51/ccxmx51js.c +@@ -0,0 +1,90 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "ccxmx51.h" ++ ++static iomux_v3_cfg_t ccxmx51js_pads[] = { ++ /* SD1 */ ++ MX51_PAD_SD1_CLK__SD1_CLK, ++ MX51_PAD_SD1_CMD__SD1_CMD, ++ MX51_PAD_SD1_DATA0__SD1_DATA0, ++ MX51_PAD_SD1_DATA1__SD1_DATA1, ++ MX51_PAD_SD1_DATA2__SD1_DATA2, ++ MX51_PAD_SD1_DATA3__SD1_DATA3, ++ /* SD3 */ ++ MX51_PAD_NANDF_CS7__SD3_CLK, ++ MX51_PAD_NANDF_RDY_INT__SD3_CMD, ++ MX51_PAD_NANDF_D8__SD3_DATA0, ++ MX51_PAD_NANDF_D9__SD3_DATA1, ++ MX51_PAD_NANDF_D10__SD3_DATA2, ++ MX51_PAD_NANDF_D11__SD3_DATA3, ++ MX51_PAD_NANDF_D12__SD3_DAT4, ++ MX51_PAD_NANDF_D13__SD3_DAT5, ++ MX51_PAD_NANDF_D14__SD3_DAT6, ++ MX51_PAD_NANDF_D15__SD3_DAT7, ++ /* USB HOST1 */ ++ MX51_PAD_USBH1_CLK__USBH1_CLK, ++ MX51_PAD_USBH1_DIR__USBH1_DIR, ++ MX51_PAD_USBH1_NXT__USBH1_NXT, ++ MX51_PAD_USBH1_STP__USBH1_STP, ++ MX51_PAD_USBH1_DATA0__USBH1_DATA0, ++ MX51_PAD_USBH1_DATA1__USBH1_DATA1, ++ MX51_PAD_USBH1_DATA2__USBH1_DATA2, ++ MX51_PAD_USBH1_DATA3__USBH1_DATA3, ++ MX51_PAD_USBH1_DATA4__USBH1_DATA4, ++ MX51_PAD_USBH1_DATA5__USBH1_DATA5, ++ MX51_PAD_USBH1_DATA6__USBH1_DATA6, ++ MX51_PAD_USBH1_DATA7__USBH1_DATA7, ++}; ++ ++static struct esdhc_platform_data sdhc1_pdata = { ++ .cd_type = ESDHC_CD_NONE, ++ .wp_type = ESDHC_WP_NONE, ++ .caps = MMC_MODE_4BIT, ++}; ++ ++static struct esdhc_platform_data sdhc3_pdata = { ++ .cd_type = ESDHC_CD_NONE, ++ .wp_type = ESDHC_WP_NONE, ++ .caps = MMC_MODE_4BIT | MMC_MODE_8BIT, ++}; ++ ++static int ccxmx51js_init(void) ++{ ++ mxc_iomux_v3_setup_multiple_pads(ccxmx51js_pads, ARRAY_SIZE(ccxmx51js_pads)); ++ ++ if (IS_ENABLED(CONFIG_MCI_IMX_ESDHC)) { ++ imx51_add_mmc0(&sdhc1_pdata); ++ imx51_add_mmc2(&sdhc3_pdata); ++ } ++ ++ armlinux_set_architecture(ccxmx51_id->wless ? MACH_TYPE_CCWMX51JS : MACH_TYPE_CCMX51JS); ++ ++ return 0; ++} ++ ++late_initcall(ccxmx51js_init); +diff --git a/arch/arm/boards/ccxmx51/config.h b/arch/arm/boards/ccxmx51/config.h +new file mode 100644 +index 0000000..fdf2f81 +--- /dev/null ++++ b/arch/arm/boards/ccxmx51/config.h +@@ -0,0 +1,24 @@ ++/** ++ * @file ++ * @brief Global defintions for the ARM i.MX51 based ccmx51 board ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#endif /* __CONFIG_H */ +diff --git a/arch/arm/boards/ccxmx51/env/config b/arch/arm/boards/ccxmx51/env/config +new file mode 100644 +index 0000000..bbd43e7 +--- /dev/null ++++ b/arch/arm/boards/ccxmx51/env/config +@@ -0,0 +1,37 @@ ++#!/bin/sh ++ ++machine=ccmx51 ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration ++ip=none ++ ++# or set your networking parameters here ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'nfs', 'tftp' or 'nand' ++kernel_loc=nand ++# can be either 'net', 'nand' or 'initrd' ++rootfs_loc=nand ++ ++# rootfs ++rootfs_type=cramfs ++ ++# kernel ++kernelimage_type=zimage ++kernel_img=/dev/nand0.kernel ++ ++autoboot_timeout=3 ++ ++bootargs="console=ttymxc0,115200" ++ ++device_type="nand" ++nand_device="mxc_nand" ++nand_parts="512k(barebox)ro,256k(bareboxenv),3328k(kernel),-(root)" ++rootfs_mtdblock_nand=3 ++ ++# set a fancy prompt (if support is compiled in) ++PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " +diff --git a/arch/arm/boards/ccxmx51/flash_header.c b/arch/arm/boards/ccxmx51/flash_header.c +new file mode 100644 +index 0000000..c148eea +--- /dev/null ++++ b/arch/arm/boards/ccxmx51/flash_header.c +@@ -0,0 +1,84 @@ ++#include ++#include ++#include ++ ++void __naked __flash_header_start go(void) ++{ ++ barebox_arm_head(); ++} ++ ++struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { ++ { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, }, ++ { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, ++ { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, ++ { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, }, ++ { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, }, ++ { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, ++ { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, ++ { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, ++ { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, ++ { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, ++ { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, ++ { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, }, ++ { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, }, ++ { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, }, ++ { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, }, ++ { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, }, ++ { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, }, ++ { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, }, ++ { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, ++ { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, ++ { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, }, ++ { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, }, ++ { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, ++ { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, ++ { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, ++ { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, ++ { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, ++}; ++ ++#define APP_DEST 0x90000000 ++ ++struct imx_flash_header __flash_header_section flash_header = { ++ .app_code_jump_vector = APP_DEST + 0x1000, ++ .app_code_barker = APP_CODE_BARKER, ++ .app_code_csf = 0, ++ .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), ++ .super_root_key = 0, ++ .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), ++ .app_dest = APP_DEST, ++ .dcd_barker = DCD_BARKER, ++ .dcd_block_len = sizeof (dcd_entry), ++}; ++ ++unsigned long __image_len_section barebox_len = DCD_BAREBOX_SIZE; ++ +diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c +index 38f28be..b40713d 100644 +--- a/arch/arm/boards/chumby_falconwing/falconwing.c ++++ b/arch/arm/boards/chumby_falconwing/falconwing.c +@@ -316,7 +316,7 @@ static void falconwing_init_usb(void) + /* bring USB hub out of reset */ + gpio_direction_output(GPIO_USB_HUB_RESET, 1); + +- imx_usb_phy_enable(); ++ imx23_usb_phy_enable(); + + add_generic_usb_ehci_device(-1, IMX_USB_BASE, NULL); + } +diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +index 3cc7a72..35c114d 100644 +--- a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c ++++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c +@@ -53,6 +53,11 @@ struct imx_nand_platform_data nand_info = { + }; + + static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = { ++ /* UART1 */ ++ MX51_PAD_UART1_RXD__UART1_RXD, ++ MX51_PAD_UART1_TXD__UART1_TXD, ++ MX51_PAD_UART1_RTS__UART1_RTS, ++ MX51_PAD_UART1_CTS__UART1_CTS, + /* FEC */ + MX51_PAD_DISP2_DAT1__FEC_RX_ER, + MX51_PAD_DISP2_DAT15__FEC_TDATA0, +@@ -141,12 +146,8 @@ static int eukrea_cpuimx51_console_init(void) + + imx51_init_lowlevel(800); + +- writel(0, 0x73fa8228); +- writel(0, 0x73fa822c); +- writel(0, 0x73fa8230); +- writel(0, 0x73fa8234); +- + imx51_add_uart0(); ++ + return 0; + } + +diff --git a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c +index 9168ed8..1283e17 100644 +--- a/arch/arm/boards/freescale-mx28-evk/mx28-evk.c ++++ b/arch/arm/boards/freescale-mx28-evk/mx28-evk.c +@@ -22,17 +22,18 @@ + #include + #include + #include ++#include + + #include + #include + #include + #include ++#include ++#include + + #include + #include + +-#include +- + #include + + #define MX28EVK_FEC_PHY_RESET_GPIO 141 +@@ -118,6 +119,27 @@ static struct mxs_mci_platform_data mci_pdata = { + }; + + /* fec */ ++static void mx28_evk_get_ethaddr(void) ++{ ++ u8 mac_ocotp[3], mac[6]; ++ int ret; ++ ++ ret = mxs_ocotp_read(mac_ocotp, 3, 0); ++ if (ret != 3) { ++ pr_err("Reading MAC from OCOTP failed!\n"); ++ return; ++ } ++ ++ mac[0] = 0x00; ++ mac[1] = 0x04; ++ mac[2] = 0x9f; ++ mac[3] = mac_ocotp[2]; ++ mac[4] = mac_ocotp[1]; ++ mac[5] = mac_ocotp[0]; ++ ++ eth_register_ethaddr(0, mac); ++} ++ + static void __init mx28_evk_fec_reset(void) + { + mdelay(1); +@@ -208,6 +230,10 @@ static int mx28_evk_devices_init(void) + add_generic_device("stmfb", 0, NULL, IMX_FB_BASE, 4096, + IORESOURCE_MEM, &mx28_evk_fb_pdata); + ++ add_generic_device("ocotp", 0, NULL, IMX_OCOTP_BASE, 0, ++ IORESOURCE_MEM, NULL); ++ mx28_evk_get_ethaddr(); /* must be after registering ocotp */ ++ + imx_enable_enetclk(); + mx28_evk_fec_reset(); + add_generic_device("fec_imx", 0, NULL, IMX_FEC0_BASE, 0, +diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c +index 0bb2ffe..3a568d0 100644 +--- a/arch/arm/boards/freescale-mx51-pdk/board.c ++++ b/arch/arm/boards/freescale-mx51-pdk/board.c +@@ -48,6 +48,12 @@ static struct fec_platform_data fec_info = { + }; + + static iomux_v3_cfg_t f3s_pads[] = { ++ /* UART1 */ ++ MX51_PAD_UART1_RXD__UART1_RXD, ++ MX51_PAD_UART1_TXD__UART1_TXD, ++ MX51_PAD_UART1_RTS__UART1_RTS, ++ MX51_PAD_UART1_CTS__UART1_CTS, ++ /* FEC */ + MX51_PAD_EIM_EB2__FEC_MDIO, + MX51_PAD_EIM_EB3__FEC_RDATA1, + MX51_PAD_EIM_CS2__FEC_RDATA2, +@@ -246,6 +252,7 @@ static int f3s_devices_init(void) + imx51_iim_register_fec_ethaddr(); + imx51_add_fec(&fec_info); + imx51_add_mmc0(NULL); ++ imx51_add_mmc1(NULL); + + armlinux_set_bootparams((void *)0x90000100); + armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); +@@ -268,12 +275,8 @@ static int f3s_console_init(void) + { + mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); + +- writel(0, 0x73fa8228); +- writel(0, 0x73fa822c); +- writel(0, 0x73fa8230); +- writel(0, 0x73fa8234); +- + imx51_add_uart0(); ++ + return 0; + } + +diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c +index 3d3b820..3523949 100644 +--- a/arch/arm/boards/mini2440/mini2440.c ++++ b/arch/arm/boards/mini2440/mini2440.c +@@ -39,6 +39,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -297,8 +298,7 @@ static int mini2440_devices_init(void) + reg |= 0x10000; + writel(reg, S3C_MISCCR); + +- add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, S3C24X0_NAND_BASE, +- 0, IORESOURCE_MEM, &nand_info); ++ s3c24xx_add_nand(&nand_info); + + add_dm9000_device(0, S3C_CS4_BASE + 0x300, S3C_CS4_BASE + 0x304, + IORESOURCE_MEM_16BIT, &dm9000_data); +@@ -312,12 +312,9 @@ static int mini2440_devices_init(void) + devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + #endif +- add_generic_device("s3c_mci", 0, NULL, S3C2410_SDI_BASE, 0, +- IORESOURCE_MEM, &mci_data); +- add_generic_device("s3c_fb", 0, NULL, S3C2410_LCD_BASE, 0, +- IORESOURCE_MEM, &s3c24x0_fb_data); +- add_generic_device("ohci", 0, NULL, S3C2410_USB_HOST_BASE, 0x100, +- IORESOURCE_MEM, NULL); ++ s3c24xx_add_mci(&mci_data); ++ s3c24xx_add_fb(&s3c24x0_fb_data); ++ s3c24xx_add_ohci(); + armlinux_set_bootparams((void*)S3C_SDRAM_BASE + 0x100); + armlinux_set_architecture(MACH_TYPE_MINI2440); + +@@ -344,8 +341,7 @@ static int mini2440_console_init(void) + s3c_gpio_mode(GPH2_TXD0); + s3c_gpio_mode(GPH3_RXD0); + +- add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE, +- S3C_UART1_SIZE, IORESOURCE_MEM, NULL); ++ s3c24xx_add_uart1(); + return 0; + } + +diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c +index 173892a..ccc0510 100644 +--- a/arch/arm/boards/nhk8815/setup.c ++++ b/arch/arm/boards/nhk8815/setup.c +@@ -55,15 +55,15 @@ static struct nomadik_nand_platform_data nhk8815_nand_data = { + static struct resource nhk8815_nand_resources[] = { + { + .start = NAND_IO_ADDR, +- .size = 0xfff, ++ .end = NAND_IO_ADDR + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = NAND_IO_CMD, +- .size = 0xfff, ++ .end = NAND_IO_CMD + 0xfff, + .flags = IORESOURCE_MEM, + }, { + .start = NAND_IO_DATA, +- .size = 0xfff, ++ .end = NAND_IO_CMD + 0xfff, + .flags = IORESOURCE_MEM, + } + }; +diff --git a/arch/arm/boards/pcm038/pcm970.c b/arch/arm/boards/pcm038/pcm970.c +index ca10afb..df9b852 100644 +--- a/arch/arm/boards/pcm038/pcm970.c ++++ b/arch/arm/boards/pcm038/pcm970.c +@@ -55,7 +55,7 @@ static void pcm970_usbh2_init(void) + static struct resource pcm970_ide_resources[] = { + { + .start = IMX_PCMCIA_MEM_BASE, +- .size = SZ_1K, ++ .end = IMX_PCMCIA_MEM_BASE + SZ_1K - 1, + .flags = IORESOURCE_MEM, + }, + }; +diff --git a/arch/arm/configs/at91sam9m10g45ek_defconfig b/arch/arm/configs/at91sam9m10g45ek_defconfig +index b72e964..e22f80a 100644 +--- a/arch/arm/configs/at91sam9m10g45ek_defconfig ++++ b/arch/arm/configs/at91sam9m10g45ek_defconfig +@@ -1,5 +1,4 @@ + CONFIG_ARCH_AT91SAM9G45=y +-CONFIG_MACH_AT91SAM9M10G45EK=y + CONFIG_AEABI=y + # CONFIG_CMD_ARM_CPUINFO is not set + CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +@@ -75,3 +74,4 @@ CONFIG_LED_TRIGGERS=y + CONFIG_FS_FAT=y + CONFIG_FS_FAT_WRITE=y + CONFIG_FS_FAT_LFN=y ++CONFIG_LZO_DECOMPRESS=y +diff --git a/arch/arm/configs/ccmx51_defconfig b/arch/arm/configs/ccmx51_defconfig +new file mode 100644 +index 0000000..d14de55 +--- /dev/null ++++ b/arch/arm/configs/ccmx51_defconfig +@@ -0,0 +1,55 @@ ++CONFIG_ARCH_IMX=y ++CONFIG_ARCH_IMX51=y ++CONFIG_MACH_CCMX51=y ++CONFIG_AEABI=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_MALLOC_SIZE=0x2000000 ++CONFIG_LONGHELP=y ++CONFIG_GLOB=y ++CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/ccxmx51/env" ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MTEST=y ++CONFIG_CMD_FLASH=y ++CONFIG_CMD_BOOTM_ZLIB=y ++CONFIG_CMD_BOOTM_BZLIB=y ++CONFIG_CMD_BOOTM_SHOW_TYPE=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_UNLZO=y ++CONFIG_CMD_I2C=y ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++CONFIG_DRIVER_NET_SMC911X=y ++CONFIG_DRIVER_NET_FEC_IMX=y ++CONFIG_DRIVER_SPI_IMX=y ++CONFIG_I2C=y ++CONFIG_I2C_IMX=y ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_NAND_IMX=y ++CONFIG_USB=y ++CONFIG_USB_EHCI=y ++CONFIG_MCI=y ++# CONFIG_MCI_WRITE is not set ++CONFIG_MCI_IMX_ESDHC=y ++CONFIG_FS_CRAMFS=y ++CONFIG_FS_FAT=y ++CONFIG_FS_FAT_LFN=y +diff --git a/arch/arm/configs/eukrea_cpuimx25_defconfig b/arch/arm/configs/eukrea_cpuimx25_defconfig +index 94ae670..f7207e8 100644 +--- a/arch/arm/configs/eukrea_cpuimx25_defconfig ++++ b/arch/arm/configs/eukrea_cpuimx25_defconfig +@@ -8,6 +8,7 @@ CONFIG_MMU=y + CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 + CONFIG_MALLOC_SIZE=0x800000 + CONFIG_EXPERIMENTAL=y ++CONFIG_MALLOC_TLSF=y + CONFIG_LONGHELP=y + CONFIG_GLOB=y + CONFIG_HUSH_FANCY_PROMPT=y +diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig +index a888765..880beb6 100644 +--- a/arch/arm/configs/eukrea_cpuimx35_defconfig ++++ b/arch/arm/configs/eukrea_cpuimx35_defconfig +@@ -9,6 +9,7 @@ CONFIG_MMU=y + CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 + CONFIG_MALLOC_SIZE=0x800000 + CONFIG_EXPERIMENTAL=y ++CONFIG_MALLOC_TLSF=y + CONFIG_LONGHELP=y + CONFIG_GLOB=y + CONFIG_HUSH_FANCY_PROMPT=y +diff --git a/arch/arm/configs/eukrea_cpuimx51_defconfig b/arch/arm/configs/eukrea_cpuimx51_defconfig +index f6fd7bc..7261796 100644 +--- a/arch/arm/configs/eukrea_cpuimx51_defconfig ++++ b/arch/arm/configs/eukrea_cpuimx51_defconfig +@@ -7,6 +7,7 @@ CONFIG_MMU=y + CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 + CONFIG_MALLOC_SIZE=0x2000000 + CONFIG_EXPERIMENTAL=y ++CONFIG_MALLOC_TLSF=y + CONFIG_LONGHELP=y + CONFIG_GLOB=y + CONFIG_HUSH_FANCY_PROMPT=y +diff --git a/arch/arm/configs/usb_a9260_defconfig b/arch/arm/configs/usb_a9260_defconfig +index 85e7878..a9574c4 100644 +--- a/arch/arm/configs/usb_a9260_defconfig ++++ b/arch/arm/configs/usb_a9260_defconfig +@@ -6,6 +6,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y + CONFIG_MMU=y + CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 + CONFIG_EXPERIMENTAL=y ++CONFIG_MALLOC_TLSF=y + CONFIG_PROMPT="USB-9G20:" + CONFIG_LONGHELP=y + CONFIG_GLOB=y +diff --git a/arch/arm/configs/usb_a9263_128mib_defconfig b/arch/arm/configs/usb_a9263_128mib_defconfig +index 23bc3d7..d31057f 100644 +--- a/arch/arm/configs/usb_a9263_128mib_defconfig ++++ b/arch/arm/configs/usb_a9263_128mib_defconfig +@@ -1,12 +1,13 @@ + CONFIG_ARCH_AT91SAM9263=y + CONFIG_MACH_USB_A9263=y ++CONFIG_AT91_HAVE_SRAM_128M=y + CONFIG_AEABI=y + # CONFIG_CMD_ARM_CPUINFO is not set +-CONFIG_AT91_HAVE_SRAM_128M=y + CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y + CONFIG_MMU=y + CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 + CONFIG_EXPERIMENTAL=y ++CONFIG_MALLOC_TLSF=y + CONFIG_PROMPT="USB-9263:" + CONFIG_LONGHELP=y + CONFIG_GLOB=y +diff --git a/arch/arm/configs/usb_a9263_defconfig b/arch/arm/configs/usb_a9263_defconfig +index 96ea3e1..b57c300 100644 +--- a/arch/arm/configs/usb_a9263_defconfig ++++ b/arch/arm/configs/usb_a9263_defconfig +@@ -6,6 +6,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y + CONFIG_MMU=y + CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 + CONFIG_EXPERIMENTAL=y ++CONFIG_MALLOC_TLSF=y + CONFIG_PROMPT="USB-9263:" + CONFIG_LONGHELP=y + CONFIG_GLOB=y +@@ -22,7 +23,6 @@ CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/usb-a926x/env" + CONFIG_CMD_EDIT=y + CONFIG_CMD_SLEEP=y + CONFIG_CMD_SAVEENV=y +-CONFIG_CMD_LOADENV=y + CONFIG_CMD_EXPORT=y + CONFIG_CMD_PRINTENV=y + CONFIG_CMD_READLINE=y +diff --git a/arch/arm/configs/usb_a9g20_128mib_defconfig b/arch/arm/configs/usb_a9g20_128mib_defconfig +index c25d7de..6b02342 100644 +--- a/arch/arm/configs/usb_a9g20_128mib_defconfig ++++ b/arch/arm/configs/usb_a9g20_128mib_defconfig +@@ -1,12 +1,13 @@ + CONFIG_ARCH_AT91SAM9G20=y + CONFIG_MACH_USB_A9G20=y ++CONFIG_AT91_HAVE_SRAM_128M=y + CONFIG_AEABI=y + # CONFIG_CMD_ARM_CPUINFO is not set +-CONFIG_AT91_HAVE_SRAM_128M=y + CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y + CONFIG_MMU=y + CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 + CONFIG_EXPERIMENTAL=y ++CONFIG_MALLOC_TLSF=y + CONFIG_PROMPT="USB-9G20:" + CONFIG_LONGHELP=y + CONFIG_GLOB=y +diff --git a/arch/arm/configs/usb_a9g20_defconfig b/arch/arm/configs/usb_a9g20_defconfig +index d645adb..30bf380 100644 +--- a/arch/arm/configs/usb_a9g20_defconfig ++++ b/arch/arm/configs/usb_a9g20_defconfig +@@ -6,6 +6,7 @@ CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y + CONFIG_MMU=y + CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40000 + CONFIG_EXPERIMENTAL=y ++CONFIG_MALLOC_TLSF=y + CONFIG_PROMPT="USB-9G20:" + CONFIG_LONGHELP=y + CONFIG_GLOB=y +diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile +index e30ae1c..93a34a9 100644 +--- a/arch/arm/cpu/Makefile ++++ b/arch/arm/cpu/Makefile +@@ -7,6 +7,7 @@ obj-y += start.o + # Any variants can be called as start-armxyz.S + # + obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o ++obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o + obj-$(CONFIG_MMU) += mmu.o + obj-$(CONFIG_CPU_32v4T) += cache-armv4.o + obj-$(CONFIG_CPU_32v5) += cache-armv5.o +diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c +index c19f931..607f357 100644 +--- a/arch/arm/cpu/mmu.c ++++ b/arch/arm/cpu/mmu.c +@@ -147,7 +147,7 @@ static int arm_mmu_remap_sdram(struct memory_bank *bank) + if ((phys & (SZ_1M - 1)) || (bank->size & (SZ_1M - 1))) + return -EINVAL; + +- ptes = memalign(0x400, num_ptes * sizeof(u32)); ++ ptes = memalign(PAGE_SIZE, num_ptes * sizeof(u32)); + + debug("ptes: 0x%p ttb_start: 0x%08lx ttb_end: 0x%08lx\n", + ptes, ttb_start, ttb_end); +@@ -165,6 +165,9 @@ static int arm_mmu_remap_sdram(struct memory_bank *bank) + pte += 256; + } + ++ dma_flush_range((unsigned long)ttb, (unsigned long)ttb + 0x4000); ++ dma_flush_range((unsigned long)ptes, num_ptes * sizeof(u32)); ++ + tlb_invalidate(); + + return 0; +@@ -299,11 +302,9 @@ void *dma_alloc_coherent(size_t size) + size = PAGE_ALIGN(size); + ret = xmemalign(4096, size); + +-#ifdef CONFIG_MMU + dma_inv_range((unsigned long)ret, (unsigned long)ret + size); + + remap_range(ret, size, PTE_FLAGS_UNCACHED); +-#endif + + return ret; + } +@@ -320,9 +321,7 @@ void *phys_to_virt(unsigned long phys) + + void dma_free_coherent(void *mem, size_t size) + { +-#ifdef CONFIG_MMU + remap_range(mem, size, PTE_FLAGS_CACHED); +-#endif + + free(mem); + } +diff --git a/arch/arm/cpu/mmuinfo.c b/arch/arm/cpu/mmuinfo.c +new file mode 100644 +index 0000000..6bea34e +--- /dev/null ++++ b/arch/arm/cpu/mmuinfo.c +@@ -0,0 +1,111 @@ ++/* ++ * mmuinfo.c - Show MMU/cache information from cp15 registers ++ * ++ * Copyright (c) Jan Luebbe , Pengutronix ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++static char *inner_attr[] = { ++ "0b000 Non-cacheable", ++ "0b001 Strongly-ordered", ++ "0b010 (reserved)", ++ "0b011 Device", ++ "0b100 (reserved)", ++ "0b101 Write-Back, Write-Allocate", ++ "0b110 Write-Through", ++ "0b111 Write-Back, no Write-Allocate", ++}; ++ ++static char *outer_attr[] = { ++ "0b00 Non-cacheable", ++ "0b01 Write-Back, Write-Allocate", ++ "0b10 Write-Through, no Write-Allocate", ++ "0b11 Write-Back, no Write-Allocate", ++}; ++ ++static void decode_par(unsigned long par) ++{ ++ printf(" Physical Address [31:12]: 0x%08lx\n", par & 0xFFFFF000); ++ printf(" Reserved [11]: 0x%lx\n", (par >> 11) & 0x1); ++ printf(" Not Outer Shareable [10]: 0x%lx\n", (par >> 10) & 0x1); ++ printf(" Non-Secure [9]: 0x%lx\n", (par >> 9) & 0x1); ++ printf(" Impl. def. [8]: 0x%lx\n", (par >> 8) & 0x1); ++ printf(" Shareable [7]: 0x%lx\n", (par >> 7) & 0x1); ++ printf(" Inner mem. attr. [6:4]: 0x%lx (%s)\n", (par >> 4) & 0x7, ++ inner_attr[(par >> 4) & 0x7]); ++ printf(" Outer mem. attr. [3:2]: 0x%lx (%s)\n", (par >> 2) & 0x3, ++ outer_attr[(par >> 2) & 0x3]); ++ printf(" SuperSection [1]: 0x%lx\n", (par >> 1) & 0x1); ++ printf(" Failure [0]: 0x%lx\n", (par >> 0) & 0x1); ++} ++ ++static int do_mmuinfo(int argc, char *argv[]) ++{ ++ unsigned long addr = 0, priv_read, priv_write; ++ ++ if (argc < 2) ++ return COMMAND_ERROR_USAGE; ++ ++ addr = strtoul_suffix(argv[1], NULL, 0); ++ ++ __asm__ __volatile__( ++ "mcr p15, 0, %0, c7, c8, 0 @ write VA to PA translation (priv read)\n" ++ : ++ : "r" (addr) ++ : "memory"); ++ ++ __asm__ __volatile__( ++ "mrc p15, 0, %0, c7, c4, 0 @ read PAR\n" ++ : "=r" (priv_read) ++ : ++ : "memory"); ++ ++ __asm__ __volatile__( ++ "mcr p15, 0, %0, c7, c8, 1 @ write VA to PA translation (priv write)\n" ++ : ++ : "r" (addr) ++ : "memory"); ++ ++ __asm__ __volatile__( ++ "mrc p15, 0, %0, c7, c4, 0 @ read PAR\n" ++ : "=r" (priv_write) ++ : ++ : "memory"); ++ ++ printf("PAR result for 0x%08lx: \n", addr); ++ printf(" privileged read: 0x%08lx\n", priv_read); ++ decode_par(priv_read); ++ printf(" privileged write: 0x%08lx\n", priv_write); ++ decode_par(priv_write); ++ ++ return 0; ++} ++ ++BAREBOX_CMD_HELP_START(mmuinfo) ++BAREBOX_CMD_HELP_USAGE("mmuinfo
\n") ++BAREBOX_CMD_HELP_SHORT("Show MMU/cache information for an address.\n") ++BAREBOX_CMD_HELP_END ++ ++BAREBOX_CMD_START(mmuinfo) ++ .cmd = do_mmuinfo, ++ .usage = "mmuinfo
", ++ BAREBOX_CMD_HELP(cmd_mmuinfo_help) ++BAREBOX_CMD_END +diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c +index 3c282ee..523179d 100644 +--- a/arch/arm/cpu/start.c ++++ b/arch/arm/cpu/start.c +@@ -81,13 +81,11 @@ void __naked __bare_init reset(void) + r &= ~(CR_M | CR_C | CR_B | CR_S | CR_R | CR_V); + r |= CR_I; + +- if (!(r & CR_U)) +- /* catch unaligned access on architectures which do not +- * support unaligned access */ +- r |= CR_A; +- else +- r &= ~CR_A; +- ++#if __LINUX_ARM_ARCH__ >= 6 ++ r |= CR_U; ++#else ++ r |= CR_A; ++#endif + + #ifdef __ARMEB__ + r |= CR_B; +diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h +new file mode 100644 +index 0000000..cb9cd1b +--- /dev/null ++++ b/arch/arm/include/asm/dma.h +@@ -0,0 +1,8 @@ ++/* ++ * Copyright (C) 2012 by Marc Kleine-Budde ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#include +diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h +index f5ae7a8..a66da8c 100644 +--- a/arch/arm/include/asm/mmu.h ++++ b/arch/arm/include/asm/mmu.h +@@ -1,9 +1,12 @@ + #ifndef __ASM_MMU_H + #define __ASM_MMU_H + +-#include +-#include ++#include + #include ++#include ++#include ++ ++#include + + #define PMD_SECT_DEF_UNCACHED (PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT) + #define PMD_SECT_DEF_CACHED (PMD_SECT_WB | PMD_SECT_DEF_UNCACHED) +@@ -23,6 +26,12 @@ static inline void setup_dma_coherent(unsigned long offset) + { + } + ++#define dma_alloc dma_alloc ++static inline void *dma_alloc(size_t size) ++{ ++ return xmemalign(64, ALIGN(size, 64)); ++} ++ + #ifdef CONFIG_MMU + void *dma_alloc_coherent(size_t size); + void dma_free_coherent(void *mem, size_t size); +diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c +index 033e2eb..3a00437 100644 +--- a/arch/arm/lib/bootm.c ++++ b/arch/arm/lib/bootm.c +@@ -80,7 +80,7 @@ static int __do_bootm_linux(struct image_data *data, int swap) + + if (data->initrd_res) { + initrd_start = data->initrd_res->start; +- initrd_size = data->initrd_res->size; ++ initrd_size = resource_size(data->initrd_res); + } + + if (bootm_verbose(data)) { +@@ -154,7 +154,7 @@ static int do_bootz_linux_fdt(int fd, struct image_data *data) + } + } else { + +- of_res = request_sdram_region("oftree", r->start + r->size, end); ++ of_res = request_sdram_region("oftree", r->start + resource_size(r), end); + if (!of_res) { + perror("zImage: oftree request_sdram_region"); + return -ENOMEM; +@@ -310,9 +310,9 @@ static int aimage_load_resource(int fd, struct resource *r, void* buf, int ps) + { + int ret; + void *image = (void *)r->start; +- unsigned to_read = ps - r->size % ps; ++ unsigned to_read = ps - resource_size(r) % ps; + +- ret = read_full(fd, image, r->size); ++ ret = read_full(fd, image, resource_size(r)); + if (ret < 0) + return ret; + +diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c +index 3297a89..b56ca14 100644 +--- a/arch/arm/mach-at91/at91sam9260_devices.c ++++ b/arch/arm/mach-at91/at91sam9260_devices.c +@@ -111,12 +111,12 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) {} + static struct resource nand_resources[] = { + [0] = { + .start = AT91_CHIPSELECT_3, +- .size = SZ_256M, ++ .end = AT91_CHIPSELECT_3 + SZ_256M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_BASE_SYS + AT91_ECC, +- .size = 512, ++ .end = AT91_BASE_SYS + AT91_ECC + 512 - 1, + .flags = IORESOURCE_MEM, + } + }; +diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c +index 2ebc4da..7f916d2 100644 +--- a/arch/arm/mach-at91/at91sam9263_devices.c ++++ b/arch/arm/mach-at91/at91sam9263_devices.c +@@ -113,12 +113,12 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) {} + static struct resource nand_resources[] = { + [0] = { + .start = AT91_CHIPSELECT_3, +- .size = SZ_256M, ++ .end = AT91_CHIPSELECT_3 + SZ_256M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_BASE_SYS + AT91_ECC0, +- .size = 512, ++ .end = AT91_BASE_SYS + AT91_ECC0 + 512 - 1, + .flags = IORESOURCE_MEM, + } + }; +diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c +index d406bcc..22b455e 100644 +--- a/arch/arm/mach-at91/at91sam9g45_devices.c ++++ b/arch/arm/mach-at91/at91sam9g45_devices.c +@@ -93,12 +93,12 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) {} + static struct resource nand_resources[] = { + [0] = { + .start = AT91_CHIPSELECT_3, +- .size = SZ_256M, ++ .end = AT91_CHIPSELECT_3 + SZ_256M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_BASE_SYS + AT91_ECC, +- .size = 512, ++ .end = AT91_BASE_SYS + AT91_ECC + 512 - 1, + .flags = IORESOURCE_MEM, + } + }; +diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c +index 50bad7f..26a380d 100644 +--- a/arch/arm/mach-at91/at91sam9x5_devices.c ++++ b/arch/arm/mach-at91/at91sam9x5_devices.c +@@ -130,12 +130,12 @@ void at91_add_device_eth(int id, struct at91_ether_platform_data *data) {} + static struct resource nand_resources[] = { + [0] = { + .start = AT91_CHIPSELECT_3, +- .size = SZ_256M, ++ .end = AT91_CHIPSELECT_3 + SZ_256M - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AT91_BASE_SYS + AT91_PMECC, +- .size = 512, ++ .end = AT91_BASE_SYS + AT91_PMECC + 512 - 1, + .flags = IORESOURCE_MEM, + } + }; +diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig +index 564e2fe..5b77245 100644 +--- a/arch/arm/mach-imx/Kconfig ++++ b/arch/arm/mach-imx/Kconfig +@@ -26,6 +26,7 @@ config ARCH_TEXT_BASE + default 0x7ff00000 if MACH_TQMA53 + default 0x97f00000 if MACH_TX51 + default 0x4fc00000 if MACH_MX6Q_ARM2 ++ default 0x97f00000 if MACH_CCMX51 + + config BOARDINFO + default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25 +@@ -50,6 +51,7 @@ config BOARDINFO + default "TQ tqma53" if MACH_TQMA53 + default "Ka-Ro tx51" if MACH_TX51 + default "Freescale i.MX6q armadillo2" if MACH_MX6Q_ARM2 ++ default "ConnectCore i.MX51" if MACH_CCMX51 + + choice + prompt "Select boot mode" +@@ -391,7 +393,7 @@ choice + prompt "i.MX51 Board Type" + + config MACH_FREESCALE_MX51_PDK +- select DEFAULT_ENVIRONMENT_GENERIC_NEW ++ select HAVE_DEFAULT_ENVIRONMENT_NEW + bool "Freescale i.MX51 PDK" + + config MACH_EUKREA_CPUIMX51SD +@@ -405,6 +407,23 @@ config MACH_TX51 + help + Say Y here if you are using the Ka-Ro tx51 board + ++config MACH_CCMX51 ++ bool "ConnectCore i.MX51" ++ select IMX_IIM ++ select SPI ++ select DRIVER_SPI_IMX ++ select MFD_MC13XXX ++ help ++ Say Y here if you are using Digi ConnectCore (W)i-i.MX51 ++ equipped with a Freescale i.MX51 Processor ++ ++config MACH_CCMX51_BASEBOARD ++ bool "Digi development board for CCMX51 module" ++ depends on MACH_CCMX51 ++ default y ++ help ++ This adds board specific devices that can be found on Digi ++ evaluation board for CCMX51 module. + + endchoice + +@@ -517,7 +536,7 @@ menu "i.MX specific settings " + + config IMX_CLKO + bool "clko command" +- depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX35 || ARCH_IMX25 ++ depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX35 || ARCH_IMX25 || ARCH_IMX51 + help + The i.MX SoCs have a Pin which can output different reference frequencies. + Say y here if you want to have the clko command which lets you select the +diff --git a/arch/arm/mach-imx/clko.c b/arch/arm/mach-imx/clko.c +index 0e4fbcc..aeafaa9 100644 +--- a/arch/arm/mach-imx/clko.c ++++ b/arch/arm/mach-imx/clko.c +@@ -6,15 +6,18 @@ + + static int do_clko(int argc, char *argv[]) + { +- int opt, div = 0, src = -2, ret; ++ int opt, div = 0, src = -2, num = 1, ret; + +- while((opt = getopt(argc, argv, "d:s:")) > 0) { ++ while((opt = getopt(argc, argv, "n:d:s:")) > 0) { + switch(opt) { ++ case 'n': ++ num = simple_strtoul(optarg, NULL, 0); ++ break; + case 'd': + div = simple_strtoul(optarg, NULL, 0); + break; + case 's': +- src = simple_strtoul(optarg, NULL, 0); ++ src = simple_strtol(optarg, NULL, 0); + break; + } + } +@@ -23,17 +26,19 @@ static int do_clko(int argc, char *argv[]) + return COMMAND_ERROR_USAGE; + + if (src == -1) { +- imx_clko_set_src(-1); ++ imx_clko_set_src(num, -1); + return 0; + } + + if (src != -2) +- imx_clko_set_src(src); ++ imx_clko_set_src(num, src); + + if (div != 0) { +- ret = imx_clko_set_div(div); +- if (ret != div) +- printf("limited divider to %d\n", ret); ++ ret = imx_clko_set_div(num, div); ++ if (ret < 0) ++ printf("CLKO-line %i not supported.\n", num); ++ else if (ret != div) ++ printf("Divider limited to %d.\n", ret); + } + + return 0; +@@ -42,7 +47,8 @@ static int do_clko(int argc, char *argv[]) + static __maybe_unused char cmd_clko_help[] = + "Usage: clko [OPTION]...\n" + "Route different signals to the i.MX clko pin\n" +-" -d
Divider\n" ++" -n Number of CLKO-line (Default 1)\n" ++" -d
Divider\n" + " -s Clock select. See Ref. Manual for valid sources. Use -1\n" + " for disabling clock output\n"; + +diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c +index 4f5895c..4e77ece 100644 +--- a/arch/arm/mach-imx/clocksource.c ++++ b/arch/arm/mach-imx/clocksource.c +@@ -38,7 +38,7 @@ + #include + + #define GPT(x) __REG(IMX_TIM1_BASE + (x)) +-#define timer_base (IMX_TIM1_BASE) ++#define timer_base IOMEM(IMX_TIM1_BASE) + + static uint64_t imx_clocksource_read(void) + { +@@ -120,15 +120,17 @@ core_initcall(clocksource_init); + */ + void __noreturn reset_cpu (unsigned long addr) + { ++ void __iomem *wdt = IOMEM(IMX_WDT_BASE); ++ + /* Disable watchdog and set Time-Out field to 0 */ +- writew(0x0, IMX_WDT_BASE + WDOG_WCR); ++ writew(0x0, wdt + WDOG_WCR); + + /* Write Service Sequence */ +- writew(0x5555, IMX_WDT_BASE + WDOG_WSR); +- writew(0xaaaa, IMX_WDT_BASE + WDOG_WSR); ++ writew(0x5555, wdt + WDOG_WSR); ++ writew(0xaaaa, wdt + WDOG_WSR); + + /* Enable watchdog */ +- writew(WDOG_WCR_WDE, IMX_WDT_BASE + WDOG_WCR); ++ writew(WDOG_WCR_WDE, wdt + WDOG_WCR); + + while (1); + /*NOTREACHED*/ +diff --git a/arch/arm/mach-imx/iim.c b/arch/arm/mach-imx/iim.c +index f2ace8a..0da8ea0 100644 +--- a/arch/arm/mach-imx/iim.c ++++ b/arch/arm/mach-imx/iim.c +@@ -84,7 +84,7 @@ static int do_fuse_sense(void __iomem *reg_base, unsigned int bank, + } + + static ssize_t imx_iim_cdev_read(struct cdev *cdev, void *buf, size_t count, +- ulong offset, ulong flags) ++ loff_t offset, ulong flags) + { + ulong size, i; + struct iim_priv *priv = cdev->priv; +@@ -94,7 +94,7 @@ static ssize_t imx_iim_cdev_read(struct cdev *cdev, void *buf, size_t count, + if ((sense_param = dev_get_param(cdev->dev, "explicit_sense_enable"))) + explicit_sense = simple_strtoul(sense_param, NULL, 0); + +- size = min((ulong)count, priv->banksize - offset); ++ size = min((loff_t)count, priv->banksize - offset); + if (explicit_sense) { + for (i = 0; i < size; i++) { + int row_val; +@@ -176,7 +176,7 @@ out: + #endif /* CONFIG_IMX_IIM_FUSE_BLOW */ + + static ssize_t imx_iim_cdev_write(struct cdev *cdev, const void *buf, size_t count, +- ulong offset, ulong flags) ++ loff_t offset, ulong flags) + { + ulong size, i; + struct iim_priv *priv = cdev->priv; +@@ -186,7 +186,7 @@ static ssize_t imx_iim_cdev_write(struct cdev *cdev, const void *buf, size_t cou + if ((write_param = dev_get_param(cdev->dev, "permanent_write_enable"))) + blow_enable = simple_strtoul(write_param, NULL, 0); + +- size = min((ulong)count, priv->banksize - offset); ++ size = min((loff_t)count, priv->banksize - offset); + #ifdef CONFIG_IMX_IIM_FUSE_BLOW + if (blow_enable) { + for (i = 0; i < size; i++) { +diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h +index 1082178..050b7f8 100644 +--- a/arch/arm/mach-imx/include/mach/clock.h ++++ b/arch/arm/mach-imx/include/mach/clock.h +@@ -30,9 +30,11 @@ ulong imx_get_lcdclk(void); + ulong imx_get_i2cclk(void); + ulong imx_get_mmcclk(void); + ulong imx_get_cspiclk(void); ++ulong imx_get_ipgclk(void); ++ulong imx_get_usbclk(void); + +-int imx_clko_set_div(int div); +-void imx_clko_set_src(int src); ++int imx_clko_set_div(int num, int div); ++void imx_clko_set_src(int num, int src); + + void imx_dump_clocks(void); + +diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h +index 5de0fa7..dbf5862 100644 +--- a/arch/arm/mach-imx/include/mach/devices-imx51.h ++++ b/arch/arm/mach-imx/include/mach/devices-imx51.h +@@ -67,11 +67,11 @@ static inline struct device_d *imx51_add_nand(struct imx_nand_platform_data *pda + struct resource res[] = { + { + .start = MX51_NFC_BASE_ADDR, +- .size = SZ_4K, ++ .end = MX51_NFC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX51_NFC_AXI_BASE_ADDR, +- .size = SZ_4K, ++ .end = MX51_NFC_AXI_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; +diff --git a/arch/arm/mach-imx/include/mach/devices-imx53.h b/arch/arm/mach-imx/include/mach/devices-imx53.h +index a9fe454..0fc4b5c 100644 +--- a/arch/arm/mach-imx/include/mach/devices-imx53.h ++++ b/arch/arm/mach-imx/include/mach/devices-imx53.h +@@ -61,11 +61,11 @@ static inline struct device_d *imx53_add_nand(struct imx_nand_platform_data *pda + struct resource res[] = { + { + .start = MX53_NFC_BASE_ADDR, +- .size = SZ_4K, ++ .end = MX53_NFC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, { + .start = MX53_NFC_AXI_BASE_ADDR, +- .size = SZ_4K, ++ .end = MX53_NFC_AXI_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + }; +diff --git a/arch/arm/mach-imx/include/mach/iomux-mx51.h b/arch/arm/mach-imx/include/mach/iomux-mx51.h +index c7f5169..36c8989 100644 +--- a/arch/arm/mach-imx/include/mach/iomux-mx51.h ++++ b/arch/arm/mach-imx/include/mach/iomux-mx51.h +@@ -256,13 +256,13 @@ + #define MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL) +-#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) ++#define MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) + #define MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) + #define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2) + #define MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL) +-#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) +@@ -270,7 +270,7 @@ + #define MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x9f8, 0, NO_PAD_CTRL) +-#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 0x17, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x998, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) +@@ -283,13 +283,13 @@ + #define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) +-#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 0x17, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5) + #define MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) +-#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 0x17, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5) + #define MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, __NA_, 0, NO_PAD_CTRL) +@@ -316,7 +316,7 @@ + #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_PAD_CTRL_4) + #define MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x938, 0, NO_PAD_CTRL) +-#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL) ++#define MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL) + #define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL) + #define MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, __NA_, 0, NO_PAD_CTRL) +@@ -672,23 +672,23 @@ + #define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, __NA_, 0, MX51_PAD_CTRL_5) +-#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x9d0, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0xa24, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, __NA_, 0, MX51_PAD_CTRL_5) +-#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x9d4, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0xa20, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, __NA_, 0, MX51_PAD_CTRL_5) +-#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x9d8, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x9fc, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x8f4, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, __NA_, 0, MX51_PAD_CTRL_5) +-#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0xa00, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, __NA_, 0, NO_PAD_CTRL) +@@ -698,7 +698,7 @@ + #define MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x8f0, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x968, 1, NO_PAD_CTRL) +-#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0xa08, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x8ec, 1, NO_PAD_CTRL) + #define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, __NA_, 0, NO_PAD_CTRL) +@@ -746,16 +746,16 @@ + #define MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x920, 1, MX51_ECSPI_PAD_CTRL) + #define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) + #define MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x924, 0, MX51_ECSPI_PAD_CTRL) +-#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) + #define MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL) +-#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL) + #define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(__NA_, 0x04c, 0, 0x000, 0, NO_PAD_CTRL) + #define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(__NA_, 0x050, 0, 0x000, 0, NO_PAD_CTRL) + #define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(__NA_, 0x054, 0, 0x000, 0, NO_PAD_CTRL) + #define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(__NA_, 0x058, 0, 0x000, 0, NO_PAD_CTRL) +-#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(__NA_, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) ++#define MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x7bc, 0x3b4, 2, 0x91c, 3, MX51_ECSPI_PAD_CTRL) + #define MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x9b0, 2, MX51_I2C_PAD_CTRL) + #define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) + #define MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x914, 3, MX51_ECSPI_PAD_CTRL) +@@ -766,19 +766,19 @@ + #define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) + #define MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +-#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 0x12, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) +-#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 0x12, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x924, 1, MX51_ECSPI_PAD_CTRL) + #define MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL) + #define MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, __NA_, 0, NO_PAD_CTRL) +-#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x9b8, 3, MX51_I2C_PAD_CTRL) + #define MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x90c, 1, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL) +-#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL) + #define MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL) +@@ -786,27 +786,27 @@ + #define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL) +-#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL) +-#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL) +-#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL) +-#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) + #define MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL) +-#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL) + #define MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL) +-#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL) + #define MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL) + #define MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL) + +diff --git a/arch/arm/mach-imx/speed-imx21.c b/arch/arm/mach-imx/speed-imx21.c +index 6ab1dca..4729583 100644 +--- a/arch/arm/mach-imx/speed-imx21.c ++++ b/arch/arm/mach-imx/speed-imx21.c +@@ -16,6 +16,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -162,9 +163,13 @@ void imx_dump_clocks(void) + * Returns the new divider (which may be smaller + * than the desired one) + */ +-int imx_clko_set_div(int div) ++int imx_clko_set_div(int num, int div) + { + ulong pcdr; ++ ++ if (num != 1) ++ return -ENODEV; ++ + div--; + div &= 0x7; + +@@ -178,11 +183,11 @@ int imx_clko_set_div(int div) + /* + * Set the clock source for the CLKO pin + */ +-void imx_clko_set_src(int src) ++void imx_clko_set_src(int num, int src) + { + unsigned long ccsr; + +- if (src < 0) { ++ if (src < 0 || num != 1) { + return; + } + +diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c +index f6dcacb..ed14113 100644 +--- a/arch/arm/mach-imx/speed-imx25.c ++++ b/arch/arm/mach-imx/speed-imx25.c +@@ -1,4 +1,5 @@ + #include ++#include + #include + #include + #include +@@ -111,10 +112,13 @@ void imx_dump_clocks(void) + * the new divider (which may be smaller + * than the desired one) + */ +-int imx_clko_set_div(int div) ++int imx_clko_set_div(int num, int div) + { + unsigned long mcr = readl(IMX_CCM_BASE + 0x64); + ++ if (num != 1) ++ return -ENODEV; ++ + div -= 1; + div &= 0x3f; + +@@ -129,10 +133,13 @@ int imx_clko_set_div(int div) + /* + * Set the clock source for the CLKO pin + */ +-void imx_clko_set_src(int src) ++void imx_clko_set_src(int num, int src) + { + unsigned long mcr = readl(IMX_CCM_BASE + 0x64); + ++ if (num != 1) ++ return; ++ + if (src < 0) { + mcr &= ~(1 << 30); + writel(mcr, IMX_CCM_BASE + 0x64); +diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c +index aba5097..644fd04 100644 +--- a/arch/arm/mach-imx/speed-imx27.c ++++ b/arch/arm/mach-imx/speed-imx27.c +@@ -16,6 +16,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -189,9 +190,13 @@ void imx_dump_clocks(void) + * the new divider (which may be smaller + * than the desired one) + */ +-int imx_clko_set_div(int div) ++int imx_clko_set_div(int num, int div) + { + ulong pcdr; ++ ++ if (num != 1) ++ return -ENODEV; ++ + div--; + div &= 0x7; + +@@ -205,10 +210,13 @@ int imx_clko_set_div(int div) + /* + * Set the clock source for the CLKO pin + */ +-void imx_clko_set_src(int src) ++void imx_clko_set_src(int num, int src) + { + unsigned long ccsr; + ++ if (num != 1) ++ return; ++ + if (src < 0) { + PCDR0 &= ~(1 << 25); + return; +diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c +index 1e1c39f..684dc14 100644 +--- a/arch/arm/mach-imx/speed-imx35.c ++++ b/arch/arm/mach-imx/speed-imx35.c +@@ -16,6 +16,7 @@ + */ + + #include ++#include + #include + #include + #include +@@ -84,7 +85,7 @@ unsigned long imx_get_ahbclk(void) + return fref / aad->ahb; + } + +-static unsigned long imx_get_ipgclk(void) ++unsigned long imx_get_ipgclk(void) + { + ulong clk = imx_get_ahbclk(); + +@@ -203,10 +204,13 @@ void imx_dump_clocks(void) + * the new divider (which may be smaller + * than the desired one) + */ +-int imx_clko_set_div(int div) ++int imx_clko_set_div(int num, int div) + { + unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR); + ++ if (num != 1) ++ return -ENODEV; ++ + div -= 1; + div &= 0x3f; + +@@ -221,10 +225,13 @@ int imx_clko_set_div(int div) + /* + * Set the clock source for the CLKO pin + */ +-void imx_clko_set_src(int src) ++void imx_clko_set_src(int num, int src) + { + unsigned long cosr = readl(IMX_CCM_BASE + CCM_COSR); + ++ if (num != 1) ++ return; ++ + if (src < 0) { + cosr &= ~(1 << 5); + writel(cosr, IMX_CCM_BASE + CCM_COSR); +diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c +index 8d1ecf3..87fbc75 100644 +--- a/arch/arm/mach-imx/speed-imx51.c ++++ b/arch/arm/mach-imx/speed-imx51.c +@@ -1,12 +1,19 @@ + #include + #include + #include ++#include + #include ++#include + #include + + static u32 ccm_readl(u32 ofs) + { +- return readl(MX51_CCM_BASE_ADDR + ofs); ++ return readl(IOMEM(MX51_CCM_BASE_ADDR) + ofs); ++} ++ ++static void ccm_writel(u32 val, u32 ofs) ++{ ++ writel(val, MX51_CCM_BASE_ADDR + ofs); + } + + static unsigned long ckil_get_rate(void) +@@ -142,7 +149,7 @@ unsigned long imx_get_uartclk(void) + return parent_rate / (prediv * podf); + } + +-static unsigned long imx_get_ahbclk(void) ++unsigned long imx_get_ahbclk(void) + { + u32 reg, div; + +@@ -221,6 +228,70 @@ unsigned long imx_get_usbclk(void) + return rate / (prediv * podf); + } + ++/* ++ * Set the divider of the CLKO pin. Returns ++ * the new divider (which may be smaller ++ * than the desired one) ++ */ ++int imx_clko_set_div(int num, int div) ++{ ++ u32 ccosr = ccm_readl(MX5_CCM_CCOSR); ++ ++ div--; ++ ++ switch (num) { ++ case 1: ++ div &= 0x7; ++ ccosr &= ~(0x7 << 4); ++ ccosr |= div << 4; ++ ccm_writel(ccosr, MX5_CCM_CCOSR); ++ break; ++ case 2: ++ div &= 0x7; ++ ccosr &= ~(0x7 << 21); ++ ccosr |= div << 21; ++ ccm_writel(ccosr, MX5_CCM_CCOSR); ++ break; ++ default: ++ return -ENODEV; ++ } ++ ++ return div + 1; ++} ++ ++/* ++ * Set the clock source for the CLKO pin ++ */ ++void imx_clko_set_src(int num, int src) ++{ ++ u32 ccosr = ccm_readl(MX5_CCM_CCOSR); ++ ++ switch (num) { ++ case 1: ++ if (src < 0) { ++ ccosr &= ~(1 << 7); ++ break; ++ } ++ ccosr &= ~0xf; ++ ccosr |= src & 0xf; ++ ccosr |= 1 << 7; ++ break; ++ case 2: ++ if (src < 0) { ++ ccosr &= ~(1 << 24); ++ break; ++ } ++ ccosr &= ~(0x1f << 16); ++ ccosr |= (src & 0x1f) << 16; ++ ccosr |= 1 << 24; ++ break; ++ default: ++ return; ++ } ++ ++ ccm_writel(ccosr, MX5_CCM_CCOSR); ++} ++ + void imx_dump_clocks(void) + { + printf("pll1: %ld\n", pll1_main_get_rate()); +diff --git a/arch/arm/mach-imx/speed-imx53.c b/arch/arm/mach-imx/speed-imx53.c +index 634341e..653dae3 100644 +--- a/arch/arm/mach-imx/speed-imx53.c ++++ b/arch/arm/mach-imx/speed-imx53.c +@@ -2,6 +2,7 @@ + #include + #include + #include ++#include + #include "mach/clock-imx51_53.h" + + static u32 ccm_readl(u32 ofs) +@@ -139,7 +140,7 @@ unsigned long imx_get_uartclk(void) + return parent_rate / (prediv * podf); + } + +-static unsigned long imx_get_ahbclk(void) ++unsigned long imx_get_ahbclk(void) + { + u32 reg, div; + +diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig +index 3348a3c..746c986 100644 +--- a/arch/arm/mach-mxs/Kconfig ++++ b/arch/arm/mach-mxs/Kconfig +@@ -61,6 +61,7 @@ config MACH_TX28 + + config MACH_MX28EVK + bool "mx28-evk" ++ select MXS_OCOTP + help + Say Y here if you are using the Freescale i.MX28-EVK board + +@@ -80,6 +81,25 @@ config MXS_OCOTP + internal view). Don't use register offsets here, the SET, CLR and + TGL registers are not mapped! + ++config MXS_OCOTP_WRITABLE ++ bool "OCOTP write support" ++ depends on MXS_OCOTP ++ help ++ Enable this option to add writing to OCOTP. ++ Warning: blown bits can not be unblown. Use with care. ++ ++ Before being actually able to blow the bits, you need to explicitely ++ enable writing: ++ ocotp0.permanent_write_enable=1 ++ ++config MXS_CMD_BCB ++ depends on NAND_MXS ++ tristate "Nand bcb command" ++ help ++ To be able to boot from NAND the i.MX23/28 need a Boot Control Block ++ in flash. This option enabled the 'bcb' command which can be used to ++ generate this block during runtime. ++ + endmenu + + menu "Board specific settings " +diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile +index 172d928..fe93096 100644 +--- a/arch/arm/mach-mxs/Makefile ++++ b/arch/arm/mach-mxs/Makefile +@@ -1,5 +1,6 @@ +-obj-y += imx.o iomux-imx.o reset-imx.o ++obj-y += imx.o iomux-imx.o power.o common.o + obj-$(CONFIG_DRIVER_VIDEO_STM) += imx_lcd_clk.o +-obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o clocksource-imx23.o usb.o +-obj-$(CONFIG_ARCH_IMX28) += speed-imx28.o clocksource-imx28.o ++obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o clocksource-imx23.o usb-imx23.o soc-imx23.o ++obj-$(CONFIG_ARCH_IMX28) += speed-imx28.o clocksource-imx28.o usb-imx28.o soc-imx28.o + obj-$(CONFIG_MXS_OCOTP) += ocotp.o ++obj-$(CONFIG_MXS_CMD_BCB) += bcb.o +diff --git a/arch/arm/mach-mxs/bcb.c b/arch/arm/mach-mxs/bcb.c +new file mode 100644 +index 0000000..d0a3ddc +--- /dev/null ++++ b/arch/arm/mach-mxs/bcb.c +@@ -0,0 +1,399 @@ ++/* ++ * (C) Copyright 2011 Wolfram Sang, Pengutronix e.K. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * Based on a similar function in Karo Electronics TX28-U-Boot (flash.c). ++ * Probably written by Lothar Waßmann (like tx28.c). ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#define FCB_START_BLOCK 0 ++#define NUM_FCB_BLOCKS 1 ++#define MAX_FCB_BLOCKS 32768 ++ ++#define GPMI_TIMING0 0x00000070 ++#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xff << 16) ++#define GPMI_TIMING0_ADDRESS_SETUP_OFFSET 16 ++#define GPMI_TIMING0_DATA_HOLD_MASK (0xff << 8) ++#define GPMI_TIMING0_DATA_HOLD_OFFSET 8 ++#define GPMI_TIMING0_DATA_SETUP_MASK 0xff ++#define GPMI_TIMING0_DATA_SETUP_OFFSET 0 ++ ++#define GPMI_TIMING1 0x00000080 ++ ++#define BCH_MODE 0x00000020 ++ ++#define BCH_FLASH0LAYOUT0 0x00000080 ++#define BCH_FLASHLAYOUT0_NBLOCKS_MASK (0xff << 24) ++#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 ++#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) ++#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 ++#define BCH_FLASHLAYOUT0_ECC0_MASK (0xf << 12) ++#define BCH_FLASHLAYOUT0_ECC0_OFFSET 12 ++#define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff ++#define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0 ++ ++#define BCH_FLASH0LAYOUT1 0x00000090 ++#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) ++#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 ++#define BCH_FLASHLAYOUT1_ECCN_MASK (0xf << 12) ++#define BCH_FLASHLAYOUT1_ECCN_OFFSET 12 ++#define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff ++#define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0 ++ ++struct mx28_nand_timing { ++ u8 data_setup; ++ u8 data_hold; ++ u8 address_setup; ++ u8 dsample_time; ++ u8 nand_timing_state; ++ u8 tREA; ++ u8 tRLOH; ++ u8 tRHOH; ++}; ++ ++struct mx28_fcb { ++ u32 checksum; ++ u32 fingerprint; ++ u32 version; ++ struct mx28_nand_timing timing; ++ u32 page_data_size; ++ u32 total_page_size; ++ u32 sectors_per_block; ++ u32 number_of_nands; /* not used by ROM code */ ++ u32 total_internal_die; /* not used by ROM code */ ++ u32 cell_type; /* not used by ROM code */ ++ u32 ecc_blockn_type; ++ u32 ecc_block0_size; ++ u32 ecc_blockn_size; ++ u32 ecc_block0_type; ++ u32 metadata_size; ++ u32 ecc_blocks_per_page; ++ u32 rsrvd[6]; /* not used by ROM code */ ++ u32 bch_mode; ++ u32 boot_patch; ++ u32 patch_sectors; ++ u32 fw1_start_page; ++ u32 fw2_start_page; ++ u32 fw1_sectors; ++ u32 fw2_sectors; ++ u32 dbbt_search_area; ++ u32 bb_mark_byte; ++ u32 bb_mark_startbit; ++ u32 bb_mark_phys_offset; ++}; ++ ++struct mx28_dbbt_header { ++ u32 checksum; ++ u32 fingerprint; ++ u32 version; ++ u32 number_bb; ++ u32 number_pages; ++ u8 spare[492]; ++}; ++ ++struct mx28_dbbt { ++ u32 nand_number; ++ u32 number_bb; ++ u32 bb_num[2040 / 4]; ++}; ++ ++#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) ++#define GETBIT(v,n) (((v) >> (n)) & 0x1) ++ ++static u8 calculate_parity_13_8(u8 d) ++{ ++ u8 p = 0; ++ ++ p |= (GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 3) ^ GETBIT(d, 2)) << 0; ++ p |= (GETBIT(d, 7) ^ GETBIT(d, 5) ^ GETBIT(d, 4) ^ GETBIT(d, 2) ^ GETBIT(d, 1)) << 1; ++ p |= (GETBIT(d, 7) ^ GETBIT(d, 6) ^ GETBIT(d, 5) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 2; ++ p |= (GETBIT(d, 7) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 0)) << 3; ++ p |= (GETBIT(d, 6) ^ GETBIT(d, 4) ^ GETBIT(d, 3) ^ GETBIT(d, 2) ^ GETBIT(d, 1) ^ GETBIT(d, 0)) << 4; ++ return p; ++} ++ ++static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) ++{ ++ int i; ++ u8 *src = _src; ++ u8 *ecc = _ecc; ++ ++ for (i = 0; i < size; i++) ++ ecc[i] = calculate_parity_13_8(src[i]); ++} ++ ++static u32 calc_chksum(void *buf, size_t size) ++{ ++ u32 chksum = 0; ++ u8 *bp = buf; ++ size_t i; ++ ++ for (i = 0; i < size; i++) ++ chksum += bp[i]; ++ ++ return ~chksum; ++} ++ ++/* ++ Physical organisation of data in NAND flash: ++ metadata ++ payload chunk 0 (may be empty) ++ ecc for metadata + payload chunk 0 ++ payload chunk 1 ++ ecc for payload chunk 1 ++... ++ payload chunk n ++ ecc for payload chunk n ++ */ ++ ++static int calc_bb_offset(struct mtd_info *mtd, struct mx28_fcb *fcb) ++{ ++ int bb_mark_offset; ++ int chunk_data_size = fcb->ecc_blockn_size * 8; ++ int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13; ++ int chunk_total_size = chunk_data_size + chunk_ecc_size; ++ int bb_mark_chunk, bb_mark_chunk_offs; ++ ++ bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8; ++ if (fcb->ecc_block0_size == 0) ++ bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13; ++ ++ bb_mark_chunk = bb_mark_offset / chunk_total_size; ++ bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size); ++ if (bb_mark_chunk_offs > chunk_data_size) { ++ printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n", ++ bb_mark_chunk_offs); ++ return -EINVAL; ++ } ++ bb_mark_offset -= bb_mark_chunk * chunk_ecc_size; ++ return bb_mark_offset; ++} ++ ++static struct mx28_fcb *create_fcb(struct mtd_info *mtd, void *buf, unsigned fw1_start_block, ++ size_t fw_size, unsigned fw2_start_block) ++{ ++ u32 fl0, fl1, t0; ++ int metadata_size; ++ int bb_mark_bit_offs; ++ struct mx28_fcb *fcb; ++ int fcb_offs; ++ void __iomem *bch_regs = (void *)MXS_BCH_BASE; ++ void __iomem *gpmi_regs = (void *)MXS_GPMI_BASE; ++ ++ fl0 = readl(bch_regs + BCH_FLASH0LAYOUT0); ++ fl1 = readl(bch_regs + BCH_FLASH0LAYOUT1); ++ t0 = readl(gpmi_regs + GPMI_TIMING0); ++ metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); ++ ++ fcb = buf + ALIGN(metadata_size, 4); ++ fcb_offs = (void *)fcb - buf; ++ ++ memset(buf, 0x00, fcb_offs); ++ memset(fcb, 0x00, sizeof(*fcb)); ++ memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb)); ++ ++ strncpy((char *)&fcb->fingerprint, "FCB ", 4); ++ fcb->version = cpu_to_be32(1); ++ ++ fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP); ++ fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD); ++ fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP); ++ ++ fcb->page_data_size = mtd->writesize; ++ fcb->total_page_size = mtd->writesize + mtd->oobsize; ++ fcb->sectors_per_block = mtd->erasesize / mtd->writesize; ++ ++ fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0); ++ fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE); ++ fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN); ++ fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE); ++ ++ fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); ++ fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS); ++ fcb->bch_mode = readl(bch_regs + BCH_MODE); ++/* ++ fcb->boot_patch = 0; ++ fcb->patch_sectors = 0; ++*/ ++ fcb->fw1_start_page = fw1_start_block / mtd->writesize; ++ fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize); ++ ++ if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) { ++ fcb->fw2_start_page = fw2_start_block / mtd->writesize; ++ fcb->fw2_sectors = fcb->fw1_sectors; ++ } ++ ++ fcb->dbbt_search_area = 1; ++ ++ bb_mark_bit_offs = calc_bb_offset(mtd, fcb); ++ if (bb_mark_bit_offs < 0) ++ return ERR_PTR(bb_mark_bit_offs); ++ fcb->bb_mark_byte = bb_mark_bit_offs / 8; ++ fcb->bb_mark_startbit = bb_mark_bit_offs % 8; ++ fcb->bb_mark_phys_offset = mtd->writesize; ++ ++ fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4); ++ return fcb; ++} ++ ++static int find_fcb(struct mtd_info *mtd, void *ref, int page) ++{ ++ int ret = 0; ++ struct nand_chip *chip = mtd->priv; ++ void *buf = malloc(mtd->erasesize); ++ ++ if (buf == NULL) ++ return -ENOMEM; ++ ++ chip->select_chip(mtd, 0); ++ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); ++ ret = chip->ecc.read_page_raw(mtd, chip, buf); ++ if (ret) { ++ printf("Failed to read FCB from page %u: %d\n", page, ret); ++ return ret; ++ } ++ chip->select_chip(mtd, -1); ++ if (memcmp(buf, ref, mtd->writesize) == 0) { ++ printf("%s: Found FCB in page %u (%08x)\n", __func__, ++ page, page * mtd->writesize); ++ ret = 1; ++ } ++ free(buf); ++ return ret; ++} ++ ++static int write_fcb(struct mtd_info *mtd, void *buf, int block) ++{ ++ int ret; ++ struct nand_chip *chip = mtd->priv; ++ int page = block / mtd->writesize; ++ struct erase_info erase_opts = { ++ .mtd = mtd, ++ .addr = block, ++ .len = mtd->erasesize, ++ .callback = NULL, ++ }; ++ ++ ret = find_fcb(mtd, buf, page); ++ if (ret > 0) { ++ printf("FCB at block %08x is up to date\n", block); ++ return 0; ++ } ++ ++ ret = mtd->erase(mtd, &erase_opts); ++ if (ret) { ++ printf("Failed to erase FCB block %08x\n", block); ++ return ret; ++ } ++ ++ printf("Writing FCB to block %08x\n", block); ++ chip->select_chip(mtd, 0); ++ ret = chip->write_page(mtd, chip, buf, page, 0, 1); ++ if (ret) { ++ printf("Failed to write FCB to block %08x: %d\n", block, ret); ++ } ++ chip->select_chip(mtd, -1); ++ return ret; ++} ++ ++int update_bcb(int argc, char *argv[]) ++{ ++ int ret; ++ int block; ++ void *buf; ++ struct mx28_fcb *fcb; ++ struct cdev *tmp_cdev, *bcb_cdev, *firmware_cdev; ++ unsigned long fw2_offset = 0; ++ struct mtd_info *mtd; ++ unsigned fcb_written = 0; ++ ++ if (argc == 1) ++ return COMMAND_ERROR_USAGE; ++ ++ tmp_cdev = cdev_by_name("nand0"); ++ if (!tmp_cdev || !tmp_cdev->mtd) { ++ pr_err("%s: No NAND device!\n", __func__); ++ return -ENODEV; ++ } ++ ++ mtd = tmp_cdev->mtd; ++ ++ bcb_cdev = cdev_by_name("nand0.bcb"); ++ if (!bcb_cdev) { ++ pr_err("%s: No FCB device!\n", __func__); ++ return -ENODEV; ++ } ++ ++ firmware_cdev = cdev_by_name(argv[1]); ++ if (!firmware_cdev) { ++ pr_err("%s: Bootstream-Image not found!\n", __func__); ++ return -ENODEV; ++ } ++ ++ if (argc > 2) { ++ tmp_cdev = cdev_by_name(argv[2]); ++ if (!tmp_cdev) { ++ pr_err("%s: Redundant Bootstream-Image not found!\n", __func__); ++ return -ENODEV; ++ } ++ fw2_offset = tmp_cdev->offset; ++ } ++ ++ buf = malloc(mtd->erasesize); ++ if (!buf) ++ return -ENOMEM; ++ ++ fcb = create_fcb(mtd, buf, firmware_cdev->offset, firmware_cdev->size, fw2_offset); ++ if (IS_ERR(fcb)) { ++ printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); ++ return PTR_ERR(fcb); ++ } ++ encode_hamming_13_8(fcb, (void *)fcb + 512, 512); ++ ++ for (block = bcb_cdev->offset; block < bcb_cdev->offset + bcb_cdev->size / 2; ++ block += mtd->erasesize) { ++ ++ if (nand_isbad_bbt(mtd, block, false)) ++ continue; ++ ++ ret = write_fcb(mtd, buf, block); ++ if (ret) { ++ printf("Failed to write FCB to block %u\n", block); ++ return ret; ++ } ++ ++ fcb_written++; ++ } ++ ++ return fcb_written ? 0 : -ENOSPC; ++} ++ ++BAREBOX_CMD_HELP_START(bcb) ++BAREBOX_CMD_HELP_USAGE("bcb [second_bootstream]\n") ++BAREBOX_CMD_HELP_SHORT("Write a BCB to NAND flash which an MX23/28 needs to boot.\n") ++BAREBOX_CMD_HELP_TEXT ("Example: bcb nand0.bootstream\n") ++BAREBOX_CMD_HELP_END ++ ++BAREBOX_CMD_START(bcb) ++ .cmd = update_bcb, ++ .usage = "Writes a MX23/28 BCB data structure to flash", ++ BAREBOX_CMD_HELP(cmd_bcb_help) ++BAREBOX_CMD_END +diff --git a/arch/arm/mach-mxs/common.c b/arch/arm/mach-mxs/common.c +new file mode 100644 +index 0000000..3730633 +--- /dev/null ++++ b/arch/arm/mach-mxs/common.c +@@ -0,0 +1,33 @@ ++#include ++#include ++#include ++#include ++ ++#define MXS_BLOCK_SFTRST (1 << 31) ++#define MXS_BLOCK_CLKGATE (1 << 30) ++ ++int mxs_reset_block(void __iomem *reg, int just_enable) ++{ ++ /* Clear SFTRST */ ++ writel(MXS_BLOCK_SFTRST, reg + BIT_CLR); ++ mdelay(1); ++ ++ /* Clear CLKGATE */ ++ writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR); ++ ++ if (!just_enable) { ++ /* Set SFTRST */ ++ writel(MXS_BLOCK_SFTRST, reg + BIT_SET); ++ mdelay(1); ++ } ++ ++ /* Clear SFTRST */ ++ writel(MXS_BLOCK_SFTRST, reg + BIT_CLR); ++ mdelay(1); ++ ++ /* Clear CLKGATE */ ++ writel(MXS_BLOCK_CLKGATE, reg + BIT_CLR); ++ mdelay(1); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-mxs/include/mach/clock-imx23.h b/arch/arm/mach-mxs/include/mach/clock-imx23.h +index 723f343..6507792 100644 +--- a/arch/arm/mach-mxs/include/mach/clock-imx23.h ++++ b/arch/arm/mach-mxs/include/mach/clock-imx23.h +@@ -18,11 +18,13 @@ unsigned imx_get_emiclk(void); + unsigned imx_get_ioclk(void); + unsigned imx_get_armclk(void); + unsigned imx_get_hclk(void); ++unsigned imx_set_hclk(unsigned); + unsigned imx_get_xclk(void); + unsigned imx_get_sspclk(unsigned); + unsigned imx_set_sspclk(unsigned, unsigned, int); + unsigned imx_set_ioclk(unsigned); + unsigned imx_set_lcdifclk(unsigned); + unsigned imx_get_lcdifclk(void); ++void imx_enable_nandclk(void); + + #endif /* MACH_CLOCK_IMX23_H */ +diff --git a/arch/arm/mach-mxs/include/mach/clock-imx28.h b/arch/arm/mach-mxs/include/mach/clock-imx28.h +index 45fb043..0604f0a 100644 +--- a/arch/arm/mach-mxs/include/mach/clock-imx28.h ++++ b/arch/arm/mach-mxs/include/mach/clock-imx28.h +@@ -18,6 +18,7 @@ unsigned imx_get_emiclk(void); + unsigned imx_get_ioclk(unsigned); + unsigned imx_get_armclk(void); + unsigned imx_get_hclk(void); ++unsigned imx_set_hclk(unsigned); + unsigned imx_get_xclk(void); + unsigned imx_get_sspclk(unsigned); + unsigned imx_set_sspclk(unsigned, unsigned, int); +@@ -26,6 +27,7 @@ unsigned imx_set_lcdifclk(unsigned); + unsigned imx_get_lcdifclk(void); + unsigned imx_get_fecclk(void); + void imx_enable_enetclk(void); ++void imx_enable_nandclk(void); + + #endif /* MACH_CLOCK_IMX28_H */ + +diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h +new file mode 100644 +index 0000000..52747e2 +--- /dev/null ++++ b/arch/arm/mach-mxs/include/mach/dma.h +@@ -0,0 +1,145 @@ ++/* ++ * Freescale i.MX28 APBH DMA ++ * ++ * Copyright (C) 2011 Marek Vasut ++ * on behalf of DENX Software Engineering GmbH ++ * ++ * Based on code from LTIB: ++ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __DMA_H__ ++#define __DMA_H__ ++ ++#include ++ ++#ifndef CONFIG_ARCH_DMA_PIO_WORDS ++#define DMA_PIO_WORDS 15 ++#else ++#define DMA_PIO_WORDS CONFIG_ARCH_DMA_PIO_WORDS ++#endif ++ ++#define MXS_DMA_ALIGNMENT 32 ++ ++/* ++ * MXS DMA channels ++ */ ++enum { ++ MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0, ++ MXS_DMA_CHANNEL_AHB_APBH_SSP1, ++ MXS_DMA_CHANNEL_AHB_APBH_SSP2, ++ MXS_DMA_CHANNEL_AHB_APBH_SSP3, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI0, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI1, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI2, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI3, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI4, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI5, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI6, ++ MXS_DMA_CHANNEL_AHB_APBH_GPMI7, ++ MXS_DMA_CHANNEL_AHB_APBH_SSP, ++ MXS_MAX_DMA_CHANNELS, ++}; ++ ++/* ++ * MXS DMA hardware command. ++ * ++ * This structure describes the in-memory layout of an entire DMA command, ++ * including space for the maximum number of PIO accesses. See the appropriate ++ * reference manual for a detailed description of what these fields mean to the ++ * DMA hardware. ++ */ ++#define MXS_DMA_DESC_COMMAND_MASK 0x3 ++#define MXS_DMA_DESC_COMMAND_OFFSET 0 ++#define MXS_DMA_DESC_COMMAND_NO_DMAXFER 0x0 ++#define MXS_DMA_DESC_COMMAND_DMA_WRITE 0x1 ++#define MXS_DMA_DESC_COMMAND_DMA_READ 0x2 ++#define MXS_DMA_DESC_COMMAND_DMA_SENSE 0x3 ++#define MXS_DMA_DESC_CHAIN (1 << 2) ++#define MXS_DMA_DESC_IRQ (1 << 3) ++#define MXS_DMA_DESC_NAND_LOCK (1 << 4) ++#define MXS_DMA_DESC_NAND_WAIT_4_READY (1 << 5) ++#define MXS_DMA_DESC_DEC_SEM (1 << 6) ++#define MXS_DMA_DESC_WAIT4END (1 << 7) ++#define MXS_DMA_DESC_HALT_ON_TERMINATE (1 << 8) ++#define MXS_DMA_DESC_TERMINATE_FLUSH (1 << 9) ++#define MXS_DMA_DESC_PIO_WORDS_MASK (0xf << 12) ++#define MXS_DMA_DESC_PIO_WORDS_OFFSET 12 ++#define MXS_DMA_DESC_BYTES_MASK (0xffff << 16) ++#define MXS_DMA_DESC_BYTES_OFFSET 16 ++ ++struct mxs_dma_cmd { ++ unsigned long next; ++ unsigned long data; ++ union { ++ dma_addr_t address; ++ unsigned long alternate; ++ }; ++ unsigned long pio_words[DMA_PIO_WORDS]; ++}; ++ ++/* ++ * MXS DMA command descriptor. ++ * ++ * This structure incorporates an MXS DMA hardware command structure, along ++ * with metadata. ++ */ ++#define MXS_DMA_DESC_FIRST (1 << 0) ++#define MXS_DMA_DESC_LAST (1 << 1) ++#define MXS_DMA_DESC_READY (1 << 31) ++ ++struct mxs_dma_desc { ++ struct mxs_dma_cmd cmd; ++ unsigned int flags; ++ dma_addr_t address; ++ void *buffer; ++ struct list_head node; ++}; ++ ++/** ++ * MXS DMA channel ++ * ++ * This structure represents a single DMA channel. The MXS platform code ++ * maintains an array of these structures to represent every DMA channel in the ++ * system (see mxs_dma_channels). ++ */ ++#define MXS_DMA_FLAGS_IDLE 0 ++#define MXS_DMA_FLAGS_BUSY (1 << 0) ++#define MXS_DMA_FLAGS_FREE 0 ++#define MXS_DMA_FLAGS_ALLOCATED (1 << 16) ++#define MXS_DMA_FLAGS_VALID (1 << 31) ++ ++struct mxs_dma_chan { ++ const char *name; ++ unsigned long dev; ++ struct mxs_dma_device *dma; ++ unsigned int flags; ++ unsigned int active_num; ++ unsigned int pending_num; ++ struct list_head active; ++ struct list_head done; ++}; ++ ++struct mxs_dma_desc *mxs_dma_desc_alloc(void); ++void mxs_dma_desc_free(struct mxs_dma_desc *); ++int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc); ++ ++int mxs_dma_go(int chan); ++int mxs_dma_init(void); ++ ++#endif /* __DMA_H__ */ +diff --git a/arch/arm/mach-mxs/include/mach/imx23-regs.h b/arch/arm/mach-mxs/include/mach/imx23-regs.h +index 60f5bf9..7ea3057 100644 +--- a/arch/arm/mach-mxs/include/mach/imx23-regs.h ++++ b/arch/arm/mach-mxs/include/mach/imx23-regs.h +@@ -27,6 +27,9 @@ + #endif + + #define IMX_MEMORY_BASE 0x40000000 ++#define MXS_APBH_BASE 0x80004000 ++#define MXS_BCH_BASE 0x8000a000 ++#define MXS_GPMI_BASE 0x8000c000 + #define IMX_UART1_BASE 0x8006c000 + #define IMX_UART2_BASE 0x8006e000 + #define IMX_DBGUART_BASE 0x80070000 +diff --git a/arch/arm/mach-mxs/include/mach/imx28-regs.h b/arch/arm/mach-mxs/include/mach/imx28-regs.h +index 9a2052c..16bf5f7 100644 +--- a/arch/arm/mach-mxs/include/mach/imx28-regs.h ++++ b/arch/arm/mach-mxs/include/mach/imx28-regs.h +@@ -23,15 +23,19 @@ + #define IMX_SRAM_BASE 0x00000000 + #define IMX_MEMORY_BASE 0x40000000 + +-#define IMX_NFC_BASE 0x8000C000 ++#define MXS_APBH_BASE 0x80004000 ++#define MXS_BCH_BASE 0x8000a000 ++#define MXS_GPMI_BASE 0x8000c000 + #define IMX_SSP0_BASE 0x80010000 + #define IMX_SSP1_BASE 0x80012000 + #define IMX_SSP2_BASE 0x80014000 + #define IMX_SSP3_BASE 0x80016000 + #define IMX_IOMUXC_BASE 0x80018000 ++#define IMX_DIGCTL_BASE 0x8001c000 + #define IMX_OCOTP_BASE 0x8002c000 + #define IMX_FB_BASE 0x80030000 + #define IMX_CCM_BASE 0x80040000 ++#define IMX_POWER_BASE 0x80044000 + #define IMX_WDT_BASE 0x80056000 + #define IMX_I2C0_BASE 0x80058000 + #define IMX_I2C1_BASE 0x8005a000 +@@ -42,6 +46,9 @@ + #define IMX_UART3_BASE 0x80070000 + #define IMX_UART4_BASE 0x80072000 + #define IMX_DBGUART_BASE 0x80074000 ++#define IMX_USBPHY0_BASE 0x8007c000 ++#define IMX_USBPHY1_BASE 0x8007e000 ++#define IMX_USB_BASE 0x80080000 + #define IMX_FEC0_BASE 0x800F0000 + #define IMX_FEC1_BASE 0x800F4000 + +diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h +new file mode 100644 +index 0000000..182ed8a +--- /dev/null ++++ b/arch/arm/mach-mxs/include/mach/mxs.h +@@ -0,0 +1,6 @@ ++#ifndef __MACH_MXS_H ++#define __MACH_MXS_H ++ ++int mxs_reset_block(void __iomem *reg, int just_enable); ++ ++#endif /* __MACH_MXS_H */ +diff --git a/arch/arm/mach-mxs/include/mach/power.h b/arch/arm/mach-mxs/include/mach/power.h +new file mode 100644 +index 0000000..f429b3c +--- /dev/null ++++ b/arch/arm/mach-mxs/include/mach/power.h +@@ -0,0 +1,8 @@ ++#ifndef __MACH_POWER_H ++#define __MACH_POWER_H ++ ++void imx_power_prepare_usbphy(void); ++int imx_get_vddio(void); ++int imx_set_vddio(int); ++ ++#endif /* __MACH_POWER_H */ +diff --git a/arch/arm/mach-mxs/include/mach/usb.h b/arch/arm/mach-mxs/include/mach/usb.h +index af7d885..2d31b0d 100644 +--- a/arch/arm/mach-mxs/include/mach/usb.h ++++ b/arch/arm/mach-mxs/include/mach/usb.h +@@ -1,6 +1,9 @@ + #ifndef __MACH_USB_H + #define __MACH_USB_H + +-int imx_usb_phy_enable(void); ++int imx23_usb_phy_enable(void); ++ ++int imx28_usb_phy0_enable(void); ++int imx28_usb_phy1_enable(void); + + #endif /* __MACH_USB_H */ +diff --git a/arch/arm/mach-mxs/iomux-imx.c b/arch/arm/mach-mxs/iomux-imx.c +index 6bcde03..a3ecb94 100644 +--- a/arch/arm/mach-mxs/iomux-imx.c ++++ b/arch/arm/mach-mxs/iomux-imx.c +@@ -131,7 +131,7 @@ void imx_gpio_mode(uint32_t m) + if (BK_PRESENT(m)) { + reg_offset = calc_pullup_reg(gpio_pin); + writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + +- (GET_BITKEEPER(m) == 1 ? BIT_SET : BIT_CLR)); ++ (GET_BITKEEPER(m) == 1 ? BIT_CLR : BIT_SET)); + } + + if (GET_FUNC(m) == IS_GPIO) { +diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c +index 38f9ffd..7824402 100644 +--- a/arch/arm/mach-mxs/ocotp.c ++++ b/arch/arm/mach-mxs/ocotp.c +@@ -25,27 +25,45 @@ + #include + #include + #include ++#include ++#include + + #define DRIVERNAME "ocotp" + +-#define OCOTP_WORD_OFFSET 0x20 ++#define OCOTP_CTRL 0x0 ++# define OCOTP_CTRL_ADDR_MASK 0x3f ++# define OCOTP_CTRL_BUSY (1 << 8) ++# define OCOTP_CTRL_ERROR (1 << 9) ++# define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) ++# define OCOTP_CTRL_WR_UNLOCK 0x3e770000 ++ ++#define OCOTP_DATA 0x10 + +-#define BM_OCOTP_CTRL_BUSY (1 << 8) +-#define BM_OCOTP_CTRL_ERROR (1 << 9) +-#define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12) ++#define OCOTP_WORD_OFFSET 0x20 + + struct ocotp_priv { + struct cdev cdev; + void __iomem *base; + }; + ++static int mxs_ocotp_wait_busy(struct ocotp_priv *priv) ++{ ++ uint64_t start = get_time_ns(); ++ ++ /* check both BUSY and ERROR cleared */ ++ while (readl(priv->base + OCOTP_CTRL) & (OCOTP_CTRL_BUSY | OCOTP_CTRL_ERROR)) ++ if (is_timeout(start, MSECOND)) ++ return -ETIMEDOUT; ++ ++ return 0; ++} ++ + static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count, +- ulong offset, ulong flags) ++ loff_t offset, ulong flags) + { + struct ocotp_priv *priv = cdev->priv; + void __iomem *base = priv->base; +- size_t size = min((ulong)count, cdev->size - offset); +- uint64_t start; ++ size_t size = min((loff_t)count, cdev->size - offset); + int i; + + /* +@@ -54,25 +72,20 @@ static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count, + */ + + /* try to clear ERROR bit */ +- writel(BM_OCOTP_CTRL_ERROR, base + BIT_CLR); ++ writel(OCOTP_CTRL_ERROR, base + OCOTP_CTRL + BIT_CLR); + +- /* check both BUSY and ERROR cleared */ +- start = get_time_ns(); +- while (readl(base) & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) +- if (is_timeout(start, MSECOND)) +- return -ETIMEDOUT; ++ if (mxs_ocotp_wait_busy(priv)) ++ return -ETIMEDOUT; + + /* open OCOTP banks for read */ +- writel(BM_OCOTP_CTRL_RD_BANK_OPEN, base + BIT_SET); ++ writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_SET); + + /* approximately wait 32 hclk cycles */ + udelay(1); + + /* poll BUSY bit becoming cleared */ +- start = get_time_ns(); +- while (readl(base) & BM_OCOTP_CTRL_BUSY) +- if (is_timeout(start, MSECOND)) +- return -ETIMEDOUT; ++ if (mxs_ocotp_wait_busy(priv)) ++ return -ETIMEDOUT; + + for (i = 0; i < size; i++) + /* When reading bytewise, we need to hop over the SET/CLR/TGL regs */ +@@ -80,16 +93,107 @@ static ssize_t mxs_ocotp_cdev_read(struct cdev *cdev, void *buf, size_t count, + (((i + offset) & 0xfc) << 2) + ((i + offset) & 3)); + + /* close banks for power saving */ +- writel(BM_OCOTP_CTRL_RD_BANK_OPEN, base + BIT_CLR); ++ writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_CLR); + + return size; + } + ++static ssize_t mxs_ocotp_cdev_write(struct cdev *cdev, const void *buf, size_t count, ++ loff_t offset, ulong flags) ++{ ++ struct ocotp_priv *priv = cdev->priv; ++ void __iomem *base = priv->base; ++ const char *write_param; ++ unsigned int write_enabled = 0; ++ unsigned long old_hclk, aligned_offset; ++ int old_vddio, num_words, num_bytes, i, ret = 0; ++ u8 *work_buf; ++ u32 reg; ++ ++ write_param = dev_get_param(cdev->dev, "permanent_write_enable"); ++ if (write_param) ++ write_enabled = simple_strtoul(write_param, NULL, 0); ++ ++ if (!write_param || !write_enabled) ++ return -EPERM; ++ ++ /* we can only work on u32, so calc some helpers */ ++ aligned_offset = offset & ~3UL; ++ num_words = DIV_ROUND_UP(offset - aligned_offset + count, 4); ++ num_bytes = num_words << 2; ++ ++ /* read in all words which will be modified */ ++ work_buf = xmalloc(num_bytes); ++ ++ i = mxs_ocotp_cdev_read(cdev, work_buf, num_bytes, aligned_offset, 0); ++ if (i != num_bytes) { ++ ret = -ENXIO; ++ goto free_mem; ++ } ++ ++ /* modify read words with to be written data */ ++ for (i = 0; i < count; i++) ++ work_buf[offset - aligned_offset + i] |= ((u8 *)buf)[i]; ++ ++ /* prepare system for OTP write */ ++ old_hclk = imx_get_hclk(); ++ old_vddio = imx_get_vddio(); ++ ++ imx_set_hclk(24000000); ++ imx_set_vddio(2800000); ++ ++ writel(OCOTP_CTRL_RD_BANK_OPEN, base + OCOTP_CTRL + BIT_CLR); ++ ++ if (mxs_ocotp_wait_busy(priv)) { ++ ret = -ETIMEDOUT; ++ goto restore_system; ++ } ++ ++ /* write word for word via data register */ ++ for (i = 0; i < num_words; i++) { ++ reg = readl(base + OCOTP_CTRL) & ~OCOTP_CTRL_ADDR_MASK; ++ reg |= OCOTP_CTRL_WR_UNLOCK | ((aligned_offset >> 2) + i); ++ writel(reg, base + OCOTP_CTRL); ++ ++ writel(((u32 *)work_buf)[i], base + OCOTP_DATA); ++ ++ if (mxs_ocotp_wait_busy(priv)) { ++ ret = -ETIMEDOUT; ++ goto restore_system; ++ } ++ ++ mdelay(2); ++ } ++ ++restore_system: ++ imx_set_vddio(old_vddio); ++ imx_set_hclk(old_hclk); ++free_mem: ++ free(work_buf); ++ ++ return ret; ++} ++ + static struct file_operations mxs_ocotp_ops = { + .read = mxs_ocotp_cdev_read, + .lseek = dev_lseek_default, + }; + ++static int mxs_ocotp_write_enable_set(struct device_d *dev, struct param_d *param, ++ const char *val) ++{ ++ unsigned long write_enable; ++ ++ if (!val) ++ return -EINVAL; ++ ++ write_enable = simple_strtoul(val, NULL, 0); ++ if (write_enable > 1) ++ return -EINVAL; ++ ++ return dev_param_set_generic(dev, param, write_enable ? "1" : "0"); ++} ++ + static int mxs_ocotp_probe(struct device_d *dev) + { + int err; +@@ -106,6 +210,18 @@ static int mxs_ocotp_probe(struct device_d *dev) + if (err < 0) + return err; + ++ if (IS_ENABLED(CONFIG_MXS_OCOTP_WRITABLE)) { ++ mxs_ocotp_ops.write = mxs_ocotp_cdev_write; ++ ++ err = dev_add_param(dev, "permanent_write_enable", ++ mxs_ocotp_write_enable_set, NULL, 0); ++ if (err < 0) ++ return err; ++ err = dev_set_param(dev, "permanent_write_enable", "0"); ++ if (err < 0) ++ return err; ++ } ++ + return 0; + } + +diff --git a/arch/arm/mach-mxs/power.c b/arch/arm/mach-mxs/power.c +new file mode 100644 +index 0000000..f4d0b9e +--- /dev/null ++++ b/arch/arm/mach-mxs/power.c +@@ -0,0 +1,84 @@ ++/* ++ * i.MX28 power related functions ++ * ++ * Copyright 2011 Sascha Hauer, Pengutronix ++ * Copyright (C) 2012 Wolfram Sang, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++#include ++#include ++#include ++#include ++ ++#define POWER_CTRL (IMX_POWER_BASE + 0x0) ++#define POWER_CTRL_CLKGATE 0x40000000 ++ ++#define POWER_VDDIOCTRL (IMX_POWER_BASE + 0x60) ++ ++#define POWER_STS (IMX_POWER_BASE + 0xc0) ++#define POWER_STS_VBUSVALID 0x00000002 ++#define POWER_STS_BVALID 0x00000004 ++#define POWER_STS_AVALID 0x00000008 ++ ++#define POWER_DEBUG (IMX_POWER_BASE + 0x110) ++#define POWER_DEBUG_BVALIDPIOLOCK 0x00000002 ++#define POWER_DEBUG_AVALIDPIOLOCK 0x00000004 ++#define POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 ++ ++#define TRG_MASK 0x1f ++ ++int imx_get_vddio(void) ++{ ++ u32 val; ++ ++ val = readl(POWER_VDDIOCTRL) & TRG_MASK; ++ if (val > 0x10) ++ val = 0x10; ++ ++ return 2800000 + val * 50000; ++} ++ ++int imx_set_vddio(int new_voltage_uV) ++{ ++ u32 reg, val; ++ ++ if (new_voltage_uV < 2800000 || new_voltage_uV > 3600000) ++ return -EINVAL; ++ ++ val = (new_voltage_uV - 2800000) / 50000; ++ reg = readl(POWER_VDDIOCTRL) & ~TRG_MASK; ++ writel(reg | val, POWER_VDDIOCTRL); ++ ++ /* ++ * Wait for power to become stable. We just wait, because DC_OK can ++ * only detect rising voltages for DCDC. For all other cases, bootlets ++ * also do simple waiting, although horribly nested. We just take the ++ * maximum value of all cases from the bootlets and then add some. ++ */ ++ mdelay(30); ++ ++ return 2800000 + val * 50000; ++} ++ ++void imx_power_prepare_usbphy(void) ++{ ++ u32 reg; ++ ++ /* ++ * Set these bits so that we can force the OTG bits high ++ * so the ARC core operates properly ++ */ ++ writel(POWER_CTRL_CLKGATE, POWER_CTRL + BIT_CLR); ++ ++ writel(POWER_DEBUG_VBUSVALIDPIOLOCK | ++ POWER_DEBUG_AVALIDPIOLOCK | ++ POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + BIT_SET); ++ ++ reg = readl(POWER_STS); ++ reg |= POWER_STS_BVALID | POWER_STS_AVALID | POWER_STS_VBUSVALID; ++ writel(reg, POWER_STS); ++} +diff --git a/arch/arm/mach-mxs/reset-imx.c b/arch/arm/mach-mxs/reset-imx.c +deleted file mode 100644 +index cfb3548..0000000 +--- a/arch/arm/mach-mxs/reset-imx.c ++++ /dev/null +@@ -1,61 +0,0 @@ +-/* +- * (C) Copyright 2010 Juergen Beisert - Pengutronix +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +- +-#include +-#include +-#include +-#include +-#include +- +-#define HW_RTC_CTRL 0x000 +-# define BM_RTC_CTRL_WATCHDOGEN (1 << 4) +-#define HW_RTC_CTRL_SET 0x004 +-#define HW_RTC_CTRL_CLR 0x008 +-#define HW_RTC_CTRL_TOG 0x00C +- +-#define HW_RTC_WATCHDOG 0x050 +-#define HW_RTC_WATCHDOG_SET 0x054 +-#define HW_RTC_WATCHDOG_CLR 0x058 +-#define HW_RTC_WATCHDOG_TOG 0x05C +- +-#define WDOG_COUNTER_RATE 1000 /* 1 kHz clock */ +- +-#define HW_RTC_PERSISTENT1 0x070 +-# define BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER 0x80000000 +-#define HW_RTC_PERSISTENT1_SET 0x074 +-#define HW_RTC_PERSISTENT1_CLR 0x078 +-#define HW_RTC_PERSISTENT1_TOG 0x07C +- +-/* +- * Reset the cpu by setting up the watchdog timer and let it time out +- * +- * TODO There is a much easier way to reset the CPU: Refer bit 2 in +- * the HW_CLKCTRL_RESET register, data sheet page 106/4-30 +- */ +-void __noreturn reset_cpu (unsigned long addr) +-{ +- writel(WDOG_COUNTER_RATE, IMX_WDT_BASE + HW_RTC_WATCHDOG); +- writel(BM_RTC_CTRL_WATCHDOGEN, IMX_WDT_BASE + HW_RTC_CTRL_SET); +- writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER, IMX_WDT_BASE + HW_RTC_PERSISTENT1); +- +- while (1) +- ; +- /*NOTREACHED*/ +-} +-EXPORT_SYMBOL(reset_cpu); +diff --git a/arch/arm/mach-mxs/soc-imx23.c b/arch/arm/mach-mxs/soc-imx23.c +new file mode 100644 +index 0000000..6819b3c +--- /dev/null ++++ b/arch/arm/mach-mxs/soc-imx23.c +@@ -0,0 +1,37 @@ ++/* ++ * (c) 2012 Juergen Beisert ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Collection of some SoC specific functions ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#define HW_CLKCTRL_RESET 0x120 ++# define HW_CLKCTRL_RESET_CHIP (1 << 1) ++ ++/* Reset the full i.MX23 SoC via a chipset feature */ ++void __noreturn reset_cpu(unsigned long addr) ++{ ++ u32 reg; ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET); ++ writel(reg | HW_CLKCTRL_RESET_CHIP, IMX_CCM_BASE + HW_CLKCTRL_RESET); ++ ++ while (1) ++ ; ++ /*NOTREACHED*/ ++} ++EXPORT_SYMBOL(reset_cpu); +diff --git a/arch/arm/mach-mxs/soc-imx28.c b/arch/arm/mach-mxs/soc-imx28.c +new file mode 100644 +index 0000000..a181b75 +--- /dev/null ++++ b/arch/arm/mach-mxs/soc-imx28.c +@@ -0,0 +1,37 @@ ++/* ++ * (c) 2012 Juergen Beisert ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Collection of some SoC specific functions ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#define HW_CLKCTRL_RESET 0x1e0 ++# define HW_CLKCTRL_RESET_CHIP (1 << 1) ++ ++/* Reset the full i.MX28 SoC via a chipset feature */ ++void __noreturn reset_cpu(unsigned long addr) ++{ ++ u32 reg; ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_RESET); ++ writel(reg | HW_CLKCTRL_RESET_CHIP, IMX_CCM_BASE + HW_CLKCTRL_RESET); ++ ++ while (1) ++ ; ++ /*NOTREACHED*/ ++} ++EXPORT_SYMBOL(reset_cpu); +diff --git a/arch/arm/mach-mxs/speed-imx23.c b/arch/arm/mach-mxs/speed-imx23.c +index b10c786..5d0c90d 100644 +--- a/arch/arm/mach-mxs/speed-imx23.c ++++ b/arch/arm/mach-mxs/speed-imx23.c +@@ -47,6 +47,8 @@ + # define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) + # define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) + #define HW_CLKCTRL_GPMI 0x080 ++# define CLKCTRL_GPMI_CLKGATE (1 << 31) ++# define CLKCTRL_GPMI_DIV_MASK 0x3ff + /* note: no set/clear register! */ + #define HW_CLKCTRL_SPDIF 0x090 + /* note: no set/clear register! */ +@@ -184,12 +186,34 @@ unsigned imx_get_hclk(void) + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) { + rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; +- rate >>= 5U; /* / 32 */ ++ rate = DIV_ROUND_UP(rate, 32); + } else +- rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; ++ rate = DIV_ROUND_UP(rate, ++ readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f); + return rate * 1000; + } + ++unsigned imx_set_hclk(unsigned nc) ++{ ++ unsigned root_rate = imx_get_armclk(); ++ unsigned reg, div; ++ ++ div = DIV_ROUND_UP(root_rate, nc); ++ if ((div == 0) || (div >= 32)) ++ return 0; ++ ++ if ((root_rate < nc) && (root_rate == 64000000)) ++ div = 3; ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & ~0x3f; ++ writel(reg | div, IMX_CCM_BASE + HW_CLKCTRL_HBUS); ++ ++ while (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & (1 << 31)) ++ ; ++ ++ return imx_get_hclk(); ++} ++ + /* + * Source of UART, debug UART, audio, PWM, dri, timer, digctl + */ +@@ -266,6 +290,23 @@ unsigned imx_set_sspclk(unsigned index, unsigned nc, int high) + return imx_get_sspclk(index); + } + ++void imx_enable_nandclk(void) ++{ ++ uint32_t reg; ++ ++ /* Clear bypass bit; refman says clear, but fsl-code does set. Hooray! */ ++ writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, ++ IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_SET); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_GPMI) & ~CLKCTRL_GPMI_CLKGATE; ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI); ++ udelay(1000); ++ /* Initialize DIV to 1 */ ++ reg &= ~CLKCTRL_GPMI_DIV_MASK; ++ reg |= 1; ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI); ++} ++ + void imx_dump_clocks(void) + { + printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000); +diff --git a/arch/arm/mach-mxs/speed-imx28.c b/arch/arm/mach-mxs/speed-imx28.c +index 67cdbdf..df55f64 100644 +--- a/arch/arm/mach-mxs/speed-imx28.c ++++ b/arch/arm/mach-mxs/speed-imx28.c +@@ -48,6 +48,8 @@ + # define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) + # define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) + #define HW_CLKCTRL_GPMI 0x0d0 ++# define CLKCTRL_GPMI_CLKGATE (1 << 31) ++# define CLKCTRL_GPMI_DIV_MASK 0x3ff + /* note: no set/clear register! */ + #define HW_CLKCTRL_SPDIF 0x0e0 + /* note: no set/clear register! */ +@@ -251,12 +253,34 @@ unsigned imx_get_hclk(void) + + if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) { + rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; +- rate /= 32; ++ rate = DIV_ROUND_UP(rate, 32); + } else +- rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; ++ rate = DIV_ROUND_UP(rate, ++ readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f); + return rate * 1000; + } + ++unsigned imx_set_hclk(unsigned nc) ++{ ++ unsigned root_rate = imx_get_armclk(); ++ unsigned reg, div; ++ ++ div = DIV_ROUND_UP(root_rate, nc); ++ if ((div == 0) || (div >= 32)) ++ return 0; ++ ++ if ((root_rate < nc) && (root_rate == 64000000)) ++ div = 3; ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & ~0x3f; ++ writel(reg | div, IMX_CCM_BASE + HW_CLKCTRL_HBUS); ++ ++ while (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & (1 << 31)) ++ ; ++ ++ return imx_get_hclk(); ++} ++ + /* + * Source of UART, debug UART, audio, PWM, dri, timer, digctl + */ +@@ -376,6 +400,23 @@ void imx_enable_enetclk(void) + IMX_CCM_BASE + HW_CLKCTRL_ENET); + } + ++void imx_enable_nandclk(void) ++{ ++ uint32_t reg; ++ ++ /* Clear bypass bit; refman says clear, but fsl-code does set. Hooray! */ ++ writel(CLKCTRL_CLKSEQ_BYPASS_GPMI, ++ IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + BIT_SET); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_GPMI) & ~CLKCTRL_GPMI_CLKGATE; ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI); ++ udelay(1000); ++ /* Initialize DIV to 1 */ ++ reg &= ~CLKCTRL_GPMI_DIV_MASK; ++ reg |= 1; ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_GPMI); ++} ++ + void imx_dump_clocks(void) + { + printf("mpll: %10u kHz\n", imx_get_mpllclk() / 1000); +diff --git a/arch/arm/mach-mxs/usb-imx23.c b/arch/arm/mach-mxs/usb-imx23.c +new file mode 100644 +index 0000000..9aaf4bc +--- /dev/null ++++ b/arch/arm/mach-mxs/usb-imx23.c +@@ -0,0 +1,65 @@ ++/* ++ * i.MX23 USBPHY setup ++ * ++ * Copyright 2011 Sascha Hauer, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++ ++#define USBPHY_PWD (IMX_USBPHY_BASE + 0x0) ++ ++#define USBPHY_CTRL (IMX_USBPHY_BASE + 0x30) ++#define USBPHY_CTRL_SFTRST 0x80000000 ++#define USBPHY_CTRL_CLKGATE 0x40000000 ++ ++#define CLK_PLLCTRL0 (IMX_CCM_BASE + 0x0) ++#define PLLCTRL0_EN_USB_CLKS 0x00040000 ++ ++#define DIGCTRL_CTRL (IMX_DIGCTL_BASE + 0x0) ++#define DIGCTL_CTRL_USB_CLKGATE 0x00000004 ++ ++#define SET 0x4 ++#define CLR 0x8 ++ ++int imx23_usb_phy_enable(void) ++{ ++ imx_power_prepare_usbphy(); ++ ++ /* Reset USBPHY module */ ++ writel(USBPHY_CTRL_SFTRST, USBPHY_CTRL + SET); ++ udelay(10); ++ ++ /* Remove CLKGATE and SFTRST */ ++ writel(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST, USBPHY_CTRL + CLR); ++ ++ /* Turn on the USB clocks */ ++ writel(PLLCTRL0_EN_USB_CLKS, CLK_PLLCTRL0 + SET); ++ writel(DIGCTL_CTRL_USB_CLKGATE, DIGCTRL_CTRL + CLR); ++ ++ /* Power up the PHY */ ++ writel(0, USBPHY_PWD); ++ ++ /* ++ * Set precharge bit to cure overshoot problems at the ++ * start of packets ++ */ ++ writel(1, USBPHY_CTRL + SET); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-mxs/usb-imx28.c b/arch/arm/mach-mxs/usb-imx28.c +new file mode 100644 +index 0000000..61d59c3 +--- /dev/null ++++ b/arch/arm/mach-mxs/usb-imx28.c +@@ -0,0 +1,101 @@ ++/* ++ * i.MX28 USBPHY setup ++ * ++ * Copyright 2011 Sascha Hauer, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++ ++#define POWER_CTRL (IMX_POWER_BASE + 0x0) ++#define POWER_CTRL_CLKGATE 0x40000000 ++ ++#define POWER_STS (IMX_POWER_BASE + 0xc0) ++#define POWER_STS_VBUSVALID 0x00000002 ++#define POWER_STS_BVALID 0x00000004 ++#define POWER_STS_AVALID 0x00000008 ++ ++#define POWER_DEBUG (IMX_POWER_BASE + 0x110) ++#define POWER_DEBUG_BVALIDPIOLOCK 0x00000002 ++#define POWER_DEBUG_AVALIDPIOLOCK 0x00000004 ++#define POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 ++ ++#define USBPHY_PWD 0x0 ++ ++#define USBPHY_CTRL 0x30 ++#define USBPHY_CTRL_SFTRST (1 << 31) ++#define USBPHY_CTRL_CLKGATE (1 << 30) ++#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) ++#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) ++ ++#define CLK_PLL0CTRL0 (IMX_CCM_BASE + 0x0) ++#define CLK_PLL1CTRL0 (IMX_CCM_BASE + 0x20) ++#define PLLCTRL0_EN_USB_CLKS (1 << 18) ++ ++#define DIGCTRL_CTRL (IMX_DIGCTL_BASE + 0x0) ++#define DIGCTL_CTRL_USB0_CLKGATE (1 << 2) ++#define DIGCTL_CTRL_USB1_CLKGATE (1 << 16) ++ ++#define SET 0x4 ++#define CLR 0x8 ++ ++static void imx28_usb_phy_reset(void __iomem *phybase) ++{ ++ /* Reset USBPHY module */ ++ writel(USBPHY_CTRL_SFTRST, phybase + USBPHY_CTRL + SET); ++ udelay(10); ++ writel(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST, ++ phybase + USBPHY_CTRL + CLR); ++} ++ ++static void imx28_usb_phy_enable(void __iomem *phybase) ++{ ++ /* Power up the PHY */ ++ writel(0, phybase + USBPHY_PWD); ++ ++ writel(USBPHY_CTRL_ENUTMILEVEL3 | USBPHY_CTRL_ENUTMILEVEL2 | 1, ++ phybase + USBPHY_CTRL + SET); ++} ++ ++int imx28_usb_phy0_enable(void) ++{ ++ imx28_usb_phy_reset((void *)IMX_USBPHY0_BASE); ++ ++ /* Turn on the USB clocks */ ++ writel(PLLCTRL0_EN_USB_CLKS, CLK_PLL0CTRL0 + SET); ++ ++ writel(DIGCTL_CTRL_USB0_CLKGATE, DIGCTRL_CTRL + CLR); ++ ++ imx28_usb_phy_enable((void *)IMX_USBPHY0_BASE); ++ ++ return 0; ++} ++ ++int imx28_usb_phy1_enable(void) ++{ ++ imx28_usb_phy_reset((void *)IMX_USBPHY1_BASE); ++ ++ /* Turn on the USB clocks */ ++ writel(PLLCTRL0_EN_USB_CLKS, CLK_PLL1CTRL0 + SET); ++ ++ writel(DIGCTL_CTRL_USB1_CLKGATE, DIGCTRL_CTRL + CLR); ++ ++ imx28_usb_phy_enable((void *)IMX_USBPHY1_BASE); ++ ++ return 0; ++} +diff --git a/arch/arm/mach-mxs/usb.c b/arch/arm/mach-mxs/usb.c +deleted file mode 100644 +index b7a9376..0000000 +--- a/arch/arm/mach-mxs/usb.c ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * i.MX23/28 USBPHY setup +- * +- * Copyright 2011 Sascha Hauer, Pengutronix +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +-#include +-#include +-#include +- +-#define POWER_CTRL (IMX_POWER_BASE + 0x0) +-#define POWER_CTRL_CLKGATE 0x40000000 +- +-#define POWER_STS (IMX_POWER_BASE + 0xc0) +-#define POWER_STS_VBUSVALID 0x00000002 +-#define POWER_STS_BVALID 0x00000004 +-#define POWER_STS_AVALID 0x00000008 +- +-#define POWER_DEBUG (IMX_POWER_BASE + 0x110) +-#define POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +-#define POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +-#define POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 +- +-#define USBPHY_PWD (IMX_USBPHY_BASE + 0x0) +- +-#define USBPHY_CTRL (IMX_USBPHY_BASE + 0x30) +-#define USBPHY_CTRL_SFTRST 0x80000000 +-#define USBPHY_CTRL_CLKGATE 0x40000000 +- +-#define CLK_PLLCTRL0 (IMX_CCM_BASE + 0x0) +-#define PLLCTRL0_EN_USB_CLKS 0x00040000 +- +-#define DIGCTRL_CTRL (IMX_DIGCTL_BASE + 0x0) +-#define DIGCTL_CTRL_USB_CLKGATE 0x00000004 +- +-#define SET 0x4 +-#define CLR 0x8 +- +-int imx_usb_phy_enable(void) +-{ +- u32 reg; +- +- /* +- * Set these bits so that we can force the OTG bits high +- * so the ARC core operates properly +- */ +- writel(POWER_CTRL_CLKGATE, POWER_CTRL + CLR); +- +- writel(POWER_DEBUG_VBUSVALIDPIOLOCK | +- POWER_DEBUG_AVALIDPIOLOCK | +- POWER_DEBUG_BVALIDPIOLOCK, POWER_DEBUG + SET); +- +- reg = readl(POWER_STS); +- reg |= POWER_STS_BVALID | POWER_STS_AVALID | POWER_STS_VBUSVALID; +- writel(reg, POWER_STS); +- +- /* Reset USBPHY module */ +- writel(USBPHY_CTRL_SFTRST, USBPHY_CTRL + SET); +- udelay(10); +- +- /* Remove CLKGATE and SFTRST */ +- writel(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST, USBPHY_CTRL + CLR); +- +- /* Turn on the USB clocks */ +- writel(PLLCTRL0_EN_USB_CLKS, CLK_PLLCTRL0 + SET); +- writel(DIGCTL_CTRL_USB_CLKGATE, DIGCTRL_CTRL + CLR); +- +- /* Power up the PHY */ +- writel(0, USBPHY_PWD); +- +- /* +- * Set precharge bit to cure overshoot problems at the +- * start of packets +- */ +- writel(1, USBPHY_CTRL + SET); +- +- return 0; +-} +- +diff --git a/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h +new file mode 100644 +index 0000000..51fd9a1 +--- /dev/null ++++ b/arch/arm/mach-samsung/include/mach/devices-s3c24xx.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright 2012 Juergen Beisert ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#ifndef INCLUDE_MACH_DEVICES_S3C24XX_H ++# define INCLUDE_MACH_DEVICES_S3C24XX_H ++ ++#include ++#include ++#include ++#include ++#include ++ ++static inline void s3c24xx_add_nand(struct s3c24x0_nand_platform_data *d) ++{ ++ add_generic_device("s3c24x0_nand", DEVICE_ID_DYNAMIC, NULL, ++ S3C24X0_NAND_BASE, 0x80, IORESOURCE_MEM, d); ++} ++ ++static inline void s3c24xx_add_mci(struct s3c_mci_platform_data *d) ++{ ++ add_generic_device("s3c_mci", DEVICE_ID_DYNAMIC, NULL, ++ S3C2410_SDI_BASE, 0x80, IORESOURCE_MEM, d); ++} ++ ++static inline void s3c24xx_add_fb(struct s3c_fb_platform_data *d) ++{ ++ add_generic_device("s3c_fb", DEVICE_ID_DYNAMIC, NULL, ++ S3C2410_LCD_BASE, 0x80, IORESOURCE_MEM, d); ++} ++ ++static inline void s3c24xx_add_ohci(void) ++{ ++ add_generic_device("ohci", DEVICE_ID_DYNAMIC, NULL, ++ S3C2410_USB_HOST_BASE, 0x100, IORESOURCE_MEM, NULL); ++} ++ ++static inline void s3c24xx_add_uart1(void) ++{ ++ add_generic_device("s3c_serial", DEVICE_ID_DYNAMIC, NULL, S3C_UART1_BASE, ++ S3C_UART1_SIZE, IORESOURCE_MEM, NULL); ++} ++ ++#endif /* INCLUDE_MACH_DEVICES_S3C24XX_H */ +diff --git a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h +index acd78b8..fa88da1 100644 +--- a/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h ++++ b/arch/arm/mach-samsung/include/mach/s3c24xx-nand.h +@@ -18,6 +18,9 @@ + * + */ + ++#ifndef MACH_S3C24XX_NAND_H ++# define MACH_S3C24XX_NAND_H ++ + #ifdef CONFIG_S3C_NAND_BOOT + extern void s3c24x0_nand_load_image(void*, int, int); + #endif +@@ -52,3 +55,5 @@ struct s3c24x0_nand_platform_data { + * @file + * @brief Basic declaration to use the s3c24x0 NAND driver + */ ++ ++#endif /* MACH_S3C24XX_NAND_H */ +diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h +index cdcb2f8..623ddfb 100644 +--- a/arch/blackfin/include/asm/bitops.h ++++ b/arch/blackfin/include/asm/bitops.h +@@ -268,7 +268,10 @@ static __inline__ int find_next_zero_bit(void *addr, int size, int offset) + return result + ffz(tmp); + } + ++#include ++#include + #include ++#include + #include + + static __inline__ int ext2_set_bit(int nr, volatile void *addr) +diff --git a/arch/blackfin/include/asm/dma.h b/arch/blackfin/include/asm/dma.h +new file mode 100644 +index 0000000..27d269f +--- /dev/null ++++ b/arch/blackfin/include/asm/dma.h +@@ -0,0 +1,13 @@ ++/* ++ * Copyright (C) 2012 by Marc Kleine-Budde ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#ifndef __ASM_DMA_H ++#define __ASM_DMA_H ++ ++/* empty */ ++ ++#endif /* __ASM_DMA_H */ +diff --git a/arch/blackfin/lib/Makefile b/arch/blackfin/lib/Makefile +index 2f77318..cefb4dc 100644 +--- a/arch/blackfin/lib/Makefile ++++ b/arch/blackfin/lib/Makefile +@@ -8,6 +8,7 @@ obj-y += smulsi3_highpart.o + obj-y += umodsi3.o + obj-y += lshrdi3.o + obj-y += ashldi3.o ++obj-y += ashrdi3.o + obj-y += divsi3.o + obj-y += modsi3.o + obj-y += cpu.o +diff --git a/arch/blackfin/lib/ashrdi3.c b/arch/blackfin/lib/ashrdi3.c +new file mode 100644 +index 0000000..b5b351e +--- /dev/null ++++ b/arch/blackfin/lib/ashrdi3.c +@@ -0,0 +1,36 @@ ++/* ++ * Copyright 2004-2009 Analog Devices Inc. ++ * ++ * Licensed under the GPL-2 or later. ++ */ ++ ++#include "gcclib.h" ++ ++#ifdef CONFIG_ARITHMETIC_OPS_L1 ++DItype __ashrdi3(DItype u, word_type b)__attribute__((l1_text)); ++#endif ++ ++DItype __ashrdi3(DItype u, word_type b) ++{ ++ DIunion w; ++ word_type bm; ++ DIunion uu; ++ ++ if (b == 0) ++ return u; ++ ++ uu.ll = u; ++ ++ bm = (sizeof(SItype) * BITS_PER_UNIT) - b; ++ if (bm <= 0) { ++ /* w.s.high = 1..1 or 0..0 */ ++ w.s.high = uu.s.high >> (sizeof(SItype) * BITS_PER_UNIT - 1); ++ w.s.low = uu.s.high >> -bm; ++ } else { ++ USItype carries = (USItype) uu.s.high << bm; ++ w.s.high = uu.s.high >> b; ++ w.s.low = ((USItype) uu.s.low >> b) | carries; ++ } ++ ++ return w.ll; ++} +diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h +index 001ebf2..bf1ac6e 100644 +--- a/arch/mips/include/asm/bitops.h ++++ b/arch/mips/include/asm/bitops.h +@@ -28,5 +28,8 @@ + #define _ASM_MIPS_BITOPS_H_ + + #include ++#include ++#include ++#include + + #endif /* _ASM_MIPS_BITOPS_H_ */ +diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h +new file mode 100644 +index 0000000..27d269f +--- /dev/null ++++ b/arch/mips/include/asm/dma.h +@@ -0,0 +1,13 @@ ++/* ++ * Copyright (C) 2012 by Marc Kleine-Budde ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#ifndef __ASM_DMA_H ++#define __ASM_DMA_H ++ ++/* empty */ ++ ++#endif /* __ASM_DMA_H */ +diff --git a/arch/mips/mach-xburst/Kconfig b/arch/mips/mach-xburst/Kconfig +index 60e411c..c72b741 100644 +--- a/arch/mips/mach-xburst/Kconfig ++++ b/arch/mips/mach-xburst/Kconfig +@@ -12,6 +12,7 @@ choice + + config BOARD_RZX50 + bool "Ritmix RZX-50" ++ select HAS_POWEROFF + select CPU_JZ4755 + + endchoice +diff --git a/arch/mips/mach-xburst/csrc-jz4750.c b/arch/mips/mach-xburst/csrc-jz4750.c +index f625b70..36e401e 100644 +--- a/arch/mips/mach-xburst/csrc-jz4750.c ++++ b/arch/mips/mach-xburst/csrc-jz4750.c +@@ -28,7 +28,7 @@ + #include + #include + +-#define JZ_TIMER_CLOCK 40000 ++#define JZ_TIMER_CLOCK 24000000 + + static uint64_t jz4750_cs_read(void) + { +@@ -38,12 +38,13 @@ static uint64_t jz4750_cs_read(void) + static struct clocksource jz4750_cs = { + .read = jz4750_cs_read, + .mask = CLOCKSOURCE_MASK(32), +- .shift = 10, + }; + + static int clocksource_init(void) + { +- jz4750_cs.mult = clocksource_hz2mult(JZ_TIMER_CLOCK, jz4750_cs.shift); ++ clocks_calc_mult_shift(&jz4750_cs.mult, &jz4750_cs.shift, ++ JZ_TIMER_CLOCK, NSEC_PER_SEC, 10); ++ + init_clock(&jz4750_cs); + + __raw_writel(TCU_OSTCSR_PRESCALE1 | TCU_OSTCSR_EXT_EN, +diff --git a/arch/mips/mach-xburst/include/mach/jz4750d_regs.h b/arch/mips/mach-xburst/include/mach/jz4750d_regs.h +index 717493b..eafdd2f 100644 +--- a/arch/mips/mach-xburst/include/mach/jz4750d_regs.h ++++ b/arch/mips/mach-xburst/include/mach/jz4750d_regs.h +@@ -15,6 +15,7 @@ + + #define TCU_BASE 0xb0002000 + #define WDT_BASE 0xb0002000 ++#define RTC_BASE 0xb0003000 + #define UART1_BASE 0xb0031000 + + /************************************************************************* +@@ -77,4 +78,34 @@ + + #define WDT_TCER_TCEN (1 << 0) + ++/************************************************************************* ++ * RTC ++ *************************************************************************/ ++#define RTC_RCR (RTC_BASE + 0x00) /* RTC Control Register */ ++#define RTC_RSR (RTC_BASE + 0x04) /* RTC Second Register */ ++#define RTC_RSAR (RTC_BASE + 0x08) /* RTC Second Alarm Register */ ++#define RTC_RGR (RTC_BASE + 0x0c) /* RTC Regulator Register */ ++ ++#define RTC_HCR (RTC_BASE + 0x20) /* Hibernate Control Register */ ++#define RTC_HWFCR (RTC_BASE + 0x24) /* Hibernate Wakeup Filter Counter Reg */ ++#define RTC_HRCR (RTC_BASE + 0x28) /* Hibernate Reset Counter Register */ ++#define RTC_HWCR (RTC_BASE + 0x2c) /* Hibernate Wakeup Control Register */ ++#define RTC_HWRSR (RTC_BASE + 0x30) /* Hibernate Wakeup Status Register */ ++#define RTC_HSPR (RTC_BASE + 0x34) /* Hibernate Scratch Pattern Register */ ++ ++/* RTC Control Register */ ++#define RTC_RCR_WRDY_BIT 7 ++#define RTC_RCR_WRDY (1 << 7) /* Write Ready Flag */ ++#define RTC_RCR_1HZ_BIT 6 ++#define RTC_RCR_1HZ (1 << RTC_RCR_1HZ_BIT) /* 1Hz Flag */ ++#define RTC_RCR_1HZIE (1 << 5) /* 1Hz Interrupt Enable */ ++#define RTC_RCR_AF_BIT 4 ++#define RTC_RCR_AF (1 << RTC_RCR_AF_BIT) /* Alarm Flag */ ++#define RTC_RCR_AIE (1 << 3) /* Alarm Interrupt Enable */ ++#define RTC_RCR_AE (1 << 2) /* Alarm Enable */ ++#define RTC_RCR_RTCE (1 << 0) /* RTC Enable */ ++ ++/* Hibernate Control Register */ ++#define RTC_HCR_PD (1 << 0) /* Power Down */ ++ + #endif /* __JZ4750D_REGS_H__ */ +diff --git a/arch/mips/mach-xburst/reset-jz4750.c b/arch/mips/mach-xburst/reset-jz4750.c +index 3540ca9..765c033 100644 +--- a/arch/mips/mach-xburst/reset-jz4750.c ++++ b/arch/mips/mach-xburst/reset-jz4750.c +@@ -29,6 +29,19 @@ + + #define JZ_EXTAL 24000000 + ++static void __noreturn jz4750d_halt(void) ++{ ++ while (1) { ++ __asm__(".set push;\n" ++ ".set mips3;\n" ++ "wait;\n" ++ ".set pop;\n" ++ ); ++ } ++ ++ unreachable(); ++} ++ + void __noreturn reset_cpu(ulong addr) + { + __raw_writew(WDT_TCSR_PRESCALE4 | WDT_TCSR_EXT_EN, (u16 *)WDT_TCSR); +@@ -44,3 +57,18 @@ void __noreturn reset_cpu(ulong addr) + unreachable(); + } + EXPORT_SYMBOL(reset_cpu); ++ ++void __noreturn poweroff() ++{ ++ u32 ctrl; ++ ++ shutdown_barebox(); ++ ++ do { ++ ctrl = readl((u32 *)RTC_RCR); ++ } while (!(ctrl & RTC_RCR_WRDY)); ++ ++ writel(RTC_HCR_PD, (u32 *)RTC_HCR); ++ jz4750d_halt(); ++} ++EXPORT_SYMBOL(poweroff); +diff --git a/arch/nios2/boards/generic/generic.c b/arch/nios2/boards/generic/generic.c +index b51b94a..2c998fe 100644 +--- a/arch/nios2/boards/generic/generic.c ++++ b/arch/nios2/boards/generic/generic.c +@@ -9,17 +9,17 @@ static int phy_address = 1; + static struct resource mac_resources[] = { + [0] = { + .start = NIOS_SOPC_TSE_BASE, +- .size = 0x400, ++ .end = NIOS_SOPC_TSE_BASE + 0x400 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = NIOS_SOPC_SGDMA_RX_BASE, +- .size = 0x40, ++ .end = 0x40 + NIOS_SOPC_SGDMA_RX_BASE - 1, + .flags = IORESOURCE_MEM, + }, + [2] = { + .start = NIOS_SOPC_SGDMA_TX_BASE, +- .size = 0x40, ++ .end = 0x40 + NIOS_SOPC_SGDMA_TX_BASE - 1, + .flags = IORESOURCE_MEM, + }, + }; +diff --git a/arch/nios2/include/asm/bitops.h b/arch/nios2/include/asm/bitops.h +index ab0e3d5..0712845 100644 +--- a/arch/nios2/include/asm/bitops.h ++++ b/arch/nios2/include/asm/bitops.h +@@ -1,4 +1,9 @@ + #ifndef _ASM_BITOPS_H + #define _ASM_BITOPS_H + ++#include ++#include ++#include ++#include ++ + #endif /* _ASM_BITOPS_H */ +diff --git a/arch/nios2/include/asm/dma-mapping.h b/arch/nios2/include/asm/dma-mapping.h +index 5b70f4c..9819a97 100644 +--- a/arch/nios2/include/asm/dma-mapping.h ++++ b/arch/nios2/include/asm/dma-mapping.h +@@ -1,8 +1,12 @@ + #ifndef __ASM_NIOS2_DMA_MAPPING_H + #define __ASM_NIOS2_DMA_MAPPING_H + ++#include ++#include ++ + #include + ++ + /* dma_alloc_coherent() return cache-line aligned allocation which is mapped + * to uncached io region. + * +@@ -22,4 +26,10 @@ static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) + return (void *)(*handle | IO_REGION_BASE); + } + ++#define dma_alloc dma_alloc ++static inline void *dma_alloc(size_t size) ++{ ++ return xmemalign(DCACHE_LINE_SIZE, ALIGN(size, DCACHE_LINE_SIZE)); ++} ++ + #endif /* __ASM_NIOS2_DMA_MAPPING_H */ +diff --git a/arch/nios2/include/asm/dma.h b/arch/nios2/include/asm/dma.h +new file mode 100644 +index 0000000..8f709d2 +--- /dev/null ++++ b/arch/nios2/include/asm/dma.h +@@ -0,0 +1,8 @@ ++/* ++ * Copyright (C) 2012 by Marc Kleine-Budde ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#include +diff --git a/arch/openrisc/Makefile b/arch/openrisc/Makefile +index fd8bbbf..1f4b175 100644 +--- a/arch/openrisc/Makefile ++++ b/arch/openrisc/Makefile +@@ -1,5 +1,7 @@ + CPPFLAGS += -D__OR1K__ -ffixed-r10 -mhard-mul -mhard-div + ++LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) ++ + board-$(CONFIG_GENERIC) := generic + + KALLSYMS += --symbol-prefix=_ +@@ -18,4 +20,6 @@ common-y += $(BOARD) + common-y += arch/openrisc/lib/ + common-y += arch/openrisc/cpu/ + ++common-y += $(LIBGCC) ++ + lds-y += arch/openrisc/cpu/barebox.lds +diff --git a/arch/openrisc/include/asm/dma.h b/arch/openrisc/include/asm/dma.h +new file mode 100644 +index 0000000..27d269f +--- /dev/null ++++ b/arch/openrisc/include/asm/dma.h +@@ -0,0 +1,13 @@ ++/* ++ * Copyright (C) 2012 by Marc Kleine-Budde ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#ifndef __ASM_DMA_H ++#define __ASM_DMA_H ++ ++/* empty */ ++ ++#endif /* __ASM_DMA_H */ +diff --git a/arch/ppc/include/asm/dma.h b/arch/ppc/include/asm/dma.h +new file mode 100644 +index 0000000..27d269f +--- /dev/null ++++ b/arch/ppc/include/asm/dma.h +@@ -0,0 +1,13 @@ ++/* ++ * Copyright (C) 2012 by Marc Kleine-Budde ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#ifndef __ASM_DMA_H ++#define __ASM_DMA_H ++ ++/* empty */ ++ ++#endif /* __ASM_DMA_H */ +diff --git a/arch/ppc/mach-mpc85xx/include/mach/clocks.h b/arch/ppc/mach-mpc85xx/include/mach/clocks.h +index 9477168..2ab367b 100644 +--- a/arch/ppc/mach-mpc85xx/include/mach/clocks.h ++++ b/arch/ppc/mach-mpc85xx/include/mach/clocks.h +@@ -10,8 +10,6 @@ struct sys_info { + unsigned long freqLocalBus; + }; + +-#define NSEC_PER_SEC 1000000000L +- + unsigned long fsl_get_bus_freq(ulong dummy); + unsigned long fsl_get_timebase_clock(void); + void fsl_get_sys_info(struct sys_info *sysInfo); +diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c +index 90a9741..96fa100 100644 +--- a/arch/sandbox/board/hostfile.c ++++ b/arch/sandbox/board/hostfile.c +@@ -34,7 +34,7 @@ struct hf_priv { + struct hf_platform_data *pdata; + }; + +-static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, ulong offset, ulong flags) ++static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, loff_t offset, ulong flags) + { + struct hf_platform_data *hf = cdev->priv; + int fd = hf->fd; +@@ -45,7 +45,7 @@ static ssize_t hf_read(struct cdev *cdev, void *buf, size_t count, ulong offset, + return linux_read(fd, buf, count); + } + +-static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, ulong offset, ulong flags) ++static ssize_t hf_write(struct cdev *cdev, const void *buf, size_t count, loff_t offset, ulong flags) + { + struct hf_platform_data *hf = cdev->priv; + int fd = hf->fd; +diff --git a/arch/sandbox/include/asm/dma.h b/arch/sandbox/include/asm/dma.h +new file mode 100644 +index 0000000..4595367 +--- /dev/null ++++ b/arch/sandbox/include/asm/dma.h +@@ -0,0 +1,13 @@ ++/* ++ * Copyright (C) 2012 by Marc Kleine-Budde ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#ifndef __ASM_DMA_H ++#define __ASM_DMA_H ++ ++/* empty*/ ++ ++#endif /* __ASM_DMA_H */ +diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h +index b43afa3..830b1a5 100644 +--- a/arch/x86/include/asm/bitops.h ++++ b/arch/x86/include/asm/bitops.h +@@ -27,6 +27,11 @@ + #ifndef _ASM_X86_BITOPS_H_ + #define _ASM_X86_BITOPS_H_ + +-/* nothing special yet */ ++#define BITS_PER_LONG 32 ++ ++#include ++#include ++#include ++#include + + #endif /* _ASM_X86_BITOPS_H_ */ +diff --git a/arch/x86/include/asm/dma.h b/arch/x86/include/asm/dma.h +new file mode 100644 +index 0000000..27d269f +--- /dev/null ++++ b/arch/x86/include/asm/dma.h +@@ -0,0 +1,13 @@ ++/* ++ * Copyright (C) 2012 by Marc Kleine-Budde ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#ifndef __ASM_DMA_H ++#define __ASM_DMA_H ++ ++/* empty */ ++ ++#endif /* __ASM_DMA_H */ +diff --git a/commands/Kconfig b/commands/Kconfig +index 52e1f17..2478e3f 100644 +--- a/commands/Kconfig ++++ b/commands/Kconfig +@@ -6,6 +6,10 @@ config COMMAND_SUPPORT + depends on !SHELL_NONE + default y + ++config HAS_POWEROFF ++ bool ++ default n ++ + if COMMAND_SUPPORT + + menu "commands " +@@ -25,6 +29,10 @@ config CMD_SLEEP + tristate + prompt "sleep" + ++config CMD_MSLEEP ++ tristate ++ prompt "msleep" ++ + config CMD_SAVEENV + tristate + select ENV_HANDLING +@@ -198,6 +206,20 @@ config CMD_AUTOMOUNT + this directory available (discover USB devices, bring network interface + up and finally mount the filesystem). + ++config CMD_BASENAME ++ tristate ++ prompt "basename" ++ help ++ Strip directory and suffix from filenames and store the result in a ++ environment variable ++ ++config CMD_DIRNAME ++ tristate ++ prompt "dirname" ++ help ++ Strip last component of file name and store the result in a ++ environment variable ++ + endmenu + + menu "console " +@@ -422,6 +444,11 @@ config CMD_RESET + tristate + prompt "reset" + ++config CMD_POWEROFF ++ tristate ++ depends on HAS_POWEROFF ++ prompt "poweroff" ++ + config CMD_GO + tristate + prompt "go" +@@ -552,6 +579,25 @@ config CMD_USB + help + The usb command allows to rescan for USB devices. + ++menuconfig CMD_WD ++ bool ++ depends on WATCHDOG ++ prompt "wd command " ++ help ++ The 'wd' command which allows to start, stop and trigger the onboard ++ watchdog. ++ ++if CMD_WD ++ ++config CMD_WD_DEFAULT_TIMOUT ++ int ++ prompt "default timeout" ++ help ++ Define the default timeout value in [seconds] if the first call of ++ 'wd' is done without a timeout value (which means the watchdog gets ++ enabled and re-triggered with the default timeout value). ++endif ++ + endmenu + + endif +diff --git a/commands/Makefile b/commands/Makefile +index 4c8a0a9..54191b4 100644 +--- a/commands/Makefile ++++ b/commands/Makefile +@@ -1,3 +1,4 @@ ++obj-y += stddev.o + obj-$(CONFIG_CMD_BOOTM) += bootm.o + obj-$(CONFIG_CMD_UIMAGE) += uimage.o + obj-$(CONFIG_CMD_LINUX16) += linux16.o +@@ -10,7 +11,9 @@ obj-$(CONFIG_CMD_MTEST) += memtest.o + obj-$(CONFIG_CMD_EDIT) += edit.o + obj-$(CONFIG_CMD_EXEC) += exec.o + obj-$(CONFIG_CMD_SLEEP) += sleep.o ++obj-$(CONFIG_CMD_MSLEEP) += msleep.o + obj-$(CONFIG_CMD_RESET) += reset.o ++obj-$(CONFIG_CMD_POWEROFF) += poweroff.o + obj-$(CONFIG_CMD_GO) += go.o + obj-$(CONFIG_NET) += net.o + obj-$(CONFIG_CMD_PARTITION) += partition.o +@@ -57,6 +60,7 @@ obj-$(CONFIG_CMD_MENU) += menu.o + obj-$(CONFIG_CMD_PASSWD) += passwd.o + obj-$(CONFIG_CMD_LOGIN) += login.o + obj-$(CONFIG_CMD_LED) += led.o ++obj-$(CONFIG_CMD_WD) += wd.o + obj-$(CONFIG_CMD_LED_TRIGGER) += trigger.o + obj-$(CONFIG_CMD_USB) += usb.o + obj-$(CONFIG_CMD_TIME) += time.o +@@ -66,3 +70,5 @@ obj-$(CONFIG_CMD_IOMEM) += iomem.o + obj-$(CONFIG_CMD_LINUX_EXEC) += linux_exec.o + obj-$(CONFIG_CMD_AUTOMOUNT) += automount.o + obj-$(CONFIG_CMD_GLOBAL) += global.o ++obj-$(CONFIG_CMD_BASENAME) += basename.o ++obj-$(CONFIG_CMD_DIRNAME) += dirname.o +diff --git a/commands/basename.c b/commands/basename.c +new file mode 100644 +index 0000000..b47ff8c +--- /dev/null ++++ b/commands/basename.c +@@ -0,0 +1,47 @@ ++/* ++ * basename.c - strip directory and suffix from filenames ++ * ++ * Copyright (c) 2012 Sascha Hauer , Pengutronix ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++ ++static int do_basename(int argc, char *argv[]) ++{ ++ if (argc != 3) ++ return COMMAND_ERROR_USAGE; ++ ++ setenv(argv[2], basename(argv[1])); ++ ++ return 0; ++} ++ ++BAREBOX_CMD_HELP_START(basename) ++BAREBOX_CMD_HELP_USAGE("basename NAME BASENAME\n") ++BAREBOX_CMD_HELP_SHORT("strip NAME and store into $BASENAME\n") ++BAREBOX_CMD_HELP_END ++ ++BAREBOX_CMD_START(basename) ++ .cmd = do_basename, ++ .usage = "strip directory and suffix from filenames", ++ BAREBOX_CMD_HELP(cmd_basename_help) ++BAREBOX_CMD_END +diff --git a/commands/bootm.c b/commands/bootm.c +index 2989d39..3c47ab5 100644 +--- a/commands/bootm.c ++++ b/commands/bootm.c +@@ -383,8 +383,7 @@ static int do_bootm(int argc, char *argv[]) + if (data.os_res) + printf("OS image is at 0x%08x-0x%08x\n", + data.os_res->start, +- data.os_res->start + +- data.os_res->size - 1); ++ data.os_res->end); + else + printf("OS image not yet relocated\n"); + +@@ -399,8 +398,7 @@ static int do_bootm(int argc, char *argv[]) + if (data.initrd_res) + printf("initrd is at 0x%08x-0x%08x\n", + data.initrd_res->start, +- data.initrd_res->start + +- data.initrd_res->size - 1); ++ data.initrd_res->end); + else + printf("initrd image not yet relocated\n"); + } +diff --git a/commands/crc.c b/commands/crc.c +index df22941..8f80e42 100644 +--- a/commands/crc.c ++++ b/commands/crc.c +@@ -47,9 +47,12 @@ static int file_crc(char* filename, ulong start, ulong size, ulong *crc, + } + + if (start > 0) { +- ret = lseek(fd, start, SEEK_SET); +- if (ret == -1) { ++ off_t lseek_ret; ++ errno = 0; ++ lseek_ret = lseek(fd, start, SEEK_SET); ++ if (lseek_ret == (off_t)-1 && errno) { + perror("lseek"); ++ ret = -1; + goto out; + } + } +@@ -84,8 +87,8 @@ out: + + static int do_crc(int argc, char *argv[]) + { +- ulong start = 0, size = ~0, total = 0; +- ulong crc = 0, vcrc = 0; ++ loff_t start = 0, size = ~0; ++ ulong crc = 0, vcrc = 0, total = 0; + char *filename = "/dev/mem"; + #ifdef CONFIG_CMD_CRC_CMP + char *vfilename = NULL; +diff --git a/commands/digest.c b/commands/digest.c +index 8432914..07cbec9 100644 +--- a/commands/digest.c ++++ b/commands/digest.c +@@ -51,7 +51,7 @@ static int do_digest(char *algorithm, int argc, char *argv[]) + argv++; + while (*argv) { + char *filename = "/dev/mem"; +- ulong start = 0, size = ~0; ++ loff_t start = 0, size = ~0; + + /* arguments are either file, file+area or area */ + if (parse_area_spec(*argv, &start, &size)) { +@@ -66,7 +66,7 @@ static int do_digest(char *algorithm, int argc, char *argv[]) + for (i = 0; i < d->length; i++) + printf("%02x", hash[i]); + +- printf(" %s\t0x%08lx ... 0x%08lx\n", filename, start, start + size); ++ printf(" %s\t0x%08llx ... 0x%08llx\n", filename, start, start + size); + + argv++; + } +diff --git a/commands/dirname.c b/commands/dirname.c +new file mode 100644 +index 0000000..cf1d0a0 +--- /dev/null ++++ b/commands/dirname.c +@@ -0,0 +1,47 @@ ++/* ++ * dirname.c - strip directory and suffix from filenames ++ * ++ * Copyright (c) 2012 Sascha Hauer , Pengutronix ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++ ++static int do_dirname(int argc, char *argv[]) ++{ ++ if (argc != 3) ++ return COMMAND_ERROR_USAGE; ++ ++ setenv(argv[2], dirname(argv[1])); ++ ++ return 0; ++} ++ ++BAREBOX_CMD_HELP_START(dirname) ++BAREBOX_CMD_HELP_USAGE("dirname NAME DIRNAME\n") ++BAREBOX_CMD_HELP_SHORT("strip last componext of NAME and store into $DIRNAME\n") ++BAREBOX_CMD_HELP_END ++ ++BAREBOX_CMD_START(dirname) ++ .cmd = do_dirname, ++ .usage = "strip last component from file name", ++ BAREBOX_CMD_HELP(cmd_dirname_help) ++BAREBOX_CMD_END +diff --git a/commands/flash.c b/commands/flash.c +index 1fcb1cf..d71349a 100644 +--- a/commands/flash.c ++++ b/commands/flash.c +@@ -41,7 +41,7 @@ static int do_flerase(int argc, char *argv[]) + int fd; + char *filename = NULL; + struct stat s; +- unsigned long start = 0, size = ~0; ++ loff_t start = 0, size = ~0; + int ret = 0; + + if (argc == 1) +@@ -109,7 +109,7 @@ static int do_protect(int argc, char *argv[]) + char *filename = NULL; + struct stat s; + int prot = 1; +- unsigned long start = 0, size = ~0; ++ loff_t start = 0, size = ~0; + int ret = 0, err; + + if (argc == 1) +diff --git a/commands/go.c b/commands/go.c +index e9e9d40..14569a5 100644 +--- a/commands/go.c ++++ b/commands/go.c +@@ -92,5 +92,5 @@ BAREBOX_CMD_START(go) + .cmd = do_go, + .usage = "start application at address or file", + BAREBOX_CMD_HELP(cmd_go_help) +- BAREBOX_CMD_COMPLETE(cammand_var_complete) ++ BAREBOX_CMD_COMPLETE(command_var_complete) + BAREBOX_CMD_END +diff --git a/commands/iomem.c b/commands/iomem.c +index 70355fd..c22878c 100644 +--- a/commands/iomem.c ++++ b/commands/iomem.c +@@ -32,8 +32,7 @@ static void __print_resources(struct resource *res, int indent) + + printf(PRINTF_CONVERSION_RESOURCE " - " PRINTF_CONVERSION_RESOURCE + " (size " PRINTF_CONVERSION_RESOURCE ") %s\n", res->start, +- res->start + res->size - 1, +- res->size, res->name); ++ res->end, resource_size(res), res->name); + + list_for_each_entry(r, &res->children, sibling) + __print_resources(r, indent + 1); +diff --git a/commands/ls.c b/commands/ls.c +index ad609f3..fbcbadc 100644 +--- a/commands/ls.c ++++ b/commands/ls.c +@@ -35,7 +35,7 @@ static void ls_one(const char *path, struct stat *s) + unsigned int namelen = strlen(path); + + mkmodestr(s->st_mode, modestr); +- printf("%s %10lu %*.*s\n", modestr, s->st_size, namelen, namelen, path); ++ printf("%s %10llu %*.*s\n", modestr, s->st_size, namelen, namelen, path); + } + + int ls(const char *path, ulong flags) +diff --git a/commands/mem.c b/commands/mem.c +index 080bfde..5322def 100644 +--- a/commands/mem.c ++++ b/commands/mem.c +@@ -43,7 +43,7 @@ + #define PRINTF(fmt,args...) + #endif + +-#define RW_BUF_SIZE (ulong)4096 ++#define RW_BUF_SIZE 4096 + static char *rw_buf; + + static char *DEVMEM = "/dev/mem"; +@@ -55,7 +55,7 @@ static char *DEVMEM = "/dev/mem"; + */ + #define DISP_LINE_LEN 16 + +-int memory_display(char *addr, ulong offs, ulong nbytes, int size) ++int memory_display(char *addr, loff_t offs, ulong nbytes, int size) + { + ulong linebytes, i; + u_char *cp; +@@ -72,7 +72,7 @@ int memory_display(char *addr, ulong offs, ulong nbytes, int size) + u_char *ucp = (u_char *)linebuf; + uint count = 52; + +- printf("%08lx:", offs); ++ printf("%08llx:", offs); + linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes; + + for (i = 0; i < linebytes; i += size) { +@@ -108,7 +108,7 @@ int memory_display(char *addr, ulong offs, ulong nbytes, int size) + return 0; + } + +-static int open_and_lseek(const char *filename, int mode, off_t pos) ++static int open_and_lseek(const char *filename, int mode, loff_t pos) + { + int fd, ret; + +@@ -163,7 +163,7 @@ static int mem_parse_options(int argc, char *argv[], char *optstr, int *mode, + + static int do_mem_md(int argc, char *argv[]) + { +- ulong start = 0, size = 0x100; ++ loff_t start = 0, size = 0x100; + int r, now; + int ret = 0; + int fd; +@@ -180,6 +180,8 @@ static int do_mem_md(int argc, char *argv[]) + } + if (size == ~0) + size = 0x100; ++ } else { ++ return COMMAND_ERROR_USAGE; + } + + fd = open_and_lseek(filename, mode | O_RDONLY, start); +@@ -187,7 +189,7 @@ static int do_mem_md(int argc, char *argv[]) + return 1; + + do { +- now = min(size, RW_BUF_SIZE); ++ now = min(size, (loff_t)RW_BUF_SIZE); + r = read(fd, rw_buf, now); + if (r < 0) { + perror("read"); +@@ -240,7 +242,7 @@ static int do_mem_mw(int argc, char *argv[]) + int fd; + char *filename = DEVMEM; + int mode = O_RWSIZE_4; +- ulong adr; ++ loff_t adr; + + if (mem_parse_options(argc, argv, "bwld:", &mode, NULL, &filename) < 0) + return 1; +@@ -248,7 +250,7 @@ static int do_mem_mw(int argc, char *argv[]) + if (optind + 1 >= argc) + return COMMAND_ERROR_USAGE; + +- adr = strtoul_suffix(argv[optind++], NULL, 0); ++ adr = strtoull_suffix(argv[optind++], NULL, 0); + + fd = open_and_lseek(filename, mode | O_WRONLY, adr); + if (fd < 0) +@@ -300,7 +302,7 @@ BAREBOX_CMD_END + + static int do_mem_cmp(int argc, char *argv[]) + { +- ulong addr1, addr2, count = ~0; ++ loff_t addr1, addr2, count = ~0; + int mode = O_RWSIZE_1; + char *sourcefile = DEVMEM; + char *destfile = DEVMEM; +@@ -316,8 +318,8 @@ static int do_mem_cmp(int argc, char *argv[]) + if (optind + 2 > argc) + return COMMAND_ERROR_USAGE; + +- addr1 = strtoul_suffix(argv[optind], NULL, 0); +- addr2 = strtoul_suffix(argv[optind + 1], NULL, 0); ++ addr1 = strtoull_suffix(argv[optind], NULL, 0); ++ addr2 = strtoull_suffix(argv[optind + 1], NULL, 0); + + if (optind + 2 == argc) { + if (sourcefile == DEVMEM) { +@@ -330,7 +332,7 @@ static int do_mem_cmp(int argc, char *argv[]) + } + count = statbuf.st_size - addr1; + } else { +- count = strtoul_suffix(argv[optind + 2], NULL, 0); ++ count = strtoull_suffix(argv[optind + 2], NULL, 0); + } + + sourcefd = open_and_lseek(sourcefile, mode | O_RDONLY, addr1); +@@ -348,7 +350,7 @@ static int do_mem_cmp(int argc, char *argv[]) + while (count > 0) { + int now, r1, r2, i; + +- now = min(RW_BUF_SIZE, count); ++ now = min((loff_t)RW_BUF_SIZE, count); + + r1 = read(sourcefd, rw_buf, now); + if (r1 < 0) { +@@ -409,8 +411,7 @@ BAREBOX_CMD_END + + static int do_mem_cp(int argc, char *argv[]) + { +- ulong count; +- ulong dest, src; ++ loff_t count, dest, src; + char *sourcefile = DEVMEM; + char *destfile = DEVMEM; + int sourcefd, destfd; +@@ -424,8 +425,8 @@ static int do_mem_cp(int argc, char *argv[]) + if (optind + 2 > argc) + return COMMAND_ERROR_USAGE; + +- src = strtoul_suffix(argv[optind], NULL, 0); +- dest = strtoul_suffix(argv[optind + 1], NULL, 0); ++ src = strtoull_suffix(argv[optind], NULL, 0); ++ dest = strtoull_suffix(argv[optind + 1], NULL, 0); + + if (optind + 2 == argc) { + if (sourcefile == DEVMEM) { +@@ -438,7 +439,7 @@ static int do_mem_cp(int argc, char *argv[]) + } + count = statbuf.st_size - src; + } else { +- count = strtoul_suffix(argv[optind + 2], NULL, 0); ++ count = strtoull_suffix(argv[optind + 2], NULL, 0); + } + + sourcefd = open_and_lseek(sourcefile, mode | O_RDONLY, src); +@@ -454,7 +455,7 @@ static int do_mem_cp(int argc, char *argv[]) + while (count > 0) { + int now, r, w, tmp; + +- now = min(RW_BUF_SIZE, count); ++ now = min((loff_t)RW_BUF_SIZE, count); + + r = read(sourcefd, rw_buf, now); + if (r < 0) { +@@ -516,7 +517,7 @@ BAREBOX_CMD_END + + static int do_memset(int argc, char *argv[]) + { +- ulong s, c, n; ++ loff_t s, c, n; + int fd; + char *buf; + int mode = O_RWSIZE_1; +@@ -529,9 +530,9 @@ static int do_memset(int argc, char *argv[]) + if (optind + 3 > argc) + return COMMAND_ERROR_USAGE; + +- s = strtoul_suffix(argv[optind], NULL, 0); +- c = strtoul_suffix(argv[optind + 1], NULL, 0); +- n = strtoul_suffix(argv[optind + 2], NULL, 0); ++ s = strtoull_suffix(argv[optind], NULL, 0); ++ c = strtoull_suffix(argv[optind + 1], NULL, 0); ++ n = strtoull_suffix(argv[optind + 2], NULL, 0); + + fd = open_and_lseek(file, mode | O_WRONLY, s); + if (fd < 0) +@@ -543,7 +544,7 @@ static int do_memset(int argc, char *argv[]) + while (n > 0) { + int now; + +- now = min(RW_BUF_SIZE, n); ++ now = min((loff_t)RW_BUF_SIZE, n); + + ret = write(fd, buf, now); + if (ret < 0) { +@@ -594,7 +595,7 @@ static int mem_probe(struct device_d *dev) + dev->priv = cdev; + + cdev->name = (char*)dev->resource[0].name; +- cdev->size = (unsigned long)dev->resource[0].size; ++ cdev->size = (unsigned long)resource_size(&dev->resource[0]); + cdev->ops = &memops; + cdev->dev = dev; + +@@ -623,32 +624,3 @@ static int mem_init(void) + } + + device_initcall(mem_init); +- +-static ssize_t zero_read(struct cdev *cdev, void *buf, size_t count, ulong offset, ulong flags) +-{ +- memset(buf, 0, count); +- return count; +-} +- +-static struct file_operations zeroops = { +- .read = zero_read, +- .lseek = dev_lseek_default, +-}; +- +-static int zero_init(void) +-{ +- struct cdev *cdev; +- +- cdev = xzalloc(sizeof (*cdev)); +- +- cdev->name = "zero"; +- cdev->size = ~0; +- cdev->ops = &zeroops; +- +- devfs_create(cdev); +- +- return 0; +-} +- +-device_initcall(zero_init); +- +diff --git a/commands/msleep.c b/commands/msleep.c +new file mode 100644 +index 0000000..c9fa23c +--- /dev/null ++++ b/commands/msleep.c +@@ -0,0 +1,40 @@ ++/* ++ * msleep.c - delay execution for n milliseconds ++ * ++ * Copyright (c) 2012 Steffen Trumtrar , Pengutronix ++ * ++ * derived from commands/sleep.c ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ */ ++ ++#include ++#include ++#include ++ ++static int do_msleep(int argc, char *argv[]) ++{ ++ ulong delay; ++ ++ if (argc != 2) ++ return COMMAND_ERROR_USAGE; ++ ++ delay = simple_strtoul(argv[1], NULL, 10); ++ ++ mdelay(delay); ++ ++ return 0; ++} ++ ++BAREBOX_CMD_START(msleep) ++ .cmd = do_msleep, ++ .usage = "delay execution for n milliseconds", ++BAREBOX_CMD_END +diff --git a/commands/nand.c b/commands/nand.c +index 34aa07b..6124dae 100644 +--- a/commands/nand.c ++++ b/commands/nand.c +@@ -79,6 +79,7 @@ static int do_nand(int argc, char *argv[]) + if (command & NAND_MARKBAD) { + if (optind < argc) { + int ret = 0, fd; ++ loff_t __badblock = badblock; + + printf("marking block at 0x%08x on %s as bad\n", badblock, argv[optind]); + +@@ -88,7 +89,7 @@ static int do_nand(int argc, char *argv[]) + return 1; + } + +- ret = ioctl(fd, MEMSETBADBLOCK, (void *)badblock); ++ ret = ioctl(fd, MEMSETBADBLOCK, &__badblock); + if (ret) + perror("ioctl"); + +diff --git a/commands/nandtest.c b/commands/nandtest.c +index d923e42..06b7f94 100644 +--- a/commands/nandtest.c ++++ b/commands/nandtest.c +@@ -307,11 +307,11 @@ static int do_nandtest(int argc, char *argv[]) + for (test_ofs = flash_offset; + test_ofs < flash_offset+length; + test_ofs += meminfo.erasesize) { +- ++ loff_t __test_ofs = test_ofs; + srand(seed); + seed = rand(); + +- if (ioctl(fd, MEMGETBADBLOCK, (void *)test_ofs)) { ++ if (ioctl(fd, MEMGETBADBLOCK, &__test_ofs)) { + printf("\rBad block at 0x%08x\n", + (unsigned)(test_ofs + + memregion.offset)); +diff --git a/commands/net.c b/commands/net.c +index a453f4e..e77f12f 100644 +--- a/commands/net.c ++++ b/commands/net.c +@@ -36,35 +36,6 @@ + #include + #include + +-#ifdef CONFIG_NET_RARP +-extern void RarpRequest(void); +- +-static int do_rarpb(int argc, char *argv[]) +-{ +- int size; +- +- if (NetLoopInit(RARP) < 0) +- return 1; +- +- NetOurIP = 0; +- RarpRequest(); /* Basically same as BOOTP */ +- +- if ((size = NetLoop()) < 0) +- return 1; +- +- /* NetLoop ok, update environment */ +- netboot_update_env(); +- +- return 0; +-} +- +-BAREBOX_CMD_START(rarpboot) +- .cmd = do_rarpb, +- .usage = "boot image via network using rarp/tftp protocol", +- BAREBOX_CMD_HELP("[loadAddress] [bootfilename]\n") +-BAREBOX_CMD_END +-#endif /* CONFIG_NET_RARP */ +- + static int do_ethact(int argc, char *argv[]) + { + struct eth_device *edev; +diff --git a/commands/poweroff.c b/commands/poweroff.c +new file mode 100644 +index 0000000..ebb146c +--- /dev/null ++++ b/commands/poweroff.c +@@ -0,0 +1,37 @@ ++/* ++ * poweroff.c - turn board's power off ++ * ++ * Copyright (C) 2011 Antony Pavlov ++ * ++ * This file is part of barebox. ++ * See file CREDITS for list of people who contributed to this project. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++static int cmd_poweroff(int argc, char *argv[]) ++{ ++ poweroff(); ++ ++ /* Not reached */ ++ return 1; ++} ++ ++BAREBOX_CMD_START(poweroff) ++ .cmd = cmd_poweroff, ++ .usage = "Perform POWER OFF of the board", ++BAREBOX_CMD_END +diff --git a/commands/sleep.c b/commands/sleep.c +index c5f7867..950ec08 100644 +--- a/commands/sleep.c ++++ b/commands/sleep.c +@@ -47,5 +47,5 @@ static int do_sleep(int argc, char *argv[]) + BAREBOX_CMD_START(sleep) + .cmd = do_sleep, + .usage = "delay execution for n seconds", +- BAREBOX_CMD_COMPLETE(cammand_var_complete) ++ BAREBOX_CMD_COMPLETE(command_var_complete) + BAREBOX_CMD_END +diff --git a/commands/stddev.c b/commands/stddev.c +new file mode 100644 +index 0000000..098aea8 +--- /dev/null ++++ b/commands/stddev.c +@@ -0,0 +1,106 @@ ++/* ++ * Copyright (c) 2011 Sascha Hauer , Pengutronix ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 ++ * as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++static ssize_t zero_read(struct cdev *cdev, void *buf, size_t count, loff_t offset, ulong flags) ++{ ++ memset(buf, 0, count); ++ return count; ++} ++ ++static struct file_operations zeroops = { ++ .read = zero_read, ++ .lseek = dev_lseek_default, ++}; ++ ++static int zero_init(void) ++{ ++ struct cdev *cdev; ++ ++ cdev = xzalloc(sizeof (*cdev)); ++ ++ cdev->name = "zero"; ++ cdev->flags = DEVFS_IS_CHARACTER_DEV; ++ cdev->ops = &zeroops; ++ ++ devfs_create(cdev); ++ ++ return 0; ++} ++ ++device_initcall(zero_init); ++ ++static ssize_t full_read(struct cdev *cdev, void *buf, size_t count, loff_t offset, ulong flags) ++{ ++ memset(buf, 0xff, count); ++ return count; ++} ++ ++static struct file_operations fullops = { ++ .read = full_read, ++ .lseek = dev_lseek_default, ++}; ++ ++static int full_init(void) ++{ ++ struct cdev *cdev; ++ ++ cdev = xzalloc(sizeof (*cdev)); ++ ++ cdev->name = "full"; ++ cdev->flags = DEVFS_IS_CHARACTER_DEV; ++ cdev->ops = &fullops; ++ ++ devfs_create(cdev); ++ ++ return 0; ++} ++ ++device_initcall(full_init); ++ ++static ssize_t null_write(struct cdev *cdev, const void *buf, size_t count, loff_t offset, ulong flags) ++{ ++ return count; ++} ++ ++static struct file_operations nullops = { ++ .write = null_write, ++ .lseek = dev_lseek_default, ++}; ++ ++static int null_init(void) ++{ ++ struct cdev *cdev; ++ ++ cdev = xzalloc(sizeof (*cdev)); ++ ++ cdev->name = "null"; ++ cdev->flags = DEVFS_IS_CHARACTER_DEV; ++ cdev->ops = &nullops; ++ ++ devfs_create(cdev); ++ ++ return 0; ++} ++ ++device_initcall(null_init); +diff --git a/commands/wd.c b/commands/wd.c +new file mode 100644 +index 0000000..080bab9 +--- /dev/null ++++ b/commands/wd.c +@@ -0,0 +1,68 @@ ++/* ++ * (c) 2012 Juergen Beisert ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* default timeout in [sec] */ ++static unsigned timeout = CONFIG_CMD_WD_DEFAULT_TIMOUT; ++ ++static int do_wd(int argc, char *argv[]) ++{ ++ int rc; ++ ++ if (argc > 1) { ++ if (isdigit(*argv[1])) { ++ timeout = simple_strtoul(argv[1], NULL, 0); ++ } else { ++ printf("numerical parameter expected\n"); ++ return 1; ++ } ++ } ++ ++ rc = watchdog_set_timeout(timeout); ++ if (rc < 0) { ++ switch (rc) { ++ case -EINVAL: ++ printf("Timeout value out of range\n"); ++ break; ++ case -ENOSYS: ++ printf("Watchdog cannot be disabled\n"); ++ break; ++ default: ++ printf("Watchdog fails: '%s'\n", strerror(-rc)); ++ break; ++ } ++ ++ return 1; ++ } ++ ++ return 0; ++} ++ ++BAREBOX_CMD_HELP_START(wd) ++BAREBOX_CMD_HELP_USAGE("wd [