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| author | Philipp Zabel <p.zabel@pengutronix.de> | 2019-04-26 14:29:07 +0200 |
|---|---|---|
| committer | Philipp Zabel <p.zabel@pengutronix.de> | 2019-12-02 14:19:29 +0100 |
| commit | 8f1a0c9a351c84ff63d51d5b81f028751111854e (patch) | |
| tree | f3e951ad3b034674836788ebf3a7b2d7a8adb0e1 | |
| parent | 7e093a5ec0ea9ed0176a06e06f944e128476a853 (diff) | |
| download | linux-hantro/imx8m-wip.tar.gz linux-hantro/imx8m-wip.tar.xz | |
arm64: dts: imx8mq: enable Hantro G1/G2 VPUhantro/imx8m-wip
Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video
decoder cores and a reset/control block.
Hook up the bus clock to the VPU power domain to enable handshakes, and
configure the core clocks to 600 MHz and the bus clock to 800 MHz by
default.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 04115ca6bfb5..ed61594bc8c3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -577,6 +577,7 @@ pgc_vpu: power-domain@6 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_VPU>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; }; pgc_disp: power-domain@7 { @@ -1028,6 +1029,32 @@ status = "disabled"; }; + vpu: vpu@38300000 { + compatible = "nxp,imx8mq-vpu"; + reg = <0x38300000 0x10000>, + <0x38310000 0x10000>, + <0x38320000 0x10000>; + reg-names = "g1", "g2", "ctrl"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "g1", "g2", "bus"; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, + <&clk IMX8MQ_CLK_VPU_G2>, + <&clk IMX8MQ_CLK_VPU_BUS>, + <&clk IMX8MQ_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VPU_PLL>; + assigned-clock-rates = <600000000>, <600000000>, + <800000000>, <0>; + power-domains = <&pgc_vpu>; + }; + pcie0: pcie@33800000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33800000 0x400000>, |