WIP: arm/mxs: mx23evk: add bootlets supporttuxrail-b3

This patch is currently untested.

Not-Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Not-Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>

1 files changed, 274 insertions, 0 deletions

diff --git a/arch/arm/boards/freescale-mx23-evk/bootlets.c b/arch/arm/boards/freescale-mx23-evk/bootlets.c
new file mode 100644
index 00000000..066ddff3
--- /dev/null
+++ b/arch/arm/boards/freescale-mx23-evk/bootlets.c
@@ -0,0 +1,274 @@
+/*
+ * Freescale's i.MX23 EVK main setup bootlet
+ *
+ * Copyright 2011 Juergen Beisert, Pengutronix <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootlets.h>
+#include <arch.h>
+#include <sdram.h>
+#include <power.h>
+
+
+/**
+ * The mx23EVK restrictions:
+ * - the i.MX23 CPU comes in the 169 BGA package.
+ *
+ * From the datasheet:
+ *
+ *   VDDD    VDDD      CPU       AHB      EMI
+ *    [V]   Brown-out  CLK       CLK      CLK
+ *            [V]     [MHz]     [MHz]    [MHz]
+ * ---------------------------------------------
+ * | 1.050 | 0.975 |  24.00  |  24.00 |  24.00 |
+ * ---------------------------------------------
+ * | 1.050 | 0.975 |  64.00  |  64.00 |  64.00 |
+ * ---------------------------------------------
+ * | 1.275 | 1.175 | 261.82  | 130.91 | 130.91 |
+ * ---------------------------------------------
+ * | 1.375 | 1.275 | 360.00  | 120.00 | 120.00 |
+ * ---------------------------------------------
+ * | 1.475 | 1.375 | 392.73  | 196.36 | 130.91 |
+ * ---------------------------------------------
+ * | 1.550 | 1.450 | 454.74  | 151.58 | 130.91 |
+ * ---------------------------------------------
+ *
+ * The EMI uses two primary clocks: the AHB bus HCLK and the DRAM source clock
+ * EMI_CLK. The memory controller operates at frequencies that are asynchronous
+ * to the rest of the CPU.
+ *
+ **/
+
+/** SDRAM clock in [MHz] */
+#define SDRAM_CLK 131
+
+/*
+ * VDDIO: On the MX23EVK for CPU internal purposes only
+ * Note: the external USB network and HUB device use an external linear regulator
+ */
+static const struct rail_voltage mx23evk_vddio_voltage = {
+	.main_mV = 3300,
+	.guard_mV = 3300 - 175,
+	.lin_mV = 3300 - 25,	/* cannot be disabled */
+};
+
+/* VDDM: The FIXME is specified to 2.50 V +/- 200 mV */
+static const struct rail_voltage mx23evk_vddm_voltage = {
+	.main_mV = 2500,
+};
+
+/* VDDA: On the MX23EVK for CPU internal purposes only */
+static const struct rail_voltage mx23evk_vdda_voltage = {
+	.main_mV = 1800,
+	.guard_mV = 1800 - 175,
+	.lin_mV = 0,	/* disable linear regulator */
+};
+
+/* VDDD: On the MX23EVK for CPU internal purposes only (CPU core and
+ *       SDRAM controller)
+ * As we want the CPU continue running with 24 MHz, only 1.2 V
+ * are required for the SDRAM controller to run at 132 MHz
+ */
+static const struct rail_voltage mx23evk_vddd_voltage = {
+	.main_mV = 1200,
+	.guard_mV = 1200 - 100,
+	.lin_mV = 0,	/* disable linear regulator */
+};
+
+/* Key features of the used FIXME
+ * - CL2 @ 133 MHz
+ * - CL3 @ 200 MHz
+ * - 8k refresh lines @ 64 ms
+ * - Row: A0-A12
+ * - Collumn: A0-A9
+ * - tRAS lockout supported
+ *
+ * To run this memory at 133 MHz, VDDD must be at least at 1.2 V
+ */
+static const struct reg_val_pair mx23evk_sdram[] = {
+	{ .reg = EMI_CTRL, .val = 0x1c024040, },
+
+	{ .reg = DRAM_CTRL0, .val = 0x01010001, },
+	{ .reg = DRAM_CTRL1, .val = 0x00010100, },
+	{ .reg = DRAM_CTRL2, .val = 0x01000101, },
+	{ .reg = DRAM_CTRL3, .val = 0x00000001, },
+
+	{ .reg = DRAM_CTRL4, .val = 0x00000101, },
+	{ .reg = DRAM_CTRL5, .val = 0x00000000, },
+	{ .reg = DRAM_CTRL6, .val = 0x00010000, /*
+		- enable SDRAM clock */ },
+	{ .reg = DRAM_CTRL7, .val = 0x01000001, },
+	/* why not reg 8 now ? */
+	{ .reg = DRAM_CTRL9, .val = 0x00000001, },
+	{ .reg = DRAM_CTRL10, .val = 0x07000200, },
+	{ .reg = DRAM_CTRL11, .val = 0x00070202, /*
+		- One chip select only
+		- Collumn size: 10 (= 12 - 2)
+		- CL = 2 */ },
+	{ .reg = DRAM_CTRL12, .val = 0x02020000, /*
+		- tWR = 2
+		- tRRD = 2
+		- Tcke = 0 ??? */ },
+	{ .reg = DRAM_CTRL13, .val = 0x04040a01, /*
+		- Gate = 4 ????
+		- Lin = 4 ????
+		- APREBIT = 10 ????
+		- tWRT = 1 */ },
+	{ .reg = DRAM_CTRL14, .val = 0x00000201, /*
+		- auto refresh count at initializing = 2
+		- one chip select is active */ },
+	{ .reg = DRAM_CTRL15, .val = 0x02040000, /*
+		- tRP = 2
+		- tRP + auto pre-charge = 4 */ },
+	{ .reg = DRAM_CTRL16, .val = 0x02080800, /*
+		- Trmd = 2
+ 		- memory power down mode 2 ????
+ 		- auto mode 2 */ },
+	{ .reg = DRAM_CTRL17, .val = 0x19000f08, /*
+		- DLL start point = 25
+		- DLL increment = 15
+		- tRC = 8 */ },
+	{ .reg = DRAM_CTRL18, .val = 0x0d0d0000, },
+	{ .reg = DRAM_CTRL19, .val = 0x02021313, },
+	{ .reg = DRAM_CTRL20, .val = 0x02061521, /*
+		-tRCD = 2
+		-tRAS min = 6 */ },
+	{ .reg = DRAM_CTRL21, .val = 0x0000000a, },
+	{ .reg = DRAM_CTRL22, .val = 0x00080008, },
+	{ .reg = DRAM_CTRL23, .val = 0x00200020, },
+	{ .reg = DRAM_CTRL24, .val = 0x00200020, },
+	{ .reg = DRAM_CTRL25, .val = 0x00200020, },
+	{ .reg = DRAM_CTRL26, .val = REFRESH_TIMING(7812, SDRAM_CLK), /* tREF = 7.812 us */ },
+	/* 27 + 28 -> obsolete */
+	{ .reg = DRAM_CTRL29, .val = 0x00000020, },
+	{ .reg = DRAM_CTRL30, .val = 0x00000020, },
+	{ .reg = DRAM_CTRL31, .val = 0x00c80000, },
+	{ .reg = DRAM_CTRL32, .val = 0x000a23cd, /*
+		- tXSNR = 10
+		- tRASmax = 0x23cd ???? */ },
+	{ .reg = DRAM_CTRL33, .val = 0x000000c8, /*
+		- tXSR = 0xc8 ???? */ },
+	{ .reg = DRAM_CTRL34, .val = STARTUP_TIMING(200, SDRAM_CLK), /* tINIT = 200 ms */ },
+	/* 35 is missing here */
+	{ .reg = DRAM_CTRL36, .val = 0x00000101, /*
+		- bit 8 is marked as reserved! */ },
+	{ .reg = DRAM_CTRL37, .val = 0x00040001, /*
+		- enable refresh */ },
+	{ .reg = DRAM_CTRL38, .val = 0x00000000, /*
+		- EMRS2_0 = 0x0000 for DDR memory at CS0
+		- EMRS1 = 0x0000 for DDR memory */ },
+	{ .reg = DRAM_CTRL39, .val = 0x00000000, /*
+		- EMRS2_2 = 0x0000 for DDR memory at CS2
+		- EMRS2_1 = 0x0000 for DDR memory at CS1 */ },
+	{ .reg = DRAM_CTRL40, .val = 0x00010000, /*
+		- tPDEX = 1
+		- EMRS2_4 = 0x0000 for DDR memory at CS3 */ },
+	{ .reg = DRAM_CTRL8, .val = 0x01000000, /*
+		- tRAS = 1 -> lockout is supported by this SDRAM
+		- DDR mode */ },
+	{ .reg = DRAM_CTRL8, .val = 0x01010000, /*
+		- tRAS = 1 -> lockout is supported by this SDRAM
+		- DDR mode
+		- start SDRAM controller */ },
+};
+
+/*
+ * Setup the EMI related pins
+ * Note: all SDRAM related pins are using the 12 mA drive strength
+ *
+ * Important:
+ * We cannot write absolute values into some of these registers, because the
+ * ROM may need some of the other pins for different purposes (reading
+ * from SD card or NAND for example) and already initialized them!
+ */
+static const struct reg_val_pair mx23evk_emi[] = {
+	 /* A6 ... A0 (unrelated pins included!) */
+	{ .reg = PINCTL_DRIVE9 + 8, .val = 0x77777770, },
+	{ .reg = PINCTL_DRIVE9 + 4, .val = 0x22222220, },
+	/* A12 ... A7, BA0/1 */
+	{ .reg = PINCTL_DRIVE10, .val = 0x22222222, },
+	/* WE#, RAS#, CKE, CE0/1, CAS (unrelated pins included!) */
+	{ .reg = PINCTL_DRIVE11 + 8, .val = 0x77700777, },
+	{ .reg = PINCTL_DRIVE11 + 4, .val = 0x22200222, },
+
+	/* Enable these pins for their EMI usage (unrelated pins included!) */
+	{ .reg = PINCTL_MUXSEL4 + 8, .val = 0xfffc0000, },
+	{ .reg = PINCTL_MUXSEL5, .val = 0x03c00000, },
+
+	/* D7 ... D0 */
+	{ .reg = PINCTL_DRIVE12, .val = 0x22222222, },
+	/* D15 ... D8 */
+	{ .reg = PINCTL_DRIVE13, .val = 0x22222222, },
+	/* CLK#, CLK, DQS0/1, DQM0/1 */
+	{ .reg = PINCTL_DRIVE14, .val = 0x00222222, },
+
+	/* Enable these pins for their EMI usage */
+	{ .reg = PINCTL_MUXSEL6, .val = 0x00000000, },
+	{ .reg = PINCTL_MUXSEL7, .val = 0x00000000, },
+
+	/* Disable all bit keepers */
+	{ .reg = PINCTL_PULL3, .val = 0x0003ffff, },
+};
+
+/**
+ * What we do here in this minimal bootlet
+ *
+ * Setting up:
+ * - the power rails
+ * - enabling the PLL
+ * - enabling the SDRAM controller clock (EMI CLK)
+ * - initializing the external SDRAM
+ *
+ * What we do *not* here:
+ * - changing the CPU, HCLK and XCLK clock
+ */
+void platform_init(void)
+{
+	printf("bootlet: starting to init MX23EVK\n");
+
+	init_reset_state();
+
+	/* enable the sub-units we need to use */
+	init_timer_access();	/* to make udelay() work */
+	init_pmic_access();	/* to gain access to the PMIC registers */
+	init_gpio_access();	/* to gain access to the GPIO registers */
+	init_sdram_access();	/* to gain access to the SDRAM controller registers */
+
+	printf("Starting initialization rails\n");
+	/* pin voltage to outer space */
+	setup_vddio_voltage(&mx23evk_vddio_voltage);
+	/* VDDM is _off_ after reset! This call will switch this rail on */
+	setup_vddmem_voltage(&mx23evk_vddm_voltage);
+	/* analogue parts (PLL etc) */
+	setup_vdda_voltage(&mx23evk_vdda_voltage);
+	/* CPU core */
+	setup_vddd_voltage(&mx23evk_vddd_voltage);
+	printf("Finishing rails\n");
+
+	power_up_pll();
+
+	setup_memory_pins(mx23evk_emi, ARRAY_SIZE(mx23evk_emi));
+	setup_memory_clock(SDRAM_CLK);
+	printf("Initializing the SDRAM controller\n");
+	configure_sdram(mx23evk_sdram, ARRAY_SIZE(mx23evk_sdram));
+
+#if 0
+	/*
+	 * Enable this test to check if your memory setup is working
+	 * Useful only, if also "DEBUG" is enabled
+	 */
+	printf("Do memory test...\n");
+	testdram(0x40000000, 0x40000000 + 64 * 1024 * 1024);
+#endif
+	printf("Finishing initialization\n");
+}