diff options
Diffstat (limited to 'arch/arm/boards')
147 files changed, 17 insertions, 9139 deletions
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile index 98eab17af2..e0dc27cb3d 100644 --- a/arch/arm/boards/Makefile +++ b/arch/arm/boards/Makefile @@ -4,7 +4,6 @@ obj-$(CONFIG_MACH_ADVANTECH_ROM_742X) += advantech-mx6/ obj-$(CONFIG_MACH_AFI_GF) += afi-gf/ obj-$(CONFIG_MACH_ANIMEO_IP) += animeo_ip/ -obj-$(CONFIG_MACH_ARCHOSG9) += archosg9/ obj-$(CONFIG_MACH_AT91RM9200EK) += at91rm9200ek/ obj-$(CONFIG_MACH_AT91SAM9260EK) += at91sam9260ek/ obj-$(CONFIG_MACH_AT91SAM9261EK) += at91sam9261ek/ @@ -19,7 +18,6 @@ obj-$(CONFIG_MACH_BEAGLE) += beagle/ obj-$(CONFIG_MACH_BEAGLEBONE) += beaglebone/ obj-$(CONFIG_MACH_BEAGLEPLAY) += beagleplay/ obj-$(CONFIG_MACH_CALAO) += calao/ -obj-$(CONFIG_MACH_CANON_A1100) += canon-a1100/ obj-$(CONFIG_MACH_CM_FX6) += cm-fx6/ obj-$(CONFIG_MACH_NITROGEN6) += boundarydevices-nitrogen6/ obj-$(CONFIG_MACH_NOVENA) += novena/ @@ -32,14 +30,6 @@ obj-$(CONFIG_MACH_DFI_FS700_M60) += dfi-fs700-m60/ obj-$(CONFIG_MACH_DIGI_CCIMX6ULSBCPRO) += digi-ccimx6ulsom/ obj-$(CONFIG_MACH_DUCKBILL) += duckbill/ obj-$(CONFIG_MACH_DSS11) += dss11/ -obj-$(CONFIG_MACH_EDB93012) += edb93xx/ -obj-$(CONFIG_MACH_EDB9301) += edb93xx/ -obj-$(CONFIG_MACH_EDB9302A) += edb93xx/ -obj-$(CONFIG_MACH_EDB9302) += edb93xx/ -obj-$(CONFIG_MACH_EDB9307A) += edb93xx/ -obj-$(CONFIG_MACH_EDB9307) += edb93xx/ -obj-$(CONFIG_MACH_EDB9315A) += edb93xx/ -obj-$(CONFIG_MACH_EDB9315) += edb93xx/ obj-$(CONFIG_MACH_EFIKA_MX_SMARTBOOK) += efika-mx-smartbook/ obj-$(CONFIG_MACH_EMBEDSKY_E9) += embedsky-e9/ obj-$(CONFIG_MACH_EMBEST_MARSBOARD) += embest-marsboard/ @@ -65,18 +55,13 @@ obj-$(CONFIG_MACH_KAMSTRUP_MX7_CONCENTRATOR) += kamstrup-mx7-concentrator/ obj-$(CONFIG_MACH_KARO_QSXP_ML81) += karo-qsxp-ml81/ obj-$(CONFIG_MACH_KONTRON_SAMX6I) += kontron-samx6i/ obj-$(CONFIG_MACH_LENOVO_IX4_300D) += lenovo-ix4-300d/ -obj-$(CONFIG_MACH_LUBBOCK) += lubbock/ -obj-$(CONFIG_MACH_MAINSTONE) += mainstone/ obj-$(CONFIG_MACH_MARVELL_ARMADA_XP_GP) += marvell-armada-xp-gp/ obj-$(CONFIG_MACH_MARVELL_ARMADA_XP_DB) += marvell-armada-xp-db/ -obj-$(CONFIG_MACH_MB7707) += module-mb7707/ -obj-$(CONFIG_MACH_MIOA701) += mioa701/ obj-$(CONFIG_MACH_MX23EVK) += freescale-mx23-evk/ obj-$(CONFIG_MACH_MX28EVK) += freescale-mx28-evk/ obj-$(CONFIG_MACH_MYIRTECH_X335X) += myirtech-x335x/ obj-$(CONFIG_MACH_NETGEAR_RN104) += netgear-rn104/ obj-$(CONFIG_MACH_NETGEAR_RN2120) += netgear-rn2120/ -obj-$(CONFIG_MACH_NOMADIK_8815NHK) += nhk8815/ obj-$(CONFIG_MACH_NVIDIA_BEAVER) += nvidia-beaver/ obj-$(CONFIG_MACH_NVIDIA_JETSON) += nvidia-jetson-tk1/ obj-$(CONFIG_MACH_NXP_IMX6ULL_EVK) += nxp-imx6ull-evk/ @@ -86,15 +71,8 @@ obj-$(CONFIG_MACH_NXP_IMX8MN_EVK) += nxp-imx8mn-evk/ obj-$(CONFIG_MACH_NXP_IMX8MP_EVK) += nxp-imx8mp-evk/ obj-$(CONFIG_MACH_CONGATEC_QMX8P_SOM) += congatec-qmx8p/ obj-$(CONFIG_MACH_TQ_MBA8MPXL) += tqma8mpxl/ -obj-$(CONFIG_MACH_OMAP343xSDP) += omap343xdsp/ -obj-$(CONFIG_MACH_OMAP3EVM) += omap3evm/ -obj-$(CONFIG_MACH_PANDA) += panda/ obj-$(CONFIG_MACH_PCA100) += phytec-phycard-imx27/ -obj-$(CONFIG_MACH_PCAAL1) += phytec-phycard-omap3/ -obj-$(CONFIG_MACH_PCAAXL2) += phytec-phycard-omap4/ -obj-$(CONFIG_MACH_PCM027) += phytec-phycore-pxa270/ obj-$(CONFIG_MACH_PCM038) += phytec-phycore-imx27/ -obj-$(CONFIG_MACH_PCM049) += phytec-phycore-omap4460/ obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) += phytec-som-am335x/ obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/ obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += phytec-phycore-imx7/ @@ -125,13 +103,11 @@ obj-$(CONFIG_MACH_SKOV_IMX8MP) += skov-imx8mp/ obj-$(CONFIG_MACH_FREESCALE_IMX6SX_SABRESDB) += freescale-mx6sx-sabresdb/ obj-$(CONFIG_MACH_SAMA5D27_GIANTBOARD) += sama5d27-giantboard/ obj-$(CONFIG_MACH_SAMA5D27_SOM1) += sama5d27-som1/ -obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/ obj-$(CONFIG_MACH_SAMA5D3_XPLAINED) += sama5d3_xplained/ obj-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += microchip-ksz9477-evb/ obj-$(CONFIG_MACH_MICROCHIP_SAMA5D3_EDS) += microchip-sama5d3-eds/ obj-$(CONFIG_MACH_SAMA5D4_XPLAINED) += sama5d4_xplained/ obj-$(CONFIG_MACH_SAMA5D4_WIFX) += sama5d4_wifx/ -obj-$(CONFIG_MACH_SAMA5D4EK) += sama5d4ek/ obj-$(CONFIG_MACH_SCB9328) += scb9328/ obj-$(CONFIG_MACH_SEEED_ODYSSEY) += seeed-odyssey/ obj-$(CONFIG_MACH_SOCFPGA_ALTERA_SOCDK) += altera-socdk/ @@ -171,9 +147,7 @@ obj-$(CONFIG_MACH_USB_A9G20) += usb-a926x/ obj-$(CONFIG_MACH_USI_TOPKICK) += usi-topkick/ obj-$(CONFIG_MACH_VERSATILEPB) += versatile/ obj-$(CONFIG_MACH_VEXPRESS) += vexpress/ -obj-$(CONFIG_MACH_VIRT2REAL) += virt2real/ obj-$(CONFIG_MACH_ZEDBOARD) += avnet-zedboard/ -obj-$(CONFIG_MACH_ZYLONITE) += zylonite/ obj-$(CONFIG_MACH_VARISCITE_MX6) += variscite-mx6/ obj-$(CONFIG_MACH_VARISCITE_SOM_MX7) += variscite-som-mx7/ obj-$(CONFIG_MACH_VSCOM_BALTOS) += vscom-baltos/ diff --git a/arch/arm/boards/archosg9/Makefile b/arch/arm/boards/archosg9/Makefile deleted file mode 100644 index 790ff623f5..0000000000 --- a/arch/arm/boards/archosg9/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -obj-$(CONFIG_ARM_BOARD_APPEND_ATAG) += archos_features.o -lwl-y += lowlevel.o mux.o diff --git a/arch/arm/boards/archosg9/archos_features.c b/arch/arm/boards/archosg9/archos_features.c deleted file mode 100644 index 8642d344a5..0000000000 --- a/arch/arm/boards/archosg9/archos_features.c +++ /dev/null @@ -1,189 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include <common.h> -#include <asm/setup.h> -#include "archos_features.h" -#include "feature_list.h" - -static inline void *atag_data(struct tag *t) -{ - return ((void *)t) + sizeof(struct tag_header); -} - -static struct feature_tag *features; - -static void setup_feature_core(void) -{ - features->hdr.tag = FTAG_CORE; - features->hdr.size = feature_tag_size(feature_tag_core); - - memset(&features->u.core, 0, sizeof(features->u.core)); - features->u.core.magic = FEATURE_LIST_MAGIC; - features->u.core.list_revision = FEATURE_LIST_REV; - - features = feature_tag_next(features); -} -static void setup_feature_product_name(void) -{ - features->hdr.tag = FTAG_PRODUCT_NAME; - features->hdr.size = feature_tag_size(feature_tag_product_name); - - memset(&features->u.product_name, 0, sizeof(features->u.product_name)); - sprintf(features->u.product_name.name, "A80S"); - features->u.product_name.id = 0x13A8; - - features = feature_tag_next(features); -} -static void setup_feature_product_serial_number(void) -{ - features->hdr.tag = FTAG_PRODUCT_SERIAL_NUMBER; - features->hdr.size = feature_tag_size(feature_tag_product_serial); - - memset(&features->u.product_serial, 0, - sizeof(features->u.product_serial)); - - features = feature_tag_next(features); -} -static void setup_feature_product_mac_address(void) -{ - features->hdr.tag = FTAG_PRODUCT_MAC_ADDRESS; - features->hdr.size = feature_tag_size(feature_tag_product_mac_address); - - memset(&features->u.mac_address, 0, sizeof(features->u.mac_address)); - - features = feature_tag_next(features); -} -static void setup_feature_board_pcb_revision(void) -{ - features->hdr.tag = FTAG_BOARD_PCB_REVISION; - features->hdr.size = feature_tag_size(feature_tag_board_revision); - - memset(&features->u.board_revision, 0, - sizeof(features->u.board_revision)); - features->u.board_revision.revision = 5; - - features = feature_tag_next(features); -} -static void setup_feature_sdram(void) -{ - features->hdr.tag = FTAG_SDRAM; - features->hdr.size = feature_tag_size(feature_tag_sdram); - - memset(&features->u.sdram, 0, sizeof(features->u.sdram)); - sprintf(features->u.sdram.vendor , "elpida"); - sprintf(features->u.sdram.product, "EDB8064B1PB"); - features->u.sdram.clock = 400; - - features = feature_tag_next(features); -} -static void setup_feature_pmic(void) -{ - features->hdr.tag = FTAG_PMIC; - features->hdr.size = feature_tag_size(feature_tag_pmic); - - memset(&features->u.pmic, 0, sizeof(features->u.pmic)); - features->u.pmic.flags = FTAG_PMIC_TPS62361; - - features = feature_tag_next(features); -} -static void setup_feature_serial_port(void) -{ - features->hdr.tag = FTAG_SERIAL_PORT; - features->hdr.size = feature_tag_size(feature_tag_serial_port); - - memset(&features->u.serial_port, 0, sizeof(features->u.serial_port)); - features->u.serial_port.uart_id = 1; - features->u.serial_port.speed = 115200; - - features = feature_tag_next(features); -} -static void setup_feature_has_gpio_volume_keys(void) -{ - features->hdr.tag = FTAG_HAS_GPIO_VOLUME_KEYS; - features->hdr.size = feature_tag_size(feature_tag_gpio_volume_keys); - - memset(&features->u.gpio_volume_keys, 0, - sizeof(features->u.gpio_volume_keys)); - features->u.gpio_volume_keys.gpio_vol_up = 0x2B; - features->u.gpio_volume_keys.gpio_vol_down = 0x2C; - - features = feature_tag_next(features); -} -static void setup_feature_screen(void) -{ - features->hdr.tag = FTAG_SCREEN; - features->hdr.size = feature_tag_size(feature_tag_screen); - - memset(&features->u.screen, 0, sizeof(features->u.screen)); - sprintf(features->u.screen.vendor, "CMI"); - features->u.screen.backlight = 0xC8; - - features = feature_tag_next(features); -} -static void setup_feature_turbo(void) -{ - features->hdr.tag = FTAG_TURBO; - features->hdr.size = feature_tag_size(feature_tag_turbo); - - memset(&features->u.turbo, 0, sizeof(features->u.turbo)); - features->u.turbo.flag = 1; - - features = feature_tag_next(features); -} -static void setup_feature_none(void) -{ - features->hdr.tag = FTAG_NONE; - features->hdr.size = sizeof(struct feature_tag_header) >> 2; - - features = feature_tag_next(features); -} -static struct tag *setup_feature_list(struct tag * params) -{ - struct tag_feature_list *fl; - - fl = atag_data(params); - features = (struct feature_tag *)fl->data; - - setup_feature_core(); - setup_feature_product_name(); - setup_feature_product_serial_number(); - setup_feature_product_mac_address(); - setup_feature_board_pcb_revision(); - setup_feature_sdram(); - setup_feature_pmic(); - setup_feature_serial_port(); - setup_feature_has_gpio_volume_keys(); - setup_feature_screen(); - setup_feature_turbo(); - setup_feature_none(); - - fl->size = ((u32)features) - ((u32)(fl->data)); - - params->hdr.tag = ATAG_FEATURE_LIST; - params->hdr.size = (sizeof(struct tag_feature_list) + fl->size) >> 2; - - return tag_next(params); -} - -static struct tag *setup_boot_version(struct tag *params) -{ - struct tag_boot_version *bv; - - bv = atag_data(params); - - params->hdr.tag = ATAG_BOOT_VERSION; - params->hdr.size = tag_size(tag_boot_version); - - bv->major = 5; - bv->minor = 5; - bv->extra = 3; - - return tag_next(params); -} - -struct tag *archos_append_atags(struct tag *params) -{ - params = setup_feature_list(params); - params = setup_boot_version(params); - return params; -} diff --git a/arch/arm/boards/archosg9/archos_features.h b/arch/arm/boards/archosg9/archos_features.h deleted file mode 100644 index f46b9e9eb8..0000000000 --- a/arch/arm/boards/archosg9/archos_features.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __ARCHOS_FEATURES_H -#define __ARCHOS_FEATURES_H - -/* bootloader version */ -#define ATAG_BOOT_VERSION 0x5441000A - -struct tag_boot_version { - u32 major; - u32 minor; - u32 extra; -}; - -#define ATAG_FEATURE_LIST 0x5441000B - -struct tag_feature_list { - u32 size; - u8 data[0]; -}; - -struct tag *archos_append_atags(struct tag * params); - -#endif /* __ARCHOS_FEATURES_H */ diff --git a/arch/arm/boards/archosg9/board.c b/arch/arm/boards/archosg9/board.c deleted file mode 100644 index fbf05a4408..0000000000 --- a/arch/arm/boards/archosg9/board.c +++ /dev/null @@ -1,180 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include <common.h> -#include <clock.h> -#include <init.h> -#include <asm/armlinux.h> -#include <asm/mach-types.h> -#include <mach/omap/devices.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-devices.h> -#include <mach/omap/omap4_rom_usb.h> -#include <linux/sizes.h> -#include <i2c/i2c.h> -#include <gpio.h> -#include <gpio_keys.h> -#include <twl6030_pwrbtn.h> -#include <readkey.h> -#include <input/input.h> -#include "archos_features.h" - -#define GPIO_LCD_PWON 38 -#define GPIO_BRIDGE_EN 39 -#define GPIO_LCD_RST 53 -#define GPIO_LCD_STDBY 101 -#define GPIO_LCD_AVDD_EN 12 -#define GPIO_BKL_EN 122 -#define GPIO_BKL_LED 143 - -#define GPIO_5V_PWRON 36 -#define GPIO_VCC_PWRON 35 -#define GPIO_1V8_PWRON 34 -#define GPIO_GPS_ENABLE 41 - -static int archosg9_console_init(void) -{ - int ret; - - barebox_set_model("Archos G9"); - barebox_set_hostname("g9"); - - if (IS_ENABLED(CONFIG_DRIVER_SERIAL_OMAP4_USBBOOT)) { - ret = omap4_usbboot_open(); - if (!ret) { - add_generic_device("serial_omap4_usbboot", DEVICE_ID_DYNAMIC - , NULL, 0, 0, 0, NULL); - } - } - if (IS_ENABLED(CONFIG_DRIVER_SERIAL_NS16550)) { - omap44xx_add_uart1(); - } - return 0; -} -console_initcall(archosg9_console_init); - -static int archosg9_mem_init(void){ - omap_add_ram0(SZ_1G); - return 0; -} -mem_initcall(archosg9_mem_init); - -static struct i2c_board_info i2c_devices[] = { - { I2C_BOARD_INFO("twl6030", 0x48), }, -}; - -static struct twl6030_pwrbtn_platform_data pwrbtn_data = { - .code = BB_KEY_ENTER -}; -static struct gpio_keys_button keys[] = { - { .code = KEY_UP , .gpio = 43, .active_low = 1 }, - { .code = KEY_DOWN, .gpio = 44, .active_low = 1 }, -}; -static struct gpio_keys_platform_data gk_data = { - .buttons = keys, - .nbuttons = ARRAY_SIZE(keys), - .fifo_size = ARRAY_SIZE(keys)*sizeof(int) -}; - -static struct omapfb_display const archosg9_displays[] = { - { - .mode = { - .name = "g104x1", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 96000, - .left_margin = 320, - .right_margin = 1, - .hsync_len = 320, - .upper_margin = 38, - .lower_margin = 38, - .vsync_len = 2, - }, - .config = ( - OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24 - ), - .power_on_delay = 50, - .power_off_delay = 100, - }, -}; - -static void archosg9_fb_enable(int e) -{ - if (e) { - gpio_direction_output(GPIO_LCD_PWON , 1); - mdelay(50); - gpio_direction_output(GPIO_LCD_RST , 0); - gpio_direction_output(GPIO_LCD_AVDD_EN, 0); - mdelay(35); - gpio_direction_output(GPIO_BRIDGE_EN , 1); - mdelay(10); - gpio_direction_output(GPIO_LCD_STDBY , 0); - gpio_direction_output(GPIO_BKL_EN , 0); - } else { - gpio_direction_output(GPIO_BKL_EN , 1); - gpio_direction_output(GPIO_LCD_STDBY , 1); - mdelay(1); - gpio_direction_output(GPIO_BRIDGE_EN , 0); - gpio_direction_output(GPIO_LCD_AVDD_EN, 1); - mdelay(10); - gpio_direction_output(GPIO_LCD_PWON , 0); - gpio_direction_output(GPIO_LCD_RST , 1); - } -} - -static struct omapfb_platform_data archosg9_fb_data = { - .displays = archosg9_displays, - .num_displays = ARRAY_SIZE(archosg9_displays), - .dss_clk_hz = 19200000, - .bpp = 32, - .enable = archosg9_fb_enable, -}; - -static int archosg9_display_init(void) -{ - omap_add_display(&archosg9_fb_data); - - gpio_direction_output(GPIO_BKL_EN , 1); - gpio_direction_output(GPIO_LCD_RST , 1); - gpio_direction_output(GPIO_LCD_PWON , 0); - gpio_direction_output(GPIO_BRIDGE_EN , 0); - gpio_direction_output(GPIO_LCD_STDBY , 1); - gpio_direction_output(GPIO_LCD_AVDD_EN, 1); - gpio_direction_output(GPIO_BKL_LED , 0); - gpio_direction_output(GPIO_VCC_PWRON , 1); - - return 0; -} - -static int archosg9_devices_init(void){ - gpio_direction_output(GPIO_GPS_ENABLE, 0); - gpio_direction_output(GPIO_1V8_PWRON , 1); - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - omap44xx_add_i2c1(NULL); - omap44xx_add_mmc1(NULL); - if (IS_ENABLED(CONFIG_KEYBOARD_TWL6030) && - IS_ENABLED(CONFIG_KEYBOARD_GPIO)) { - add_generic_device_res("twl6030_pwrbtn", DEVICE_ID_DYNAMIC, - 0, 0, &pwrbtn_data); - add_gpio_keys_device(DEVICE_ID_DYNAMIC, &gk_data); - } - - if (IS_ENABLED(CONFIG_DRIVER_VIDEO_OMAP)) - archosg9_display_init(); - - /* - * This should be: - * armlinux_set_architecture(MACH_TYPE_OMAP4_ARCHOSG9); - * But Archos has not registered it's board to arch/arm/tools/mach-types - * So here there is the hardcoded value - */ - armlinux_set_architecture(5032); - armlinux_set_revision(5); - armlinux_set_atag_appender(archos_append_atags); - - return 0; -} -device_initcall(archosg9_devices_init); diff --git a/arch/arm/boards/archosg9/env/boot/sd-card-android b/arch/arm/boards/archosg9/env/boot/sd-card-android deleted file mode 100644 index bc2df696a2..0000000000 --- a/arch/arm/boards/archosg9/env/boot/sd-card-android +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -path=/mnt/sd -global.bootm.image=${path}/android -global.bootm.initrd=${path}/initramfs.cpio.lzo -global.linux.bootargs.base="mem=512M init=/linuxrc debug omapdss.debug=0 omapfb.debug=0 mem=512M@0xa0000000" diff --git a/arch/arm/boards/archosg9/env/boot/sd-card-linux b/arch/arm/boards/archosg9/env/boot/sd-card-linux deleted file mode 100644 index b3eaa2437d..0000000000 --- a/arch/arm/boards/archosg9/env/boot/sd-card-linux +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -path=/mnt/sd -global.bootm.image=${path}/zImage -initrd=${path}/initrd - -if [ -f ${initrd} ]; then - global.bootm.initrd=${initrd} - global.linux.bootargs.base="console=ttyO0,115200n8 root=/dev/ram0" -else - global.linux.bootargs.base="console=ttyO0,115200n8 rootwait root=/dev/mmcblk0p2" -fi diff --git a/arch/arm/boards/archosg9/env/boot/usb-android b/arch/arm/boards/archosg9/env/boot/usb-android deleted file mode 100644 index e97e0ade60..0000000000 --- a/arch/arm/boards/archosg9/env/boot/usb-android +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -path=/mnt/usb -global.bootm.image=${path}/android -global.bootm.initrd=${path}/initramfs.cpio.lzo -global.linux.bootargs.base="mem=512M init=/linuxrc debug omapdss.debug=0 omapfb.debug=0 mem=512M@0xa0000000" diff --git a/arch/arm/boards/archosg9/env/boot/usb-linux b/arch/arm/boards/archosg9/env/boot/usb-linux deleted file mode 100644 index a257138d45..0000000000 --- a/arch/arm/boards/archosg9/env/boot/usb-linux +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -path=/mnt/usb -global.bootm.image=${path}/zImage -initrd=${path}/initrd - -if [ -f ${initrd} ]; then - global.bootm.initrd=${initrd} - global.linux.bootargs.base="console=ttyO0,115200n8 root=/dev/ram0" -else - global.linux.bootargs.base="console=ttyO0,115200n8" -fi diff --git a/arch/arm/boards/archosg9/env/init/automount2 b/arch/arm/boards/archosg9/env/init/automount2 deleted file mode 100644 index fa104397e2..0000000000 --- a/arch/arm/boards/archosg9/env/init/automount2 +++ /dev/null @@ -1,7 +0,0 @@ -#!/bin/sh - -mkdir -p /mnt/sd -automount -d /mnt/sd '[ -e /dev/disk0.0 ] && mount /dev/disk0.0 /mnt/sd' - -mkdir -p /mnt/usb -automount -d /mnt/usb 'mount -t omap4_usbbootfs omap4_usbboot /mnt/usb' diff --git a/arch/arm/boards/archosg9/env/init/bootsource b/arch/arm/boards/archosg9/env/init/bootsource deleted file mode 100644 index 6145a76fe6..0000000000 --- a/arch/arm/boards/archosg9/env/init/bootsource +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -if [ -n "$nv.boot.default" ]; then - exit -fi - -if [ -f /mnt/sd/zImage ]; then - global.boot.default=sd-card-linux -elif [ -f /mnt/sd/android ]; then - global.boot.default=sd-card-android -elif [ -f /mnt/usb/zImage ]; then - global.boot.default=usb-linux -elif [ -f /mnt/usb/android ]; then - global.boot.default=usb-android -fi diff --git a/arch/arm/boards/archosg9/env/init/splash b/arch/arm/boards/archosg9/env/init/splash deleted file mode 100644 index 4441b90057..0000000000 --- a/arch/arm/boards/archosg9/env/init/splash +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -fb0.mode_name=g104x1 -splash -b0 /mnt/usb/barebox.png -fb0.enable=1 diff --git a/arch/arm/boards/archosg9/env/menu/11-boot-flash/action b/arch/arm/boards/archosg9/env/menu/11-boot-flash/action deleted file mode 100644 index f83028b4c8..0000000000 --- a/arch/arm/boards/archosg9/env/menu/11-boot-flash/action +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh -boot_order mmc2_1 -echo "Rebooting into internal flash..." -reset diff --git a/arch/arm/boards/archosg9/env/menu/11-boot-flash/title b/arch/arm/boards/archosg9/env/menu/11-boot-flash/title deleted file mode 100644 index 2628b5a13a..0000000000 --- a/arch/arm/boards/archosg9/env/menu/11-boot-flash/title +++ /dev/null @@ -1 +0,0 @@ -${RED}Reboot into internal flash${NC} diff --git a/arch/arm/boards/archosg9/env/menu/12-boot-sd/action b/arch/arm/boards/archosg9/env/menu/12-boot-sd/action deleted file mode 100644 index 19bc3ff0b0..0000000000 --- a/arch/arm/boards/archosg9/env/menu/12-boot-sd/action +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh -boot_order mmc1 -echo "Rebooting into SD card..." -reset diff --git a/arch/arm/boards/archosg9/env/menu/12-boot-sd/title b/arch/arm/boards/archosg9/env/menu/12-boot-sd/title deleted file mode 100644 index 92e940f3b5..0000000000 --- a/arch/arm/boards/archosg9/env/menu/12-boot-sd/title +++ /dev/null @@ -1 +0,0 @@ -${RED}Reboot into SD card${NC} diff --git a/arch/arm/boards/archosg9/env/menu/13-boot-usb/action b/arch/arm/boards/archosg9/env/menu/13-boot-usb/action deleted file mode 100644 index 885acbaa2d..0000000000 --- a/arch/arm/boards/archosg9/env/menu/13-boot-usb/action +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh -boot_order usb_1 -echo "Rebooting over usb..." -reset diff --git a/arch/arm/boards/archosg9/env/menu/13-boot-usb/title b/arch/arm/boards/archosg9/env/menu/13-boot-usb/title deleted file mode 100644 index 76edccd6ad..0000000000 --- a/arch/arm/boards/archosg9/env/menu/13-boot-usb/title +++ /dev/null @@ -1 +0,0 @@ -${RED}Reboot over usb${NC} diff --git a/arch/arm/boards/archosg9/feature_list.h b/arch/arm/boards/archosg9/feature_list.h deleted file mode 100644 index 0b726cd1a3..0000000000 --- a/arch/arm/boards/archosg9/feature_list.h +++ /dev/null @@ -1,352 +0,0 @@ -#ifndef _FEATURE_LIST_H -#define _FEATURE_LIST_H - -/* - This file comes from: - http://gitorious.org/archos/archos-gpl-gen9-kernel-ics/blobs/raw/master/ - arch/arm/include/asm/feature_list.h -*/ - -#define FEATURE_LIST_MAGIC 0xFEA01234 - -#define FEATURE_LIST_REV 0x00000001 - -struct feature_tag_header { - u32 size; - u32 tag; -}; - -struct feature_tag_generic { - u32 vendor; - u32 product; - u32 type; - u32 revision; - u32 flags; -}; - -#define FTAG_NONE 0x00000000 - -#define FTAG_CORE 0x00000001 -struct feature_tag_core { - u32 magic; - u32 list_revision; - u32 flags; -}; - -/* product specific */ -#define FTAG_PRODUCT_NAME 0x00000002 -struct feature_tag_product_name { - char name[64]; - u32 id; -}; -#define FTAG_PRODUCT_SERIAL_NUMBER 0x00000003 -struct feature_tag_product_serial { - u32 serial[4]; -}; - -#define FTAG_PRODUCT_MAC_ADDRESS 0x00000004 -struct feature_tag_product_mac_address { - u8 addr[6]; - u8 reserved1; - u8 reserved2; -}; - -#define FTAG_PRODUCT_OEM 0x00000005 -struct feature_tag_product_oem { - char name[16]; - u32 id; -}; - -#define FTAG_PRODUCT_ZONE 0x00000006 -struct feature_tag_product_zone { - char name[16]; - u32 id; -}; - -/* board pcb specific */ -#define FTAG_BOARD_PCB_REVISION 0x00000010 -struct feature_tag_board_revision { - u32 revision; -}; - -/* clock and ram setup */ -#define FTAG_CLOCK 0x00000011 -struct feature_tag_clock { - u32 clock; -}; - -#define FTAG_SDRAM 0x00000012 -struct feature_tag_sdram { - char vendor[16]; - char product[32]; - u32 type; - u32 revision; - u32 flags; - u32 clock; - /* custom params */ - u32 param_0; - u32 param_1; - u32 param_2; - u32 param_3; - u32 param_4; - u32 param_5; - u32 param_6; - u32 param_7; -}; - -/* PMIC */ -#define FTAG_PMIC 0x00000013 -#define FTAG_PMIC_TPS62361 0x00000001 -struct feature_tag_pmic { - u32 flags; -}; - -/* serial port */ -#define FTAG_SERIAL_PORT 0x00000020 -struct feature_tag_serial_port { - u32 uart_id; - u32 speed; -}; - -/* turbo bit */ -#define FTAG_TURBO 0x00000014 -struct feature_tag_turbo { - u32 flag; -}; - -/*** features ****/ -#define FTAG_HAS_GPIO_VOLUME_KEYS 0x00010001 -struct feature_tag_gpio_volume_keys { - u32 gpio_vol_up; - u32 gpio_vol_down; - u32 flags; -}; - -#define FTAG_HAS_ELECTRICAL_SHORTCUT 0x00010002 -#define FTAG_HAS_DCIN 0x00010003 -struct feature_tag_dcin { - u32 autodetect; -}; - -/* external screen support */ -#define FTAG_HAS_EXT_SCREEN 0x00010004 - -#define EXT_SCREEN_TYPE_TVOUT 0x00000001 -#define EXT_SCREEN_TYPE_HDMI 0x00000002 -#define EXT_SCREEN_TYPE_VGA 0x00000004 -struct feature_tag_ext_screen { - u32 type; - u32 revision; -}; - -/* wireless lan */ -#define FTAG_HAS_WIFI 0x00010005 - -#define WIFI_TYPE_TIWLAN 0x00000001 -struct feature_tag_wifi { - u32 vendor; - u32 product; - u32 type; - u32 revision; - u32 flags; -}; - -/* bluetooth */ -#define FTAG_HAS_BLUETOOTH 0x00010006 - -#define BLUETOOTH_TYPE_TIWLAN 0x00000001 -struct feature_tag_bluetooth { - u32 vendor; - u32 product; - u32 type; - u32 revision; - u32 flags; -}; - -/* accelerometer */ -#define FTAG_HAS_ACCELEROMETER 0x00010007 -struct feature_tag_accelerometer { - u32 vendor; - u32 product; - u32 type; - u32 revision; - u32 flags; -}; - -/* gyroscope */ -#define FTAG_HAS_GYROSCOPE 0x00010008 - -/* compass */ -#define FTAG_HAS_COMPASS 0x00010009 - -/* gps */ -#define FTAG_HAS_GPS 0x0001000a -#define GPS_FLAG_DISABLED 0x00000001 -struct feature_tag_gps { - u32 vendor; - u32 product; - u32 revision; - u32 flags; -}; - -/* camera */ -#define FTAG_HAS_CAMERA 0x0001000b - -/* harddisk controller */ -#define FTAG_HAS_HARDDISK_CONTROLLER 0x0001000c -#define HDCONTROLLER_TYPE_SATA 0x00000001 -struct feature_tag_harddisk_controller { - u32 vendor; - u32 product; - u32 type; - u32 revision; - u32 flags; -}; - -/* harddisk */ -#define FTAG_HAS_HARDDISK 0x0001000d - -#define HARDDISK_TYPE_SATA 0x00000001 -#define HARDDISK_TYPE_PATA 0x00000002 -struct feature_tag_harddisk { - u32 vendor; - u32 product; - u32 type; - u32 revision; - u32 flags; -}; - -/* touchscreen */ -#define FTAG_HAS_TOUCHSCREEN 0x0001000e - -#define TOUCHSCREEN_TYPE_CAPACITIVE 0x00000001 -#define TOUCHSCREEN_TYPE_RESISTIVE 0x00000002 - -#define TOUCHSCREEN_FLAG_MULTITOUCH 0x00000001 -struct feature_tag_touchscreen { - u32 vendor; - u32 product; - u32 type; - u32 revision; - u32 flags; -}; - -/* microphone */ -#define FTAG_HAS_MICROPHONE 0x0001000f - -/* external SDMMC slot */ -#define FTAG_HAS_EXT_MMCSD_SLOT 0x00010010 -#define MMCSD_FLAG_CARDDETECT 0x00000001 -#define MMCSD_FLAG_CARDPREDETECT 0x00000002 - -struct feature_tag_mmcsd { - u32 width; - u32 voltagemask; - u32 revision; - u32 flags; -}; - -/* ambient light sensor */ -#define FTAG_HAS_AMBIENT_LIGHT_SENSOR 0x00010011 - -/* proximity sensor */ -#define FTAG_HAS_PROXIMITY_SENSOR 0x00010012 - -/* gps */ -#define FTAG_HAS_GSM 0x00010013 - -/* dect */ -#define FTAG_HAS_DECT 0x00010014 - -/* hsdpa data modem */ -#define FTAG_HAS_HSDPA 0x00010015 - -/* near field communication */ -#define FTAG_HAS_NFC 0x00010016 - -#define FTAG_GPIO_KEYS 0x00010017 -struct feature_tag_gpio_keys { -#define GPIO_KEYS_LONG_PRESS 0x00010000 - u32 vol_up; - u32 vol_down; - u32 ok; - u32 reserved[5]; -}; - -#define FTAG_SCREEN 0x00010018 -struct feature_tag_screen { - char vendor[16]; - u32 type; - u32 revision; - u32 vcom; - u32 backlight; - u32 reserved[5]; -}; - -#define FTAG_WIFI_PA 0x00010019 -struct feature_tag_wifi_pa { - char vendor[16]; - u32 type; -}; - -/* loudspeaker */ -#define FTAG_HAS_SPEAKER 0x0001001a - -#define SPEAKER_FLAG_STEREO 0x00000001 -#define SPEAKER_FLAG_OWN_VOLCTRL 0x00000002 -struct feature_tag_speaker { - u32 flags; -}; - -#define FTAG_BATTERY 0x0001001b -struct feature_tag_battery { - u32 type; -}; -#define BATTERY_TYPE_HIGHRS 0x00000000 -#define BATTERY_TYPE_LOWRS 0x00000001 - - -#define feature_tag_next(t) \ - ((struct feature_tag *)((u32 *)(t) + (t)->hdr.size)) -#define feature_tag_size(type) \ - ((sizeof(struct feature_tag_header) + sizeof(struct type)) >> 2) -#define for_each_feature_tag(t, base) \ - for (t = base; t->hdr.size; t = feature_tag_next(t)) - - -struct feature_tag { - struct feature_tag_header hdr; - union { - struct feature_tag_core core; - struct feature_tag_generic generic; - struct feature_tag_product_name product_name; - struct feature_tag_product_serial product_serial; - struct feature_tag_product_oem product_oem; - struct feature_tag_product_zone product_zone; - struct feature_tag_product_mac_address mac_address; - struct feature_tag_board_revision board_revision; - struct feature_tag_clock clock; - struct feature_tag_sdram sdram; - struct feature_tag_pmic pmic; - struct feature_tag_turbo turbo; - struct feature_tag_serial_port serial_port; - struct feature_tag_gpio_volume_keys gpio_volume_keys; - struct feature_tag_dcin dcin; - struct feature_tag_ext_screen ext_screen; - struct feature_tag_wifi wifi; - struct feature_tag_bluetooth bluetooth; - struct feature_tag_accelerometer accelerometer; - struct feature_tag_harddisk_controller harddisk_controller; - struct feature_tag_harddisk harddisk; - struct feature_tag_touchscreen touchscreen; - struct feature_tag_gps gps; - struct feature_tag_speaker speaker; - struct feature_tag_mmcsd mmcsd; - struct feature_tag_gpio_keys gpio_keys; - struct feature_tag_screen screen; - struct feature_tag_wifi_pa wifi_pa; - struct feature_tag_battery battery; - } u; -}; - -#endif /* _FEATURE_LIST_H */ diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c deleted file mode 100644 index 2c3d0e1ee4..0000000000 --- a/arch/arm/boards/archosg9/lowlevel.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include <common.h> -#include <io.h> -#include <init.h> -#include <linux/sizes.h> -#include <mach/omap/generic.h> -#include <mach/omap/omap4-mux.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-generic.h> -#include <mach/omap/omap4-clock.h> -#include <mach/omap/syslib.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include "mux.h" - -#define TPS62361_VSEL0_GPIO 7 - -static const struct ddr_regs ddr_regs_400_mhz_2cs = { - .tim1 = 0x10EB0662, - .tim2 = 0x20370DD2, - .tim3 = 0x00B1C33F, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80000EB9, - .config_final = 0x80001AB9, - .zq_config = 0xD00B3215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -static noinline void archosg9_init_lowlevel(void) -{ - struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_19M2_MPU1200; - struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; - struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; - struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; - struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; - - archosg9_set_muxconf_regs(); - - omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1380); - - /* Enable all clocks */ - omap4_enable_all_clocks(); - writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); - - /* Configure all DPLL's at 100% OPP */ - omap4_configure_mpu_dpll(&mpu); - omap4_configure_iva_dpll(&iva); - omap4_configure_per_dpll(&per); - omap4_configure_abe_dpll(&abe); - omap4_configure_usb_dpll(&usb); - - omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); -} - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - omap4_save_bootinfo((void *)r0); - - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) - goto out; - - arm_setup_stack(0x4030d000); - - archosg9_init_lowlevel(); -out: - barebox_arm_entry(0x80000000, SZ_1G, NULL); -} diff --git a/arch/arm/boards/archosg9/mux.c b/arch/arm/boards/archosg9/mux.c deleted file mode 100644 index d51ccefba4..0000000000 --- a/arch/arm/boards/archosg9/mux.c +++ /dev/null @@ -1,262 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -#include <common.h> -#include <init.h> -#include <io.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-mux.h> -#include <mach/omap/omap4-clock.h> -#include "mux.h" - -static const struct pad_conf_entry core_padconf_array[] = { - { GPMC_AD0 , IEN | PTU | M1 }, - { GPMC_AD1 , IEN | PTU | M1 }, - { GPMC_AD2 , IEN | PTU | M1 }, - { GPMC_AD3 , IEN | PTU | M1 }, - { GPMC_AD4 , IEN | PTU | M1 }, - { GPMC_AD5 , IEN | PTU | M1 }, - { GPMC_AD6 , IEN | PTU | M1 }, - { GPMC_AD7 , IEN | PTU | M1 }, - { GPMC_AD8 , IEN | PTD | M3 }, - { GPMC_AD9 , IEN | PTU | M0 }, - { GPMC_AD10 , IEN | PTU | M3 }, - { GPMC_AD11 , IEN | PTU | M3 }, - { GPMC_AD12 , IEN | PTD | M3 }, - { GPMC_AD13 , PTD | M3 }, - { GPMC_AD14 , PTD | M3 }, - { GPMC_AD15 , PTD | M3 }, - { GPMC_A16 , IEN | PTD | M7 }, - { GPMC_A17 , IEN | PTD | M3 }, - { GPMC_A18 , IEN | PTD | M1 }, - { GPMC_A19 , IEN | PTU | M3 }, - { GPMC_A20 , IEN | PTU | M3 }, - { GPMC_A21 , IEN | PTD | M7 }, - { GPMC_A22 , IEN | PTD | M1 }, - { GPMC_A23 , IEN | PTD | M1 }, - { GPMC_A24 , IEN | PTD | M3 }, - { GPMC_A25 , IEN | PTU | M3 }, - { GPMC_NCS0 , IEN | PTU | M0 }, - { GPMC_NCS1 , IEN | PTU | M7 }, - { GPMC_NCS2 , IEN | PTU | M7 }, - { GPMC_NCS3 , IEN | PTU | M3 }, - { GPMC_NWP , IEN | PTD | M0 }, - { GPMC_CLK , IEN | PTD | M0 }, - { GPMC_NADV_ALE , IEN | PTD | M0 }, - { GPMC_NOE , IEN | PTU | M1 }, - { GPMC_NWE , IEN | PTU | M1 }, - { GPMC_NBE0_CLE , IEN | PTD | M0 }, - { GPMC_NBE1 , IEN | PTD | M7 }, - { GPMC_WAIT0 , IEN | PTU | M0 }, - { GPMC_WAIT1 , IEN | PTU | M7 }, - { GPMC_WAIT2 , IEN | PTD | M7 }, - { GPMC_NCS4 , IEN | PTD | M3 }, - { GPMC_NCS5 , IEN | PTD | M7 }, - { GPMC_NCS6 , IEN | PTD | M7 }, - { GPMC_NCS7 , IEN | PTD | M7 }, - { GPIO63 , M0 }, - { GPIO64 , M0 }, - { GPIO65 , M0 }, - { GPIO66 , IEN | M0 }, - { CSI21_DX0 , IEN | PTD | M7 }, - { CSI21_DY0 , IEN | PTD | M7 }, - { CSI21_DX1 , IEN | PTD | M7 }, - { CSI21_DY1 , IEN | PTD | M7 }, - { CSI21_DX2 , IEN | PTD | M7 }, - { CSI21_DY2 , IEN | PTD | M7 }, - { CSI21_DX3 , IEN | PTD | M7 }, - { CSI21_DY3 , IEN | PTD | M7 }, - { CSI21_DX4 , IEN | PTD | M7 }, - { CSI21_DY4 , IEN | PTD | M7 }, - { CSI22_DX0 , IEN | PTD | M7 }, - { CSI22_DY0 , IEN | PTD | M7 }, - { CSI22_DX1 , IEN | PTD | M7 }, - { CSI22_DY1 , IEN | PTD | M7 }, - { CAM_SHUTTER , PTD | M0 }, - { CAM_STROBE , PTD | M0 }, - { CAM_GLOBALRESET , PTD | M3 }, - { USBB1_ULPITLL_CLK , IEN | PTD | M0 }, - { USBB1_ULPITLL_STP , PTU | M0 }, - { USBB1_ULPITLL_DIR , IEN | PTD | M0 }, - { USBB1_ULPITLL_NXT , IEN | PTD | M0 }, - { USBB1_ULPITLL_DAT0 , IEN | PTD | M0 }, - { USBB1_ULPITLL_DAT1 , IEN | PTD | M0 }, - { USBB1_ULPITLL_DAT2 , IEN | PTD | M0 }, - { USBB1_ULPITLL_DAT3 , IEN | PTD | M0 }, - { USBB1_ULPITLL_DAT4 , IEN | PTD | M0 }, - { USBB1_ULPITLL_DAT5 , IEN | PTD | M0 }, - { USBB1_ULPITLL_DAT6 , IEN | PTD | M0 }, - { USBB1_ULPITLL_DAT7 , IEN | PTD | M0 }, - { USBB1_HSIC_DATA , M0 }, - { USBB1_HSIC_STROBE , M0 }, - { USBC1_ICUSB_DP , M0 }, - { USBC1_ICUSB_DM , M0 }, - { SDMMC1_CLK , PTU | M0 }, - { SDMMC1_CMD , IEN | PTU | M0 }, - { SDMMC1_DAT0 , IEN | PTU | M0 }, - { SDMMC1_DAT1 , IEN | PTU | M0 }, - { SDMMC1_DAT2 , IEN | PTU | M0 }, - { SDMMC1_DAT3 , IEN | PTU | M0 }, - { SDMMC1_DAT4 , IEN | PTU | M0 }, - { SDMMC1_DAT5 , IEN | PTU | M0 }, - { SDMMC1_DAT6 , IEN | PTU | M0 }, - { SDMMC1_DAT7 , IEN | PTU | M0 }, - { ABE_MCBSP2_CLKX , IEN | M0 }, - { ABE_MCBSP2_DR , IEN | M0 }, - { ABE_MCBSP2_DX , M0 }, - { ABE_MCBSP2_FSX , IEN | M0 }, - { ABE_MCBSP1_CLKX , IEN | PTD | M7 }, - { ABE_MCBSP1_DR , IEN | PTD | M7 }, - { ABE_MCBSP1_DX , M0 }, - { ABE_MCBSP1_FSX , IEN | M0 }, - { ABE_PDM_UL_DATA , IEN | PTD | M7 }, - { ABE_PDM_DL_DATA , IEN | PTD | M7 }, - { ABE_PDM_FRAME , IEN | PTD | M7 }, - { ABE_PDM_LB_CLK , IEN | PTD | M7 }, - { ABE_CLKS , IEN | PTD | M7 }, - { ABE_DMIC_CLK1 , IEN | PTD | M7 }, - { ABE_DMIC_DIN1 , IEN | PTD | M7 }, - { ABE_DMIC_DIN2 , IEN | PTD | M3 }, - { ABE_DMIC_DIN3 , IEN | PTD | M3 }, - { UART2_CTS , IEN | PTU | M0 }, - { UART2_RTS , M0 }, - { UART2_RX , IEN | M0 }, - { UART2_TX , M0 }, - { HDQ_SIO , IEN | M7 }, - { I2C1_SCL , IEN | M0 }, - { I2C1_SDA , IEN | M0 }, - { I2C2_SCL , IEN | M0 }, - { I2C2_SDA , IEN | M0 }, - { I2C3_SCL , IEN | M0 }, - { I2C3_SDA , IEN | M0 }, - { I2C4_SCL , IEN | M0 }, - { I2C4_SDA , IEN | M0 }, - { MCSPI1_CLK , IEN | M0 }, - { MCSPI1_SOMI , IEN | M0 }, - { MCSPI1_SIMO , IEN | M0 }, - { MCSPI1_CS0 , IEN | PTD | M0 }, - { MCSPI1_CS1 , IEN | PTU | M1 }, - { MCSPI1_CS2 , M3 }, - { MCSPI1_CS3 , IEN | PTU | M7 }, - { UART3_CTS_RCTX , M1 }, - { UART3_RTS_SD , M0 }, - { UART3_RX_IRRX , IEN | PTU | M3 }, - { UART3_TX_IRTX , M0 }, - { SDMMC5_CLK , PTU | M0 }, - { SDMMC5_CMD , IEN | PTU | M0 }, - { SDMMC5_DAT0 , IEN | PTU | M0 }, - { SDMMC5_DAT1 , IEN | PTU | M0 }, - { SDMMC5_DAT2 , IEN | PTU | M0 }, - { SDMMC5_DAT3 , IEN | PTU | M0 }, - { MCSPI4_CLK , IEN | M0 }, - { MCSPI4_SIMO , IEN | M0 }, - { MCSPI4_SOMI , IEN | M0 }, - { MCSPI4_CS0 , IEN | PTD | M0 }, - { UART4_RX , IEN | M0 }, - { UART4_TX , M0 }, - { USBB2_ULPITLL_CLK , M3 }, - { USBB2_ULPITLL_STP , M5 }, - { USBB2_ULPITLL_DIR , M5 }, - { USBB2_ULPITLL_NXT , M5 }, - { USBB2_ULPITLL_DAT0 , M5 }, - { USBB2_ULPITLL_DAT1 , M5 }, - { USBB2_ULPITLL_DAT2 , M5 }, - { USBB2_ULPITLL_DAT3 , M5 }, - { USBB2_ULPITLL_DAT4 , M5 }, - { USBB2_ULPITLL_DAT5 , M5 }, - { USBB2_ULPITLL_DAT6 , M5 }, - { USBB2_ULPITLL_DAT7 , M5 }, - { USBB2_HSIC_DATA , M3 }, - { USBB2_HSIC_STROBE , M3 }, - { KPD_COL3 , IEN | PTD | M1 }, - { KPD_COL4 , IEN | PTD | M1 }, - { KPD_COL5 , IEN | PTD | M1 }, - { KPD_COL0 , IEN | PTD | M1 }, - { KPD_COL1 , IEN | PTD | M3 }, - { KPD_COL2 , IEN | PTD | M3 }, - { KPD_ROW3 , IEN | PTD | M1 }, - { KPD_ROW4 , IEN | PTD | M1 }, - { KPD_ROW5 , IEN | PTD | M1 }, - { KPD_ROW0 , IEN | PTD | M1 }, - { KPD_ROW1 , IEN | PTD | M1 }, - { KPD_ROW2 , IEN | PTD | M1 }, - { USBA0_OTG_CE , PTU | M0 }, - { USBA0_OTG_DP , M0 }, - { USBA0_OTG_DM , M0 }, - { FREF_CLK1_OUT , IEN | PTD | M7 }, - { FREF_CLK2_OUT , IEN | PTD | M7 }, - { SYS_NIRQ1 , IEN | PTU | M0 }, - { SYS_NIRQ2 , IEN | PTU | M0 }, - { SYS_BOOT0 , IEN | PTD | M0 }, - { SYS_BOOT1 , IEN | PTD | M0 }, - { SYS_BOOT2 , IEN | PTD | M0 }, - { SYS_BOOT3 , IEN | PTD | M0 }, - { SYS_BOOT4 , IEN | PTD | M0 }, - { SYS_BOOT5 , IEN | PTD | M0 }, - { DPM_EMU0 , IEN | PTU | M0 }, - { DPM_EMU1 , IEN | PTU | M3 }, - { DPM_EMU2 , IEN | PTD | M7 }, - { DPM_EMU3 , M5 }, - { DPM_EMU4 , M5 }, - { DPM_EMU5 , M5 }, - { DPM_EMU6 , M5 }, - { DPM_EMU7 , M5 }, - { DPM_EMU8 , M5 }, - { DPM_EMU9 , M5 }, - { DPM_EMU10 , M5 }, - { DPM_EMU11 , M5 }, - { DPM_EMU12 , M5 }, - { DPM_EMU13 , M5 }, - { DPM_EMU14 , M5 }, - { DPM_EMU15 , M5 }, - { DPM_EMU16 , M5 }, - { DPM_EMU17 , M5 }, - { DPM_EMU18 , M5 }, - { DPM_EMU19 , M5 }, - { CSI22_DX2 , IEN | PTD | M7 }, - { CSI22_DY2 , IEN | PTD | M7 }, -}; - -static const struct pad_conf_entry wkup_padconf_array[] = { - { GPIO_WK0 , IEN | PTD | M7 }, - { GPIO_WK1 , IEN | PTD | M7 }, - { GPIO_WK2 , IEN | PTD | M7 }, - { GPIO_WK3 , IEN | PTU | M7 }, - { GPIO_WK4 , IEN | PTD | M7 }, - { SR_SCL , IEN | M0 }, - { SR_SDA , IEN | M0 }, - { FREF_XTAL_IN , M0 }, - { FREF_SLICER_IN , M0 }, - { FREF_CLK_IOREQ , IEN | PTD | M0 }, - { FREF_CLK0_OUT , IEN | PTD | M7 }, - { FREF_CLK3_REQ , IEN | PTD | M7 }, - { FREF_CLK3_OUT , IEN | PTD | M7 }, - { FREF_CLK4_REQ , IEN | PTU | M3 }, - { FREF_CLK4_OUT , IEN | PTD | M0 }, - { SYS_32K , IEN | M0 }, - { SYS_NRESPWRON , M0 }, - { SYS_NRESWARM , M0 }, - { SYS_PWR_REQ , IEN | PTU | M0 }, - { SYS_PWRON_RESET_OUT , IEN | PTD | M0 }, - { SYS_BOOT6 , IEN | M0 }, - { SYS_BOOT7 , IEN | M0 }, - { JTAG_NTRST , IEN | PTD | M0 }, - { JTAG_TCK , IEN | PTD | M0 }, - { JTAG_RTCK , PTD | M0 }, - { JTAG_TMS_TMSC , IEN | M0 }, - { JTAG_TDI , IEN | PTU | M0 }, - { JTAG_TDO , IEN | PTU | M0 }, -}; - -void archosg9_set_muxconf_regs(void) -{ - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, - core_padconf_array, ARRAY_SIZE(core_padconf_array)); - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, - wkup_padconf_array, ARRAY_SIZE(wkup_padconf_array)); - - /* gpio_wk7 is used for controlling TPS on 4460 */ - if (omap4_revision() >= OMAP4460_ES1_0) { - /* Enable GPIO-1 clocks before TPS initialization */ - omap4_enable_gpio1_wup_clocks(); - } -} diff --git a/arch/arm/boards/archosg9/mux.h b/arch/arm/boards/archosg9/mux.h deleted file mode 100644 index d4b0c9da86..0000000000 --- a/arch/arm/boards/archosg9/mux.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _MUX_H -#define _MUX_H - -void archosg9_set_muxconf_regs(void); - -#endif /* _MUX_H */ diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c index e4610722f6..e22bc420b5 100644 --- a/arch/arm/boards/beagle/lowlevel.c +++ b/arch/arm/boards/beagle/lowlevel.c @@ -164,17 +164,18 @@ static void sdrc_init(void) static noinline int beagle_board_init_sdram(void) { - struct barebox_arm_boarddata *bd = (void *)OMAP3_SRAM_SCRATCH_SPACE + 0x10; + handoff_add_arm_machine(MACH_TYPE_OMAP3_BEAGLE); - boarddata_create(bd, MACH_TYPE_OMAP3_BEAGLE); - - barebox_arm_entry(0x80000000, SZ_128M, bd); + barebox_arm_entry(0x80000000, SZ_128M, NULL); } ENTRY_FUNCTION(start_omap3_beagleboard_sdram, bootinfo, r1, r2) { omap3_save_bootinfo((void *)bootinfo); + relocate_to_current_adr(); + setup_c(); + beagle_board_init_sdram(); } @@ -190,7 +191,6 @@ ENTRY_FUNCTION(start_omap3_beagleboard_sdram, bootinfo, r1, r2) static noinline int beagle_board_init(void) { int in_sdram = omap3_running_in_sdram(); - struct barebox_arm_boarddata bd; if (!in_sdram) omap3_core_init(); @@ -203,9 +203,9 @@ static noinline int beagle_board_init(void) if (!in_sdram) sdrc_init(); - boarddata_create(&bd, MACH_TYPE_OMAP3_BEAGLE); + handoff_add_arm_machine(MACH_TYPE_OMAP3_BEAGLE); - barebox_arm_entry(0x80000000, SZ_128M, &bd); + barebox_arm_entry(0x80000000, SZ_128M, NULL); } ENTRY_FUNCTION(start_omap3_beagleboard_sram, bootinfo, r1, r2) diff --git a/arch/arm/boards/canon-a1100/Makefile b/arch/arm/boards/canon-a1100/Makefile deleted file mode 100644 index 458f520900..0000000000 --- a/arch/arm/boards/canon-a1100/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -lwl-y += lowlevel.o diff --git a/arch/arm/boards/canon-a1100/lowlevel.c b/arch/arm/boards/canon-a1100/lowlevel.c deleted file mode 100644 index 47a9564e0f..0000000000 --- a/arch/arm/boards/canon-a1100/lowlevel.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> - -extern char __dtb_canon_a1100_start[]; - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - void *fdt; - - arm_cpu_lowlevel_init(); - - fdt = __dtb_canon_a1100_start + get_runtime_offset(); - - /* FIXME: can we determine RAM size using CP15 register? - * - * see http://chdk.setepontos.com/index.php?topic=5980.90 - * - * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363e/Bgbcdeca.html - * 4.2.19. c6, MPU memory region programming registers - * - * But the 'cpuinfo' command says that the Protection - * unit is disabled. - * The Control Register value (mrc p15, 0, %0, c0, c1, 4) - * is 0x00051078. - */ - - barebox_arm_entry(0x0, SZ_64M, fdt); -} diff --git a/arch/arm/boards/chumby_falconwing/lowlevel.c b/arch/arm/boards/chumby_falconwing/lowlevel.c index fdda6ba5f2..e823767739 100644 --- a/arch/arm/boards/chumby_falconwing/lowlevel.c +++ b/arch/arm/boards/chumby_falconwing/lowlevel.c @@ -9,12 +9,9 @@ static noinline void continue_imx_entry(size_t size) { - static struct barebox_arm_boarddata boarddata = { - .magic = BAREBOX_ARM_BOARDDATA_MAGIC, - .machine = MACH_TYPE_CHUMBY, - }; + handoff_add_arm_machine(MACH_TYPE_CHUMBY); - barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); + barebox_arm_entry(IMX_MEMORY_BASE, size, NULL); } ENTRY_FUNCTION(start_chumby_falconwing, r0, r1, r2) diff --git a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c index 447ef0dc66..2468f304e7 100644 --- a/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c +++ b/arch/arm/boards/crystalfontz-cfa10036/lowlevel.c @@ -9,12 +9,9 @@ static noinline void continue_imx_entry(size_t size) { - static struct barebox_arm_boarddata boarddata = { - .magic = BAREBOX_ARM_BOARDDATA_MAGIC, - .machine = MACH_TYPE_CFA10036, - }; + handoff_add_arm_machine(MACH_TYPE_CFA10036); - barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); + barebox_arm_entry(IMX_MEMORY_BASE, size, NULL); } ENTRY_FUNCTION(start_cfa10036, r0, r1, r2) diff --git a/arch/arm/boards/edb93xx/Makefile b/arch/arm/boards/edb93xx/Makefile deleted file mode 100644 index be969bde20..0000000000 --- a/arch/arm/boards/edb93xx/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += edb93xx.o -lwl-y += flash_cfg.o pll_cfg.o sdram_cfg.o diff --git a/arch/arm/boards/edb93xx/early_udelay.h b/arch/arm/boards/edb93xx/early_udelay.h deleted file mode 100644 index b902c3bfb7..0000000000 --- a/arch/arm/boards/edb93xx/early_udelay.h +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - -#include <common.h> - -/* delay execution before timers are initialized */ -static inline void early_udelay(uint32_t usecs) -{ - /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ - register uint32_t loops = usecs * (1000 / 20); - - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} diff --git a/arch/arm/boards/edb93xx/edb93xx.c b/arch/arm/boards/edb93xx/edb93xx.c deleted file mode 100644 index a3fb14822a..0000000000 --- a/arch/arm/boards/edb93xx/edb93xx.c +++ /dev/null @@ -1,121 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - -#include <common.h> -#include <driver.h> -#include <environment.h> -#include <fs.h> -#include <init.h> -#include <asm/armlinux.h> -#include <io.h> -#include <malloc.h> -#include <asm/mach-types.h> -#include <mach/ep93xx/ep93xx-regs.h> -#include <platform_data/eth-ep93xx.h> -#include "edb93xx.h" - -#define DEVCFG_U1EN (1 << 18) - -static struct ep93xx_eth_platform_data ep93xx_eth_info = { - .xcv_type = PHY_INTERFACE_MODE_MII, - .phy_addr = 1, -}; - -static int ep93xx_mem_init(void) -{ - arm_add_mem_device("ram0", CONFIG_EP93XX_SDRAM_BANK0_BASE, - CONFIG_EP93XX_SDRAM_BANK0_SIZE); -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2) - arm_add_mem_device("ram1", CONFIG_EP93XX_SDRAM_BANK1_BASE, - CONFIG_EP93XX_SDRAM_BANK1_SIZE); -#endif -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3) - arm_add_mem_device("ram2", CONFIG_EP93XX_SDRAM_BANK2_BASE, - CONFIG_EP93XX_SDRAM_BANK2_SIZE); -#endif -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4) - arm_add_mem_device("ram3", CONFIG_EP93XX_SDRAM_BANK3_BASE, - CONFIG_EP93XX_SDRAM_BANK3_SIZE); -#endif - - return 0; -} -mem_initcall(ep93xx_mem_init); - -static int ep93xx_devices_init(void) -{ - add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x60000000, EDB93XX_CFI_FLASH_SIZE, 0); - - /* - * Create partitions that should be - * not touched by any regular user - */ - devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); - - protect_file("/dev/env0", 1); - - /* - * Up to 32MiB NOR type flash, connected to - * CS line 6, data width is 16 bit - */ - add_generic_device("ep93xx_eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM, - &ep93xx_eth_info); - - armlinux_set_architecture(MACH_TYPE); - - return 0; -} - -device_initcall(ep93xx_devices_init); - -static int edb93xx_console_init(void) -{ - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; - char *shortname, *board; - - /* - * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of - * 14.7456/2 MHz - */ - uint32_t value = readl(&syscon->pwrcnt); - value |= SYSCON_PWRCNT_UART_BAUD; - writel(value, &syscon->pwrcnt); - - /* Enable UART1 */ - value = readl(&syscon->devicecfg); - value |= DEVCFG_U1EN; - writel(0xAA, &syscon->sysswlock); - writel(value, &syscon->devicecfg); - - if (IS_ENABLED(CONFIG_MACH_EDB9301)) - shortname = "EDB9301"; - else if (IS_ENABLED(CONFIG_MACH_EDB9302)) - shortname = "EDB9302"; - else if (IS_ENABLED(CONFIG_MACH_EDB9302)) - shortname = "EDB9302A"; - else if (IS_ENABLED(CONFIG_MACH_EDB9307)) - shortname = "EDB9307"; - else if (IS_ENABLED(CONFIG_MACH_EDB9307A)) - shortname = "EDB9307A"; - else if (IS_ENABLED(CONFIG_MACH_EDB9312)) - shortname = "EDB9312"; - else if (IS_ENABLED(CONFIG_MACH_EDB9315)) - shortname = "EDB9315"; - else if (IS_ENABLED(CONFIG_MACH_EDB9315A)) - shortname = "EDB9315A"; - else - shortname = "unknown"; - - board = basprintf("Cirrus Logic %s", shortname); - barebox_set_model(board); - free(board); - barebox_set_hostname(shortname); - - add_generic_device("pl010_serial", DEVICE_ID_DYNAMIC, NULL, UART1_BASE, 4096, - IORESOURCE_MEM, NULL); - - return 0; -} - -console_initcall(edb93xx_console_init); diff --git a/arch/arm/boards/edb93xx/edb93xx.h b/arch/arm/boards/edb93xx/edb93xx.h deleted file mode 100644 index efbe87684e..0000000000 --- a/arch/arm/boards/edb93xx/edb93xx.h +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - -#if defined(CONFIG_MACH_EDB9301) -#define MACH_TYPE MACH_TYPE_EDB9301 -#elif defined(CONFIG_MACH_EDB9302) -#define MACH_TYPE MACH_TYPE_EDB9302 -#elif defined(CONFIG_MACH_EDB9302A) -#define MACH_TYPE MACH_TYPE_EDB9302A -#elif defined(CONFIG_MACH_EDB9307) -#define MACH_TYPE MACH_TYPE_EDB9307 -#elif defined(CONFIG_MACH_EDB9307A) -#define MACH_TYPE MACH_TYPE_EDB9307A -#elif defined(CONFIG_MACH_EDB9312) -#define MACH_TYPE MACH_TYPE_EDB9312 -#elif defined(CONFIG_MACH_EDB9315) -#define MACH_TYPE MACH_TYPE_EDB9315 -#elif defined(CONFIG_MACH_EDB9315A) -#define MACH_TYPE MACH_TYPE_EDB9315A -#endif - -#if defined(CONFIG_MACH_EDB9301) || defined(CONFIG_MACH_EDB9302) || \ - defined(CONFIG_MACH_EDB9302A) -#define EDB93XX_CFI_FLASH_SIZE (16 * 1024 * 1024) -#elif defined(CONFIG_MACH_EDB9307) || defined(CONFIG_MACH_EDB9307A) || \ - defined(CONFIG_MACH_EDB9312) || defined(CONFIG_MACH_EDB9315) || \ - defined(CONFIG_MACH_EDB9315A) -#define EDB93XX_CFI_FLASH_SIZE (32 * 1024 * 1024) -#endif diff --git a/arch/arm/boards/edb93xx/env/bin/boot b/arch/arm/boards/edb93xx/env/bin/boot deleted file mode 100644 index 143f3d018d..0000000000 --- a/arch/arm/boards/edb93xx/env/bin/boot +++ /dev/null @@ -1,48 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ x${rootfs_boot_media} = xflash ]; -then - rootfs_img=/dev/nor0.rootfs_${active_cfg} - - if [ x${active_cfg} = x1 ]; - then - rootfs_blkdev=/dev/mtdblock4 - cfg_1_ro="ro" - cfg_2_ro="" - else - rootfs_blkdev=/dev/mtdblock6 - cfg_1_ro="" - cfg_2_ro="ro" - fi - - bootargs_rootfs="root=${rootfs_blkdev} rootfstype=squashfs ro" -elif [ x${rootfs_boot_media} = xnet ]; -then - bootargs_rootfs="root=/dev/nfs nfsroot=${eth0.serverip}:/srv/nfs/${board},v3,nolock,tcp ip=${eth0.ipaddr}" -else - echo "ERROR: \$rootfs_boot_media invalid: ${rootfs_boot_media}" - exit 1 -fi - -if [ x${kernel_boot_media} = xflash ]; -then - kernel_img=/dev/nor0.kernel_${active_cfg} -elif [ x${kernel_boot_media} = xnet ]; -then - cd / - tftp ${board}/kernel.img || exit 1 - kernel_img=/kernel.img -else - echo "ERROR: \$kernel_boot_media invalid: ${kernel_boot_media}" - exit 1 -fi - -source /env/bin/set_nor_parts - -bootargs_mtd="mtdparts=physmap-flash.0:${nor_parts}" - -bootargs="${bootargs_common} ${bootargs_mtd} ${bootargs_rootfs}" - -bootm ${kernel_img}
\ No newline at end of file diff --git a/arch/arm/boards/edb93xx/env/bin/flash_partition b/arch/arm/boards/edb93xx/env/bin/flash_partition deleted file mode 100644 index ded40aa8a3..0000000000 --- a/arch/arm/boards/edb93xx/env/bin/flash_partition +++ /dev/null @@ -1,22 +0,0 @@ -#!/bin/sh - -if [ $# != 2 ]; -then - echo "Usage: $0 <image> <partition>" - exit 1 -fi - -image=$1 -partition=$2 - -echo "Unlocking ${partition}" -unprotect ${partition} - -echo "Erasing ${partition}" -erase ${partition} - -echo "Flashing ${image} to ${partition}" -cp ${image} ${partition} - -echo "Locking ${partition}" -protect ${partition} diff --git a/arch/arm/boards/edb93xx/env/bin/init b/arch/arm/boards/edb93xx/env/bin/init deleted file mode 100644 index c6b5aed271..0000000000 --- a/arch/arm/boards/edb93xx/env/bin/init +++ /dev/null @@ -1,19 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config - -# add partitions to barebox -. /env/bin/set_nor_parts -addpart /dev/nor0 ${nor_parts} - -echo -echo -n "Hit any key to stop autoboot: " -timeout -a $autoboot_timeout -if [ $? != 0 ]; then - exit -fi - -boot
\ No newline at end of file diff --git a/arch/arm/boards/edb93xx/env/bin/set_nor_parts b/arch/arm/boards/edb93xx/env/bin/set_nor_parts deleted file mode 100644 index 38321fa8cc..0000000000 --- a/arch/arm/boards/edb93xx/env/bin/set_nor_parts +++ /dev/null @@ -1,3 +0,0 @@ -#!/bin/sh - -nor_parts="256k(barebox)ro,128k(env_boot),128k(env_boot.bak),1664k(kernel_1)${cfg_1_ro},6144k(rootfs_1)${cfg_1_ro},1664k(kernel_2)${cfg_2_ro},6144k(rootfs_2)${cfg_2_ro},128k(cfg_app),128k(cfg_app.bak)"
\ No newline at end of file diff --git a/arch/arm/boards/edb93xx/env/bin/update_kernel b/arch/arm/boards/edb93xx/env/bin/update_kernel deleted file mode 100644 index 3e4b9b0b8e..0000000000 --- a/arch/arm/boards/edb93xx/env/bin/update_kernel +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ $# != 1 ]; -then - echo "Usage: $0 <1/2>" - exit 1 -fi - -partition=/dev/nor0.kernel_$1 - -cd / -tftp ${board}/kernel.img || exit 1 - -flash_partition kernel.img ${partition} diff --git a/arch/arm/boards/edb93xx/env/bin/update_rootfs b/arch/arm/boards/edb93xx/env/bin/update_rootfs deleted file mode 100644 index 52a3699fd0..0000000000 --- a/arch/arm/boards/edb93xx/env/bin/update_rootfs +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -. /env/config - -if [ $# != 1 ]; -then - echo "Usage: $0 <1/2>" - exit 1 -fi - -partition=/dev/nor0.rootfs_$1 - -cd / -tftp ${board}/rootfs.img || exit 1 - -flash_partition rootfs.img ${partition} diff --git a/arch/arm/boards/edb93xx/env/config b/arch/arm/boards/edb93xx/env/config deleted file mode 100644 index 3266272742..0000000000 --- a/arch/arm/boards/edb93xx/env/config +++ /dev/null @@ -1,16 +0,0 @@ -#!/bin/sh - -eth0.ipaddr=192.168.0.50 -eth0.netmask=255.255.0.0 -eth0.serverip=192.168.0.8 -#eth0.ethaddr= - -board=edb9301 -autoboot_timeout=3 -active_cfg=1 -bootargs_common="console=ttyAM0,115200" - -# valid media: flash/net -kernel_boot_media=flash -rootfs_boot_media=flash - diff --git a/arch/arm/boards/edb93xx/flash_cfg.c b/arch/arm/boards/edb93xx/flash_cfg.c deleted file mode 100644 index 2c471c7721..0000000000 --- a/arch/arm/boards/edb93xx/flash_cfg.c +++ /dev/null @@ -1,22 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - -/* Flash setup for Cirrus edb93xx boards */ - -#include <common.h> -#include <mach/ep93xx/ep93xx-regs.h> -#include <io.h> - -#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ - SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ - 1 << SMC_BCR_MW_SHIFT) - -/* Called from assembly */ -void flash_cfg(void); - -void flash_cfg(void) -{ - struct smc_regs *smc = (struct smc_regs *)SMC_BASE; - - writel(SMC_BCR6_VALUE, &smc->bcr6); -} diff --git a/arch/arm/boards/edb93xx/pll_cfg.c b/arch/arm/boards/edb93xx/pll_cfg.c deleted file mode 100644 index 1a1c01aba2..0000000000 --- a/arch/arm/boards/edb93xx/pll_cfg.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> -// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> - -/* PLL setup for Cirrus edb93xx boards */ - -#include <common.h> -#include <io.h> -#include "pll_cfg.h" -#include "early_udelay.h" - -/* Called from assembly */ -void pll_cfg(void); - -void pll_cfg(void) -{ - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; - - /* setup PLL1 */ - writel(CLKSET1_VAL, &syscon->clkset1); - - /* - * flush the pipeline - * writing to CLKSET1 causes the EP93xx to enter standby for between - * 8 ms to 16 ms, until PLL1 stabilizes - */ - asm("nop"); - asm("nop"); - asm("nop"); - asm("nop"); - asm("nop"); - - /* setup PLL2 */ - writel(CLKSET2_VAL, &syscon->clkset2); - - /* - * the user's guide recommends to wait at least 1 ms for PLL2 to - * stabilize - */ - early_udelay(1000); -} diff --git a/arch/arm/boards/edb93xx/pll_cfg.h b/arch/arm/boards/edb93xx/pll_cfg.h deleted file mode 100644 index 662c92337a..0000000000 --- a/arch/arm/boards/edb93xx/pll_cfg.h +++ /dev/null @@ -1,53 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - -/* PLL register values for Cirrus edb93xx boards */ - -#include <config.h> -#include <mach/ep93xx/ep93xx-regs.h> - -#if defined(CONFIG_MACH_EDB9301) -/* - * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 - * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, - * pll1_x2: 331776000.000000, pll1_out: 331776000.000000 - */ -#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ - 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ - SYSCON_CLKSET1_NBYP1 | \ - 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) -#elif defined(CONFIG_MACH_EDB9302) || defined(CONFIG_MACH_EDB9302A) || \ - defined(CONFIG_MACH_EDB9307) || defined(CONFIG_MACH_EDB9307A) || \ - defined CONFIG_MACH_EDB9312 || defined(CONFIG_MACH_EDB9315) ||\ - defined(CONFIG_MACH_EDB9315A) -/* - * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2 - * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000, - * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000 - */ -#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ - 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ - SYSCON_CLKSET1_NBYP1 | \ - 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) -#else -#error "Undefined board" -#endif - -/* - * usb_div: 4, nbyp2: 1, pll2_en: 1 - * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, - * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 - */ -#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ - SYSCON_CLKSET2_PLL2_EN | \ - SYSCON_CLKSET2_NBYP2 | \ - 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) diff --git a/arch/arm/boards/edb93xx/sdram_cfg.c b/arch/arm/boards/edb93xx/sdram_cfg.c deleted file mode 100644 index 3cee834910..0000000000 --- a/arch/arm/boards/edb93xx/sdram_cfg.c +++ /dev/null @@ -1,128 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> -// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> - -#include <common.h> -#include <io.h> -#include "sdram_cfg.h" -#include "early_udelay.h" - -#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \ - (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) - -#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ - (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0 - -static void precharge_all_banks(void); -static void setup_refresh_timer(void); -static void program_mode_registers(void); - -/* Called from assembly */ -void sdram_cfg(void); - -void sdram_cfg(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - unsigned long pc = get_pc(); - - if (pc < CONFIG_EP93XX_SDRAM_BANK3_BASE + CONFIG_EP93XX_SDRAM_BANK3_SIZE) - return; - - writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG); - - /* Issue continous NOP commands */ - writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); - - early_udelay(200); - - precharge_all_banks(); - - setup_refresh_timer(); - - program_mode_registers(); - - /* Select normal operation mode */ - writel(GLCONFIG_CKE, &sdram->glconfig); -} - -static void precharge_all_banks(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Issue PRECHARGE ALL commands */ - writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig); - - /* - * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always - * issued. - * - * Cirrus proposes a workaround which consists in performing a read from - * each bank to force the precharge. This causes some boards to hang. - * Writing to the SDRAM banks instead of reading has the same - * side-effect (the SDRAM controller issues the necessary precharges), - * but is known to work on all supported boards - */ - - PRECHARGE_BANK(0); - -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2) - PRECHARGE_BANK(1); -#endif - -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3) - PRECHARGE_BANK(2); -#endif - -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4) - PRECHARGE_BANK(3); -#endif -} - -static void setup_refresh_timer(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Load refresh timer with 10 to issue refresh every 10 cycles */ - writel(0x0a, &sdram->refrshtimr); - - /* - * Wait at least 80 clock cycles to provide 8 refresh cycles - * to all SDRAMs - */ - early_udelay(1); - - /* - * Program refresh timer with normal value - * We need 8192 refresh cycles every 64ms - * at 15ns (HCLK >= 66MHz) per cycle: - * 64ms / 8192 = 7.8125us - * 7.8125us / 15ns = 520 (0x208) - */ - /* - * TODO: redboot uses 0x1e0 for the slowest possible device - * but i don't understand how this value is calculated - */ - writel(0x208, &sdram->refrshtimr); -} - -static void program_mode_registers(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Select mode register update mode */ - writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); - - PROGRAM_MODE_REG(0); - -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 2) - PROGRAM_MODE_REG(1); -#endif - -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS >= 3) - PROGRAM_MODE_REG(2); -#endif - -#if (CONFIG_EP93XX_SDRAM_NUM_BANKS == 4) - PROGRAM_MODE_REG(3); -#endif -} diff --git a/arch/arm/boards/edb93xx/sdram_cfg.h b/arch/arm/boards/edb93xx/sdram_cfg.h deleted file mode 100644 index ddb9e442ed..0000000000 --- a/arch/arm/boards/edb93xx/sdram_cfg.h +++ /dev/null @@ -1,125 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Matthias Kaehlcke <matthias@kaehlcke.net> -// SPDX-FileCopyrightText: 2006 Dominic Rath <Dominic.Rath@gmx.de> - -#include <config.h> -#include <mach/ep93xx/ep93xx-regs.h> - -#define SDRAM_BASE_ADDR CONFIG_EP93XX_SDRAM_BANK0_BASE - -#ifdef CONFIG_EP93XX_SDCE0_PHYS_OFFSET -#define SDRAM_DEVCFG_REG devcfg0 -#elif defined(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) -#define SDRAM_DEVCFG_REG devcfg3 -#else -#error "SDRAM bank configuration" -#endif - -#if defined(CONFIG_MACH_EDB9301) || defined(CONFIG_MACH_EDB9302) ||\ - defined(CONFIG_MACH_EDB9302A) -/* - * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM - * - * CLK cycle time min: - * @ CAS latency = 3: 7.5ns - * @ CAS latency = 2: 10ns - * We're running at 66MHz (EDB9301) / 100Mhz (EDB9302(a)) external - * bus speed (HCLK), with a cycle time of 15ns / 10ns, so it's safe - * to use CAS latency = 2 - * - * RAS-to-CAS delay min: - * 20ns - * At 15ns/10ns cycle time, we use RAS-to-CAS delay = 2 - * - * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear - * as four blocks of 8MB size, instead of eight blocks of 4MB size: - * - * EDB9301/EDB9302: - * - * 0x00000000 - 0x007fffff - * 0x01000000 - 0x017fffff - * 0x04000000 - 0x047fffff - * 0x05000000 - 0x057fffff - * - * - * EDB9302a: - * - * 0xc0000000 - 0xc07fffff - * 0xc1000000 - 0xc17fffff - * 0xc4000000 - 0xc47fffff - * 0xc5000000 - 0xc57fffff - * - * BANKCOUNT = 1: This is a device with four banks - */ - -#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ - SDRAM_DEVCFG_SROMLL | \ - SDRAM_DEVCFG_CASLAT_2 | \ - SDRAM_DEVCFG_RASTOCAS_2 | \ - SDRAM_DEVCFG_EXTBUSWIDTH) - -/* - * 16 bit ext. bus - * - * A[22:09] is output as SYA[13:0] - * CAS latency: 2 - * Burst type: sequential - * Burst length: 8 (required for 16 bit ext. bus) - * SYA[13:0] = 0x0023 - */ -#define SDRAM_MODE_REG_VAL 0x4600 - -#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */ -#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */ -#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */ -#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */ - -#elif defined(CONFIG_MACH_EDB9307) || defined(CONFIG_MACH_EDB9307A) ||\ - defined CONFIG_MACH_EDB9312 || defined(CONFIG_MACH_EDB9315) ||\ - defined(CONFIG_MACH_EDB9315A) -/* - * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM - * - * CLK cycle time min: - * @ CAS latency = 3: 7.5ns - * @ CAS latency = 2: 10ns - * We're running at 100MHz (10ns cycle time) external bus speed (HCLK), - * so it's safe to use CAS latency = 2 - * - * RAS-to-CAS delay min: - * 20ns - * At 10ns cycle time, we use RAS-to-CAS delay = 2 - * - * EDB9307, EDB9312, EDB9315: - * - * 0x00000000 - 0x01ffffff - * 0x04000000 - 0x05ffffff - * - * - * EDB9307a, EDB9315a: - * - * 0xc0000000 - 0xc1ffffff - * 0xc4000000 - 0xc5ffffff - */ - -#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ - SDRAM_DEVCFG_SROMLL | \ - SDRAM_DEVCFG_CASLAT_2 | \ - SDRAM_DEVCFG_RASTOCAS_2) - -/* - * 32 bit ext. bus - * - * A[23:10] is output as SYA[13:0] - * CAS latency: 2 - * Burst type: sequential - * Burst length: 4 - * SYA[13:0] = 0x0022 - */ -#define SDRAM_MODE_REG_VAL 0x8800 - -#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */ -#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */ -#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */ -#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */ -#endif diff --git a/arch/arm/boards/freescale-mx23-evk/lowlevel.c b/arch/arm/boards/freescale-mx23-evk/lowlevel.c index 195ade3a7f..2f31b4fd0c 100644 --- a/arch/arm/boards/freescale-mx23-evk/lowlevel.c +++ b/arch/arm/boards/freescale-mx23-evk/lowlevel.c @@ -9,12 +9,9 @@ static noinline void continue_imx_entry(size_t size) { - static struct barebox_arm_boarddata boarddata = { - .magic = BAREBOX_ARM_BOARDDATA_MAGIC, - .machine = MACH_TYPE_MX23EVK, - }; + handoff_add_arm_machine(MACH_TYPE_MX23EVK); - barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); + barebox_arm_entry(IMX_MEMORY_BASE, size, NULL); } ENTRY_FUNCTION(start_imx23_evk, r0, r1, r2) diff --git a/arch/arm/boards/imx233-olinuxino/lowlevel.c b/arch/arm/boards/imx233-olinuxino/lowlevel.c index 91c1ba3dba..e4b6b1207f 100644 --- a/arch/arm/boards/imx233-olinuxino/lowlevel.c +++ b/arch/arm/boards/imx233-olinuxino/lowlevel.c @@ -13,12 +13,9 @@ static noinline void continue_imx_entry(size_t size) { - static struct barebox_arm_boarddata boarddata = { - .magic = BAREBOX_ARM_BOARDDATA_MAGIC, - .machine = MACH_TYPE_IMX233_OLINUXINO, - }; + handoff_add_arm_machine(MACH_TYPE_IMX233_OLINUXINO); - barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); + barebox_arm_entry(IMX_MEMORY_BASE, size, NULL); } ENTRY_FUNCTION(start_barebox_olinuxino_imx23, r0, r1, r2) diff --git a/arch/arm/boards/karo-tx28/lowlevel.c b/arch/arm/boards/karo-tx28/lowlevel.c index 3be5f521e1..e423d5ecab 100644 --- a/arch/arm/boards/karo-tx28/lowlevel.c +++ b/arch/arm/boards/karo-tx28/lowlevel.c @@ -17,12 +17,9 @@ static noinline void continue_imx_entry(size_t size) { - static struct barebox_arm_boarddata boarddata = { - .magic = BAREBOX_ARM_BOARDDATA_MAGIC, - .machine = MACH_TYPE_TX28, - }; + handoff_add_arm_machine(MACH_TYPE_TX28); - barebox_arm_entry(IMX_MEMORY_BASE, size, &boarddata); + barebox_arm_entry(IMX_MEMORY_BASE, size, NULL); } ENTRY_FUNCTION(start_barebox_karo_tx28, r0, r1, r2) diff --git a/arch/arm/boards/lubbock/Makefile b/arch/arm/boards/lubbock/Makefile deleted file mode 100644 index da63d2625f..0000000000 --- a/arch/arm/boards/lubbock/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/lubbock/board.c b/arch/arm/boards/lubbock/board.c deleted file mode 100644 index af046e110a..0000000000 --- a/arch/arm/boards/lubbock/board.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> - -#include <common.h> -#include <driver.h> -#include <environment.h> -#include <fs.h> -#include <init.h> -#include <led.h> -#include <gpio.h> -#include <pwm.h> -#include <linux/sizes.h> - -#include <mach/pxa/devices.h> -#include <mach/pxa/mfp-pxa27x.h> -#include <mach/pxa/pxa-regs.h> -#include <mach/pxa/udc_pxa2xx.h> -#include <mach/pxa/mci_pxa2xx.h> - -#include <platform_data/eth-smc91111.h> -#include <asm/armlinux.h> -#include <asm/io.h> -#include <asm/mmu.h> - -#include <asm/mach-types.h> - -#define ECOR 0x8000 -#define ECOR_RESET 0x80 -#define ECOR_LEVEL_IRQ 0x40 -#define ECOR_WR_ATTRIB 0x04 -#define ECOR_ENABLE 0x01 - -#define ECSR 0x8002 -#define ECSR_IOIS8 0x20 -#define ECSR_PWRDWN 0x04 -#define ECSR_INT 0x02 - -static struct smc91c111_pdata smsc91x_pdata = { - .control_setup = 0x0800, - .config_setup = 0x10b2, - .bus_width = 16, - .addr_shift = 2, -}; - -static unsigned long lubbock_pin_config[] = { - GPIO15_nCS_1, /* CS1 - Flash */ - GPIO78_nCS_2, /* CS2 - Baseboard FGPA + SRAM */ - GPIO79_nCS_3, /* CS3 - SMC ethernet */ - GPIO80_nCS_4, /* CS4 - SA1111 */ - - /* LCD - 16bpp DSTN */ - GPIOxx_LCD_DSTN_16BPP, - - /* FFUART */ - GPIO34_FFUART_RXD, - GPIO35_FFUART_CTS, - GPIO36_FFUART_DCD, - GPIO37_FFUART_DSR, - GPIO38_FFUART_RI, - GPIO39_FFUART_TXD, - GPIO40_FFUART_DTR, - GPIO41_FFUART_RTS, -}; - -static int lubbock_devices_init(void) -{ - void *nor0_iospace; - - armlinux_set_architecture(MACH_TYPE_LUBBOCK); - - pxa_add_uart((void *)0x40100000, 0); - pxa_add_pwm((void *)0x40b00000, 0); - - nor0_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_64M); - add_cfi_flash_device(0, (ulong)nor0_iospace, SZ_64M, 0); - add_cfi_flash_device(1, 0x04000000, SZ_64M, 0); - devfs_add_partition("nor0", SZ_2M, SZ_256K, DEVFS_PARTITION_FIXED, - "env0"); - add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, - 0x0c000300, 0xff4000, IORESOURCE_MEM, - &smsc91x_pdata); - return 0; -} - -device_initcall(lubbock_devices_init); - -static void smc_init(void) -{ - /* SMC91c96 */ - void __iomem *attaddr = (void __iomem *)0x0e000000; - - writel(ECOR_RESET, attaddr + (ECOR << 2)); - mdelay(100); - writel(0, attaddr + (ECOR << 2)); - writel(ECOR_ENABLE, attaddr + (ECOR << 2)); - - /* force 16-bit mode */ - writel(0, attaddr + (ECSR << 2)); - mdelay(100); -} - -static int lubbock_coredevice_init(void) -{ - barebox_set_model("Lubbock PXA25x"); - barebox_set_hostname("lubbock"); - pxa2xx_mfp_config(ARRAY_AND_SIZE(lubbock_pin_config)); - smc_init(); - return 0; -} -coredevice_initcall(lubbock_coredevice_init); - -static int lubbock_mem_init(void) -{ - arm_add_mem_device("ram0", 0xa0000000, SZ_64M); - add_mem_device("sram0", 0x0a000000, SZ_1M, IORESOURCE_MEM_WRITEABLE); - return 0; -} -mem_initcall(lubbock_mem_init); diff --git a/arch/arm/boards/lubbock/env/boot/nor-ubi b/arch/arm/boards/lubbock/env/boot/nor-ubi deleted file mode 100644 index 533605e86a..0000000000 --- a/arch/arm/boards/lubbock/env/boot/nor-ubi +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nor0.kernel" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:linux_root ubi.mtd=nor0.root rootfstype=ubifs" diff --git a/arch/arm/boards/lubbock/env/init/mtdparts-nor b/arch/arm/boards/lubbock/env/init/mtdparts-nor deleted file mode 100644 index b5c4e32411..0000000000 --- a/arch/arm/boards/lubbock/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)" -kernelname="application-flash" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/lubbock/env/nv/linux.bootargs.console b/arch/arm/boards/lubbock/env/nv/linux.bootargs.console deleted file mode 100644 index 476b1fbe49..0000000000 --- a/arch/arm/boards/lubbock/env/nv/linux.bootargs.console +++ /dev/null @@ -1 +0,0 @@ -console=ttyS0,115200 diff --git a/arch/arm/boards/lubbock/lowlevel.c b/arch/arm/boards/lubbock/lowlevel.c deleted file mode 100644 index ef6b544a26..0000000000 --- a/arch/arm/boards/lubbock/lowlevel.c +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <init.h> -#include <io.h> - -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <linux/sizes.h> -#include <mach/pxa/pxa-regs.h> -#include <mach/pxa/regs-ost.h> - -/* - * Memory settings - */ -#define DEFAULT_MSC0_VAL 0x23d223d2 -#define DEFAULT_MSC1_VAL 0x3ff1a441 -#define DEFAULT_MSC2_VAL 0x7ff17ff1 -#define DEFAULT_MDCNFG_VAL 0x00001ac9 -#define DEFAULT_MDREFR_VAL 0x00018018 -#define DEFAULT_MDMRS_VAL 0x00000000 - -#define DEFAULT_FLYCNFG_VAL 0x00000000 -#define DEFAULT_SXCNFG_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define DEFAULT_MECR_VAL 0x00000000 -#define DEFAULT_MCMEM0_VAL 0x00010504 -#define DEFAULT_MCMEM1_VAL 0x00010504 -#define DEFAULT_MCATT0_VAL 0x00010504 -#define DEFAULT_MCATT1_VAL 0x00010504 -#define DEFAULT_MCIO0_VAL 0x00004715 -#define DEFAULT_MCIO1_VAL 0x00004715 - -static inline void writelrb(uint32_t val, volatile u32 __iomem *addr) -{ - writel(val, addr); - barrier(); - readl(addr); - barrier(); -} - -static inline void pxa_wait_ticks(int ticks) -{ - writel(0, &OSCR); - while (readl(&OSCR) < ticks) - barrier(); -} - -static inline void pxa2xx_dram_init(void) -{ - uint32_t tmp; - int i; - /* - * 1) Initialize Asynchronous static memory controller - */ - - writelrb(DEFAULT_MSC0_VAL, &MSC0); - writelrb(DEFAULT_MSC1_VAL, &MSC1); - writelrb(DEFAULT_MSC2_VAL, &MSC2); - /* - * 2) Initialize Card Interface - */ - - /* MECR: Memory Expansion Card Register */ - writelrb(DEFAULT_MECR_VAL, &MECR); - /* MCMEM0: Card Interface slot 0 timing */ - writelrb(DEFAULT_MCMEM0_VAL, &MCMEM0); - /* MCMEM1: Card Interface slot 1 timing */ - writelrb(DEFAULT_MCMEM1_VAL, &MCMEM1); - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - writelrb(DEFAULT_MCATT0_VAL, &MCATT0); - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - writelrb(DEFAULT_MCATT1_VAL, &MCATT1); - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - writelrb(DEFAULT_MCIO0_VAL, &MCIO0); - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - writelrb(DEFAULT_MCIO1_VAL, &MCIO1); - - /* - * 3) Configure Fly-By DMA register - */ - - writelrb(DEFAULT_FLYCNFG_VAL, &FLYCNFG); - - /* - * 4) Initialize Timing for Sync Memory (SDCLK0) - */ - - /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. - */ - - /* Read current MDREFR config and zero out DRI */ - tmp = readl(&MDREFR) & ~0xfff; - /* Add user-specified DRI */ - tmp |= DEFAULT_MDREFR_VAL & 0xfff; - /* Configure important bits */ - tmp |= MDREFR_K0RUN | MDREFR_SLFRSH; - tmp &= ~(MDREFR_APD | MDREFR_E1PIN); - - /* Write MDREFR back */ - writelrb(tmp, &MDREFR); - - /* - * 5) Initialize Synchronous Static Memory (Flash/Peripherals) - */ - - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. - */ - writelrb(DEFAULT_SXCNFG_VAL, &SXCNFG); - - /* - * 6) Initialize SDRAM - */ - - writelrb(DEFAULT_MDREFR_VAL & ~MDREFR_SLFRSH, &MDREFR); - writelrb(DEFAULT_MDREFR_VAL | MDREFR_E1PIN, &MDREFR); - - /* - * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure - * but not enable each SDRAM partition pair. - */ - - writelrb(DEFAULT_MDCNFG_VAL & - ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), &MDCNFG); - /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ - pxa_wait_ticks(0x300); - - /* - * 8) Trigger a number (usually 8) refresh cycles by attempting - * non-burst read or write accesses to disabled SDRAM, as commonly - * specified in the power up sequence documented in SDRAM data - * sheets. The address(es) used for this purpose must not be - * cacheable. - */ - for (i = 9; i >= 0; i--) { - writel(i, 0xa0000000); - barrier(); - } - /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). - */ - - tmp = DEFAULT_MDCNFG_VAL & - (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3); - tmp |= readl(&MDCNFG); - writelrb(tmp, &MDCNFG); - - /* - * 10) Write MDMRS. - */ - - writelrb(DEFAULT_MDMRS_VAL, &MDMRS); - - /* - * 11) Enable APD - */ - - if (DEFAULT_MDREFR_VAL & MDREFR_APD) { - tmp = readl(&MDREFR); - tmp |= MDREFR_APD; - writelrb(tmp, &MDREFR); - } -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - unsigned long pssr = PSPR; - unsigned long pc = get_pc(); - - arm_cpu_lowlevel_init(); - CKEN |= CKEN_OSTIMER | CKEN_MEMC | CKEN_FFUART; - - /* - * When not running from SDRAM, get it out of self refresh, and/or - * initialize it. - */ - if (!(pc >= 0xa0000000 && pc < 0xb0000000)) - pxa2xx_dram_init(); - - if ((pssr >= 0xa0000000 && pssr < 0xb0000000) || - (pssr >= 0x04000000 && pssr < 0x10000000)) - asm("mov pc, %0" : : "r"(pssr) : ); - - barebox_arm_entry(0xa0000000, SZ_64M, 0); -} diff --git a/arch/arm/boards/mainstone/Makefile b/arch/arm/boards/mainstone/Makefile deleted file mode 100644 index da63d2625f..0000000000 --- a/arch/arm/boards/mainstone/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/mainstone/board.c b/arch/arm/boards/mainstone/board.c deleted file mode 100644 index 979a4f3609..0000000000 --- a/arch/arm/boards/mainstone/board.c +++ /dev/null @@ -1,118 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2015 Robert Jarzmik <robert.jarzmik@free.fr> - -#include <common.h> -#include <driver.h> -#include <environment.h> -#include <fs.h> -#include <init.h> -#include <led.h> -#include <gpio.h> -#include <pwm.h> -#include <linux/sizes.h> - -#include <mach/pxa/devices.h> -#include <mach/pxa/mfp-pxa27x.h> -#include <mach/pxa/pxa-regs.h> -#include <mach/pxa/udc_pxa2xx.h> -#include <mach/pxa/mci_pxa2xx.h> - -#include <platform_data/eth-smc91111.h> -#include <asm/armlinux.h> -#include <asm/io.h> -#include <asm/mmu.h> - -#include <asm/mach-types.h> - -static struct smc91c111_pdata smsc91x_pdata = { - .word_aligned_short_writes = true, -}; - -static unsigned long mainstone_pin_config[] = { - GPIO15_nCS_1, /* CS1 - Flash */ - GPIO78_nCS_2, /* CS2 - Baseboard FGPA + SRAM */ - GPIO80_nCS_4, /* CS4 - SMC ethernet */ - - /* Ethernet: static memory VLIO */ - GPIO18_RDY, - - /* PC Card */ - GPIO48_nPOE, - GPIO49_nPWE, - GPIO50_nPIOR, - GPIO51_nPIOW, - GPIO85_nPCE_1, - GPIO54_nPCE_2, - GPIO79_PSKTSEL, - GPIO55_nPREG, - GPIO56_nPWAIT, - GPIO57_nIOIS16, - - /* MMC */ - GPIO32_MMC_CLK, - GPIO112_MMC_CMD, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - - /* LCD - 16bpp DSTN */ - GPIOxx_LCD_TFT_16BPP, - - /* Backlight */ - GPIO16_PWM0_OUT, - - /* FFUART */ - GPIO34_FFUART_RXD, - GPIO35_FFUART_CTS, - GPIO36_FFUART_DCD, - GPIO37_FFUART_DSR, - GPIO38_FFUART_RI, - GPIO39_FFUART_TXD, - GPIO40_FFUART_DTR, - GPIO41_FFUART_RTS, -}; - -static int mainstone_devices_init(void) -{ - void *nor0_iospace; - - armlinux_set_architecture(MACH_TYPE_MAINSTONE); - - pxa_add_uart((void *)0x40100000, 0); - pxa_add_pwm((void *)0x40b00000, 0); - - nor0_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_64M); - add_cfi_flash_device(0, (ulong)nor0_iospace, SZ_64M, 0); - add_cfi_flash_device(1, 0x04000000, SZ_64M, 0); - devfs_add_partition("nor0", SZ_2M, SZ_256K, DEVFS_PARTITION_FIXED, - "env0"); - add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, - 0x10000300, 0xff4000, IORESOURCE_MEM, - &smsc91x_pdata); - return 0; -} - -device_initcall(mainstone_devices_init); - -static int mainstone_coredevice_init(void) -{ - /* - * Put the board in superspeed (520 MHz) to speed-up logo/OS loading. - */ - CCCR = CCCR_A | 0x20290; - - barebox_set_model("Mainstone PXA27x"); - barebox_set_hostname("mainstone"); - pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config)); - return 0; -} -coredevice_initcall(mainstone_coredevice_init); - -static int mainstone_mem_init(void) -{ - arm_add_mem_device("ram0", 0xa0000000, SZ_64M); - add_mem_device("sram0", 0x0a000000, SZ_1M, IORESOURCE_MEM_WRITEABLE); - return 0; -} -mem_initcall(mainstone_mem_init); diff --git a/arch/arm/boards/mainstone/env/boot/nor-ubi b/arch/arm/boards/mainstone/env/boot/nor-ubi deleted file mode 100644 index 533605e86a..0000000000 --- a/arch/arm/boards/mainstone/env/boot/nor-ubi +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nor0.kernel" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:linux_root ubi.mtd=nor0.root rootfstype=ubifs" diff --git a/arch/arm/boards/mainstone/env/init/mtdparts-nor b/arch/arm/boards/mainstone/env/init/mtdparts-nor deleted file mode 100644 index b5c4e32411..0000000000 --- a/arch/arm/boards/mainstone/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="2048k@0(nor0.barebox)ro,256k(nor0.barebox-env),256k(nor0.barebox-logo),256k(nor0.barebox-logo2),5120k(nor0.kernel),-(nor0.root)" -kernelname="application-flash" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/mainstone/env/nv/linux.bootargs.console b/arch/arm/boards/mainstone/env/nv/linux.bootargs.console deleted file mode 100644 index 476b1fbe49..0000000000 --- a/arch/arm/boards/mainstone/env/nv/linux.bootargs.console +++ /dev/null @@ -1 +0,0 @@ -console=ttyS0,115200 diff --git a/arch/arm/boards/mainstone/lowlevel.c b/arch/arm/boards/mainstone/lowlevel.c deleted file mode 100644 index 29d12f7424..0000000000 --- a/arch/arm/boards/mainstone/lowlevel.c +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <init.h> -#include <io.h> - -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <linux/sizes.h> -#include <mach/pxa/pxa-regs.h> -#include <mach/pxa/regs-ost.h> - -/* - * Memory settings - */ -#define DEFAULT_MSC0_VAL 0x23F2B8F2 -#define DEFAULT_MSC1_VAL 0x7ff0fff1 -/* - * MSC2: static partitions 4 and 5 - * - * [31] 0 - RBUFF5 - * [30:28] 111 - RRR5 - * [27:24] 1111- RDN5 - * [23:20] 1111- RDF5 - * [19] 0 - RBW5 - * [18:16] 000 - RT5 - * [15] 0 - RBUFF4: Slow device (don't wait for data return) - * [14:12] 111 - RRR4: Toff=(2*RRR + 1)*CLK_MEM (from nCS=1 to next nCS=0) - * [11:8] 1111- RDN4: T=2*RDN*CLK_MEM (from nOE=1 to addr hold) - * [7:4] 1111- RDF4: T=RDF*CLK_MEM of hold nOE/nPWE for read/write - * [3] 0 - RBW4: Bus width is 32 bits - * [2:0] 000 - RT4: Partition is VLIO - */ -#define DEFAULT_MSC2_VAL 0x7ff0fff4 - -/* - * MDCNFG: SDRAM Configuration Register - * - * [31] 0 - Memory map 0/1 uses normal 256 MBytes - * [30] 0 - dcacx2: no extra column addressing - * [29] 0 - reserved - * [28] 0 - SA1111 compatiblity mode - * [27] 0 - latch return data with return clock - * [26] 0 - alternate addressing for pair 2/3 - * [25:24] 00 - timings - * [23] 0 - internal banks in lower partition 2/3 (not used) - * [22:21] 00 - row address bits for partition 2/3 (not used) - * [20:19] 00 - column address bits for partition 2/3 (not used) - * [18] 0 - SDRAM partition 2/3 width is 32 bit - * [17] 0 - SDRAM partition 3 disabled - * [16] 0 - SDRAM partition 2 disabled - * [15] 0 - Stack1 : see stack0 - * [14] 0 - dcacx0 : no extra column addressing - * [13] 0 - stack0 : stack = 0b00 => SDRAM address placed on MA<24:10> - * [12] 0 - SA1110 compatiblity mode - * [11] 1 - always 1 - * [10] 0 - no alternate addressing for pair 0/1 - * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=7*MemClk tRC=11*MemClk - * [7] 1 - 4 internal banks in partitions 0/1 - * [06:05] 10 - drac0: 13 row address bits for partition 0/1 - * [04:03] 01 - dcac0: 9 column address bits for partition 0/1 - * [02] 0 - SDRAM partition 0/1 width is 32 bit - * [01] 1 - enable SDRAM partition 1 - * [00] 1 - enable SDRAM partition 0 - * - * Configuration is for 1 bank of 64MBytes (13 rows * 9 cols) - * in bank0, of width 32 bits, with 4 internal banks. - * Timings (in times of SDCLK<1>): tRP = 3clk, CL=3, rRCD=3clk, - * tRAS=7clk, tRC=11clk - */ -#define DEFAULT_MDCNFG_VAL 0x00000acb - -/* - * MDREFR: SDRAM Configuration Register - * - * [25] 0 - K2FREE=0 - * [24] 0 - K1FREE=0 - * [23] 0 - K0FREE=0 - * [22] 0 - SLFRSH=0 - * [21] - * [20] 0 - APD - * [19] 0 - K2DB2=0 - * [18] 0 - K2RUN=0 - * [17] 1 - K1DB2=1 - * [16] 1 - K1RUN=1 - * [15] 0 - EP1IN - * [14] 1 - K0DB2=1 - * [13] 1 - K0RUN=1 - * [12] - * [11..0] 17 - DRI=17 - */ -#define DEFAULT_MDREFR_VAL 0x00036017 -#define DEFAULT_MDMRS_VAL 0x00320032 - -#define DEFAULT_FLYCNFG_VAL 0x00000000 -#define DEFAULT_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define DEFAULT_MECR_VAL 0x00000001 -#define DEFAULT_MCMEM0_VAL 0x00014307 -#define DEFAULT_MCMEM1_VAL 0x00014307 -#define DEFAULT_MCATT0_VAL 0x0001c787 -#define DEFAULT_MCATT1_VAL 0x0001c787 -#define DEFAULT_MCIO0_VAL 0x0001430f -#define DEFAULT_MCIO1_VAL 0x0001430f - -static inline void writelrb(uint32_t val, volatile u32 __iomem *addr) -{ - writel(val, addr); - barrier(); - readl(addr); - barrier(); -} - -static inline void pxa_wait_ticks(int ticks) -{ - writel(0, &OSCR); - while (readl(&OSCR) < ticks) - barrier(); -} - -static inline void pxa2xx_dram_init(void) -{ - uint32_t tmp, mask; - int i; - /* - * 1) Initialize Asynchronous static memory controller - */ - - writelrb(DEFAULT_MSC1_VAL, &MSC1); - writelrb(DEFAULT_MSC2_VAL, &MSC2); - /* - * 2) Initialize Card Interface - */ - - /* MECR: Memory Expansion Card Register */ - writelrb(DEFAULT_MECR_VAL, &MECR); - /* MCMEM0: Card Interface slot 0 timing */ - writelrb(DEFAULT_MCMEM0_VAL, &MCMEM0); - /* MCMEM1: Card Interface slot 1 timing */ - writelrb(DEFAULT_MCMEM1_VAL, &MCMEM1); - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - writelrb(DEFAULT_MCATT0_VAL, &MCATT0); - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - writelrb(DEFAULT_MCATT1_VAL, &MCATT1); - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - writelrb(DEFAULT_MCIO0_VAL, &MCIO0); - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - writelrb(DEFAULT_MCIO1_VAL, &MCIO1); - - /* - * 3) Configure Fly-By DMA register - */ - - writelrb(DEFAULT_FLYCNFG_VAL, &FLYCNFG); - - /* - * 4) Initialize Timing for Sync Memory (SDCLK0) - */ - - /* - * Before accessing MDREFR we need a valid DRI field, so we set - * this to power on defaults + DRI field. - */ - - /* Read current MDREFR config and zero out DRI */ - tmp = readl(&MDREFR) & ~0xfff; - tmp |= DEFAULT_MDREFR_VAL & 0xfff; - writelrb(tmp, &MDREFR); - - /* clear the free-running clock bits (clear K0Free, K1Free, K2Free) */ - mask = MDREFR_K0FREE | MDREFR_K1FREE | MDREFR_K2FREE | - MDREFR_K0DB2 | MDREFR_K0DB4 | MDREFR_K1DB2 | MDREFR_K2DB2 | - MDREFR_K0RUN | MDREFR_K1RUN | MDREFR_K2RUN; - tmp &= ~mask; - tmp |= (DEFAULT_MDREFR_VAL & mask); - writelrb(tmp, &MDREFR); - - /* - * 5) Initialize Synchronous Static Memory (Flash/Peripherals) - */ - - /* Initialize SXCNFG register. Assert the enable bits. - * - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be written - * at this time. - */ - writelrb(DEFAULT_SXCNFG_VAL, &SXCNFG); - - /* - * 6) Initialize SDRAM - */ - - tmp &= ~MDREFR_SLFRSH; - writelrb(tmp, &MDREFR); - tmp |= MDREFR_E1PIN; - writelrb(tmp, &MDREFR); - - /* - * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure - * but not enable each SDRAM partition pair. - */ - - mask = MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3; - writelrb(DEFAULT_MDCNFG_VAL & ~mask, &MDCNFG); - - /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */ - pxa_wait_ticks(0x300); - - /* - * 8) Trigger a number (usually 8) refresh cycles by attempting - * non-burst read or write accesses to disabled SDRAM, as commonly - * specified in the power up sequence documented in SDRAM data - * sheets. The address(es) used for this purpose must not be - * cacheable. - */ - for (i = 9; i >= 0; i--) { - readl(0xa0000000); - barrier(); - } - /* - * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1). - */ - - tmp = (readl(&MDCNFG) & ~mask) | (DEFAULT_MDCNFG_VAL & mask); - writelrb(tmp, &MDCNFG); - - /* - * 10) Write MDMRS. - */ - writelrb(DEFAULT_MDMRS_VAL, &MDMRS); - - /* - * 11) Enable APD - */ - if (DEFAULT_MDREFR_VAL & MDREFR_APD) { - tmp = readl(&MDREFR); - tmp |= MDREFR_APD; - writelrb(tmp, &MDREFR); - } -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - unsigned long pssr = PSPR; - unsigned long pc = get_pc(); - - arm_cpu_lowlevel_init(); - CKEN |= CKEN_OSTIMER | CKEN_MEMC | CKEN_FFUART; - - /* - * When not running from SDRAM, get it out of self refresh, and/or - * initialize it. - */ - if (!(pc >= 0xa0000000 && pc < 0xb0000000)) - pxa2xx_dram_init(); - - if ((pssr >= 0xa0000000 && pssr < 0xb0000000) || - (pssr >= 0x04000000 && pssr < 0x10000000)) - asm("mov pc, %0" : : "r"(pssr) : ); - - barebox_arm_entry(0xa0000000, SZ_64M, 0); -} diff --git a/arch/arm/boards/mioa701/Makefile b/arch/arm/boards/mioa701/Makefile deleted file mode 100644 index bf17869fb2..0000000000 --- a/arch/arm/boards/mioa701/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o gpio0_poweroff.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/mioa701/board.c b/arch/arm/boards/mioa701/board.c deleted file mode 100644 index 685c78611b..0000000000 --- a/arch/arm/boards/mioa701/board.c +++ /dev/null @@ -1,274 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> - -#include <common.h> -#include <driver.h> -#include <environment.h> -#include <fs.h> -#include <init.h> -#include <led.h> -#include <gpio.h> -#include <pwm.h> - -#include <mach/pxa/devices.h> -#include <mach/pxa/mfp-pxa27x.h> -#include <mach/pxa/pxa-regs.h> -#include <mach/pxa/udc_pxa2xx.h> -#include <mach/pxa/mci_pxa2xx.h> - -#include <asm/armlinux.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/mmu.h> - -#include "mioa701.h" - -/* - * LTM0305A776C LCD panel timings - * - * see: - * - the LTM0305A776C datasheet, - * - and the PXA27x Programmers' manual - */ -static struct pxafb_videomode mioa701_ltm0305a776c = { - { - .pixclock = 220000, /* CLK=4.545 MHz */ - .xres = 240, - .yres = 320, - .hsync_len = 4, - .vsync_len = 2, - .left_margin = 6, - .right_margin = 4, - .upper_margin = 5, - .lower_margin = 3, - }, - .bpp = 16, -}; - -static void mioa701_lcd_power(int on) -{ - gpio_set_value(GPIO87_LCD_POWER, on); -} - -static void mioa701_lcd_backlight(int on) -{ - struct pwm_device *pwm0 = pwm_request("pwm0"); - - /* - * The backlight has a base frequency of 250kHz (<=> 4 ms). - */ - if (on) { - pwm_enable(pwm0); - pwm_config(pwm0, 2000 * 1024, 4000 * 1024); - } else { - pwm_disable(pwm0); - } - pwm_free(pwm0); -} - -static struct pxafb_platform_data mioa701_pxafb_info = { - .mode = &mioa701_ltm0305a776c, - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, - .lcd_power = mioa701_lcd_power, - .backlight_power = mioa701_lcd_backlight, -}; - -#define MIO_LED(_name, _gpio) \ - { .gpio = _gpio, .active_low = 1, .led = { .name = #_name, } } -static struct gpio_led leds[] = { - MIO_LED(charging, GPIO10_LED_nCharging), - MIO_LED(blue, GPIO97_LED_nBlue), - MIO_LED(orange, GPIO98_LED_nOrange), - MIO_LED(vibra, GPIO82_LED_nVibra), - MIO_LED(keyboard, GPIO115_LED_nKeyboard), -}; - - -static int is_usb_connected(void) -{ - return !gpio_get_value(GPIO13_nUSB_DETECT); -} - -static struct pxa2xx_udc_mach_info mioa701_udc_info = { - .udc_is_connected = is_usb_connected, - .gpio_pullup = GPIO22_USB_ENABLE, -}; - -static struct pxamci_platform_data mioa701_mmc_info = { - .gpio_power = GPIO91_SDIO_EN, -}; - -static int mioa701_devices_init(void) -{ - int i; - void *docg3_iospace; - - pxa_add_pwm((void *)0x40b00000, 0); - pxa_add_fb((void *)0x44000000, &mioa701_pxafb_info); - pxa_add_mmc((void *)0x41100000, DEVICE_ID_DYNAMIC, &mioa701_mmc_info); - docg3_iospace = map_io_sections(0x0, (void *)0xe0000000, 0x2000); - add_generic_device("docg3", DEVICE_ID_DYNAMIC, NULL, (ulong) docg3_iospace, - 0x2000, IORESOURCE_MEM, NULL); - armlinux_set_architecture(MACH_TYPE_MIOA701); - - for (i = 0; i < ARRAY_SIZE(leds); i++) - led_gpio_register(&leds[i]); - add_generic_device("pxa27x-udc", 0, NULL, 0x40600000, - 1024, IORESOURCE_MEM, &mioa701_udc_info); - return 0; -} - -device_initcall(mioa701_devices_init); - -static unsigned long mioa701_pin_config[] = { - /* Mio global */ - MIO_CFG_OUT(GPIO9_CHARGE_EN, AF0, DRIVE_LOW), - MIO_CFG_OUT(GPIO18_POWEROFF, AF0, DRIVE_LOW), - MFP_CFG_OUT(GPIO3, AF0, DRIVE_HIGH), - MFP_CFG_OUT(GPIO4, AF0, DRIVE_HIGH), - MIO_CFG_IN(GPIO80_MAYBE_CHARGE_VDROP, AF0), - - /* Backlight PWM 0 */ - GPIO16_PWM0_OUT, - - /* LCD */ - GPIOxx_LCD_TFT_16BPP, - MIO_CFG_OUT(GPIO87_LCD_POWER, AF0, DRIVE_LOW), - - /* MMC */ - GPIO32_MMC_CLK, - GPIO92_MMC_DAT_0, - GPIO109_MMC_DAT_1, - GPIO110_MMC_DAT_2, - GPIO111_MMC_DAT_3, - GPIO112_MMC_CMD, - MIO_CFG_IN(GPIO78_SDIO_RO, AF0), - MIO_CFG_IN(GPIO15_SDIO_INSERT, AF0), - MIO_CFG_OUT(GPIO91_SDIO_EN, AF0, DRIVE_LOW), - - /* USB */ - MIO_CFG_IN(GPIO13_nUSB_DETECT, AF0), - MIO_CFG_OUT(GPIO22_USB_ENABLE, AF0, DRIVE_LOW), - - /* QCI */ - GPIO12_CIF_DD_7, - GPIO17_CIF_DD_6, - GPIO50_CIF_DD_3, - GPIO51_CIF_DD_2, - GPIO52_CIF_DD_4, - GPIO53_CIF_MCLK, - GPIO54_CIF_PCLK, - GPIO55_CIF_DD_1, - GPIO81_CIF_DD_0, - GPIO82_CIF_DD_5, - GPIO84_CIF_FV, - GPIO85_CIF_LV, - - /* Bluetooth */ - MIO_CFG_IN(GPIO14_BT_nACTIVITY, AF0), - GPIO44_BTUART_CTS, - GPIO42_BTUART_RXD, - GPIO45_BTUART_RTS, - GPIO43_BTUART_TXD, - MIO_CFG_OUT(GPIO83_BT_ON, AF0, DRIVE_LOW), - MIO_CFG_OUT(GPIO77_BT_UNKNOWN1, AF0, DRIVE_HIGH), - MIO_CFG_OUT(GPIO86_BT_MAYBE_nRESET, AF0, DRIVE_HIGH), - - /* GPS */ - MIO_CFG_OUT(GPIO23_GPS_UNKNOWN1, AF0, DRIVE_LOW), - MIO_CFG_OUT(GPIO26_GPS_ON, AF0, DRIVE_LOW), - MIO_CFG_OUT(GPIO27_GPS_RESET, AF0, DRIVE_LOW), - MIO_CFG_OUT(GPIO106_GPS_UNKNOWN2, AF0, DRIVE_LOW), - MIO_CFG_OUT(GPIO107_GPS_UNKNOWN3, AF0, DRIVE_LOW), - GPIO46_STUART_RXD, - GPIO47_STUART_TXD, - - /* GSM */ - MIO_CFG_OUT(GPIO24_GSM_MOD_RESET_CMD, AF0, DRIVE_LOW), - MIO_CFG_OUT(GPIO88_GSM_nMOD_ON_CMD, AF0, DRIVE_HIGH), - MIO_CFG_OUT(GPIO90_GSM_nMOD_OFF_CMD, AF0, DRIVE_HIGH), - MIO_CFG_OUT(GPIO114_GSM_nMOD_DTE_UART_STATE, AF0, DRIVE_HIGH), - MIO_CFG_IN(GPIO25_GSM_MOD_ON_STATE, AF0), - MIO_CFG_IN(GPIO113_GSM_EVENT, AF0) | WAKEUP_ON_EDGE_BOTH, - GPIO34_FFUART_RXD, - GPIO35_FFUART_CTS, - GPIO36_FFUART_DCD, - GPIO37_FFUART_DSR, - GPIO39_FFUART_TXD, - GPIO40_FFUART_DTR, - GPIO41_FFUART_RTS, - - /* Sound */ - GPIO28_AC97_BITCLK, - GPIO29_AC97_SDATA_IN_0, - GPIO30_AC97_SDATA_OUT, - GPIO31_AC97_SYNC, - GPIO89_AC97_SYSCLK, - MIO_CFG_IN(GPIO12_HPJACK_INSERT, AF0), - - /* Leds */ - MIO_CFG_OUT(GPIO10_LED_nCharging, AF0, DRIVE_HIGH), - MIO_CFG_OUT(GPIO97_LED_nBlue, AF0, DRIVE_HIGH), - MIO_CFG_OUT(GPIO98_LED_nOrange, AF0, DRIVE_HIGH), - MIO_CFG_OUT(GPIO82_LED_nVibra, AF0, DRIVE_HIGH), - MIO_CFG_OUT(GPIO115_LED_nKeyboard, AF0, DRIVE_HIGH), - - /* Keyboard */ - MIO_CFG_IN(GPIO0_KEY_POWER, AF0) | WAKEUP_ON_EDGE_BOTH, - MIO_CFG_IN(GPIO93_KEY_VOLUME_UP, AF0), - MIO_CFG_IN(GPIO94_KEY_VOLUME_DOWN, AF0), - GPIO100_KP_MKIN_0, - GPIO101_KP_MKIN_1, - GPIO102_KP_MKIN_2, - GPIO103_KP_MKOUT_0, - GPIO104_KP_MKOUT_1, - GPIO105_KP_MKOUT_2, - - /* I2C */ - GPIO117_I2C_SCL, - GPIO118_I2C_SDA, - - /* Unknown */ - MFP_CFG_IN(GPIO20, AF0), - MFP_CFG_IN(GPIO21, AF0), - MFP_CFG_IN(GPIO33, AF0), - MFP_CFG_OUT(GPIO49, AF0, DRIVE_HIGH), - MFP_CFG_OUT(GPIO57, AF0, DRIVE_HIGH), - MFP_CFG_IN(GPIO96, AF0), - MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH), -}; - -static int mioa701_coredevice_init(void) -{ - unsigned int cclk; - /* route pins */ - pxa2xx_mfp_config(ARRAY_AND_SIZE(mioa701_pin_config)); - - /* - * Put the board in superspeed (520 MHz) to speed-up logo/OS loading. - * This requires to command the Maxim 1586 to upgrade core voltage to - * 1.475 V, on the power I2C bus (device 0x14). - */ - CKEN |= CKEN_PWRI2C; - CCCR = CCCR_A | 0x20290; - PCFR = PCFR_GPR_EN | PCFR_FVC | PCFR_DC_EN | PCFR_PI2C_EN | PCFR_OPDE; - PCMD(0) = PCMD_LC | 0x1f; - PVCR = 0x14; - - cclk = 0x0b; - asm volatile("mcr p14, 0, %0, c6, c0, 0 @ set CCLK" - : : "r" (cclk) : "cc"); - - barebox_set_model("Scoter Mitac Mio A701"); - barebox_set_hostname("mioa701"); - - return 0; -} -coredevice_initcall(mioa701_coredevice_init); - -static int mioa701_mem_init(void) -{ - arm_add_mem_device("ram0", 0xa0000000, 64 * 1024 * 1024); - return 0; -} -mem_initcall(mioa701_mem_init); diff --git a/arch/arm/boards/mioa701/env/bin/barebox_update b/arch/arm/boards/mioa701/env/bin/barebox_update deleted file mode 100644 index 632c20926a..0000000000 --- a/arch/arm/boards/mioa701/env/bin/barebox_update +++ /dev/null @@ -1,11 +0,0 @@ -#!/bin/sh - -# Page+OOB specific partitions -addpart /dev/mtd0.raw 2162688@405504(barebox) - -if [ -r /barebox.BIP0 ]; then - dps1_unlock - erase /dev/mtd0.raw.barebox - cp -v /barebox.BIPO /dev/mtd0.raw.barebox - dps1_unlock -fi diff --git a/arch/arm/boards/mioa701/env/bin/console_mode b/arch/arm/boards/mioa701/env/bin/console_mode deleted file mode 100644 index aa06e920b4..0000000000 --- a/arch/arm/boards/mioa701/env/bin/console_mode +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh -# Script to run barebox in console mode - -splash /dev/mtd0.barebox-logo2 -echo -echo "Welcome to barebox console" diff --git a/arch/arm/boards/mioa701/env/bin/dps1_unlock b/arch/arm/boards/mioa701/env/bin/dps1_unlock deleted file mode 100644 index 2d7dab8c58..0000000000 --- a/arch/arm/boards/mioa701/env/bin/dps1_unlock +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh -# -# Shell to unlock the DPS1 with "12345678" key. - -mw -b 0x105e 0x31 -mw -b 0x105e 0x32 -mw -b 0x105e 0x33 -mw -b 0x105e 0x34 -mw -b 0x105e 0x35 -mw -b 0x105e 0x36 -mw -b 0x105e 0x37 -mw -b 0x105e 0x38 diff --git a/arch/arm/boards/mioa701/env/bin/dps1_update b/arch/arm/boards/mioa701/env/bin/dps1_update deleted file mode 100644 index e6535eda72..0000000000 --- a/arch/arm/boards/mioa701/env/bin/dps1_update +++ /dev/null @@ -1,12 +0,0 @@ -#!/bin/sh - -# Page+OOB specific partitions -addpart /dev/mtd0.raw 67584@202752(dps1) -uncompress /env/data/dps1.raw.gz /dps1.raw - -if [ -r /dps1.raw ]; then - dps1_unlock - erase /dev/mtd0.raw.dps1 - cp -v /dps1.raw /dev/mtd0.raw.dps1 - dps1_unlock -fi diff --git a/arch/arm/boards/mioa701/env/bin/init b/arch/arm/boards/mioa701/env/bin/init deleted file mode 100644 index e914eae32f..0000000000 --- a/arch/arm/boards/mioa701/env/bin/init +++ /dev/null @@ -1,79 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config -addpart /dev/mtd0 $mtdparts - -usbserial -s "Mio A701 usb gadget" - -gpio_get_value 22 -is_usb_connected=$? - -gpio_get_value 93 -is_vol_up=$? - -fb0.enable=1 -# Phase1: Handle Vol-Up key case : drop immediately to console -if [ $is_vol_up != 0 ]; then - console_mode - exit -fi - -# Phase2: Handle Power-On case : debounce PowerUp key or Halt -if [ $global.system.reset = "POR" -o $global.system.reset = "WKE" ]; then - powerup_released=0 - - gpio_get_value 0 - is_power_up=$? - if [ $is_power_up = 0 ]; then - powerup_released=1 - fi - msleep 500 - - gpio_get_value 0 - is_power_up=$? - if [ $is_power_up = 0 ]; then - powerup_released=1 - fi - - if [ $powerup_released = 1 ]; then - echo "Power button not held, halting" - poweroff - fi -fi - -# Phase3: display logo -led keyboard 0 -splash /dev/mtd0.barebox-logo - -# Phase4: check for SD Card override -sdcard_override -if [ $? = 0 ]; then - console_mode - exit -fi - -# Phase5: check for MTD override -mtd_env_override -if [ $? = 0 ]; then - echo "Switching to custom environment" - /env/init - exit -fi - -# Phase6: check for user interrupting auto-boot -echo "No custom environment found" -if [ $is_usb_connected != 0 ]; then - echo -n "Hit any key to stop autoboot: " - timeout -a $autoboot_timeout - if [ $? != 0 ]; then - console_mode - exit - fi -fi - -# Phase7: auto-boot linux kernel -echo "Booting linux kernel on docg3 chip ..." -bootm /dev/mtd0.kernel diff --git a/arch/arm/boards/mioa701/env/bin/mtd_env_override b/arch/arm/boards/mioa701/env/bin/mtd_env_override deleted file mode 100644 index faeb4d0d43..0000000000 --- a/arch/arm/boards/mioa701/env/bin/mtd_env_override +++ /dev/null @@ -1,4 +0,0 @@ -#!/bin/sh - -loadenv /dev/mtd0.barebox-env -exit $? diff --git a/arch/arm/boards/mioa701/env/bin/sdcard_override b/arch/arm/boards/mioa701/env/bin/sdcard_override deleted file mode 100644 index 7003fa967e..0000000000 --- a/arch/arm/boards/mioa701/env/bin/sdcard_override +++ /dev/null @@ -1,19 +0,0 @@ -#!/bin/sh -# Script to switch to execute sdcard environment scripts if available -# -# This enables an override of the default environment if an SD Card -# is inserted, has a FAT filesystem, and has a barebox.env file in -# the root directory. - -mci0.probe=1 -if [ $mci0.probe = 1 ]; then - mkdir /sdcard - mount /dev/disk0.0 /sdcard - if [ -f /sdcard/barebox.env ]; then - loadenv /sdcard/barebox.env /env.sd - /env.sd/bin/init - exit - fi -fi -trigger_error_return_code -exit diff --git a/arch/arm/boards/mioa701/env/config b/arch/arm/boards/mioa701/env/config deleted file mode 100644 index 92014511b4..0000000000 --- a/arch/arm/boards/mioa701/env/config +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -autoboot_timeout=3 - -mtdparts="2048k@384k(barebox)ro,256k(barebox-logo),256k(barebox-logo2),128k(barebox-env),5120k(kernel),-(root)" -bootargs="$bootargs mtdparts=docg3.0:$mtdparts ubi.mtd=5 rootfstype=ubifs root=ubi0:linux_root ro" diff --git a/arch/arm/boards/mioa701/env/data/dps1.raw.gz b/arch/arm/boards/mioa701/env/data/dps1.raw.gz Binary files differdeleted file mode 100644 index 9857c83e07..0000000000 --- a/arch/arm/boards/mioa701/env/data/dps1.raw.gz +++ /dev/null diff --git a/arch/arm/boards/mioa701/gpio0_poweroff.c b/arch/arm/boards/mioa701/gpio0_poweroff.c deleted file mode 100644 index 41d886d74b..0000000000 --- a/arch/arm/boards/mioa701/gpio0_poweroff.c +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> - -#include <clock.h> -#include <common.h> -#include <init.h> -#include <poweroff.h> -#include <gpio.h> -#include <poller.h> - -#include "mioa701.h" - -#define POWEROFF_SECS (4 * SECOND) - -static void blink_led_keyboard(void) -{ - gpio_set_value(GPIO115_LED_nKeyboard, 0); - mdelay(400); - gpio_set_value(GPIO115_LED_nKeyboard, 1); - mdelay(400); -} - -static void try_poweroff(void) -{ - int poweroff_released = 0; - - blink_led_keyboard(); - poweroff_released |= !gpio_get_value(GPIO0_KEY_POWER); - if (poweroff_released) - return; - - gpio_set_value(GPIO115_LED_nKeyboard, 0); - mdelay(2000); - poweroff_machine(); -} - -static void gpio0_poller_fn(struct poller_struct *poller) -{ - static uint64_t gpio0_start; - static bool gpio0_activated; - - if (!gpio_get_value(GPIO0_KEY_POWER)) { - gpio0_activated = false; - return; - } - - if (gpio0_activated) { - if (is_timeout_non_interruptible(gpio0_start, POWEROFF_SECS)) { - try_poweroff(); - gpio0_activated = false; - } - } else { - gpio0_activated = true; - gpio0_start = get_time_ns(); - } -} - -static struct poller_struct gpio0_poller = { - .func = gpio0_poller_fn, -}; - -static int gpio0_poweroff_probe(void) -{ - return poller_register(&gpio0_poller, "power-button"); -} - -device_initcall(gpio0_poweroff_probe); diff --git a/arch/arm/boards/mioa701/lowlevel.c b/arch/arm/boards/mioa701/lowlevel.c deleted file mode 100644 index 6116990402..0000000000 --- a/arch/arm/boards/mioa701/lowlevel.c +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - barebox_arm_entry(0xa0000000, SZ_64M, NULL); -} diff --git a/arch/arm/boards/mioa701/mioa701.h b/arch/arm/boards/mioa701/mioa701.h deleted file mode 100644 index 5f6d5e65f7..0000000000 --- a/arch/arm/boards/mioa701/mioa701.h +++ /dev/null @@ -1,67 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2011 Robert Jarzmik <robert.jarzmik@free.fr> - -#ifndef _MIOA701_H_ -#define _MIOA701_H_ - -#define MIO_CFG_IN(pin, af) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK)) |\ - (MFP_PIN(pin) | MFP_##af | MFP_DIR_IN)) - -#define MIO_CFG_OUT(pin, af, state) \ - ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DIR_MASK | MFP_LPM_STATE_MASK)) |\ - (MFP_PIN(pin) | MFP_##af | MFP_DIR_OUT | MFP_LPM_##state)) - -/* Global GPIOs */ -#define GPIO9_CHARGE_EN 9 -#define GPIO18_POWEROFF 18 -#define GPIO87_LCD_POWER 87 -#define GPIO96_AC_DETECT 96 -#define GPIO80_MAYBE_CHARGE_VDROP 80 /* Drop of 88mV */ - -/* USB */ -#define GPIO13_nUSB_DETECT 13 -#define GPIO22_USB_ENABLE 22 - -/* SDIO bits */ -#define GPIO78_SDIO_RO 78 -#define GPIO15_SDIO_INSERT 15 -#define GPIO91_SDIO_EN 91 - -/* Bluetooth */ -#define GPIO14_BT_nACTIVITY 14 -#define GPIO83_BT_ON 83 -#define GPIO77_BT_UNKNOWN1 77 -#define GPIO86_BT_MAYBE_nRESET 86 - -/* GPS */ -#define GPIO23_GPS_UNKNOWN1 23 -#define GPIO26_GPS_ON 26 -#define GPIO27_GPS_RESET 27 -#define GPIO106_GPS_UNKNOWN2 106 -#define GPIO107_GPS_UNKNOWN3 107 - -/* GSM */ -#define GPIO24_GSM_MOD_RESET_CMD 24 -#define GPIO88_GSM_nMOD_ON_CMD 88 -#define GPIO90_GSM_nMOD_OFF_CMD 90 -#define GPIO114_GSM_nMOD_DTE_UART_STATE 114 -#define GPIO25_GSM_MOD_ON_STATE 25 -#define GPIO113_GSM_EVENT 113 - -/* SOUND */ -#define GPIO12_HPJACK_INSERT 12 - -/* LEDS */ -#define GPIO10_LED_nCharging 10 -#define GPIO97_LED_nBlue 97 -#define GPIO98_LED_nOrange 98 -#define GPIO82_LED_nVibra 82 -#define GPIO115_LED_nKeyboard 115 - -/* Keyboard */ -#define GPIO0_KEY_POWER 0 -#define GPIO93_KEY_VOLUME_UP 93 -#define GPIO94_KEY_VOLUME_DOWN 94 - -#endif /* _MIOA701_H */ diff --git a/arch/arm/boards/module-mb7707/Makefile b/arch/arm/boards/module-mb7707/Makefile deleted file mode 100644 index da63d2625f..0000000000 --- a/arch/arm/boards/module-mb7707/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/module-mb7707/board.c b/arch/arm/boards/module-mb7707/board.c deleted file mode 100644 index 366baddf81..0000000000 --- a/arch/arm/boards/module-mb7707/board.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> - -/* This file is part of barebox. */ - -#include <common.h> -#include <init.h> -#include <driver.h> -#include <linux/usb/ehci.h> -#include <mach/uemd/hardware.h> - -static int hostname_init(void) -{ - barebox_set_hostname("mb7707"); - - return 0; -} -core_initcall(hostname_init); - -static struct ehci_platform_data ehci_pdata = { - .flags = 0, -}; - -static int mb7707_devices_init(void) -{ - add_usb_ehci_device(DEVICE_ID_DYNAMIC, UEMD_EHCI_BASE, - UEMD_EHCI_BASE + 0x10, &ehci_pdata); - - return 0; -} -device_initcall(mb7707_devices_init); diff --git a/arch/arm/boards/module-mb7707/lowlevel.c b/arch/arm/boards/module-mb7707/lowlevel.c deleted file mode 100644 index 3b529d1232..0000000000 --- a/arch/arm/boards/module-mb7707/lowlevel.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> - -/* This file is part of barebox. */ - -#define __LOWLEVEL_INIT__ - -#include <common.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <init.h> -#include <linux/sizes.h> - -#define MB7707_SRAM_BASE 0x40000000 -#define MB7707_SRAM_SIZE SZ_128M - -extern char __dtb_module_mb7707_start[]; - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - void *fdt; - - arm_cpu_lowlevel_init(); - - fdt = __dtb_module_mb7707_start + get_runtime_offset(); - - barebox_arm_entry(MB7707_SRAM_BASE, MB7707_SRAM_SIZE, fdt); -} diff --git a/arch/arm/boards/nhk8815/Makefile b/arch/arm/boards/nhk8815/Makefile deleted file mode 100644 index 0367fa7dd5..0000000000 --- a/arch/arm/boards/nhk8815/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += setup.o -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-nhk8815 diff --git a/arch/arm/boards/nhk8815/defaultenv-nhk8815/config b/arch/arm/boards/nhk8815/defaultenv-nhk8815/config deleted file mode 100644 index c05ed2704e..0000000000 --- a/arch/arm/boards/nhk8815/defaultenv-nhk8815/config +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root.$rootfs_type - -#kernelimage=zImage -kernelimage=uImage -#kernelimage=Image -#kernelimage=Image.lzo - -# Partition Size Start -# XloaderTOC + X-Loader 256KB 0x00000000 -# Memory init function 256KB 0x00040000 -# Barebox + env 2MB 0x00080000 -# Kernel Image 3MB 0x00280000 -# JFFS2 Root filesystem 22MB 0x00580000 -# JFFS2 User Data 100MB 0x01b80000 - -nand_parts="256k(xloader)ro,256k(meminit),2M(barebox),3M(kernel),22M(rootfs),100M(userfs),384k(free),128k(bareboxenv)" - -autoboot_timeout=3 - -bootargs="root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/nhk8815/lowlevel.c b/arch/arm/boards/nhk8815/lowlevel.c deleted file mode 100644 index 9ba5bbffad..0000000000 --- a/arch/arm/boards/nhk8815/lowlevel.c +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - barebox_arm_entry(0x0, SZ_64M, NULL); -} diff --git a/arch/arm/boards/nhk8815/setup.c b/arch/arm/boards/nhk8815/setup.c deleted file mode 100644 index c7a2afdbfe..0000000000 --- a/arch/arm/boards/nhk8815/setup.c +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> - -#include <common.h> -#include <init.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/nand.h> -#include <nand.h> -#include <asm/armlinux.h> -#include <asm/mach-types.h> -#include <io.h> -#include <envfs.h> - -#include <mach/nomadik/hardware.h> -#include <mach/nomadik/board.h> -#include <mach/nomadik/nand.h> -#include <mach/nomadik/fsmc.h> - -static int nhk8815_nand_init(void) -{ - /* FSMC setup for nand chip select (8-bit nand in 8815NHK) */ - writel(0x0000000E, FSMC_PCR(0)); - writel(0x000D0A00, FSMC_PMEM(0)); - writel(0x00100A00, FSMC_PATT(0)); - - /* enable access to the chip select area */ - writel(readl(FSMC_PCR(0)) | 0x04, FSMC_PCR(0)); - - return 0; -} - -static struct nomadik_nand_platform_data nhk8815_nand_data = { - .init = nhk8815_nand_init, -}; - -static struct resource nhk8815_nand_resources[] = { - { - .name = "nand_addr", - .start = NAND_IO_ADDR, - .end = NAND_IO_ADDR + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .name = "nand_cmd", - .start = NAND_IO_CMD, - .end = NAND_IO_CMD + 0xfff, - .flags = IORESOURCE_MEM, - }, { - .name = "nand_data", - .start = NAND_IO_DATA, - .end = NAND_IO_DATA + 0xfff, - .flags = IORESOURCE_MEM, - } -}; - -static struct device nhk8815_nand_device = { - .id = DEVICE_ID_DYNAMIC, - .name = "nomadik_nand", - .num_resources = ARRAY_SIZE(nhk8815_nand_resources), - .resource = nhk8815_nand_resources, - .platform_data = &nhk8815_nand_data, -}; - -static int nhk8815_mem_init(void) -{ - st8815_add_device_sdram(64 * 1024 *1024); - - return 0; -} -mem_initcall(nhk8815_mem_init); - -static int nhk8815_devices_init(void) -{ - writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20); - writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24); - writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28); - writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE); - - /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */ - writel(0x0000305b, FSMC_BCR(1)); - writel(0x00033f33, FSMC_BTR(1)); - - add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, 0x34000300, 16, - IORESOURCE_MEM, NULL); - - platform_device_register(&nhk8815_nand_device); - - armlinux_set_architecture(MACH_TYPE_NOMADIK); - - devfs_add_partition("nand0", 0x0000000, 0x040000, DEVFS_PARTITION_FIXED, "xloader_raw"); - devfs_add_partition("nand0", 0x0040000, 0x080000, DEVFS_PARTITION_FIXED, "meminit_raw"); - devfs_add_partition("nand0", 0x0080000, 0x200000, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", 0x7FE0000, 0x020000, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_nhk8815); - - return 0; -} -device_initcall(nhk8815_devices_init); - -static int nhk8815_console_init(void) -{ - barebox_set_model("Nomadik nhk8815"); - barebox_set_hostname("nhk8815"); - - st8815_register_uart(1); - - return 0; -} - -console_initcall(nhk8815_console_init); diff --git a/arch/arm/boards/omap343xdsp/Makefile b/arch/arm/boards/omap343xdsp/Makefile deleted file mode 100644 index da63d2625f..0000000000 --- a/arch/arm/boards/omap343xdsp/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/omap343xdsp/board.c b/arch/arm/boards/omap343xdsp/board.c deleted file mode 100644 index ca1cf9c58c..0000000000 --- a/arch/arm/boards/omap343xdsp/board.c +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2006-2008 Nishanth Menon <x0nishan@ti.com>, Texas Instruments (http://www.ti.com/) - -#include <common.h> -#include <console.h> -#include <init.h> -#include <driver.h> -#include <io.h> -#include <asm/armlinux.h> -#include <mach/omap/omap3-silicon.h> -#include <mach/omap/omap3-devices.h> -#include <mach/omap/gpmc.h> -#include <errno.h> - -/** - * @brief UART serial port initialization - remember to enable COM clocks in arch - * - * @return result of device registration - */ -static int sdp3430_console_init(void) -{ - barebox_set_model("Texas Instruments SDP343x"); - barebox_set_hostname("sdp343x"); - - omap3_add_uart3(); - - return 0; -} - -console_initcall(sdp3430_console_init); - -static int sdp3430_mem_init(void) -{ - omap_add_ram0(SZ_128M); - - return 0; -} -mem_initcall(sdp3430_mem_init); - -static int sdp3430_devices_init(void) -{ -#ifdef CONFIG_OMAP_GPMC - /* WP is made high and WAIT1 active Low */ - gpmc_generic_init(0x10); -#endif - - return 0; -} - -device_initcall(sdp3430_devices_init); diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c deleted file mode 100644 index 3a8165f885..0000000000 --- a/arch/arm/boards/omap343xdsp/lowlevel.c +++ /dev/null @@ -1,562 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <init.h> -#include <io.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/omap/generic.h> -#include <mach/omap/omap3-mux.h> -#include <mach/omap/sdrc.h> -#include <mach/omap/control.h> -#include <mach/omap/syslib.h> -#include <mach/omap/omap3-silicon.h> -#include <mach/omap/omap3-generic.h> -#include <mach/omap/sys_info.h> - -/** - * @brief Do the SDRC initialization for 128Meg Infenion DDR for CS0 - * - * @return void - */ -static void sdrc_init(void) -{ - /* Issue SDRC Soft reset */ - writel(0x12, OMAP3_SDRC_REG(SYSCONFIG)); - - /* Wait until Reset complete */ - while ((readl(OMAP3_SDRC_REG(STATUS)) & 0x1) == 0); - /* SDRC to normal mode */ - writel(0x10, OMAP3_SDRC_REG(SYSCONFIG)); - /* SDRC Sharing register */ - /* 32-bit SDRAM on data lane [31:0] - CS0 */ - /* pin tri-stated = 1 */ - writel(0x00000100, OMAP3_SDRC_REG(SHARING)); - - /* ----- SDRC_REG(CS0 Configuration --------- */ - /* SDRC_REG(MCFG0 register */ - writel(0x02584019, OMAP3_SDRC_REG(MCFG_0)); - - /* SDRC_REG(RFR_CTRL0 register */ - writel(0x0003DE01, OMAP3_SDRC_REG(RFR_CTRL_0)); - - /* SDRC_REG(ACTIM_CTRLA0 register */ - writel(0X5A9A4486, OMAP3_SDRC_REG(ACTIM_CTRLA_0)); - - /* SDRC_REG(ACTIM_CTRLB0 register */ - writel(0x00000010, OMAP3_SDRC_REG(ACTIM_CTRLB_0)); - - /* Disble Power Down of CKE cuz of 1 CKE on combo part */ - writel(0x00000081, OMAP3_SDRC_REG(POWER)); - - /* SDRC_REG(Manual command register */ - /* NOP command */ - writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0)); - /* Precharge command */ - writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0)); - /* Auto-refresh command */ - writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0)); - /* Auto-refresh command */ - writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0)); - - /* SDRC MR0 register */ - /* CAS latency = 3 */ - /* Write Burst = Read Burst */ - /* Serial Mode */ - writel(0x00000032, OMAP3_SDRC_REG(MR_0)); /* Burst length =4 */ - - /* SDRC DLLA control register */ - /* Enable DLL A */ - writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL)); - - /* wait until DLL is locked */ - while ((readl(OMAP3_SDRC_REG(DLLA_STATUS)) & 0x4) == 0); -} - -/** - * @brief Do the pin muxing required for Board operation. - * - * See @ref MUX_VAL for description of the muxing mode. Since some versions - * of Linux depend on all pin muxing being done at barebox level, we may need to - * enable CONFIG_MACH_OMAP_ADVANCED_MUX to enable the full fledged pin muxing. - * - * @return void - */ -static void mux_config(void) -{ - /* Essential MUX Settings */ - MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /* SDRC_D0 */ - MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /* SDRC_D1 */ - MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /* SDRC_D2 */ - MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /* SDRC_D3 */ - MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /* SDRC_D4 */ - MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /* SDRC_D5 */ - MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /* SDRC_D6 */ - MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /* SDRC_D7 */ - MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /* SDRC_D8 */ - MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /* SDRC_D9 */ - MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /* SDRC_D10 */ - MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /* SDRC_D11 */ - MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /* SDRC_D12 */ - MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /* SDRC_D13 */ - MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /* SDRC_D14 */ - MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /* SDRC_D15 */ - MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /* SDRC_D16 */ - MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /* SDRC_D17 */ - MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /* SDRC_D18 */ - MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /* SDRC_D19 */ - MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /* SDRC_D20 */ - MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /* SDRC_D21 */ - MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /* SDRC_D22 */ - MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /* SDRC_D23 */ - MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /* SDRC_D24 */ - MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /* SDRC_D25 */ - MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /* SDRC_D26 */ - MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /* SDRC_D27 */ - MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /* SDRC_D28 */ - MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /* SDRC_D29 */ - MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /* SDRC_D30 */ - MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /* SDRC_D31 */ - MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /* SDRC_CLK */ - MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /* SDRC_DQS0 */ - MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /* SDRC_DQS1 */ - MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /* SDRC_DQS2 */ - MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /* SDRC_DQS3 */ - /* GPMC */ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); /* GPMC_A1 */ - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); /* GPMC_A2 */ - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); /* GPMC_A3 */ - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); /* GPMC_A4 */ - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); /* GPMC_A5 */ - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); /* GPMC_A6 */ - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); /* GPMC_A7 */ - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); /* GPMC_A8 */ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); /* GPMC_A9 */ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); /* GPMC_A10 */ - MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)); /* GPMC_D0 */ - MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)); /* GPMC_D1 */ - MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)); /* GPMC_D2 */ - MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)); /* GPMC_D3 */ - MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)); /* GPMC_D4 */ - MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)); /* GPMC_D5 */ - MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)); /* GPMC_D6 */ - MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)); /* GPMC_D7 */ - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); /* GPMC_D8 */ - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); /* GPMC_D9 */ - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); /* GPMC_D10 */ - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); /* GPMC_D11 */ - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); /* GPMC_D12 */ - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); /* GPMC_D13 */ - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); /* GPMC_D14 */ - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); /* GPMC_D15 */ - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /* GPMC_NCS0 */ - MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)); /* GPMC_NCS1 */ - MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)); /* GPMC_NCS2 */ - MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)); /* GPMC_NCS3 */ - /* GPIO_55 - FLASH_DIS */ - MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4)); - /* GPIO_56 - TORCH_EN */ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)); - /* GPIO_57 - AGPS SLP */ - MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M4)); - /* GPMC_58 - WLAN_IRQ */ - MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M4)); - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); /* GPMC_CLK */ - /* GPMC_NADV_ALE */ - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /* GPMC_NOE */ - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /* GPMC_NWE */ - /* GPMC_NBE0_CLE */ - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M4)); /* GPIO_61 -BT_SHUTDN */ - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /* GPMC_NWP */ - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /* GPMC_WAIT0 */ - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); /* GPMC_WAIT1 */ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /* GPIO_64 */ - MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /* GPIO_65 */ - - /* SERIAL INTERFACE */ - /* UART3_CTS_RCTX */ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); - /* UART3_RTS_SD */ - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); - /* UART3_RX_IRRX */ - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); - /* UART3_TX_IRTX */ - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); - /* HSUSB0_CLK */ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); - /* HSUSB0_STP */ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); - /* HSUSB0_DIR */ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); - /* HSUSB0_NXT */ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); - /* HSUSB0_DATA0 */ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); - /* HSUSB0_DATA1 */ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); - /* HSUSB0_DATA2 */ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); - /* HSUSB0_DATA3 */ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); - /* HSUSB0_DATA4 */ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); - /* HSUSB0_DATA5 */ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); - /* HSUSB0_DATA6 */ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); - /* HSUSB0_DATA7 */ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /* I2C1_SCL */ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /* I2C1_SDA */ -#ifdef CONFIG_MACH_OMAP_ADVANCED_MUX - /* DSS */ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /* DSS_PCLK */ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /* DSS_HSYNC */ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /* DSS_VSYNC */ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /* DSS_ACBIAS */ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /* DSS_DATA0 */ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /* DSS_DATA1 */ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /* DSS_DATA2 */ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /* DSS_DATA3 */ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /* DSS_DATA4 */ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /* DSS_DATA5 */ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /* DSS_DATA6 */ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /* DSS_DATA7 */ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /* DSS_DATA8 */ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /* DSS_DATA9 */ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /* DSS_DATA10 */ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /* DSS_DATA11 */ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /* DSS_DATA12 */ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /* DSS_DATA13 */ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /* DSS_DATA14 */ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /* DSS_DATA15 */ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /* DSS_DATA16 */ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /* DSS_DATA17 */ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /* DSS_DATA18 */ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /* DSS_DATA19 */ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /* DSS_DATA20 */ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /* DSS_DATA21 */ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /* DSS_DATA22 */ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /* DSS_DATA23 */ - /* CAMERA */ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)); /* CAM_HS */ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)); /* CAM_VS */ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)); /* CAM_XCLKA */ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)); /* CAM_PCLK */ - /* GPIO_98 - CAM_RESET */ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)); /* CAM_D0 */ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)); /* CAM_D1 */ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)); /* CAM_D2 */ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)); /* CAM_D3 */ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)); /* CAM_D4 */ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)); /* CAM_D5 */ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)); /* CAM_D6 */ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)); /* CAM_D7 */ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)); /* CAM_D8 */ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)); /* CAM_D9 */ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)); /* CAM_D10 */ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)); /* CAM_D11 */ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)); /* CAM_XCLKB */ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /* GPIO_167 */ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)); /* CAM_STROBE */ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)); /* CSI2_DX0 */ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)); /* CSI2_DY0 */ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)); /* CSI2_DX1 */ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)); /* CSI2_DY1 */ - /* AUDIO INTERFACE */ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)); /* MCBSP2_FSX */ - /* MCBSP2_CLKX */ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)); /* MCBSP2_DR */ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)); /* MCBSP2_DX */ - /* EXPANSION CARD */ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /* MMC1_CLK */ - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /* MMC1_CMD */ - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /* MMC1_DAT0 */ - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /* MMC1_DAT1 */ - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /* MMC1_DAT2 */ - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /* MMC1_DAT3 */ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /* MMC1_DAT4 */ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /* MMC1_DAT5 */ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /* MMC1_DAT6 */ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /* MMC1_DAT7 */ - /* WIRELESS LAN */ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | DIS | M0)); /* MMC2_CLK */ - MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)); /* MMC2_CMD */ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)); /* MMC2_DAT0 */ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)); /* MMC2_DAT1 */ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)); /* MMC2_DAT2 */ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)); /* MMC2_DAT3 */ - /* MMC2_DIR_DAT0 */ - MUX_VAL(CP(MMC2_DAT4), (IDIS | PTD | DIS | M1)); - /* MMC2_DIR_DAT1 */ - MUX_VAL(CP(MMC2_DAT5), (IDIS | PTD | DIS | M1)); - /* MMC2_DIR_CMD */ - MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | DIS | M1)); - /* MMC2_CLKIN */ - MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)); - /* BLUETOOTH */ - /* MCBSP3_DX */ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)); - /* MCBSP3_DR */ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)); - /* MCBSP3_CLKX */ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)); - /* MCBSP3_FSX */ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)); /* UART2_CTS */ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)); /* UART2_RTS */ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)); /* UART2_TX */ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)); /* UART2_RX */ - /* MODEM INTERFACE */ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); /* UART1_TX */ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); /* UART1_RTS */ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); /* UART1_CTS */ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); /* UART1_RX */ - /* SSI1_DAT_RX */ - MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)); - MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)); /* SSI1_FLAG_RX */ - MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)); /* SSI1_RDY_RX */ - MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)); /* SSI1_WAKE */ - /* MCBSP1_CLKR */ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)); - /* GPIO_157 - BT_WKUP */ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)); - /* MCBSP1_DX */ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)); /* MCBSP1_DR */ - /* MCBSP_CLKS */ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)); - /* MCBSP1_FSX */ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)); - /* MCBSP1_CLKX */ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)); - /* SERIAL INTERFACE */ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /* I2C2_SCL */ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /* I2C2_SDA */ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /* I2C3_SCL */ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /* I2C3_SDA */ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)); /* I2C4_SCL */ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)); /* I2C4_SDA */ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)); /* HDQ_SIO */ - /* MCSPI1_CLK */ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)); - /* MCSPI1_SIMO */ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)); - /* MCSPI1_SOMI */ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)); - /* MCSPI1_CS0 */ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)); - /* MCSPI1_CS1 */ - MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)); - /* GPIO_176-NOR_DPD */ - MUX_VAL(CP(MCSPI1_CS2), (IDIS | PTD | DIS | M4)); - /* MCSPI1_CS3 */ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)); - /* MCSPI2_CLK */ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)); - /* MCSPI2_SIMO */ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)); - /* MCSPI2_SOMI */ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)); - /* MCSPI2_CS0 */ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M0)); - /* MCSPI2_CS1 */ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M0)); - - /* CONTROL AND DEBUG */ - MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /* SYS_32K */ - MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /* SYS_CLKREQ */ - MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /* SYS_NIRQ */ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /* GPIO_2 - PEN_IRQ */ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /* GPIO_3 */ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)); /* GPIO_4 - MMC1_WP */ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)); /* GPIO_5 - LCD_ENVDD */ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)); /* GPIO_6 - LAN_INTR0 */ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)); /* GPIO_7 - MMC2_WP */ - /* GPIO_8-LCD_ENBKL */ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)); - /* SYS_OFF_MODE */ - MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); - /* SYS_CLKOUT1 */ - MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)); /* GPIO_186 */ - MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /* JTAG_NTRST */ - MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /* JTAG_TCK */ - MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /* JTAG_TMS */ - MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /* JTAG_TDI */ - MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)); /* JTAG_EMU0 */ - MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)); /* JTAG_EMU1 */ - /* HSUSB1_TLL_STP */ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M0)); - /* HSUSB1_TLL_CLK */ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M0)); - /* HSUSB1_TLL_DATA0 */ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | DIS | M1)); - /* MCSPI3_CS0 */ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | DIS | M1)); - /* HSUSB1_TLL_DATA2 */ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M1)); - /* HSUSB1_TLL_DATA7 */ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | DIS | M1)); - /* HSUSB1_TLL_DATA4 */ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB1_TLL_DATA5 */ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB1_TLL_DATA6 */ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB1_TLL_DATA3 */ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB1_TLL_DIR */ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB1_TLL_NXT */ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB2_TLL_CLK */ - MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB2_TLL_STP */ - MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB2_TLL_DIR */ - MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB2_TLL_NXT */ - MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB2_TLL_DATA0 */ - MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M0)); - /* HSUSB2_TLL_DATA1 */ - MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M0)); - - /* DIE TO DIE */ - MUX_VAL(CP(D2D_MCAD0), (IEN | PTD | EN | M0)); /* D2D_MCAD0 */ - MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)); /* D2D_MCAD1 */ - MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)); /* D2D_MCAD2 */ - MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)); /* D2D_MCAD3 */ - MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)); /* D2D_MCAD4 */ - MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)); /* D2D_MCAD5 */ - MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)); /* D2D_MCAD6 */ - MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)); /* D2D_MCAD7 */ - MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)); /* D2D_MCAD8 */ - MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)); /* D2D_MCAD9 */ - MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)); /* D2D_MCAD10 */ - MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)); /* D2D_MCAD11 */ - MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)); /* D2D_MCAD12 */ - MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)); /* D2D_MCAD13 */ - MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)); /* D2D_MCAD14 */ - MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)); /* D2D_MCAD15 */ - MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)); /* D2D_MCAD16 */ - MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)); /* D2D_MCAD17 */ - MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)); /* D2D_MCAD18 */ - MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)); /* D2D_MCAD19 */ - MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)); /* D2D_MCAD20 */ - MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)); /* D2D_MCAD21 */ - MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)); /* D2D_MCAD22 */ - MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)); /* D2D_MCAD23 */ - MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)); /* D2D_MCAD24 */ - MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)); /* D2D_MCAD25 */ - MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)); /* D2D_MCAD26 */ - MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)); /* D2D_MCAD27 */ - MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)); /* D2D_MCAD28 */ - MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)); /* D2D_MCAD29 */ - MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)); /* D2D_MCAD30 */ - MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)); /* D2D_MCAD31 */ - MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)); /* D2D_MCAD32 */ - MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)); /* D2D_MCAD33 */ - MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)); /* D2D_MCAD34 */ - MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)); /* D2D_MCAD35 */ - MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)); /* D2D_MCAD36 */ - /* D2D_CLK26MI */ - MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)); - /* D2D_NRESPWRON */ - MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)); - /* D2D_NRESWARM */ - MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)); - /* D2D_ARM9NIRQ */ - MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)); - /* D2D_UMA2P6FIQ */ - MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)); - /* D2D_SPINT */ - MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)); - /* D2D_FRINT */ - MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)); - /* D2D_DMAREQ0 */ - MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)); - /* D2D_DMAREQ1 */ - MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)); - /* D2D_DMAREQ2 */ - MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)); - /* D2D_DMAREQ3 */ - MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)); - /* D2D_N3GTRST */ - MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)); - /* D2D_N3GTDI */ - MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)); - /* D2D_N3GTDO */ - MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)); - /* D2D_N3GTMS */ - MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)); - /* D2D_N3GTCK */ - MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)); - /* D2D_N3GRTCK */ - MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)); - /* D2D_MSTDBY */ - MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)); - /* D2D_SWAKEUP */ - MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)); - /* D2D_IDLEREQ */ - MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)); - /* D2D_IDLEACK */ - MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)); - /* D2D_MWRITE */ - MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)); - /* D2D_SWRITE */ - MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)); - /* D2D_MREAD */ - MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)); - /* D2D_SREAD */ - MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)); - /* D2D_MBUSFLAG */ - MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)); - /* D2D_SBUSFLAG */ - MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)); - /* SDRC_CKE0 */ - MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); - /* SDRC_CKE1 NOT USED */ - MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); -#endif /* CONFIG_MACH_OMAP_ADVANCED_MUX */ -} - -/** - * @brief The basic entry point for board initialization. - * - * This is called as part of machine init (after arch init). - * This is again called with stack in SRAM, so not too many - * constructs possible here. - * - * @return void - */ -static int sdp343x_board_init(void) -{ - int in_sdram = omap3_running_in_sdram(); - - if (!in_sdram) - omap3_core_init(); - - mux_config(); - if (!in_sdram) - sdrc_init(); - - return 0; -} - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - omap3_save_bootinfo((void *)r0); - - arm_cpu_lowlevel_init(); - - sdp343x_board_init(); - - barebox_arm_entry(0x80000000, SZ_128M, NULL); -} diff --git a/arch/arm/boards/omap3evm/Makefile b/arch/arm/boards/omap3evm/Makefile deleted file mode 100644 index da63d2625f..0000000000 --- a/arch/arm/boards/omap3evm/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/omap3evm/board.c b/arch/arm/boards/omap3evm/board.c deleted file mode 100644 index 37dbc0044e..0000000000 --- a/arch/arm/boards/omap3evm/board.c +++ /dev/null @@ -1,83 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: 2009 Sanjeev Premi <premi@ti.com>, Texas Instruments Incorporated (http://www.ti.com/) - -/** - * @file - * @brief Board Initialization routines for OMAP3EVM. - * - * This board is based on OMAP3530. - * More on OMAP3530 (including documentation can be found here): - * http://focus.ti.com/docs/prod/folders/print/omap3530.html - * - * This file provides initialization in two stages: - * @li Boot time initialization - just get SDRAM working. - * This is run from SRAM - so no case constructs and global vars can be used. - * @li Run time initialization - this is for the rest of the initializations - * such as flash, uart etc. - * - * Boot time initialization includes: - * @li SDRAM initialization. - * @li Pin Muxing relevant for the EVM. - * - * Run time initialization includes - * @li serial @ref serial_ns16550.c driver device definition - * - * Originally from arch/arm/boards/omap/board-beagle.c - */ - -#include <common.h> -#include <console.h> -#include <init.h> -#include <driver.h> -#include <io.h> -#include <linux/sizes.h> -#include <asm/armlinux.h> -#include <mach/omap/omap3-silicon.h> -#include <mach/omap/omap3-mux.h> -#include <mach/omap/gpmc.h> -#include <errno.h> -#include <asm/mach-types.h> -#include <mach/omap/omap3-devices.h> - -/** - * @brief Initialize the serial port to be used as console. - * - * @return result of device registration - */ -static int omap3evm_init_console(void) -{ - barebox_set_model("Texas Instruments omap3evm"); - barebox_set_hostname("omap3evm"); - - if (IS_ENABLED(CONFIG_OMAP_UART1)) - omap3_add_uart1(); - if (IS_ENABLED(CONFIG_OMAP_UART3)) - omap3_add_uart3(); - - return 0; -} -console_initcall(omap3evm_init_console); - -static int omap3evm_mem_init(void) -{ - omap_add_ram0(SZ_128M); - - return 0; -} -mem_initcall(omap3evm_mem_init); - -static int omap3evm_init_devices(void) -{ -#ifdef CONFIG_OMAP_GPMC - /* - * WP is made high and WAIT1 active Low - */ - gpmc_generic_init(0x10); -#endif - omap3_add_mmc1(NULL); - - armlinux_set_architecture(MACH_TYPE_OMAP3EVM); - - return 0; -} -device_initcall(omap3evm_init_devices); diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c deleted file mode 100644 index 5797acc14e..0000000000 --- a/arch/arm/boards/omap3evm/lowlevel.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <io.h> -#include <init.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/omap/generic.h> -#include <mach/omap/omap3-mux.h> -#include <mach/omap/sdrc.h> -#include <mach/omap/control.h> -#include <mach/omap/syslib.h> -#include <mach/omap/omap3-silicon.h> -#include <mach/omap/omap3-generic.h> -#include <mach/omap/sys_info.h> - - -/* - * Boot-time initialization(s) - */ - -/** - * @brief Initialize the SDRC module - * - * @return void - */ -static void sdrc_init(void) -{ - /* SDRAM software reset */ - /* No idle ack and RESET enable */ - writel(0x1A, OMAP3_SDRC_REG(SYSCONFIG)); - sdelay(100); - /* No idle ack and RESET disable */ - writel(0x18, OMAP3_SDRC_REG(SYSCONFIG)); - - /* SDRC Sharing register */ - /* 32-bit SDRAM on data lane [31:0] - CS0 */ - /* pin tri-stated = 1 */ - writel(0x00000100, OMAP3_SDRC_REG(SHARING)); - - /* ----- SDRC Registers Configuration --------- */ - /* SDRC_MCFG0 register */ - writel(0x02584099, OMAP3_SDRC_REG(MCFG_0)); - - /* SDRC_RFR_CTRL0 register */ - writel(0x54601, OMAP3_SDRC_REG(RFR_CTRL_0)); - - /* SDRC_ACTIM_CTRLA0 register */ - writel(0xA29DB4C6, OMAP3_SDRC_REG(ACTIM_CTRLA_0)); - - /* SDRC_ACTIM_CTRLB0 register */ - writel(0x12214, OMAP3_SDRC_REG(ACTIM_CTRLB_0)); - - /* Disble Power Down of CKE due to 1 CKE on combo part */ - writel(0x00000081, OMAP3_SDRC_REG(POWER)); - - /* SDRC_MANUAL command register */ - /* NOP command */ - writel(0x00000000, OMAP3_SDRC_REG(MANUAL_0)); - /* Precharge command */ - writel(0x00000001, OMAP3_SDRC_REG(MANUAL_0)); - /* Auto-refresh command */ - writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0)); - /* Auto-refresh command */ - writel(0x00000002, OMAP3_SDRC_REG(MANUAL_0)); - - /* SDRC MR0 register Burst length=4 */ - writel(0x00000032, OMAP3_SDRC_REG(MR_0)); - - /* SDRC DLLA control register */ - writel(0x0000000A, OMAP3_SDRC_REG(DLLA_CTRL)); - - return; -} - -/** - * @brief Do the necessary pin muxing required for OMAP3EVM. Some pins in OMAP3 - * do not have alternate modes. We don't program these pins. - * - * See @ref MUX_VAL for description of the muxing mode. - * - * @return void - */ -static void mux_config(void) -{ - /* - * SDRC - * - SDRC_D0-SDRC_D31: Default MUX mode is mode0. - */ - - /* - * GPMC - * - GPMC_D0-GPMC_D7: Default MUX mode is mode0. - * - GPMC_NADV_ALE: Default MUX mode is mode0. - * - GPMC_NOE: Default MUX mode is mode0. - * - GPMC_NWE: Default MUX mode is mode0. - * - GPMC_WAIT0: Default MUX mode is mode0. - */ - MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)); - - MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)); - - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); - - MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)); - - /* - * Serial Interface - */ -#if defined(CONFIG_OMAP_UART1) - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)); - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)); -#elif defined(CONFIG_OMAP_UART3) - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); -#endif -} - -/** - * @brief The basic entry point for board initialization. - * - * This is called as part of machine init (after arch init). - * This is again called with stack in SRAM, so not too many - * constructs possible here. - * - * @return void - */ -static int omap3_evm_board_init(void) -{ - int in_sdram = omap3_running_in_sdram(); - - omap3_core_init(); - - mux_config(); - - /* Dont reconfigure SDRAM while running in SDRAM! */ - if (!in_sdram) - sdrc_init(); - - return 0; -} - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - omap3_save_bootinfo((void *)r0); - - arm_cpu_lowlevel_init(); - - omap3_evm_board_init(); - - barebox_arm_entry(0x80000000, SZ_128M, NULL); -} diff --git a/arch/arm/boards/panda/Makefile b/arch/arm/boards/panda/Makefile deleted file mode 100644 index 3bd91350ce..0000000000 --- a/arch/arm/boards/panda/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o mux.o diff --git a/arch/arm/boards/panda/board.c b/arch/arm/boards/panda/board.c deleted file mode 100644 index 55836d2331..0000000000 --- a/arch/arm/boards/panda/board.c +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <console.h> -#include <init.h> -#include <driver.h> -#include <io.h> -#include <gpio.h> -#include <asm/armlinux.h> -#include <asm/mach-types.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-devices.h> -#include <mach/omap/sdrc.h> -#include <mach/omap/sys_info.h> -#include <mach/omap/syslib.h> -#include <mach/omap/control.h> -#include <linux/usb/ehci.h> -#include <linux/err.h> -#include <linux/sizes.h> -#include <asm/mmu.h> -#include <envfs.h> -#include <i2c/i2c.h> -#include <led.h> - -static int board_revision; - -#define GPIO_HUB_POWER 1 -#define GPIO_HUB_NRESET_39 39 -#define GPIO_HUB_NRESET_62 62 -#define GPIO_BOARD_ID0 182 -#define GPIO_BOARD_ID1 101 -#define GPIO_BOARD_ID2 171 - -static int panda_console_init(void) -{ - barebox_set_model("Texas Instruments panda"); - barebox_set_hostname("panda"); - - omap44xx_add_uart3(); - - return 0; -} -console_initcall(panda_console_init); - -static int panda_mem_init(void) -{ - omap_add_ram0(SZ_1G); - - return 0; -} -mem_initcall(panda_mem_init); - -#ifdef CONFIG_USB_EHCI -static struct ehci_platform_data ehci_pdata = { - .flags = 0, -}; - -static void panda_ehci_init(void) -{ - u32 val; - int hub_nreset; - - if (board_revision) - hub_nreset = GPIO_HUB_NRESET_62; - else - hub_nreset = GPIO_HUB_NRESET_39; - - /* disable the power to the usb hub prior to init */ - gpio_direction_output(GPIO_HUB_POWER, 0); - gpio_set_value(GPIO_HUB_POWER, 0); - - /* reset phy+hub */ - gpio_direction_output(hub_nreset, 0); - gpio_set_value(hub_nreset, 0); - gpio_set_value(hub_nreset, 1); - val = readl(0x4a009358); - val |= (1 << 24); - val |= 0x2; - writel(val, 0x4a009358); - writel(0x7, 0x4a008180); - mdelay(10); - - writel(0x00000014, 0x4a064010); - writel(0x8000001c, 0x4a064040); - - /* enable power to hub */ - gpio_set_value(GPIO_HUB_POWER, 1); - - omap44xx_add_ehci(&ehci_pdata); -} -#else -static void panda_ehci_init(void) -{} -#endif - -static void __init panda_boardrev_init(void) -{ - board_revision = gpio_get_value(GPIO_BOARD_ID0); - board_revision |= (gpio_get_value(GPIO_BOARD_ID1)<<1); - board_revision |= (gpio_get_value(GPIO_BOARD_ID2)<<2); - - pr_info("PandaBoard Revision: %03d\n", board_revision); -} - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("twl6030", 0x48), - }, -}; - -struct gpio_led panda_leds[] = { - { - .gpio = 7, - .led = { - .name = "heartbeat", - }, - }, -}; - -static void panda_led_init(void) -{ - led_gpio_register(&panda_leds[0]); - led_set_trigger(LED_TRIGGER_HEARTBEAT, &panda_leds[0].led); -} - -static int panda_devices_init(void) -{ - panda_boardrev_init(); - - if (gpio_get_value(182)) { - /* enable software ioreq */ - sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1); - /* set for sys_clk (38.4MHz) */ - sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0); - /* set divisor to 2 */ - sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1); - /* set the clock source to active */ - sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1); - /* enable clocks */ - sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); - } else { - /* enable software ioreq */ - sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1); - /* set for PER_DPLL */ - sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2); - /* set divisor to 16 */ - sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf); - /* set the clock source to active */ - sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1); - /* enable clocks */ - sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); - } - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - omap44xx_add_i2c1(NULL); - omap44xx_add_mmc1(NULL); - - panda_ehci_init(); - - panda_led_init(); - armlinux_set_architecture(MACH_TYPE_OMAP4_PANDA); - - return 0; -} -device_initcall(panda_devices_init); diff --git a/arch/arm/boards/panda/env/boot/mmc b/arch/arm/boards/panda/env/boot/mmc deleted file mode 100644 index db638f8cf8..0000000000 --- a/arch/arm/boards/panda/env/boot/mmc +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -global.bootm.image="/boot/zImage" -#global.bootm.oftree="/boot/oftree" -global.linux.bootargs.dyn.root="root=mmcblk0p2 rootfstype=ext3 rootwait" diff --git a/arch/arm/boards/panda/env/network/eth0-discover b/arch/arm/boards/panda/env/network/eth0-discover deleted file mode 100644 index 77552d30b3..0000000000 --- a/arch/arm/boards/panda/env/network/eth0-discover +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -# Panda has a network adapter on USB - -usb diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c deleted file mode 100644 index f535e7f9a4..0000000000 --- a/arch/arm/boards/panda/lowlevel.c +++ /dev/null @@ -1,81 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) - -#include <common.h> -#include <init.h> -#include <io.h> -#include <linux/sizes.h> -#include <mach/omap/generic.h> -#include <mach/omap/omap4-mux.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-generic.h> -#include <mach/omap/omap4-clock.h> -#include <mach/omap/syslib.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> - -#include "mux.h" - -#define TPS62361_VSEL0_GPIO 7 - -static const struct ddr_regs ddr_regs_400_mhz_2cs = { - /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/ - .tim1 = 0x10eb0662, - .tim2 = 0x20370dd2, - .tim3 = 0x00b1c33f, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80000eb9, - .config_final = 0x80001ab9, - .zq_config = 0xD00b3215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -static void noinline panda_init_lowlevel(void) -{ - struct dpll_param core = OMAP4_CORE_DPLL_PARAM_38M4_DDR400; - struct dpll_param mpu = OMAP4_MPU_DPLL_PARAM_38M4_MPU600; - struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_38M4; - struct dpll_param per = OMAP4_PER_DPLL_PARAM_38M4; - struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_38M4; - struct dpll_param usb = OMAP4_USB_DPLL_PARAM_38M4; - unsigned int rev = omap4_revision(); - - writel(CM_SYS_CLKSEL_38M4, CM_SYS_CLKSEL); - - /* Configure all DPLL's at 100% OPP */ - omap4_configure_mpu_dpll(&mpu); - omap4_configure_iva_dpll(&iva); - omap4_configure_per_dpll(&per); - omap4_configure_abe_dpll(&abe); - omap4_configure_usb_dpll(&usb); - - /* Enable all clocks */ - omap4_enable_all_clocks(); - - panda_set_muxconf_regs(); - - omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); - - if (rev < OMAP4460_ES1_0) - omap4430_scale_vcores(); - else - omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1210); -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - omap4_save_bootinfo((void *)r0); - - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) - goto out; - - arm_setup_stack(0x4030d000); - - panda_init_lowlevel(); -out: - barebox_arm_entry(0x80000000, SZ_1G, NULL); -} diff --git a/arch/arm/boards/panda/mux.c b/arch/arm/boards/panda/mux.c deleted file mode 100644 index b5e1e79c8f..0000000000 --- a/arch/arm/boards/panda/mux.c +++ /dev/null @@ -1,260 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <init.h> -#include <io.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-mux.h> -#include <mach/omap/omap4-clock.h> - -#include "mux.h" - -static const struct pad_conf_entry core_padconf_array[] = { - { GPMC_AD0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat0 */ }, - { GPMC_AD1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat1 */ }, - { GPMC_AD2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat2 */ }, - { GPMC_AD3, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat3 */ }, - { GPMC_AD4, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat4 */ }, - { GPMC_AD5, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat5 */ }, - { GPMC_AD6, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat6 */ }, - { GPMC_AD7, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat7 */ }, - { GPMC_AD8, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3 /* gpio_32 */ }, - { GPMC_AD9, PTU | IEN | M3 /* gpio_33 */ }, - { GPMC_AD10, PTU | IEN | M3 /* gpio_34 */ }, - { GPMC_AD11, PTU | IEN | M3 /* gpio_35 */ }, - { GPMC_AD12, PTU | IEN | M3 /* gpio_36 */ }, - { GPMC_AD13, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_37 */ }, - { GPMC_AD14, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_38 */ }, - { GPMC_AD15, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_39 */ }, - { GPMC_A16, M3 /* gpio_40 */ }, - { GPMC_A17, PTD | M3 /* gpio_41 */ }, - { GPMC_A18, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row6 */ }, - { GPMC_A19, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row7 */ }, - { GPMC_A20, IEN | M3 /* gpio_44 */ }, - { GPMC_A21, M3 /* gpio_45 */ }, - { GPMC_A22, M3 /* gpio_46 */ }, - { GPMC_A23, OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col7 */ }, - { GPMC_A24, PTD | M3 /* gpio_48 */ }, - { GPMC_A25, PTD | M3 /* gpio_49 */ }, - { GPMC_NCS0, M3 /* gpio_50 */ }, - { GPMC_NCS1, IEN | M3 /* gpio_51 */ }, - { GPMC_NCS2, IEN | M3 /* gpio_52 */ }, - { GPMC_NCS3, IEN | M3 /* gpio_53 */ }, - { GPMC_NWP, M3 /* gpio_54 */ }, - { GPMC_CLK, PTD | M3 /* gpio_55 */ }, - { GPMC_NADV_ALE, M3 /* gpio_56 */ }, - { GPMC_NOE, PTU | IEN | OFF_EN | OFF_OUT_PTD | M1 /* sdmmc2_clk */ }, - { GPMC_NWE, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_cmd */ }, - { GPMC_NBE0_CLE, M3 /* gpio_59 */ }, - { GPMC_NBE1, PTD | M3 /* gpio_60 */ }, - { GPMC_WAIT0, PTU | IEN | M3 /* gpio_61 */ }, - { GPMC_WAIT1, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_62 */ }, - { C2C_DATA11, PTD | M3 /* gpio_100 */ }, - { C2C_DATA12, PTD | IEN | M3 /* gpio_101 */ }, - { C2C_DATA13, PTD | M3 /* gpio_102 */ }, - { C2C_DATA14, M1 /* dsi2_te0 */ }, - { C2C_DATA15, PTD | M3 /* gpio_104 */ }, - { HDMI_HPD, M0 /* hdmi_hpd */ }, - { HDMI_CEC, M0 /* hdmi_cec */ }, - { HDMI_DDC_SCL, PTU | M0 /* hdmi_ddc_scl */ }, - { HDMI_DDC_SDA, PTU | IEN | M0 /* hdmi_ddc_sda */ }, - { CSI21_DX0, IEN | M0 /* csi21_dx0 */ }, - { CSI21_DY0, IEN | M0 /* csi21_dy0 */ }, - { CSI21_DX1, IEN | M0 /* csi21_dx1 */ }, - { CSI21_DY1, IEN | M0 /* csi21_dy1 */ }, - { CSI21_DX2, IEN | M0 /* csi21_dx2 */ }, - { CSI21_DY2, IEN | M0 /* csi21_dy2 */ }, - { CSI21_DX3, PTD | M7 /* csi21_dx3 */ }, - { CSI21_DY3, PTD | M7 /* csi21_dy3 */ }, - { CSI21_DX4, PTD | OFF_EN | OFF_PD | OFF_IN | M7 /* csi21_dx4 */ }, - { CSI21_DY4, PTD | OFF_EN | OFF_PD | OFF_IN | M7 /* csi21_dy4 */ }, - { CSI22_DX0, IEN | M0 /* csi22_dx0 */ }, - { CSI22_DY0, IEN | M0 /* csi22_dy0 */ }, - { CSI22_DX1, IEN | M0 /* csi22_dx1 */ }, - { CSI22_DY1, IEN | M0 /* csi22_dy1 */ }, - { CAM_SHUTTER, OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* cam_shutter */ }, - { CAM_STROBE, OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* cam_strobe */ }, - { CAM_GLOBALRESET, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_83 */ }, - { USBB1_ULPITLL_CLK, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_clk */ }, - { USBB1_ULPITLL_STP, OFF_EN | OFF_OUT_PTD | M4 /* usbb1_ulpiphy_stp */ }, - { USBB1_ULPITLL_DIR, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dir */ }, - { USBB1_ULPITLL_NXT, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_nxt */ }, - { USBB1_ULPITLL_DAT0, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat0 */ }, - { USBB1_ULPITLL_DAT1, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat1 */ }, - { USBB1_ULPITLL_DAT2, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat2 */ }, - { USBB1_ULPITLL_DAT3, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat3 */ }, - { USBB1_ULPITLL_DAT4, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat4 */ }, - { USBB1_ULPITLL_DAT5, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat5 */ }, - { USBB1_ULPITLL_DAT6, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat6 */ }, - { USBB1_ULPITLL_DAT7, IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat7 */ }, - { USBB1_HSIC_DATA, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usbb1_hsic_data */ }, - { USBB1_HSIC_STROBE, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usbb1_hsic_strobe */ }, - { USBC1_ICUSB_DP, IEN | M0 /* usbc1_icusb_dp */ }, - { USBC1_ICUSB_DM, IEN | M0 /* usbc1_icusb_dm */ }, - { SDMMC1_CLK, PTU | OFF_EN | OFF_OUT_PTD | M0 /* sdmmc1_clk */ }, - { SDMMC1_CMD, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_cmd */ }, - { SDMMC1_DAT0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat0 */ }, - { SDMMC1_DAT1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat1 */ }, - { SDMMC1_DAT2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat2 */ }, - { SDMMC1_DAT3, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat3 */ }, - { SDMMC1_DAT4, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat4 */ }, - { SDMMC1_DAT5, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat5 */ }, - { SDMMC1_DAT6, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat6 */ }, - { SDMMC1_DAT7, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat7 */ }, - { ABE_MCBSP2_CLKX, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp2_clkx */ }, - { ABE_MCBSP2_DR, IEN | OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp2_dr */ }, - { ABE_MCBSP2_DX, OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp2_dx */ }, - { ABE_MCBSP2_FSX, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp2_fsx */ }, - { ABE_MCBSP1_CLKX, IEN | M1 /* abe_slimbus1_clock */ }, - { ABE_MCBSP1_DR, IEN | M1 /* abe_slimbus1_data */ }, - { ABE_MCBSP1_DX, OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp1_dx */ }, - { ABE_MCBSP1_FSX, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp1_fsx */ }, - { ABE_PDM_UL_DATA, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_ul_data */ }, - { ABE_PDM_DL_DATA, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_dl_data */ }, - { ABE_PDM_FRAME, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_frame */ }, - { ABE_PDM_LB_CLK, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_lb_clk */ }, - { ABE_CLKS, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_clks */ }, - { ABE_DMIC_CLK1, M0 /* abe_dmic_clk1 */ }, - { ABE_DMIC_DIN1, IEN | M0 /* abe_dmic_din1 */ }, - { ABE_DMIC_DIN2, IEN | M0 /* abe_dmic_din2 */ }, - { ABE_DMIC_DIN3, IEN | M0 /* abe_dmic_din3 */ }, - { UART2_CTS, PTU | IEN | M0 /* uart2_cts */ }, - { UART2_RTS, M0 /* uart2_rts */ }, - { UART2_RX, PTU | IEN | M0 /* uart2_rx */ }, - { UART2_TX, M0 /* uart2_tx */ }, - { HDQ_SIO, M3 /* gpio_127 */ }, - { I2C1_SCL, PTU | IEN | M0 /* i2c1_scl */ }, - { I2C1_SDA, PTU | IEN | M0 /* i2c1_sda */ }, - { I2C2_SCL, PTU | IEN | M0 /* i2c2_scl */ }, - { I2C2_SDA, PTU | IEN | M0 /* i2c2_sda */ }, - { I2C3_SCL, PTU | IEN | M0 /* i2c3_scl */ }, - { I2C3_SDA, PTU | IEN | M0 /* i2c3_sda */ }, - { I2C4_SCL, PTU | IEN | M0 /* i2c4_scl */ }, - { I2C4_SDA, PTU | IEN | M0 /* i2c4_sda */ }, - { MCSPI1_CLK, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_clk */ }, - { MCSPI1_SOMI, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_somi */ }, - { MCSPI1_SIMO, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_simo */ }, - { MCSPI1_CS0, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_cs0 */ }, - { MCSPI1_CS1, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3 /* mcspi1_cs1 */ }, - { MCSPI1_CS2, PTU | OFF_EN | OFF_OUT_PTU | M3 /* gpio_139 */ }, - { MCSPI1_CS3, PTU | IEN | M3 /* gpio_140 */ }, - { UART3_CTS_RCTX, PTU | IEN | M0 /* uart3_tx */ }, - { UART3_RTS_SD, M0 /* uart3_rts_sd */ }, - { UART3_RX_IRRX, IEN | M0 /* uart3_rx */ }, - { UART3_TX_IRTX, M0 /* uart3_tx */ }, - { SDMMC5_CLK, PTU | IEN | OFF_EN | OFF_OUT_PTD | M0 /* sdmmc5_clk */ }, - { SDMMC5_CMD, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_cmd */ }, - { SDMMC5_DAT0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat0 */ }, - { SDMMC5_DAT1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat1 */ }, - { SDMMC5_DAT2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat2 */ }, - { SDMMC5_DAT3, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat3 */ }, - { MCSPI4_CLK, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_clk */ }, - { MCSPI4_SIMO, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_simo */ }, - { MCSPI4_SOMI, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_somi */ }, - { MCSPI4_CS0, PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_cs0 */ }, - { UART4_RX, IEN | M0 /* uart4_rx */ }, - { UART4_TX, M0 /* uart4_tx */ }, - { USBB2_ULPITLL_CLK, IEN | M3 /* gpio_157 */ }, - { USBB2_ULPITLL_STP, IEN | M5 /* dispc2_data23 */ }, - { USBB2_ULPITLL_DIR, IEN | M5 /* dispc2_data22 */ }, - { USBB2_ULPITLL_NXT, IEN | M5 /* dispc2_data21 */ }, - { USBB2_ULPITLL_DAT0, IEN | M5 /* dispc2_data20 */ }, - { USBB2_ULPITLL_DAT1, IEN | M5 /* dispc2_data19 */ }, - { USBB2_ULPITLL_DAT2, IEN | M5 /* dispc2_data18 */ }, - { USBB2_ULPITLL_DAT3, IEN | M5 /* dispc2_data15 */ }, - { USBB2_ULPITLL_DAT4, IEN | M5 /* dispc2_data14 */ }, - { USBB2_ULPITLL_DAT5, IEN | M5 /* dispc2_data13 */ }, - { USBB2_ULPITLL_DAT6, IEN | M5 /* dispc2_data12 */ }, - { USBB2_ULPITLL_DAT7, IEN | M5 /* dispc2_data11 */ }, - { USBB2_HSIC_DATA, PTD | OFF_EN | OFF_OUT_PTU | M3 /* gpio_169 */ }, - { USBB2_HSIC_STROBE, PTD | OFF_EN | OFF_OUT_PTU | M3 /* gpio_170 */ }, - { UNIPRO_TX0, PTD | IEN | M3 /* gpio_171 */ }, - { UNIPRO_TY0, OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col1 */ }, - { UNIPRO_TX1, OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col2 */ }, - { UNIPRO_TY1, OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col3 */ }, - { UNIPRO_TX2, PTU | IEN | M3 /* gpio_0 */ }, - { UNIPRO_TY2, PTU | IEN | M3 /* gpio_1 */ }, - { UNIPRO_RX0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row0 */ }, - { UNIPRO_RY0, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row1 */ }, - { UNIPRO_RX1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row2 */ }, - { UNIPRO_RY1, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row3 */ }, - { UNIPRO_RX2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row4 */ }, - { UNIPRO_RY2, PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row5 */ }, - { USBA0_OTG_CE, PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* usba0_otg_ce */ }, - { USBA0_OTG_DP, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usba0_otg_dp */ }, - { USBA0_OTG_DM, IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usba0_otg_dm */ }, - { FREF_CLK1_OUT, M0 /* fref_clk1_out */ }, - { FREF_CLK2_OUT, PTD | IEN | M3 /* gpio_182 */ }, - { SYS_NIRQ1, PTU | IEN | M0 /* sys_nirq1 */ }, - { SYS_NIRQ2, PTU | IEN | M0 /* sys_nirq2 */ }, - { SYS_BOOT0, PTU | IEN | M3 /* gpio_184 */ }, - { SYS_BOOT1, M3 /* gpio_185 */ }, - { SYS_BOOT2, PTD | IEN | M3 /* gpio_186 */ }, - { SYS_BOOT3, M3 /* gpio_187 */ }, - { SYS_BOOT4, M3 /* gpio_188 */ }, - { SYS_BOOT5, PTD | IEN | M3 /* gpio_189 */ }, - { DPM_EMU0, IEN | M0 /* dpm_emu0 */ }, - { DPM_EMU1, IEN | M0 /* dpm_emu1 */ }, - { DPM_EMU2, IEN | M0 /* dpm_emu2 */ }, - { DPM_EMU3, IEN | M5 /* dispc2_data10 */ }, - { DPM_EMU4, IEN | M5 /* dispc2_data9 */ }, - { DPM_EMU5, IEN | M5 /* dispc2_data16 */ }, - { DPM_EMU6, IEN | M5 /* dispc2_data17 */ }, - { DPM_EMU7, IEN | M5 /* dispc2_hsync */ }, - { DPM_EMU8, IEN | M5 /* dispc2_pclk */ }, - { DPM_EMU9, IEN | M5 /* dispc2_vsync */ }, - { DPM_EMU10, IEN | M5 /* dispc2_de */ }, - { DPM_EMU11, IEN | M5 /* dispc2_data8 */ }, - { DPM_EMU12, IEN | M5 /* dispc2_data7 */ }, - { DPM_EMU13, IEN | M5 /* dispc2_data6 */ }, - { DPM_EMU14, IEN | M5 /* dispc2_data5 */ }, - { DPM_EMU15, IEN | M5 /* dispc2_data4 */ }, - { DPM_EMU16, M3 /* gpio_27 */ }, - { DPM_EMU17, IEN | M5 /* dispc2_data2 */ }, - { DPM_EMU18, IEN | M5 /* dispc2_data1 */ }, - { DPM_EMU19, IEN | M5 /* dispc2_data0 */ }, -}; - -static const struct pad_conf_entry wkup_padconf_array[] = { - { GPIO_WK0, IEN | M0 /* sim_io */ }, - { GPIO_WK1, M0 /* sim_clk */ }, - { GPIO_WK2, M0 /* sim_reset */ }, - { GPIO_WK3, PTU | IEN | M0 /* sim_cd */ }, - { GPIO_WK4, M0 /* sim_pwrctrl */ }, - { SR_SCL, PTU | IEN | M0 /* sr_scl */ }, - { SR_SDA, PTU | IEN | M0 /* sr_sda */ }, - { FREF_XTAL_IN, M0 /* # */ }, - { FREF_SLICER_IN, M0 /* fref_slicer_in */ }, - { FREF_CLK_IOREQ, M0 /* fref_clk_ioreq */ }, - { FREF_CLK0_OUT, M2 /* sys_drm_msecure */ }, - { FREF_CLK3_REQ, PTU | IEN | M0 /* # */ }, - { FREF_CLK3_OUT, M0 /* fref_clk3_out */ }, - { FREF_CLK4_REQ, PTU | IEN | M0 /* # */ }, - { FREF_CLK4_OUT, M0 /* # */ }, - { SYS_32K, IEN | M0 /* sys_32k */ }, - { SYS_NRESPWRON, M0 /* sys_nrespwron */ }, - { SYS_NRESWARM, M0 /* sys_nreswarm */ }, - { SYS_PWR_REQ, PTU | M0 /* sys_pwr_req */ }, - { SYS_PWRON_RESET_OUT, M3 /* gpio_wk29 */ }, - { SYS_BOOT6, IEN | M3 /* gpio_wk9 */ }, - { SYS_BOOT7, IEN | M3 /* gpio_wk10 */ }, - { FREF_CLK3_REQ, M3 /* gpio_wk30 */ }, - { FREF_CLK4_REQ, M3 /* gpio_wk7 */ }, - { FREF_CLK4_OUT, M3 /* gpio_wk8 */ }, -}; - -void panda_set_muxconf_regs(void) -{ - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, - ARRAY_SIZE(core_padconf_array)); - - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, - ARRAY_SIZE(wkup_padconf_array)); - - /* gpio_wk7 is used for controlling TPS on 4460 */ - if (omap4_revision() >= OMAP4460_ES1_0) { - writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + FREF_CLK4_REQ); - /* Enable GPIO-1 clocks before TPS initialization */ - omap4_enable_gpio1_wup_clocks(); - } -} diff --git a/arch/arm/boards/panda/mux.h b/arch/arm/boards/panda/mux.h deleted file mode 100644 index 540d4e5d34..0000000000 --- a/arch/arm/boards/panda/mux.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BOARD_MUX_H -#define __BOARD_MUX_H - -void panda_set_muxconf_regs(void); - -#endif /* __BOARD_MUX_H */ diff --git a/arch/arm/boards/phytec-phycard-omap3/Makefile b/arch/arm/boards/phytec-phycard-omap3/Makefile deleted file mode 100644 index 16f198b38c..0000000000 --- a/arch/arm/boards/phytec-phycard-omap3/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2011 Juergen Kilb <j.kilb@phytec.de> - -obj-y += pca-a-l1.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/phytec-phycard-omap3/env/config b/arch/arm/boards/phytec-phycard-omap3/env/config deleted file mode 100644 index a3f452b3d1..0000000000 --- a/arch/arm/boards/phytec-phycard-omap3/env/config +++ /dev/null @@ -1,77 +0,0 @@ -#!/bin/sh - -#user= - -# Enter MAC address here if not retrieved automatically -#eth0.ethaddr=de:ad:be:ef:00:00 - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.serverip=a.b.c.d -#eth0.gateway=a.b.c.d - -# can be either 'tftp', 'nfs', 'nand' or 'disk' -kernel_loc=nand -# can be either 'net', 'nand', 'disk' or 'initrd' -rootfs_loc=nand - -# for flash based rootfs: 'jffs2' or 'ubifs' -# in case of disk any regular filesystem like 'ext2', 'ext3', 'reiserfs' -rootfs_type=jffs2 -# where is the rootfs in case of 'rootfs_loc=disk' (linux name) -rootfs_part_linux_dev=mmcblk0p4 -rootfsimage=rootfs-${global.hostname}.$rootfs_type - -# where is the kernel image in case of 'kernel_loc=disk' -kernel_part=disk0.2 - -# The image type of the kernel. Can be uimage, zimage, raw or raw_lzo -#kernelimage=zImage-${global.hostname} -kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -bareboximage=barebox-${global.hostname}.bin -bareboxenvimage=barebox-${global.hostname}.bin - -if [ -n $user ]; then - bareboximage="$user"-"$bareboximage" - bareboxenvimage="$user"-"$bareboxenvimage" - kernelimage="$user"-"$kernelimage" - rootfsimage="$user"-"$rootfsimage" - nfsroot="/home/$user/nfsroot/${global.hostname}" -else - nfsroot="/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyO2,115200" - -# the following displays are supported -# pd050vl1 (640 x 480) -# pd035vl1 (640 x 480) -# pd104slf (800 x 600) -# pm070wl4 (800 x 480) -# -# omapfb.mode=<display>:<mode>,[,...] -# omapfb.debug=<y|n> -# - Enable debug printing. You have to have OMAPFB debug support enabled -# in kernel config. -# -bootargs="$bootargs omapdss.def_disp=pd050vl1" -#bootargs="$bootargs omapdss.def_disp=pd035vl1" -#bootargs="$bootargs omapdss.def_disp=pd104slf" -#bootargs="$bootargs omapdss.def_disp=pm070wl4" - -nand_parts="128k(x-loader)ro,512k(barebox),128k(bareboxenv),4M(kernel),-(root)" -nand_device=omap2-nand.0 -rootfs_mtdblock_nand=4 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " diff --git a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c b/arch/arm/boards/phytec-phycard-omap3/lowlevel.c deleted file mode 100644 index 56fbdf12ad..0000000000 --- a/arch/arm/boards/phytec-phycard-omap3/lowlevel.c +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <io.h> -#include <init.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> -#include <mach/omap/omap3-mux.h> -#include <mach/omap/generic.h> -#include <mach/omap/sdrc.h> -#include <mach/omap/control.h> -#include <mach/omap/syslib.h> -#include <mach/omap/omap3-silicon.h> -#include <mach/omap/omap3-generic.h> -#include <mach/omap/sys_info.h> - -/* Slower full frequency range default timings for x32 operation */ -#define SDP_SDRC_SHARING 0x00000100 -/* Diabling power down mode using CKE pin */ -#define SDP_SDRC_POWER_POP 0x00000081 -/* rkw - need to find of 90/72 degree recommendation for speed like before. */ -#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ - (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) - -/* used to create an array of memory configuartions. */ -struct sdrc_config { - u32 cs_cfg; - u32 mcfg; - u32 mr; - u32 actim_ctrla; - u32 actim_ctrlb; - u32 rfr_ctrl; -} const sdrc_config[] = { -/* max cs_size for autodetection, common timing */ -/* 2x256MByte, 14 Rows, 10 Columns , RBC (BAL=2) */ -{ 0x00000004, 0x03590099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201}, -/* MT46H32M32LF 2x128MByte, 13 Rows, 10 Columns */ -{ 0x00000001, 0x02584099, 0x00000032, 0x9A9DB4C6, 0x00011216, 0x0004e201}, -/* MT46H64M32LF 1x256MByte, 14 Rows, 10 Columns */ -{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201}, -/* MT64H128M32L2 2x256MByte, 14 Rows, 10 Columns */ -{ 0x00000002, 0x03588099, 0x00000032, 0x629DB4C6, 0x00011113, 0x0004e201}, -}; - -/* - * Boot-time initialization(s) - */ - -/********************************************************************* - * init_sdram_ddr() - Init DDR controller. - *********************************************************************/ -static void init_sdram_ddr(void) -{ - /* reset sdrc controller */ - writel(SOFTRESET, OMAP3_SDRC_REG(SYSCONFIG)); - wait_on_value(1<<0, 1<<0, OMAP3_SDRC_REG(STATUS), 12000000); - writel(0, OMAP3_SDRC_REG(SYSCONFIG)); - - /* setup sdrc to ball mux */ - writel(SDP_SDRC_SHARING, OMAP3_SDRC_REG(SHARING)); - writel(SDP_SDRC_POWER_POP, OMAP3_SDRC_REG(POWER)); - - /* set up dll */ - writel(SDP_SDRC_DLLAB_CTRL, OMAP3_SDRC_REG(DLLA_CTRL)); - sdelay(0x2000); /* give time to lock */ - -} -/********************************************************************* - * config_sdram_ddr() - Init DDR on dev board. - *********************************************************************/ -static void config_sdram_ddr(u8 cs, u8 cfg) -{ - - writel(sdrc_config[cfg].mcfg, OMAP3_SDRC_REG(MCFG_0) + (0x30 * cs)); - writel(sdrc_config[cfg].actim_ctrla, OMAP3_SDRC_REG(ACTIM_CTRLA_0) + (0x28 * cs)); - writel(sdrc_config[cfg].actim_ctrlb, OMAP3_SDRC_REG(ACTIM_CTRLB_0) + (0x28 * cs)); - writel(sdrc_config[cfg].rfr_ctrl, OMAP3_SDRC_REG(RFR_CTRL_0) + (0x30 * cs)); - - writel(CMD_NOP, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); - - sdelay(5000); - - writel(CMD_PRECHARGE, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); - writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); - writel(CMD_AUTOREFRESH, OMAP3_SDRC_REG(MANUAL_0) + (0x30 * cs)); - - /* set mr0 */ - writel(sdrc_config[cfg].mr, OMAP3_SDRC_REG(MR_0) + (0x30 * cs)); - - sdelay(2000); -} - -/** - * @brief Initialize the SDRC module - * Initialisation for 1x256MByte but normally - * done by x-loader. - * @return void - */ -static void pcaal1_sdrc_init(void) -{ - u32 test0, test1; - signed char cfg; - - init_sdram_ddr(); - - config_sdram_ddr(0, 0); /* 256MByte at CS0 */ - config_sdram_ddr(1, 0); /* 256MByte at CS1 */ - - test0 = get_ram_size((long *) 0x80000000, SZ_256M); - test1 = get_ram_size((long *) 0xA0000000, SZ_256M); - - /* mask out lower nible, its not tested with - in common/memsize.c */ - test1 &= 0xfffffff0; - - if ((test1 > 0) && (test1 != test0)) - hang(); - - cfg = -1; /* illegal configuration found */ - - if (test1 == 0) { - init_sdram_ddr(); - writel((sdrc_config[(uchar) cfg].mcfg & 0xfffc00ff), OMAP3_SDRC_REG(MCFG_1)); - - /* 1 x 256MByte */ - if (test0 == SZ_256M) - cfg = 2; - - if (cfg != -1) { - config_sdram_ddr(0, cfg); - writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG)); - } - return; - } - - /* reinit both cs with correct size */ - /* 2 x 128MByte */ - if (test0 == SZ_128M) - cfg = 1; - /* 2 x 256MByte */ - if (test0 == SZ_256M) - cfg = 3; - - if (cfg != -1) { - init_sdram_ddr(); - writel(sdrc_config[(uchar) cfg].cs_cfg, OMAP3_SDRC_REG(CS_CFG)); - config_sdram_ddr(0, cfg); - config_sdram_ddr(1, cfg); - } -} - -/** - * @brief Do the necessary pin muxing required for phyCARD-A-L1. - * Some pins in OMAP3 do not have alternate modes. - * We don't program these pins. - * - * See @ref MUX_VAL for description of the muxing mode. - * - * @return void - */ -static void pcaal1_mux_config(void) -{ - /* - * Serial Interface - */ - MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)); - MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | EN | M0)); - MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); - - /* GPMC */ - MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); - MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); - - /* ETH_PME (GPIO_55) */ - MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M4)); - /* #CS5 (Ethernet) */ - MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)); - /* ETH_FIFO_SEL (GPIO_57) */ - MUX_VAL(CP(GPMC_NCS6), (IDIS | PTD | EN | M4)); - /* ETH_AMDIX_EN (GPIO_58) */ - MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M4)); - /* ETH_nRST (GPIO_64) */ - MUX_VAL(CP(GPMC_WAIT2), (IDIS | PTU | EN | M4)); - - /* HSMMC1 */ - MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); - MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); - MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); - - /* USBOTG_nRST (GPIO_63) */ - MUX_VAL(CP(GPMC_WAIT1), (IDIS | PTU | EN | M4)); - - /* USBH_nRST (GPIO_65) */ - MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4)); -} - -/** - * @brief The basic entry point for board initialization. - * - * This is called as part of machine init (after arch init). - * This is again called with stack in SRAM, so not too many - * constructs possible here. - * - * @return void - */ -static int pcaal1_board_init(void) -{ - int in_sdram = omap3_running_in_sdram(); - - if (!in_sdram) - omap3_core_init(); - - pcaal1_mux_config(); - /* Dont reconfigure SDRAM while running in SDRAM! */ - if (!in_sdram) - pcaal1_sdrc_init(); - - return 0; -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - omap3_save_bootinfo((void *)r0); - - arm_cpu_lowlevel_init(); - - pcaal1_board_init(); - - barebox_arm_entry(0x80000000, SZ_256M, NULL); -} diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c deleted file mode 100644 index d878dba082..0000000000 --- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.c +++ /dev/null @@ -1,164 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/** - * @file - * @brief Board Initialization routines for the phyCARD-A-L1 - * - * This board is based on OMAP3530. - * More on OMAP3530 (including documentation can be found here): - * http://focus.ti.com/docs/prod/folders/print/omap3530.html - * - * This file provides initialization in two stages: - * @li Boot time initialization - just get SDRAM working. - * This is run from SRAM - so no case constructs and global vars can be used. - * @li Run time initialization - this is for the rest of the initializations - * such as flash, uart etc. - * - * Boot time initialization includes: - * @li SDRAM initialization. - * @li Pin Muxing relevant for the EVM. - * - * Run time initialization includes - * @li serial @ref serial_ns16550.c driver device definition - * - * Originally from arch/arm/boards/omap/board-beagle.c - * - * Copyright (C) 2011 Phytec Messtechnik GmbH - http://www.phytec.de/ - * Juergen Kilb <j.kilb@phytec.de> - * - * based on code from Texas Instruments / board-beagle.c - * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ - * Sanjeev Premi <premi@ti.com> - */ - -#include <common.h> -#include <console.h> -#include <driver.h> -#include <errno.h> -#include <init.h> -#include <nand.h> -#include <linux/sizes.h> -#include <asm/armlinux.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <linux/err.h> -#include <mach/omap/gpmc.h> -#include <mach/omap/gpmc_nand.h> -#include <mach/omap/omap_hsmmc.h> -#include <mach/omap/sdrc.h> -#include <mach/omap/omap3-silicon.h> -#include <mach/omap/sys_info.h> -#include <mach/omap/omap3-devices.h> - -#define SMC911X_BASE 0x2c000000 - -/** - * @brief Initialize the serial port to be used as console. - * - * @return result of device registration - */ -static int pcaal1_init_console(void) -{ - barebox_set_model("Phytec phyCARD-OMAP3"); - barebox_set_hostname("phycard-omap3"); - - omap3_add_uart3(); - - return 0; -} -console_initcall(pcaal1_init_console); - -#ifdef CONFIG_DRIVER_NET_SMC911X -/** GPMC timing for our SMSC9221 device */ -static struct gpmc_config smsc_cfg = { - .cfg = { - 0x41001000, /*CONF1 */ - 0x00040500, /*CONF2 */ - 0x00000000, /*CONF3 */ - 0x04000500, /*CONF4 */ - 0x05050505, /*CONF5 */ - 0x000002c1, /*CONF6 */ - }, - .base = SMC911X_BASE, - /* GPMC address map as small as possible */ - .size = GPMC_SIZE_16M, -}; - -/* - * Routine: setup_net_chip - * Description: Setting up the configuration GPMC registers specific to the - * Ethernet hardware. - */ -static void pcaal1_setup_net_chip(void) -{ - gpmc_cs_config(5, &smsc_cfg); -} -#endif - -static int pcaal1_mem_init(void) -{ - -#ifdef CONFIG_OMAP_GPMC - /* - * WP is made high and WAIT1 active Low - */ - gpmc_generic_init(0x10); -#endif - omap3_add_sram0(); - - - omap_add_ram0(get_sdr_cs_size(SDRC_CS0_OSET)); - printf("found %s at SDCS0\n", size_human_readable(get_sdr_cs_size(SDRC_CS0_OSET))); - - if ((get_sdr_cs_size(SDRC_CS1_OSET) != 0) && (get_sdr_cs1_base() != OMAP_SDRC_CS0)) { - arm_add_mem_device("ram1", get_sdr_cs1_base(), get_sdr_cs_size(SDRC_CS1_OSET)); - printf("found %s at SDCS1\n", size_human_readable(get_sdr_cs_size(SDRC_CS1_OSET))); - } - - return 0; -} -mem_initcall(pcaal1_mem_init); - -struct omap_hsmmc_platform_data pcaal1_hsmmc_plat = { - .f_max = 26000000, -}; - -static struct gpmc_nand_platform_data nand_plat = { - .device_width = 16, - .ecc_mode = OMAP_ECC_BCH8_CODE_HW, - .nand_cfg = &omap3_nand_cfg, -}; - -static int pcaal1_init_devices(void) -{ - omap_add_gpmc_nand_device(&nand_plat); - - omap3_add_mmc1(&pcaal1_hsmmc_plat); - -#ifdef CONFIG_DRIVER_NET_SMC911X - pcaal1_setup_net_chip(); - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, SMC911X_BASE, SZ_4K, - IORESOURCE_MEM, NULL); -#endif - - armlinux_set_architecture(MACH_TYPE_PCAAL1); - - return 0; -} -device_initcall(pcaal1_init_devices); - -static int pcaal1_late_init(void) -{ -#ifdef CONFIG_PARTITION - devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "x-loader"); - dev_add_bb_dev("self_raw", "x_loader0"); - - devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - - devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); -#endif - return 0; -} -late_initcall(pcaal1_late_init); diff --git a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h b/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h deleted file mode 100644 index 7e7dadc587..0000000000 --- a/arch/arm/boards/phytec-phycard-omap3/pca-a-l1.h +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2008 Raghavendra KH <r-khandenahally@ti.com>, Texas Instruments (http://www.ti.com/) - -/** - * @file - * @brief exported generic APIs which various board files implement - * - * This file will not contain any board specific implementations. - */ - -#ifndef __BOARD_OMAP_H_ -#define __BOARD_OMAP_H_ - -/** Generic Board initialization called from platform.S */ -void board_init(void); - -#endif /* __BOARD_OMAP_H_ */ diff --git a/arch/arm/boards/phytec-phycard-omap4/Makefile b/arch/arm/boards/phytec-phycard-omap4/Makefile deleted file mode 100644 index 0ac095becc..0000000000 --- a/arch/arm/boards/phytec-phycard-omap4/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2012 Jan Weitzel <j.weitzel@phytec.de> - -obj-y += pca-a-xl2.o -lwl-y += mux.o lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-phytec-phycard-omap4 diff --git a/arch/arm/boards/phytec-phycard-omap4/defaultenv-phytec-phycard-omap4/bin/nand_bootstrap b/arch/arm/boards/phytec-phycard-omap4/defaultenv-phytec-phycard-omap4/bin/nand_bootstrap deleted file mode 100644 index f8873fabe2..0000000000 --- a/arch/arm/boards/phytec-phycard-omap4/defaultenv-phytec-phycard-omap4/bin/nand_bootstrap +++ /dev/null @@ -1,31 +0,0 @@ - -echo "copying barebox to nand..." - -mci0.probe=1 -mkdir mnt - -mount /dev/disk0.0 /mnt -if [ $? != 0 ]; then - echo "failed to mount mmc card" - exit 1 -fi - -if [ ! -f /mnt/mlo-nand.bin ]; then - echo "mlo-nand.bin not found on mmc card" - exit 1 -fi - -if [ ! -f /mnt/barebox.bin ]; then - echo "barebox.bin not found on mmc card" -fi - -gpmc_nand0.eccmode=bch8_hw_romcode -erase /dev/nand0.xload.bb -cp /mnt/mlo-nand.bin /dev/nand0.xload.bb - -gpmc_nand0.eccmode=bch8_hw -erase /dev/nand0.barebox.bb -cp /mnt/barebox.bin /dev/nand0.barebox.bb - -echo "success" - diff --git a/arch/arm/boards/phytec-phycard-omap4/defaultenv-phytec-phycard-omap4/config b/arch/arm/boards/phytec-phycard-omap4/defaultenv-phytec-phycard-omap4/config deleted file mode 100644 index 998f9fa0f2..0000000000 --- a/arch/arm/boards/phytec-phycard-omap4/defaultenv-phytec-phycard-omap4/config +++ /dev/null @@ -1,46 +0,0 @@ -#!/bin/sh - -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyO2,115200" - -nand_parts="128k(xload)ro,512k(barebox),128k(bareboxenv),4M(kernel),-(root)" -rootfs_mtdblock_nand=4 - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c b/arch/arm/boards/phytec-phycard-omap4/lowlevel.c deleted file mode 100644 index b5906234d3..0000000000 --- a/arch/arm/boards/phytec-phycard-omap4/lowlevel.c +++ /dev/null @@ -1,91 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) - -#include <common.h> -#include <init.h> -#include <io.h> -#include <linux/sizes.h> -#include <mach/omap/generic.h> -#include <mach/omap/omap4-mux.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-generic.h> -#include <mach/omap/omap4-clock.h> -#include <mach/omap/syslib.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> - -#include "mux.h" - -#define TPS62361_VSEL0_GPIO 7 - -static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { - .tim1 = 0x0EEB0662, - .tim2 = 0x20370DD2, - .tim3 = 0x00BFC33F, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80001AB1, - .config_final = 0x80001AB1, - .zq_config = 0xd0093215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -static noinline void pcaaxl2_init_lowlevel(void) -{ - struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; - struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; - struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; - struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; - struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; - struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; - unsigned int rev = omap4_revision(); - - phycard_omap4_set_muxconf_regs(); - - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); - - if (rev < OMAP4460_ES1_0) - omap4430_scale_vcores(); - else - omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320); - - writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); - - /* Configure all DPLL's at 100% OPP */ - if (rev < OMAP4460_ES1_0) - omap4_configure_mpu_dpll(&mpu44xx); - else - omap4_configure_mpu_dpll(&mpu4460); - - omap4_configure_iva_dpll(&iva); - omap4_configure_per_dpll(&per); - omap4_configure_abe_dpll(&abe); - omap4_configure_usb_dpll(&usb); - - /* Enable all clocks */ - omap4_enable_all_clocks(); - - sr32(0x4A30a31C, 8, 1, 0x1); /* enable software ioreq */ - sr32(0x4A30a31C, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */ - sr32(0x4A30a31C, 16, 4, 0x0); /* set divisor to 1 */ - sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */ - sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - omap4_save_bootinfo((void *)r0); - - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) - goto out; - - arm_setup_stack(0x4030d000); - - pcaaxl2_init_lowlevel(); -out: - barebox_arm_entry(0x80000000, SZ_512M, NULL); -} diff --git a/arch/arm/boards/phytec-phycard-omap4/mux.c b/arch/arm/boards/phytec-phycard-omap4/mux.c deleted file mode 100644 index a545ca5948..0000000000 --- a/arch/arm/boards/phytec-phycard-omap4/mux.c +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <init.h> -#include <io.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-mux.h> -#include <mach/omap/omap4-clock.h> - -#include "mux.h" - -static const struct pad_conf_entry core_padconf_array[] = { - {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ - {GPMC_AD1, (IEN | PTD | DIS | M0)}, /* gpmc_ad1 */ - {GPMC_AD2, (IEN | PTD | DIS | M0)}, /* gpmc_ad2 */ - {GPMC_AD3, (IEN | PTD | DIS | M0)}, /* gpmc_ad3 */ - {GPMC_AD4, (IEN | PTD | DIS | M0)}, /* gpmc_ad4 */ - {GPMC_AD5, (IEN | PTD | DIS | M0)}, /* gpmc_ad5 */ - {GPMC_AD6, (IEN | PTD | DIS | M0)}, /* gpmc_ad6 */ - {GPMC_AD7, (IEN | PTD | DIS | M0)}, /* gpmc_ad7 */ - {GPMC_AD8, (IEN | PTD | DIS | M0)}, /* gpmc_ad8 */ - {GPMC_AD9, (IEN | PTD | DIS | M0)}, /* gpmc_ad9 */ - {GPMC_AD10, (IEN | PTD | DIS | M0)}, /* gpmc_ad10 */ - {GPMC_AD11, (IEN | PTD | DIS | M0)}, /* gpmc_ad11 */ - {GPMC_AD12, (IEN | PTD | DIS | M0)}, /* gpmc_ad12 */ - {GPMC_AD13, (IEN | PTD | DIS | M0)}, /* gpmc_ad13 */ - {GPMC_AD14, (IEN | PTD | DIS | M0)}, /* gpmc_ad14 */ - {GPMC_AD15, (IEN | PTD | DIS | M0)}, /* gpmc_ad15 */ - {GPMC_A16, (IEN | PTD | DIS | M0)}, /* gpmc_a16 */ - {GPMC_A17, (SAFE_MODE)}, /* nc */ - {GPMC_A18, (SAFE_MODE)}, /* nc */ - {GPMC_A19, (SAFE_MODE)}, /* nc */ - {GPMC_A20, (SAFE_MODE)}, /* nc */ - {GPMC_A21, (SAFE_MODE)}, /* nc */ - {GPMC_A22, (SAFE_MODE)}, /* nc */ - {GPMC_A23, (SAFE_MODE)}, /* nc */ - {GPMC_A24, (SAFE_MODE)}, /* nc */ - {GPMC_A25, (SAFE_MODE)}, /* nc */ - {GPMC_NCS0, (IDIS | PTU | EN | M0)}, /* gpmc_nsc0 */ - {GPMC_NCS1, (IDIS | PTU | EN | M0)}, /* gpmc_nsc1 */ - {GPMC_NCS2, (SAFE_MODE)}, /* nc */ - {GPMC_NCS3, (SAFE_MODE)}, /* nc */ - {GPMC_NWP, (IEN | PTD | DIS | M0)}, /* gpmc_nwp */ - {GPMC_CLK, (PTU | IEN | M3)}, /* gpio_55 */ - {GPMC_NADV_ALE, (IDIS | PTD | DIS | M0)}, /* gpmc_ndav_ale */ - {GPMC_NOE, (IDIS | PTD | DIS | M0)}, /* gpmc_noe */ - {GPMC_NWE, (IDIS | PTD | DIS | M0)}, /* gpmc_nwe */ - {GPMC_NBE0_CLE, (IDIS | PTD | DIS | M0)}, /* gpmc_nbe0_cle */ - {GPMC_NBE1, (SAFE_MODE)}, /* nc */ - {GPMC_WAIT0, (IEN | PTU | EN | M0)}, /* gpmc_wait0 */ - {GPMC_WAIT1, (IEN | PTU | EN | M0)}, /* gpmc_wait1 */ - {C2C_DATA11, (SAFE_MODE)}, /* nc */ - {C2C_DATA12, (SAFE_MODE)}, /* nc */ - {C2C_DATA13, (IDIS | PTU | EN | M0)}, /* gpmc_nsc5 */ - {C2C_DATA14, (SAFE_MODE)}, /* nc */ - {C2C_DATA15, (SAFE_MODE)}, /* nc */ - {HDMI_HPD, (SAFE_MODE)}, /* nc */ - {HDMI_CEC, (SAFE_MODE)}, /* nc */ - {HDMI_DDC_SCL, (SAFE_MODE)}, /* nc */ - {HDMI_DDC_SDA, (SAFE_MODE)}, /* nc */ - {CSI21_DX0, (SAFE_MODE)}, /* nc */ - {CSI21_DY0, (SAFE_MODE)}, /* nc */ - {CSI21_DX1, (SAFE_MODE)}, /* nc */ - {CSI21_DY1, (SAFE_MODE)}, /* nc */ - {CSI21_DX2, (SAFE_MODE)}, /* nc */ - {CSI21_DY2, (SAFE_MODE)}, /* nc */ - {CSI21_DX3, (SAFE_MODE)}, /* nc */ - {CSI21_DY3, (SAFE_MODE)}, /* nc */ - {CSI21_DX4, (SAFE_MODE)}, /* nc */ - {CSI21_DY4, (SAFE_MODE)}, /* nc */ - {CSI22_DX0, (SAFE_MODE)}, /* nc */ - {CSI22_DY0, (SAFE_MODE)}, /* nc */ - {CSI22_DX1, (SAFE_MODE)}, /* nc */ - {CSI22_DY1, (SAFE_MODE)}, /* nc */ - {CAM_SHUTTER, (SAFE_MODE)}, /* unused */ - {CAM_STROBE, (SAFE_MODE)}, /* unused */ - {CAM_GLOBALRESET, (SAFE_MODE)}, /* unused */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (SAFE_MODE)}, /* nc */ - {USBB1_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {USBC1_ICUSB_DP, (SAFE_MODE)}, /* nc */ - {USBC1_ICUSB_DM, (SAFE_MODE)}, /* nc */ - {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ - {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ - {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ - {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ - {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ - {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (SAFE_MODE)}, /* nc */ - {SDMMC1_DAT5, (SAFE_MODE)}, /* nc */ - {SDMMC1_DAT6, (SAFE_MODE)}, /* nc */ - {SDMMC1_DAT7, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP2_CLKX, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP2_DR, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP2_DX, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP2_FSX, (SAFE_MODE)}, /* nc */ - {ABE_MCBSP1_CLKX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_DR, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_DX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_FSX, (SAFE_MODE)}, /* nc */ - {ABE_PDM_UL_DATA, (SAFE_MODE)}, /* unused */ - {ABE_PDM_DL_DATA, (SAFE_MODE)}, /* unused */ - {ABE_PDM_FRAME, (SAFE_MODE)}, /* unused */ - {ABE_PDM_LB_CLK, (SAFE_MODE)}, /* unused */ - {ABE_CLKS, (SAFE_MODE)}, /* unused */ - {ABE_DMIC_CLK1, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN1, (SAFE_MODE)}, /* unused */ - {ABE_DMIC_DIN2, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN3, (SAFE_MODE)}, /* unused */ - {UART2_CTS, (SAFE_MODE)}, /* nc */ - {UART2_RTS, (SAFE_MODE)}, /* nc */ - {UART2_RX, (SAFE_MODE)}, /* nc */ - {UART2_TX, (SAFE_MODE)}, /* nc */ - {HDQ_SIO, (SAFE_MODE)}, /* unused */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (SAFE_MODE)}, /* unused */ - {I2C2_SDA, (SAFE_MODE)}, /* unused */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (SAFE_MODE)}, /* nc */ - {I2C4_SDA, (SAFE_MODE)}, /* nc */ - {MCSPI1_CLK, (SAFE_MODE)}, /* unused */ - {MCSPI1_SOMI, (SAFE_MODE)}, /* unused */ - {MCSPI1_SIMO, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS0, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS1, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS2, (SAFE_MODE)}, /* nc */ - {MCSPI1_CS3, (SAFE_MODE)}, /* nc */ - {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ - {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ - {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ - {UART3_TX_IRTX, (M0)}, /* uart3_tx */ - {SDMMC5_CLK, (PTU | IEN | M3)}, /* goio_145 */ - {SDMMC5_CMD, (PTU | IEN | M3)}, /* goio_146 */ - {SDMMC5_DAT0, (SAFE_MODE)}, /* nc */ - {SDMMC5_DAT1, (SAFE_MODE)}, /* nc */ - {SDMMC5_DAT2, (SAFE_MODE)}, /* nc */ - {SDMMC5_DAT3, (SAFE_MODE)}, /* nc */ - {MCSPI4_CLK, (PTU | IEN | M3)}, /* gpio_151 */ - {MCSPI4_SIMO, (PTU | IEN | M3)}, /* gpio_152 */ - {MCSPI4_SOMI, (PTU | IEN | M3)}, /* gpio_153 */ - {MCSPI4_CS0, (SAFE_MODE)}, /* nc */ - {UART4_RX, (SAFE_MODE)}, /* nc */ - {UART4_TX, (SAFE_MODE)}, /* nc */ - {USBB2_ULPITLL_CLK, (SAFE_MODE)}, /* nc */ - {USBB2_ULPITLL_STP, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DIR, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_NXT, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT0, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT1, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT2, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT3, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT4, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT5, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT6, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_DAT7, (SAFE_MODE)}, /* unused */ - {USBB2_HSIC_DATA, (SAFE_MODE)}, /* unused */ - {USBB2_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX0, (SAFE_MODE)}, /* nc */ - {UNIPRO_TY0, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX1, (SAFE_MODE)}, /* nc */ - {UNIPRO_TY1, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX2, (SAFE_MODE)}, /* unused */ - {UNIPRO_TY2, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX0, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY0, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX1, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY1, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX2, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY2, (SAFE_MODE)}, /* unused */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (SAFE_MODE)}, /* nc */ - {FREF_CLK2_OUT, (SAFE_MODE)}, /* nc */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (SAFE_MODE)}, /* nc */ - {SYS_BOOT0, (M0)}, /* sys_boot */ - {SYS_BOOT1, (M0)}, /* sys_boot */ - {SYS_BOOT2, (M0)}, /* sys_boot */ - {SYS_BOOT3, (M0)}, /* sys_boot */ - {SYS_BOOT4, (M0)}, /* sys_boot */ - {SYS_BOOT5, (M0)}, /* sys_boot */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (SAFE_MODE)}, /* unused */ - {DPM_EMU3, (SAFE_MODE)}, /* unused */ - {DPM_EMU4, (SAFE_MODE)}, /* unused */ - {DPM_EMU5, (SAFE_MODE)}, /* unused */ - {DPM_EMU6, (SAFE_MODE)}, /* unused */ - {DPM_EMU7, (SAFE_MODE)}, /* unused */ - {DPM_EMU8, (SAFE_MODE)}, /* unused */ - {DPM_EMU9, (SAFE_MODE)}, /* unused */ - {DPM_EMU10, (SAFE_MODE)}, /* unused */ - {DPM_EMU11, (SAFE_MODE)}, /* unused */ - {DPM_EMU12, (SAFE_MODE)}, /* unused */ - {DPM_EMU13, (SAFE_MODE)}, /* unused */ - {DPM_EMU14, (SAFE_MODE)}, /* unused */ - {DPM_EMU15, (SAFE_MODE)}, /* unused */ - {DPM_EMU16, (SAFE_MODE)}, /* unused */ - {DPM_EMU17, (SAFE_MODE)}, /* unused */ - {DPM_EMU18, (SAFE_MODE)}, /* unused */ - {DPM_EMU19, (SAFE_MODE)}, /* unused */ -}; - -static const struct pad_conf_entry wkup_padconf_array[] = { - {GPIO_WK0, (SAFE_MODE)}, /* tbd */ - {GPIO_WK1, (SAFE_MODE)}, /* nc */ - {GPIO_WK2, (SAFE_MODE)}, /* nc */ - {GPIO_WK3, (SAFE_MODE)}, /* nc */ - {GPIO_WK4, (SAFE_MODE)}, /* nc */ - {SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ - {FREF_XTAL_IN, (M0)}, /* # */ - {FREF_SLICER_IN, (SAFE_MODE)}, /* nc */ - {FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */ - {FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {FREF_CLK3_REQ, (SAFE_MODE)}, /* nc */ - {FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {FREF_CLK4_REQ, (IEN | M3)}, /* gpio_wk7 */ - {FREF_CLK4_OUT, (M0)}, /* fref_clk4_out */ - {SYS_32K, (IEN | M0)}, /* sys_32k */ - {SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {SYS_PWRON_RESET_OUT, (M0)}, /* sys_pwron_reset_out */ - {SYS_BOOT6, (M0)}, /* sys_boot6 */ - {SYS_BOOT7, (M0)}, /* sys_boot7 */ -}; - -void phycard_omap4_set_muxconf_regs(void) -{ - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, - ARRAY_SIZE(core_padconf_array)); - - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, - ARRAY_SIZE(wkup_padconf_array)); - - /* gpio_wk7 is used for controlling TPS on 4460 */ - if (omap4_revision() >= OMAP4460_ES1_0) { - writew(M3, OMAP44XX_CONTROL_PADCONF_WKUP + FREF_CLK4_REQ); - /* Enable GPIO-1 clocks before TPS initialization */ - omap4_enable_gpio1_wup_clocks(); - } -} diff --git a/arch/arm/boards/phytec-phycard-omap4/mux.h b/arch/arm/boards/phytec-phycard-omap4/mux.h deleted file mode 100644 index 46a2434ad0..0000000000 --- a/arch/arm/boards/phytec-phycard-omap4/mux.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BOARD_MUX_H -#define __BOARD_MUX_H - -void phycard_omap4_set_muxconf_regs(void); - -#endif /* __BOARD_MUX_H */ diff --git a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c b/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c deleted file mode 100644 index f18f11c331..0000000000 --- a/arch/arm/boards/phytec-phycard-omap4/pca-a-xl2.c +++ /dev/null @@ -1,126 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2011 Sascha Hauer, Pengutronix - -#include <common.h> -#include <console.h> -#include <init.h> -#include <driver.h> -#include <io.h> -#include <gpio.h> -#include <asm/armlinux.h> -#include <asm/mach-types.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/sdrc.h> -#include <mach/omap/sys_info.h> -#include <mach/omap/syslib.h> -#include <mach/omap/control.h> -#include <linux/err.h> -#include <linux/sizes.h> -#include <nand.h> -#include <asm/mmu.h> -#include <mach/omap/gpmc.h> -#include <mach/omap/gpmc_nand.h> -#include <mach/omap/omap_hsmmc.h> -#include <mach/omap/omap4-devices.h> -#include <i2c/i2c.h> - -static int pcaaxl2_console_init(void) -{ - barebox_set_model("Phytec phyCARD-OMAP4"); - barebox_set_hostname("phycard-omap4"); - - omap44xx_add_uart3(); - - return 0; -} -console_initcall(pcaaxl2_console_init); - -static int pcaaxl2_mem_init(void) -{ - omap_add_ram0(SZ_512M); - - omap44xx_add_sram0(); - - return 0; -} -mem_initcall(pcaaxl2_mem_init); - -static struct gpmc_config net_cfg = { - .cfg = { - 0x00001000, /* CONF1 */ - 0x00080800, /* CONF2 */ - 0x00000000, /* CONF3 */ - 0x08000800, /* CONF4 */ - 0x000a0a0a, /* CONF5 */ - 0x000003c2, /* CONF6 */ - }, - .base = 0x2C000000, - .size = GPMC_SIZE_16M, -}; - -static void pcaaxl2_network_init(void) -{ - gpmc_cs_config(5, &net_cfg); - - add_ks8851_device(DEVICE_ID_DYNAMIC, net_cfg.base, net_cfg.base + 2, - IORESOURCE_MEM_16BIT, NULL); -} - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("twlcore", 0x48), - }, -}; - -static struct omap_hsmmc_platform_data mmc_device = { - .f_max = 26000000, -}; - -#define OMAP4_CONTROL_PBIASLITE 0x4A100600 -#define OMAP4_MMC1_PBIASLITE_VMODE (1<<21) -#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1<<22) -#define OMAP4_MMC1_PWRDNZ (1<<26) - -static struct gpmc_nand_platform_data nand_plat = { - .device_width = 16, - .ecc_mode = OMAP_ECC_BCH8_CODE_HW, - .nand_cfg = &omap4_nand_cfg, -}; - -static int pcaaxl2_devices_init(void) -{ - u32 value; - - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - omap44xx_add_i2c1(NULL); - - value = readl(OMAP4_CONTROL_PBIASLITE); - value &= ~OMAP4_MMC1_PBIASLITE_VMODE; - value |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ); - writel(value, OMAP4_CONTROL_PBIASLITE); - - omap44xx_add_mmc1(&mmc_device); - - gpmc_generic_init(0x10); - - pcaaxl2_network_init(); - - omap_add_gpmc_nand_device(&nand_plat); - -#ifdef CONFIG_PARTITION - devfs_add_partition("nand0", 0x00000, SZ_128K, - DEVFS_PARTITION_FIXED, "xload_raw"); - dev_add_bb_dev("xload_raw", "xload"); - devfs_add_partition("nand0", SZ_128K, SZ_512K, - DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, - DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); -#endif - - armlinux_set_architecture(MACH_TYPE_PCAAXL2); - - return 0; -} -device_initcall(pcaaxl2_devices_init); diff --git a/arch/arm/boards/phytec-phycore-omap4460/Makefile b/arch/arm/boards/phytec-phycore-omap4460/Makefile deleted file mode 100644 index c5d3950bc3..0000000000 --- a/arch/arm/boards/phytec-phycore-omap4460/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o mux.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-phytec-phycore-omap4460 diff --git a/arch/arm/boards/phytec-phycore-omap4460/board.c b/arch/arm/boards/phytec-phycore-omap4460/board.c deleted file mode 100644 index 2a176f156e..0000000000 --- a/arch/arm/boards/phytec-phycore-omap4460/board.c +++ /dev/null @@ -1,301 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2011 Sascha Hauer, Pengutronix - -#include <common.h> -#include <console.h> -#include <init.h> -#include <driver.h> -#include <gpio.h> -#include <io.h> -#include <envfs.h> -#include <asm/armlinux.h> -#include <asm/mach-types.h> -#include <mach/omap/devices.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-devices.h> -#include <mach/omap/omap4-clock.h> -#include <mach/omap/sdrc.h> -#include <mach/omap/sys_info.h> -#include <mach/omap/syslib.h> -#include <mach/omap/control.h> -#include <linux/err.h> -#include <linux/sizes.h> -#include <nand.h> -#include <asm/mmu.h> -#include <mach/omap/gpmc.h> -#include <mach/omap/gpmc_nand.h> -#include <i2c/i2c.h> - -static int pcm049_console_init(void) -{ - barebox_set_model("Phytec phyCORE-OMAP4460"); - barebox_set_hostname("phycore-omap4460"); - - omap44xx_add_uart3(); - - return 0; -} -console_initcall(pcm049_console_init); - -static int pcm049_mem_init(void) -{ -#ifdef CONFIG_1024MB_DDR2RAM - omap_add_ram0(SZ_1G); -#else - omap_add_ram0(SZ_512M); -#endif - - omap44xx_add_sram0(); - return 0; -} -mem_initcall(pcm049_mem_init); - -static struct gpmc_config net_cfg = { - .cfg = { - 0xc1001000, /* CONF1 */ - 0x00070700, /* CONF2 */ - 0x00000000, /* CONF3 */ - 0x07000700, /* CONF4 */ - 0x09060909, /* CONF5 */ - 0x000003c2, /* CONF6 */ - }, - .base = 0x2C000000, - .size = GPMC_SIZE_16M, -}; - -static void pcm049_network_init(void) -{ - gpmc_cs_config(5, &net_cfg); - - add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, 0x2C000000, 0x4000, - IORESOURCE_MEM, NULL); -} - -static struct i2c_board_info i2c_devices[] = { - { - I2C_BOARD_INFO("twl6030", 0x48), - }, -}; - -static struct gpmc_nand_platform_data nand_plat = { - .wait_mon_pin = 1, - .ecc_mode = OMAP_ECC_BCH8_CODE_HW, - .nand_cfg = &omap4_nand_cfg, -}; - -static struct omapfb_display const pcm049_displays[] = { - { - .mode = { - .name = "pd050vl1", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 25000, - .left_margin = 46, - .right_margin = 18, - .hsync_len = 96, - .upper_margin = 33, - .lower_margin = 10, - .vsync_len = 2, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* Prime-View PM070WL4 */ - { - .mode = { - .name = "pm070wl4", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 32000, - .left_margin = 86, - .right_margin = 42, - .hsync_len = 128, - .lower_margin = 10, - .upper_margin = 33, - .vsync_len = 2, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* Prime-View PD104SLF */ - { - .mode = { - .name = "pd104slf", - .refresh = 60, - .xres = 800, - .yres = 600, - .pixclock = 40000, - .left_margin = 86, - .right_margin = 42, - .hsync_len = 128, - .lower_margin = 1, - .upper_margin = 23, - .vsync_len = 4, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* EDT ETM0350G0DH6 */ - { - .mode = { - .name = "edt_etm0350G0dh6", - .refresh = 60, - .xres = 320, - .yres = 240, - .pixclock = 15720, - .left_margin = 68, - .right_margin = 20, - .hsync_len = 88, - .lower_margin = 4, - .upper_margin = 18, - .vsync_len = 22, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* EDT ETM0430G0DH6 */ - { - .mode = { - .name = "edt_etm0430G0dh6", - .refresh = 60, - .xres = 480, - .yres = 272, - .pixclock = 9000, - .left_margin = 2, - .right_margin = 2, - .hsync_len = 41, - .lower_margin = 2, - .upper_margin = 2, - .vsync_len = 10, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* EDT ETMV570G2DHU */ - { - .mode = { - .name = "edt_etmv570G2dhu", - .refresh = 60, - .xres = 640, - .yres = 480, - .pixclock = 25175, - .left_margin = 114, - .right_margin = 16, - .hsync_len = 30, - .lower_margin = 10, - .upper_margin = 35, - .vsync_len = 3, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - /* ETD ETM0700G0DH6 */ - { - .mode = { - .name = "edt_etm0700G0dh6", - .refresh = 60, - .xres = 800, - .yres = 480, - .pixclock = 33260, - .left_margin = 216, - .right_margin = 40, - .hsync_len = 128, - .lower_margin = 10, - .upper_margin = 35, - .vsync_len = 2, - }, - - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - }, - - /* CHIMEI G104X1-L03 */ - { - .mode = { - .name = "g104x1", - .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 64000, - .left_margin = 320, - .right_margin = 1, - .hsync_len = 320, - .upper_margin = 38, - .lower_margin = 38, - .vsync_len = 2, - }, - .config = (OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS | - OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IPC | - OMAP_DSS_LCD_DATALINES_24), - - .power_on_delay = 50, - .power_off_delay = 100, - }, -}; - -#define GPIO_DISPENABLE 118 -#define GPIO_BACKLIGHT 122 - -static void pcm049_fb_enable(int e) -{ - gpio_direction_output(GPIO_DISPENABLE, e); - gpio_direction_output(GPIO_BACKLIGHT, e); -} - -static struct omapfb_platform_data pcm049_fb_data = { - .displays = pcm049_displays, - .num_displays = ARRAY_SIZE(pcm049_displays), - - .dss_clk_hz = 19200000, - - .bpp = 32, - .enable = pcm049_fb_enable, -}; - -static int pcm049_devices_init(void) -{ - i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); - omap44xx_add_i2c1(NULL); - omap44xx_add_mmc1(NULL); - - gpmc_generic_init(0x10); - - if (IS_ENABLED(CONFIG_DRIVER_NET_SMC911X)) - pcm049_network_init(); - - omap_add_gpmc_nand_device(&nand_plat); - -#ifdef CONFIG_PARTITION - devfs_add_partition("nand0", 0x00000, SZ_128K, DEVFS_PARTITION_FIXED, "xload_raw"); - dev_add_bb_dev("xload_raw", "xload"); - devfs_add_partition("nand0", SZ_128K, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw"); - dev_add_bb_dev("self_raw", "self0"); - devfs_add_partition("nand0", SZ_128K + SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env_raw"); - dev_add_bb_dev("env_raw", "env0"); -#endif - - armlinux_set_architecture(MACH_TYPE_PCM049); - - omap_add_display(&pcm049_fb_data); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_phytec_phycore_omap4460); - - return 0; -} -device_initcall(pcm049_devices_init); diff --git a/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/bin/init_board b/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/bin/init_board deleted file mode 100644 index d5142ee8d0..0000000000 --- a/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/bin/init_board +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/sh -global displayargs -. /env/config - -if [ -z $display ]; then - echo "no display configured" - exit 0 -fi - -if [ $display = dvi ]; then - global.displayargs="omapdss.def_disp=dvi omapfb.mode=dvi:$dvi_resolution" - exit 0 -fi - -# Display a splash screen - -if [ -e /dev/fb0 ]; then - fb0.mode_name=$display - splash /dev/nand0.splash.bb - fb0.enable=1 -fi - -global.displayargs="panel_generic_dpi.name=$display" diff --git a/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/bin/nand_bootstrap b/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/bin/nand_bootstrap deleted file mode 100644 index 49e38dc4f0..0000000000 --- a/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/bin/nand_bootstrap +++ /dev/null @@ -1,31 +0,0 @@ -#!/bin/sh -echo "copying barebox to nand..." - -mci0.probe=1 -mkdir mnt - -mount /dev/disk0.0 /mnt -if [ $? != 0 ]; then - echo "failed to mount mmc card" - exit 1 -fi - -if [ ! -f /mnt/mlo-nand.bin ]; then - echo "mlo-nand.bin not found on mmc card" - exit 1 -fi - -if [ ! -f /mnt/barebox.bin ]; then - echo "barebox.bin not found on mmc card" -fi - -gpmc_nand0.eccmode=bch8_hw_romcode -erase /dev/nand0.xload.bb -cp /mnt/mlo-nand.bin /dev/nand0.xload.bb - -gpmc_nand0.eccmode=bch8_hw -erase /dev/nand0.barebox.bb -cp /mnt/barebox.bin /dev/nand0.barebox.bb - -echo "success" - diff --git a/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/config b/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/config deleted file mode 100644 index 1a252dd9c5..0000000000 --- a/arch/arm/boards/phytec-phycore-omap4460/defaultenv-phytec-phycore-omap4460/config +++ /dev/null @@ -1,61 +0,0 @@ -#!/bin/sh - -eth0.serverip= -user= - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=tftp -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root-${global.hostname}.$rootfs_type - -kernelimage=zImage-${global.hostname} -#kernelimage=uImage-${global.hostname} -#kernelimage=Image-${global.hostname} -#kernelimage=Image-${global.hostname}.lzo - -if [ -n $user ]; then - kernelimage="$user"-"$kernelimage" - nfsroot="$eth0.serverip:/home/$user/nfsroot/${global.hostname}" - rootfsimage="$user"-"$rootfsimage" -else - nfsroot="$eth0.serverip:/path/to/nfs/root" -fi - -autoboot_timeout=3 - -bootargs="console=ttyO2,115200" - -nand_parts="128k(xload)ro,512k(barebox),128k(bareboxenv),4M(kernel),4M(splash),-(root)" -nand_device="omap2-nand.0" -rootfs_mtdblock_nand=5 - -#Displays -# Splashscreen-Display can be either '', 'pd050vl1', 'pm070wl4', 'pd104slf', 'g104x1' -# 'edt_etm0350G0dh6', 'edt_etm0430G0dh6', 'edt_etmv570G2dhu' or 'edt_etm0700G0dh6' -# to use dvi output in kernel set 'display=dvi' and -# dvi_resolution to '640x480-60' '800x600-60' or '1024x768-60' - -display=edt_etm0700G0dh6 -#dvi_resolution=1024x768-60 - -if [ -n ${global.displayargs} ]; then - bootargs="$bootargs ${global.displayargs}" -fi - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " - diff --git a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c b/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c deleted file mode 100644 index 17194c6562..0000000000 --- a/arch/arm/boards/phytec-phycore-omap4460/lowlevel.c +++ /dev/null @@ -1,141 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: 2004-2009 Richard Woodruff <r-woodruff2@ti.com>, Texas Instruments (http://www.ti.com/) - -#include <common.h> -#include <init.h> -#include <io.h> -#include <linux/sizes.h> -#include <mach/omap/generic.h> -#include <mach/omap/omap4-mux.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-generic.h> -#include <mach/omap/omap4-clock.h> -#include <mach/omap/syslib.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> - -#include "mux.h" - -#define TPS62361_VSEL0_GPIO 182 -#define LPDDR2_2G 0x5 -#define LPDDR2_4G 0x6 -#define LPDDR2_DENSITY_MASK 0x3C -#define LPDDR2_DENSITY_SHIFT 2 -#define EMIF_SDRAM_CONFIG 0x0008 -#define EMIF_LPDDR2_MODE_REG_CONFIG 0x0050 -#define EMIF_LPDDR2_MODE_REG_DATA 0x0040 - -/* 512MB */ -static const struct ddr_regs ddr_regs_mt42L64M64_25_400_mhz = { - .tim1 = 0x0EEB0662, - .tim2 = 0x20370DD2, - .tim3 = 0x00BFC33F, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80001AB1, - .config_final = 0x80001AB1, - .zq_config = 0xd0093215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -/* 1GB */ -static const struct ddr_regs ddr_regs_mt42L128M64_25_400_mhz = { - .tim1 = 0x0EEB0663, - .tim2 = 0x205715D2, - .tim3 = 0x00BFC53F, - .phy_ctrl_1 = 0x849FF408, - .ref_ctrl = 0x00000618, - .config_init = 0x80001AB9, - .config_final = 0x80001AB9, - .zq_config = 0x50093215, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -static const struct ddr_regs ddr_regs_mt42L128M64D2LL_25_400_mhz = { - .tim1 = 0x10EB0662, - .tim2 = 0x205715D2, - .tim3 = 0x00B1C53F, - .phy_ctrl_1 = 0x849FF409, - .ref_ctrl = 0x00000618, - .config_init = 0x80001AB2, - .config_final = 0x80001AB2, - .zq_config = 0x500B3214, - .mr1 = 0x83, - .mr2 = 0x4 -}; - -static void noinline pcm049_init_lowlevel(void) -{ - unsigned int density; - - struct dpll_param core = OMAP4_CORE_DPLL_PARAM_19M2_DDR400; - struct dpll_param mpu44xx = OMAP4_MPU_DPLL_PARAM_19M2_MPU1000; - struct dpll_param mpu4460 = OMAP4_MPU_DPLL_PARAM_19M2_MPU920; - struct dpll_param iva = OMAP4_IVA_DPLL_PARAM_19M2; - struct dpll_param per = OMAP4_PER_DPLL_PARAM_19M2; - struct dpll_param abe = OMAP4_ABE_DPLL_PARAM_19M2; - struct dpll_param usb = OMAP4_USB_DPLL_PARAM_19M2; - unsigned int rev = omap4_revision(); - - phycore_omap4460_set_muxconf_regs(); - - if (IS_ENABLED(CONFIG_1024MB_DDR2RAM)) { - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); - writel(EMIF_SDRAM_CONFIG, OMAP44XX_EMIF1_BASE + - EMIF_LPDDR2_MODE_REG_CONFIG); - density = (readl(OMAP44XX_EMIF1_BASE + EMIF_LPDDR2_MODE_REG_DATA) & - LPDDR2_DENSITY_MASK) >> LPDDR2_DENSITY_SHIFT; - if (density == LPDDR2_2G) - omap4_ddr_init(&ddr_regs_mt42L128M64_25_400_mhz, &core); - else if (density == LPDDR2_4G) - omap4_ddr_init(&ddr_regs_mt42L128M64D2LL_25_400_mhz, &core); - } else { - omap4_ddr_init(&ddr_regs_mt42L64M64_25_400_mhz, &core); - } - - /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */ - if (rev < OMAP4460_ES1_0) - omap4430_scale_vcores(); - else - omap4460_scale_vcores(TPS62361_VSEL0_GPIO, 1320); - - writel(CM_SYS_CLKSEL_19M2, CM_SYS_CLKSEL); - - /* Configure all DPLL's at 100% OPP */ - if (rev < OMAP4460_ES1_0) - omap4_configure_mpu_dpll(&mpu44xx); - else - omap4_configure_mpu_dpll(&mpu4460); - - omap4_configure_iva_dpll(&iva); - omap4_configure_per_dpll(&per); - omap4_configure_abe_dpll(&abe); - omap4_configure_usb_dpll(&usb); - - /* Enable all clocks */ - omap4_enable_all_clocks(); - - sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1); /* enable software ioreq */ - sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0); /* set for sys_clk (19.2MHz) */ - sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x0); /* set divisor to 1 */ - sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1); /* activate clock source */ - sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */ -} - -void __bare_init __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - omap4_save_bootinfo((void *)r0); - - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) - goto out; - - arm_setup_stack(0x4030d000); - - pcm049_init_lowlevel(); -out: - barebox_arm_entry(0x80000000, SZ_512M, NULL); -} diff --git a/arch/arm/boards/phytec-phycore-omap4460/mux.c b/arch/arm/boards/phytec-phycore-omap4460/mux.c deleted file mode 100644 index 287c2a4826..0000000000 --- a/arch/arm/boards/phytec-phycore-omap4460/mux.c +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <init.h> -#include <io.h> -#include <mach/omap/omap4-silicon.h> -#include <mach/omap/omap4-mux.h> -#include <mach/omap/omap4-clock.h> - -#include "mux.h" - -static const struct pad_conf_entry core_padconf_array[] = { - {GPMC_AD0, (IEN | PTD | DIS | M0)}, /* gpmc_ad0 */ - {GPMC_AD1, (IEN | PTD | DIS | M0)}, /* gpmc_ad1 */ - {GPMC_AD2, (IEN | PTD | DIS | M0)}, /* gpmc_ad2 */ - {GPMC_AD3, (IEN | PTD | DIS | M0)}, /* gpmc_ad3 */ - {GPMC_AD4, (IEN | PTD | DIS | M0)}, /* gpmc_ad4 */ - {GPMC_AD5, (IEN | PTD | DIS | M0)}, /* gpmc_ad5 */ - {GPMC_AD6, (IEN | PTD | DIS | M0)}, /* gpmc_ad6 */ - {GPMC_AD7, (IEN | PTD | DIS | M0)}, /* gpmc_ad7 */ - {GPMC_AD8, (IEN | PTD | DIS | M0)}, /* gpmc_ad8 */ - {GPMC_AD9, (IEN | PTD | DIS | M0)}, /* gpmc_ad9 */ - {GPMC_AD10, (IEN | PTD | DIS | M0)}, /* gpmc_ad10 */ - {GPMC_AD11, (IEN | PTD | DIS | M0)}, /* gpmc_ad11 */ - {GPMC_AD12, (IEN | PTD | DIS | M0)}, /* gpmc_ad12 */ - {GPMC_AD13, (IEN | PTD | DIS | M0)}, /* gpmc_ad13 */ - {GPMC_AD14, (IEN | PTD | DIS | M0)}, /* gpmc_ad14 */ - {GPMC_AD15, (IEN | PTD | DIS | M0)}, /* gpmc_ad15 */ - {GPMC_A16, (IEN | PTD | DIS | M0)}, /* gpmc_a16 */ - {GPMC_A17, (IEN | PTD | DIS | M0)}, /* gpmc_a17 */ - {GPMC_A18, (IEN | PTD | DIS | M0)}, /* gpmc_a18 */ - {GPMC_A19, (IEN | PTD | DIS | M0)}, /* gpmc_a19 */ - {GPMC_A20, (IEN | PTD | DIS | M0)}, /* gpmc_a20 */ - {GPMC_A21, (IEN | PTD | DIS | M0)}, /* gpmc_a21 */ - {GPMC_A22, (IEN | PTD | DIS | M0)}, /* gpmc_a22 */ - {GPMC_A23, (IEN | PTD | DIS | M0)}, /* gpmc_a23 */ - {GPMC_A24, (IEN | PTD | DIS | M0)}, /* gpmc_a24 */ - {GPMC_A25, (IEN | PTD | DIS | M0)}, /* gpmc_a25 */ - {GPMC_NCS0, (IDIS | PTU | EN | M0)}, /* gpmc_nsc0 */ - {GPMC_NCS1, (IDIS | PTU | EN | M0)}, /* gpmc_nsc1 */ - {GPMC_NCS2, (SAFE_MODE)}, /* nc */ - {GPMC_NCS3, (SAFE_MODE)}, /* nc */ - {GPMC_NWP, (IEN | PTD | DIS | M0)}, /* gpmc_nwp */ - {GPMC_CLK, (SAFE_MODE)}, /* nc */ - {GPMC_NADV_ALE, (IDIS | PTD | DIS | M0)}, /* gpmc_ndav_ale */ - {GPMC_NOE, (IDIS | PTD | DIS | M0)}, /* gpmc_noe */ - {GPMC_NWE, (IDIS | PTD | DIS | M0)}, /* gpmc_nwe */ - {GPMC_NBE0_CLE, (IDIS | PTD | DIS | M0)}, /* gpmc_nbe0_cle */ - {GPMC_NBE1, (SAFE_MODE)}, /* nc */ - {GPMC_WAIT0, (IEN | PTU | EN | M0)}, /* gpmc_wait0 */ - {GPMC_WAIT1, (SAFE_MODE)}, /* nc */ - {C2C_DATA11, (SAFE_MODE)}, /* nc */ - {C2C_DATA12, (SAFE_MODE)}, /* nc */ - {C2C_DATA13, (IDIS | PTU | EN | M0)}, /* gpmc_nsc5 */ - {C2C_DATA14, (SAFE_MODE)}, /* nc */ - {C2C_DATA15, (SAFE_MODE)}, /* nc */ - {HDMI_HPD, (SAFE_MODE)}, /* unused */ - {HDMI_CEC, (SAFE_MODE)}, /* unused */ - {HDMI_DDC_SCL, (SAFE_MODE)}, /* unused */ - {HDMI_DDC_SDA, (SAFE_MODE)}, /* unused */ - {CSI21_DX0, (SAFE_MODE)}, /* unused */ - {CSI21_DY0, (SAFE_MODE)}, /* unused */ - {CSI21_DX1, (SAFE_MODE)}, /* unused */ - {CSI21_DY1, (SAFE_MODE)}, /* unused */ - {CSI21_DX2, (SAFE_MODE)}, /* unused */ - {CSI21_DY2, (SAFE_MODE)}, /* unused */ - {CSI21_DX3, (SAFE_MODE)}, /* unused */ - {CSI21_DY3, (SAFE_MODE)}, /* unused */ - {CSI21_DX4, (SAFE_MODE)}, /* unused */ - {CSI21_DY4, (SAFE_MODE)}, /* unused */ - {CSI22_DX0, (SAFE_MODE)}, /* unused */ - {CSI22_DY0, (SAFE_MODE)}, /* unused */ - {CSI22_DX1, (SAFE_MODE)}, /* unused */ - {CSI22_DY1, (SAFE_MODE)}, /* unused */ - {CAM_SHUTTER, (SAFE_MODE)}, /* unused */ - {CAM_STROBE, (SAFE_MODE)}, /* unused */ - {CAM_GLOBALRESET, (SAFE_MODE)}, /* unused */ - {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ - {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ - {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ - {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ - {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ - {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ - {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ - {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ - {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ - {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ - {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ - {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ - {USBB1_HSIC_DATA, (SAFE_MODE)}, /* nc */ - {USBB1_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {USBC1_ICUSB_DP, (SAFE_MODE)}, /* unused */ - {USBC1_ICUSB_DM, (SAFE_MODE)}, /* unused */ - {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ - {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ - {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ - {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ - {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ - {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ - {SDMMC1_DAT4, (SAFE_MODE)}, /* unused */ - {SDMMC1_DAT5, (SAFE_MODE)}, /* unused */ - {SDMMC1_DAT6, (SAFE_MODE)}, /* unused */ - {SDMMC1_DAT7, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP2_CLKX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP2_DR, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP2_DX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP2_FSX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_CLKX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_DR, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_DX, (SAFE_MODE)}, /* unused */ - {ABE_MCBSP1_FSX, (SAFE_MODE)}, /* unused */ - {ABE_PDM_UL_DATA, (SAFE_MODE)}, /* unused */ - {ABE_PDM_DL_DATA, (SAFE_MODE)}, /* unused */ - {ABE_PDM_FRAME, (SAFE_MODE)}, /* unused */ - {ABE_PDM_LB_CLK, (SAFE_MODE)}, /* unused */ - {ABE_CLKS, (M3)}, /* gpio_118 */ - {ABE_DMIC_CLK1, (SAFE_MODE)}, /* nc */ - {ABE_DMIC_DIN1, (SAFE_MODE)}, /* unused */ - {ABE_DMIC_DIN2, (DIS | IEN | M3)}, /* gpio_121 */ - {ABE_DMIC_DIN3, (M3)}, /* gpio_122 */ - {UART2_CTS, (SAFE_MODE)}, /* unused */ - {UART2_RTS, (SAFE_MODE)}, /* unused */ - {UART2_RX, (SAFE_MODE)}, /* unused */ - {UART2_TX, (SAFE_MODE)}, /* unused */ - {HDQ_SIO, (SAFE_MODE)}, /* unused */ - {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ - {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ - {I2C2_SCL, (SAFE_MODE)}, /* unused */ - {I2C2_SDA, (SAFE_MODE)}, /* unused */ - {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ - {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ - {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ - {I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ - {MCSPI1_CLK, (SAFE_MODE)}, /* unused */ - {MCSPI1_SOMI, (SAFE_MODE)}, /* unused */ - {MCSPI1_SIMO, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS0, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS1, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS2, (SAFE_MODE)}, /* unused */ - {MCSPI1_CS3, (SAFE_MODE)}, /* unused */ - {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ - {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ - {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ - {UART3_TX_IRTX, (M0)}, /* uart3_tx */ - {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ - {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ - {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ - {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ - {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ - {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ - {MCSPI4_CLK, (SAFE_MODE)}, /* nc */ - {MCSPI4_SIMO, (PTU | IEN | M3)}, /* gpio_152 */ - {MCSPI4_SOMI, (PTU | IEN | M3)}, /* gpio_153 */ - {MCSPI4_CS0, (SAFE_MODE)}, /* nc */ - {UART4_RX, (SAFE_MODE)}, /* unused */ - {UART4_TX, (SAFE_MODE)}, /* unused */ - {USBB2_ULPITLL_CLK, (SAFE_MODE)}, /* nc */ - {USBB2_ULPITLL_STP, (M5)}, /* dispc2_data23 */ - {USBB2_ULPITLL_DIR, (M5)}, /* dispc2_data22 */ - {USBB2_ULPITLL_NXT, (M5)}, /* dispc2_data21 */ - {USBB2_ULPITLL_DAT0, (M5)}, /* dispc2_data20 */ - {USBB2_ULPITLL_DAT1, (M5)}, /* dispc2_data19 */ - {USBB2_ULPITLL_DAT2, (M5)}, /* dispc2_data18 */ - {USBB2_ULPITLL_DAT3, (M5)}, /* dispc2_data15 */ - {USBB2_ULPITLL_DAT4, (M5)}, /* dispc2_data14 */ - {USBB2_ULPITLL_DAT5, (M5)}, /* dispc2_data13 */ - {USBB2_ULPITLL_DAT6, (M5)}, /* dispc2_data12 */ - {USBB2_ULPITLL_DAT7, (M5)}, /* dispc2_data11 */ - {USBB2_HSIC_DATA, (SAFE_MODE)}, /* nc */ - {USBB2_HSIC_STROBE, (SAFE_MODE)}, /* nc */ - {UNIPRO_TX0, (SAFE_MODE)}, /* unused */ - {UNIPRO_TY0, (SAFE_MODE)}, /* unused */ - {UNIPRO_TX1, (SAFE_MODE)}, /* unused */ - {UNIPRO_TY1, (SAFE_MODE)}, /* unused */ - {UNIPRO_TX2, (SAFE_MODE)}, /* unused */ - {UNIPRO_TY2, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX0, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY0, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX1, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY1, (SAFE_MODE)}, /* unused */ - {UNIPRO_RX2, (SAFE_MODE)}, /* unused */ - {UNIPRO_RY2, (SAFE_MODE)}, /* unused */ - {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ - {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ - {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ - {FREF_CLK1_OUT, (SAFE_MODE)}, /* nc */ - {FREF_CLK2_OUT, (SAFE_MODE)}, /* nc */ - {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ - {SYS_NIRQ2, (M0)}, /* sys_boot0 */ - {SYS_BOOT0, (M0)}, /* sys_boot */ - {SYS_BOOT1, (M0)}, /* sys_boot */ - {SYS_BOOT2, (M0)}, /* sys_boot */ - {SYS_BOOT3, (M0)}, /* sys_boot */ - {SYS_BOOT4, (M0)}, /* sys_boot */ - {SYS_BOOT5, (M0)}, /* sys_boot */ - {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ - {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ - {DPM_EMU2, (SAFE_MODE)}, /* unused */ - {DPM_EMU3, (M5)}, /* dispc2_data10 */ - {DPM_EMU4, (M5)}, /* dispc2_data9 */ - {DPM_EMU5, (M5)}, /* dispc2_data16 */ - {DPM_EMU6, (M5)}, /* dispc2_data17 */ - {DPM_EMU7, (M5)}, /* dispc2_hsync */ - {DPM_EMU8, (M5)}, /* dispc2_pclk */ - {DPM_EMU9, (M5)}, /* dispc2_vsync */ - {DPM_EMU10, (M5)}, /* dispc2_de */ - {DPM_EMU11, (M5)}, /* dispc2_data8 */ - {DPM_EMU12, (M5)}, /* dispc2_data7 */ - {DPM_EMU13, (M5)}, /* dispc2_data6 */ - {DPM_EMU14, (M5)}, /* dispc2_data5 */ - {DPM_EMU15, (M5)}, /* dispc2_data4 */ - {DPM_EMU16, (M5)}, /* dispc2_data3 */ - {DPM_EMU17, (M5)}, /* dispc2_data2 */ - {DPM_EMU18, (M5)}, /* dispc2_data1 */ - {DPM_EMU19, (M5)}, /* dispc2_data0 */ -}; - -static const struct pad_conf_entry wkup_padconf_array[] = { - {GPIO_WK0, (SAFE_MODE)}, /* nc */ - {GPIO_WK1, (SAFE_MODE)}, /* nc */ - {GPIO_WK2, (SAFE_MODE)}, /* nc */ - {GPIO_WK3, (SAFE_MODE)}, /* nc */ - {GPIO_WK4, (SAFE_MODE)}, /* nc */ - {SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ - {SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ - {FREF_XTAL_IN, (M0)}, /* # */ - {FREF_SLICER_IN, (SAFE_MODE)}, /* nc */ - {FREF_CLK_IOREQ, (SAFE_MODE)}, /* nc */ - {FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ - {FREF_CLK3_REQ, (IEN | M3)}, /* gpio_wk30 */ - {FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ - {FREF_CLK4_REQ, (M0)}, /* fref_clk4_req */ - {FREF_CLK4_OUT, (M0)}, /* fref_clk4_out */ - {SYS_32K, (IEN | M0)}, /* sys_32k */ - {SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ - {SYS_NRESWARM, (M0)}, /* sys_nreswarm */ - {SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ - {SYS_PWRON_RESET_OUT, (M0)}, /* sys_pwron_reset_out */ - {SYS_BOOT6, (M0)}, /* sys_boot6 */ - {SYS_BOOT7, (M0)}, /* sys_boot7 */ -}; - -void phycore_omap4460_set_muxconf_regs(void) -{ - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_CORE, core_padconf_array, - ARRAY_SIZE(core_padconf_array)); - - omap4_do_set_mux(OMAP44XX_CONTROL_PADCONF_WKUP, wkup_padconf_array, - ARRAY_SIZE(wkup_padconf_array)); - - /* gpio_182 is used for controlling TPS on 4460 */ - if (omap4_revision() >= OMAP4460_ES1_0) { - writew(M3, OMAP44XX_CONTROL_PADCONF_CORE + FREF_CLK2_OUT); - /* Enable GPIO-1 clocks before TPS initialization */ - omap4_enable_gpio_clocks(); - } -} diff --git a/arch/arm/boards/phytec-phycore-omap4460/mux.h b/arch/arm/boards/phytec-phycore-omap4460/mux.h deleted file mode 100644 index c84ecd32c8..0000000000 --- a/arch/arm/boards/phytec-phycore-omap4460/mux.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BOARD_MUX_H -#define __BOARD_MUX_H - -void phycore_omap4460_set_muxconf_regs(void); - -#endif /* __BOARD_MUX_H */ diff --git a/arch/arm/boards/phytec-phycore-pxa270/Makefile b/arch/arm/boards/phytec-phycore-pxa270/Makefile deleted file mode 100644 index e00d1cfd7f..0000000000 --- a/arch/arm/boards/phytec-phycore-pxa270/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel_init.o diff --git a/arch/arm/boards/phytec-phycore-pxa270/board.c b/arch/arm/boards/phytec-phycore-pxa270/board.c deleted file mode 100644 index 0283659a4e..0000000000 --- a/arch/arm/boards/phytec-phycore-pxa270/board.c +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2009 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix -// SPDX-FileCopyrightText: 2010 Marc Kleine-Budde <kernel@pengutronix.de> - -#include <common.h> -#include <driver.h> -#include <environment.h> -#include <fs.h> -#include <init.h> -#include <linux/sizes.h> - -#include <gpio.h> -#include <mach/pxa/mfp-pxa27x.h> -#include <mach/pxa/pxa-regs.h> -#include <mach/pxa/pxafb.h> -#include <mach/pxa/devices.h> - -#include <asm/armlinux.h> -#include <asm/io.h> -#include <asm/mach-types.h> -#include <asm/mmu.h> - -#define PCM990_CTRL_PHYS (void *)PXA_CS1_PHYS - -#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */ -#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */ -#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */ -#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */ -#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */ - -static void lcd_power(int on) -{ - void __iomem *ctrl3 = PCM990_CTRL_PHYS + PCM990_CTRL_REG3; - - if (on) - writeb(PCM990_CTRL_LCDPWR | PCM990_CTRL_LCDON, ctrl3); - else - writeb(0x0, ctrl3); -} - -static void backlight_power(int on) -{ - if (on) { - mdelay(20); - gpio_set_value(16, 1); - } else { - gpio_set_value(16, 0); - } -} - -static struct pxafb_videomode pxafb_mode = { - .mode = { - .pixclock = 28000, - .xres = 640, - .yres = 480, - .hsync_len = 20, - .left_margin = 103, - .right_margin = 47, - .vsync_len = 6, - .upper_margin = 28, - .lower_margin = 5, - .sync = 0, - }, - .bpp = 16, -}; - -static struct pxafb_platform_data fb_pdata = { - .mode = &pxafb_mode, - .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, - .lcd_power = lcd_power, - .backlight_power = backlight_power, -}; - -static int pcm027_mem_init(void) -{ - arm_add_mem_device("ram0", 0xa0000000, SZ_64M); - - return 0; -} -mem_initcall(pcm027_mem_init); - -static unsigned long pin_config[] = { - /* Chip Selects */ - GPIO20_nSDCS_2, - GPIO21_nSDCS_3, - GPIO15_nCS_1, - GPIO78_nCS_2, - GPIO80_nCS_4, - - /* Variable Latency I/O Ready Pin */ - GPIO18_RDY, - - /* FFUART */ - GPIO85_nPCE_1, /* enables RX */ - GPIO34_FFUART_RXD, - GPIO35_FFUART_CTS, - GPIO36_FFUART_DCD, - GPIO37_FFUART_DSR, - GPIO38_FFUART_RI, - GPIO39_FFUART_TXD, - GPIO40_FFUART_DTR, - GPIO41_FFUART_RTS, - - /* LCD */ - GPIO58_LCD_LDD_0, - GPIO59_LCD_LDD_1, - GPIO60_LCD_LDD_2, - GPIO61_LCD_LDD_3, - GPIO62_LCD_LDD_4, - GPIO63_LCD_LDD_5, - GPIO64_LCD_LDD_6, - GPIO65_LCD_LDD_7, - GPIO66_LCD_LDD_8, - GPIO67_LCD_LDD_9, - GPIO68_LCD_LDD_10, - GPIO69_LCD_LDD_11, - GPIO70_LCD_LDD_12, - GPIO71_LCD_LDD_13, - GPIO72_LCD_LDD_14, - GPIO73_LCD_LDD_15, - GPIO74_LCD_FCLK, - GPIO75_LCD_LCLK, - GPIO76_LCD_PCLK, - GPIO77_LCD_BIAS, - MFP_CFG_OUT(GPIO16, AF0, DRIVE_LOW), /* backlight */ - - /* NIC */ - GPIO33_nCS_5, - GPIO49_nPWE, -}; - -static int pcm027_devices_init(void) -{ - void *cfi_iospace; - - add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, 0x14000300, 16, - IORESOURCE_MEM, NULL); - - cfi_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_32M); - add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_iospace, SZ_32M, 0); - - pxa_add_fb((void *)0x44000000, &fb_pdata); - - armlinux_set_architecture(MACH_TYPE_PCM027); - - devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); - devfs_add_partition("nor0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env0"); - protect_file("/dev/env0", 1); - - return 0; -} - -device_initcall(pcm027_devices_init); - -static int pcm027_console_init(void) -{ - /* route pins */ - pxa2xx_mfp_config(ARRAY_AND_SIZE(pin_config)); - - /* enable clock */ - CKEN |= CKEN_FFUART; - - barebox_set_model("Phytec phyCORE-PXA270"); - barebox_set_hostname("pcm027"); - - pxa_add_uart((void *)0x40100000, 0); - - return 0; -} - -console_initcall(pcm027_console_init); diff --git a/arch/arm/boards/phytec-phycore-pxa270/config.h b/arch/arm/boards/phytec-phycore-pxa270/config.h deleted file mode 100644 index 6aba53edea..0000000000 --- a/arch/arm/boards/phytec-phycore-pxa270/config.h +++ /dev/null @@ -1,314 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -/* - * Copyright (C) 2005 Phytec Messtechnik GmbH - * Juergen Kilb, H. Klaholz <armlinux@phytec.de> - * - * Copyright (C) 2006 Pengutronix - * Sascha Hauer <s.hauer@pengutronix.de> - * Robert Schwebel <r.schwebel@pengutronix.de> - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * phyCORE-PXA270 configuration settings - * Set these to 0/1 to enable or disable the features. - */ - -#define PHYCORE_PXA270_USE_K3FLASH 0 - -/* 260 MHz or 520 MHZ */ -#define PHYCORE_PXA270_SPEED 520 - -/********************************************************************* - * CONFIG PXA270 GPIO settings * - *********************************************************************/ - -/* - * GPIO set "1" - * - *** REG GPSR0 - * GP15 == nCS1 is 1 - * GP20 == nSDCS2 is 1 - * GP21 == nSDCS3 is 1 - *** REG GPSR1 - * GP33 == nCS5 is 1 - *** REG GPSR2 - * GP78 == nCS2 is 1 - * GP80 == nCS4 is 1 - */ -#define GPSR0_DFT 0x00308000 -#define GPSR1_DFT 0x00000002 -#define GPSR2_DFT 0x00014000 - -#define CONFIG_GPSR0_VAL GPSR0_DFT -#define CONFIG_GPSR1_VAL GPSR1_DFT -#define CONFIG_GPSR2_VAL GPSR2_DFT -#define CONFIG_GPSR3_VAL GPSR3_DFT - -/* - * set Direction "1" GPIO == output else input - * - ** REG GPDR0 - * GP03 == PWR_SDA is output - * GP04 == PWR_SCL is output - * GP15 == nCS1 is output - * GP20 == nSDCS2 is output - * GP21 == nSDCS3 is output - ** REG GPDR1 - * GP33 == nCS5 is output - ** REG GPDR2 - * GP78 == nCS2 is output - * GP80 == nCS4 is output - * GP90 == LED0 is output - * GP91 == LED1 is output - */ - -#define GPDR0_DFT 0x00308018 -#define GPDR1_DFT 0x00000002 -#define GPDR2_DFT 0x00014000 - -#define CONFIG_GPDR0_VAL GPDR0_DFT -#define CONFIG_GPDR1_VAL GPDR1_DFT -#define CONFIG_GPDR2_VAL GPDR2_DFT - -/* - * set Alternate Funktions - * - ** REG GAFR0_L - * GP15 == nCS1 is AF10 - ** REG GAFR0_U - * GP18 == RDY is AF01 - * GP20 == nSDCS2 is AF01 - * GP21 == nSDCS3 is AF01 - ** REG GAFR1_L - * GP33 == nCS5 is AF10 - ** REG GAFR2_L - * GP78 == nCS2 is AF10 - ** REG GAFR2_U - * GP80 == nCS4 is AF10 - */ - -#define GAFR0_L_DFT 0x80000000 -#define GAFR0_U_DFT 0x00000510 -#define GAFR1_L_DFT 0x00000008 -#define GAFR1_U_DFT 0x00000000 -#define GAFR2_L_DFT 0x20000000 -#define GAFR2_U_DFT 0x00000002 - -#define CONFIG_GAFR0_L_VAL GAFR0_L_DFT -#define CONFIG_GAFR0_U_VAL GAFR0_U_DFT -#define CONFIG_GAFR1_L_VAL GAFR1_L_DFT -#define CONFIG_GAFR1_U_VAL GAFR1_U_DFT -#define CONFIG_GAFR2_L_VAL GAFR2_L_DFT -#define CONFIG_GAFR2_U_VAL GAFR2_U_DFT - - -/* - * Power Manager Sleep Status Register (PSSR) - * - * [6] = 0 OTG pad is not holding it's state - * [5] = 1 Read Disable Hold: receivers of all gpio pins are disabled - * [4] = 1 gpio pins are held in their sleep mode state - * [3] = 0 The processor has not been placed in standby mode by - * configuring the PWRMODE register since STS was cleared - * by a reset or by software. - * [2] = 1 nVDD_FAULT has been asserted and caused the processor to - * enter deep-sleep mode. - * [1] = 1 nBATT_FAULT has been asserted and caused the processor to - * enter deep-sleep mode. - * [0] = 1 The processor was placed in sleep mode by configuring the - * PWRMODE register. - */ - -#define CONFIG_PSSR_VAL 0x37 - - -/********************************************************************* - * CONFIG PXA270 Chipselect settings * - *********************************************************************/ - -/* - * Memory settings - * - * This is the configuration for nCS1/0 -> PLD / flash - * configuration for nCS1: - * [31] 0 - Slower Device - * [30:28] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [19] 1 - 16 Bit bus width - * [18:16] 011 - burst RAM or FLASH - * configuration for nCS0 (J3 Flash): - * [15] 0 - Slower Device - * [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [03] 0 - 32 Bit bus width - * [02:00] 011 - burst RAM or FLASH - */ -#if PHYCORE_PXA270_USE_K3FLASH == 0 -#define CONFIG_MSC0_VAL 0x128C1262 -#else -/* configuration for nCS0 (K3 Flash): - * [15] 0 - Slower Device - * [14:12] 001 - CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [11:08] 0010 - Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns - * [03] 0 - 32 Bit bus width - * [02:00] 011 - burst RAM or FLASH - */ -#define CONFIG_MSC0_VAL 0x128C12B3 -#endif - -/* - * This is the configuration for nCS3/2 - * configuration for nCS3: POWER - * - * [31] 0 - Slower Device - * [30:28] 111 - RRR3: CS deselect to CS time: 7*(2*MemClk) = 140 ns - * [27:24] 1111 - RDN3: Address to data valid in bursts: (15+1)*MemClk = 160 ns - * [23:20] 1111 - RDF3: Address for first access: (23+1)*MemClk = 240 ns - * [19] 0 - 32 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS2: PLD - * [15] 0 - Slower Device - * [14:12] 111 - RRR2: CS deselect to CS time: 7*(2*MemClk) = 140 ns - * [11:08] 1111 - RDN2: Address to data valid in bursts: (15+1)*MemClk = 160 ns - * [07:04] 1111 - RDF2: Address for first access: (23+1)*MemClk = 240 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CONFIG_MSC1_VAL 0x128c128c - -/* - * This is the configuration for nCS5/4 - * - * configuration for nCS5: LAN Controller - * [31] 0 - Slower Device - * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns - * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns - * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns - * [19] 0 - 32 Bit bus width - * [18:16] 100 - variable latency I/O - * configuration for nCS4: USB - * [15] 0 - Slower Device - * [14:12] 111 - RRR4: CS deselect to CS time: 7*(2*MemClk) = 140 ns - * [11:08] 1111 - RDN4: Address to data valid in bursts: (15+1)*MemClk = 160 ns - * [07:04] 1111 - RDF4: Address for first access: (23+1)*MemClk = 240 ns - * [03] 1 - 16 Bit bus width - * [02:00] 100 - variable latency I/O - */ -#define CONFIG_MSC2_VAL 0x1234128C - -/********************************************************************* - * CONFIG PXA270 SDRAM settings * - *********************************************************************/ - -#define CONFIG_DRAM_BASE 0xa0000000 - - -/* MDCNFG: SDRAM Configuration Register - * - * [31] 0 - Stack1 - * [30] 0 - dcacx2 - * [20] 0 - reserved - * [31:29] 000 - reserved - * [28] 1 - SA1111 compatiblity mode - * [27] 1 - latch return data with return clock - * [26] 0 - alternate addressing for pair 2/3 - * [25:24] 10 - timings - * [23] 1 - internal banks in lower partition 2/3 (not used) - * [22:21] 10 - row address bits for partition 2/3 (not used) - * [20:19] 01 - column address bits for partition 2/3 (not used) - * [18] 0 - SDRAM partition 2/3 width is 32 bit - * [17] 0 - SDRAM partition 3 disabled - * [16] 0 - SDRAM partition 2 disabled - * [15] 0 - Stack1 - * [14] 0 - dcacx0 - * [13] 0 - Stack0 - * [12] 0 - SA1110 compatiblity mode - * [11] 1 - always 1 - * [10] 0 - no alternate addressing for pair 0/1 - * [09:08] 10 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk - * [7] 1 - 4 internal banks in lower partition pair - * [06:05] 10 - 13 row address bits for partition 0/1 - * [04:03] 01 - 9 column address bits for partition 0/1 - * [02] 0 - SDRAM partition 0/1 width is 32 bit - * [01] 0 - disable SDRAM partition 1 - * [00] 1 - enable SDRAM partition 0 - */ - -/* K4S561633*/ -#define CONFIG_MDCNFG_VAL 0x0AC90AC9 - -/* MDREFR: SDRAM Refresh Control Register - * - * [31] 0 - ALTREFA - * [30] 0 - ALTREFB - * [29] 1 - K0DB4 - * [28] 0 - reserved - * [27] 0 - reserved - * [26] 0 - reserved - * [25] 1 - K2FREE: not free running - * [24] 0 - K1FREE: not free running - * [23] 1 - K0FREE: not free running - * [22] 0 - SLFRSH: self refresh disabled - * [21] 0 - reserved - * [20] 0 - APD: no auto power down - * [19] 0 - K2DB2: SDCLK2 is MemClk - * [18] 0 - K2RUN: disable SDCLK2 - * [17] 0 - K1DB2: SDCLK1 is MemClk - * [16] 1 - K1RUN: enable SDCLK1 - * [15] 1 - E1PIN: SDRAM clock enable - * [14] 1 - K0DB2: SDCLK0 is MemClk - * [13] 0 - K0RUN: disable SDCLK0 - * [12] 0 - RESERVED - * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 - */ -#define CONFIG_MDREFR_VAL 0x2281C018 - -/* MDMRS: Mode Register Set Configuration Register - * - * [31] 0 - reserved - * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) - * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) - * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) - * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) - * [15] 0 - reserved - * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. - * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. - * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. - * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. - */ -#define CONFIG_MDMRS_VAL 0x00020022 - -/********************************************************************* - * CONFIG PXA270 Clock generation * - *********************************************************************/ -#define CONFIG_FLYCNFG_VAL 0x00010001 -#define CONFIG_SXCNFG_VAL 0x40044004 -#define CONFIG_CKEN (CKEN_MEMC | CKEN_OSTIMER) - -#if PHYCORE_PXA270_SPEED == 520 -#define CONFIG_CCCR 0x00000290 /* Memory Clock is f. Table; N=2.5, L=16 => 16x13=208, 208x2,5=520 MHz */ -#elif PHYCORE_PXA270_SPEED == 260 -#define CONFIG_CCCR 0x02000288 /* Memory Clock is System-Bus Freq., N=2.5, L=8 => 8x13=104, 104x2,5=260 MHz */ -#else -#error You have specified an illegal speed. -#endif - -/********************************************************************* - * CONFIG PXA270 CF interface * - *********************************************************************/ -#define CONFIG_MECR_VAL 0x00000003 -#define CONFIG_MCMEM0_VAL 0x00010504 -#define CONFIG_MCMEM1_VAL 0x00010504 -#define CONFIG_MCATT0_VAL 0x00010504 -#define CONFIG_MCATT1_VAL 0x00010504 -#define CONFIG_MCIO0_VAL 0x00004715 -#define CONFIG_MCIO1_VAL 0x00004715 - -#endif /* __CONFIG_H */ diff --git a/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor b/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor deleted file mode 100644 index 4423943211..0000000000 --- a/arch/arm/boards/phytec-phycore-pxa270/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="512k(nor0.barebox),256k(nor0.bareboxenv),4M(nor0.kernel),-(nor0.root)" -kernelname="physmap-flash.0" - -mtdparts-add -d nor0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/phytec-phycore-pxa270/env/nv/linux.bootargs.console b/arch/arm/boards/phytec-phycore-pxa270/env/nv/linux.bootargs.console deleted file mode 100644 index 476b1fbe49..0000000000 --- a/arch/arm/boards/phytec-phycore-pxa270/env/nv/linux.bootargs.console +++ /dev/null @@ -1 +0,0 @@ -console=ttyS0,115200 diff --git a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S b/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S deleted file mode 100644 index f8f1a037e0..0000000000 --- a/arch/arm/boards/phytec-phycore-pxa270/lowlevel_init.S +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later - -/* - * This was originally from the Lubbock u-boot port. - * - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. - */ - -#include <config.h> -#include <linux/sizes.h> -#include <mach/pxa/pxa-regs.h> -#include <mach/pxa/regs-ost.h> -#include <mach/pxa/regs-intc.h> -#include <asm/barebox-arm-head.h> -#include "config.h" - -#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO <31:00> */ -#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO <63:32> */ -#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO <80:64> */ - -#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO <31:00> */ -#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ - -#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO <31:0o> */ -#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO <63:32> */ -#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO <80:64> */ - -#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO <15:00> */ -#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO <31:16> */ -#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO <47:32> */ -#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO <63:48> */ -#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO <79:64> */ -#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO <95:80> */ - -/* - * Memory setup - */ -.globl barebox_arm_reset_vector -barebox_arm_reset_vector: - bl arm_cpu_lowlevel_init - - @ Preserve r8/r7 i.e. kernel entry values - - @ Data cache might be active. - @ Be sure to flush kernel binary out of the cache, - @ whatever state it is, before it is turned off. - @ This is done by fetching through currently executed - @ memory to be sure we hit the same cache. - bic r2, pc, #0x1f - add r3, r2, #0x10000 @ 64 kb is quite enough... -1: ldr r0, [r2], #32 - teq r2, r3 - bne 1b - mcr p15, 0, r0, c7, c10, 4 @ drain WB - mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches - - @ disabling MMU and caches - mrc p15, 0, r0, c1, c0, 0 @ read control reg - bic r0, r0, #0x05 @ clear DC, MMU - bic r0, r0, #0x1000 @ clear Icache - mcr p15, 0, r0, c1, c0, 0 - /* set output */ - ldr r0, =GPSR0 - ldr r1, =CONFIG_GPSR0_VAL - str r1, [r0] - - ldr r0, =GPSR1 - ldr r1, =CONFIG_GPSR1_VAL - str r1, [r0] - - ldr r0, =GPSR2 - ldr r1, =CONFIG_GPSR2_VAL - str r1, [r0] - - /* set direction */ - ldr r0, =GPDR0 - ldr r1, =CONFIG_GPDR0_VAL - str r1, [r0] - - ldr r0, =GPDR1 - ldr r1, =CONFIG_GPDR1_VAL - str r1, [r0] - - ldr r0, =GPDR2 - ldr r1, =CONFIG_GPDR2_VAL - str r1, [r0] - - /* alternate function */ - ldr r0, =GAFR0_L - ldr r1, =CONFIG_GAFR0_L_VAL - str r1, [r0] - - ldr r0, =GAFR0_U - ldr r1, =CONFIG_GAFR0_U_VAL - str r1, [r0] - - ldr r0, =GAFR1_L - ldr r1, =CONFIG_GAFR1_L_VAL - str r1, [r0] - - ldr r0, =GAFR1_U - ldr r1, =CONFIG_GAFR1_U_VAL - str r1, [r0] - - ldr r0, =GAFR2_L - ldr r1, =CONFIG_GAFR2_L_VAL - str r1, [r0] - - ldr r0, =GAFR2_U - ldr r1, =CONFIG_GAFR2_U_VAL - str r1, [r0] - - /* enable GPIO pins */ - ldr r0, =PSSR - ldr r1, =CONFIG_PSSR_VAL - str r1, [r0] - - /* -------------------------------------------------------------------- */ - /* Enable memory interface */ - /* */ - /* The sequence below is based on the recommended init steps */ - /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ - /* Chapter 10. */ - /* -------------------------------------------------------------------- */ - - /* -------------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* -------------------------------------------------------------------- */ - - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - cmp pc, #0xa0000000 - bls mem_init - cmp pc, #0xb0000000 - bhi mem_init - b skip_mem_init - -mem_init: - ldr r1, =MDCNFG /* get memory controller base addr. */ - - /* -------------------------------------------------------------------- */ - /* Step 2a: Initialize Asynchronous static memory controller */ - /* -------------------------------------------------------------------- */ - - /* MSC registers: timing, bus width, mem type */ - - /* MSC0: nCS(0,1) */ - ldr r2, =CONFIG_MSC0_VAL - str r2, [r1, #MSC0_OFFSET] - ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ - /* that data latches */ - /* MSC1: nCS(2,3) */ - ldr r2, =CONFIG_MSC1_VAL - str r2, [r1, #MSC1_OFFSET] - ldr r2, [r1, #MSC1_OFFSET] - - /* MSC2: nCS(4,5) */ - ldr r2, =CONFIG_MSC2_VAL - str r2, [r1, #MSC2_OFFSET] - ldr r2, [r1, #MSC2_OFFSET] - - /* -------------------------------------------------------------------- */ - /* Step 2b: Initialize Card Interface */ - /* -------------------------------------------------------------------- */ - - /* MECR: Memory Expansion Card Register */ - ldr r2, =CONFIG_MECR_VAL - str r2, [r1, #MECR_OFFSET] - ldr r2, [r1, #MECR_OFFSET] - - /* MCMEM0: Card Interface slot 0 timing */ - ldr r2, =CONFIG_MCMEM0_VAL - str r2, [r1, #MCMEM0_OFFSET] - ldr r2, [r1, #MCMEM0_OFFSET] - - /* MCMEM1: Card Interface slot 1 timing */ - ldr r2, =CONFIG_MCMEM1_VAL - str r2, [r1, #MCMEM1_OFFSET] - ldr r2, [r1, #MCMEM1_OFFSET] - - /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ - ldr r2, =CONFIG_MCATT0_VAL - str r2, [r1, #MCATT0_OFFSET] - ldr r2, [r1, #MCATT0_OFFSET] - - /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ - ldr r2, =CONFIG_MCATT1_VAL - str r2, [r1, #MCATT1_OFFSET] - ldr r2, [r1, #MCATT1_OFFSET] - - /* MCIO0: Card Interface I/O Space Timing, slot 0 */ - ldr r2, =CONFIG_MCIO0_VAL - str r2, [r1, #MCIO0_OFFSET] - ldr r2, [r1, #MCIO0_OFFSET] - - /* MCIO1: Card Interface I/O Space Timing, slot 1 */ - ldr r2, =CONFIG_MCIO1_VAL - str r2, [r1, #MCIO1_OFFSET] - ldr r2, [r1, #MCIO1_OFFSET] - - /* -------------------------------------------------------------------- */ - /* Step 2c: Write FLYCNFG FIXME: what's that??? */ - /* -------------------------------------------------------------------- */ - ldr r2, =CONFIG_FLYCNFG_VAL - str r2, [r1, #FLYCNFG_OFFSET] - str r2, [r1, #FLYCNFG_OFFSET] - - /* -------------------------------------------------------------------- */ - /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ - /* -------------------------------------------------------------------- */ - - /* Before accessing MDREFR we need a valid DRI field, so we set */ - /* this to power on defaults + DRI field. */ - - ldr r4, [r1, #MDREFR_OFFSET] - ldr r2, =0xFFF - bic r4, r4, r2 - - ldr r3, =CONFIG_MDREFR_VAL - and r3, r3, r2 - - orr r4, r4, r3 - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - - orr r4, r4, #MDREFR_K0RUN - orr r4, r4, #MDREFR_K0DB4 - orr r4, r4, #MDREFR_K0FREE - orr r4, r4, #MDREFR_K2FREE - orr r4, r4, #MDREFR_K0DB2 - orr r4, r4, #MDREFR_K1DB2 - bic r4, r4, #MDREFR_K1FREE - - str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ - ldr r4, [r1, #MDREFR_OFFSET] - - /* Note: preserve the mdrefr value in r4 */ - - - /* -------------------------------------------------------------------- */ - /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ - /* -------------------------------------------------------------------- */ - - /* Initialize SXCNFG register. Assert the enable bits */ - - /* - * Write SXMRS to cause an MRS command to all enabled banks of - * synchronous static memory. Note that SXLCR need not be - * written at this time. - */ - ldr r2, =CONFIG_SXCNFG_VAL - str r2, [r1, #SXCNFG_OFFSET] - - /* -------------------------------------------------------------------- */ - /* Step 4: Initialize SDRAM */ - /* -------------------------------------------------------------------- */ - bic r4, r4, #(MDREFR_K1FREE | MDREFR_K0FREE) - - orr r4, r4, #MDREFR_K1RUN - orr r4, r4, #MDREFR_K2FREE - bic r4, r4, #MDREFR_K2DB2 - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - bic r4, r4, #MDREFR_SLFRSH - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - orr r4, r4, #MDREFR_E1PIN - str r4, [r1, #MDREFR_OFFSET] - ldr r4, [r1, #MDREFR_OFFSET] - - nop - nop - - - /* - * Step 4d: write MDCNFG with MDCNFG:DEx deasserted - * (set to 0), to configure but not enable each SDRAM - * partition pair. - */ - ldr r4, =CONFIG_MDCNFG_VAL - bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) - bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) - - str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ - ldr r4, [r1, #MDCNFG_OFFSET] - - - /* - * Step 4e: Wait for the clock to the SDRAMs to stabilize, - * 100..200 usec. - */ - ldr r3, =OSCR /* reset the OS Timer Count to zero */ - mov r2, #0 - str r2, [r3] - ldr r4, =0x300 /* really 0x2E1 is about 200 usec, */ - /* so 0x300 should be plenty */ -1: - ldr r2, [r3] - cmp r4, r2 - bgt 1b - - - /* Step 4f: Trigger a number (usually 8) refresh cycles by */ - /* attempting non-burst read or write accesses to disabled */ - /* SDRAM, as commonly specified in the power up sequence */ - /* documented in SDRAM data sheets. The address(es) used */ - /* for this purpose must not be cacheable. */ - ldr r3, =CONFIG_DRAM_BASE - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - str r2, [r3] - - - /* - * Step 4g: Write MDCNFG with enable bits asserted - * (MDCNFG:DEx set to 1) - */ - ldr r3, [r1, #MDCNFG_OFFSET] - mov r4, r3 - orr r3, r3, #MDCNFG_DE0 - str r3, [r1, #MDCNFG_OFFSET] - mov r0, r3 - - /* Step 4h: Write MDMRS. */ - ldr r2, =CONFIG_MDMRS_VAL - str r2, [r1, #MDMRS_OFFSET] - - /* enable APD */ - ldr r3, [r1, #MDREFR_OFFSET] - orr r3, r3, #MDREFR_APD - str r3, [r1, #MDREFR_OFFSET] - - /* We are finished with Intel's memory controller initialisation */ -skip_mem_init: - -wakeup: - /* Are we waking from sleep? */ - ldr r0, =RCSR - ldr r1, [r0] - and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) - str r1, [r0] - teq r1, #RCSR_SMR - - bne initirqs - - ldr r0, =PSSR - mov r1, #PSSR_PH - str r1, [r0] - - /* if so, resume at PSPR */ - ldr r0, =PSPR - ldr r1, [r0] - mov pc, r1 - - /* -------------------------------------------------------------------- */ - /* Disable (mask) all interrupts at interrupt controller */ - /* -------------------------------------------------------------------- */ - -initirqs: - mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ - ldr r2, =ICLR - str r1, [r2] - - ldr r2, =ICMR /* mask all interrupts at the controller */ - str r1, [r2] - - /* -------------------------------------------------------------------- */ - /* Clock initialisation */ - /* -------------------------------------------------------------------- */ - -initclks: - /* Disable the peripheral clocks, and set the core clock frequency */ - - /* Turn Off on-chip peripheral clocks (except for memory) */ - /* for re-configuration. */ - ldr r1, =CKEN - ldr r2, =CONFIG_CKEN - str r2, [r1] - - /* ... and write the core clock config register */ - ldr r2, =CONFIG_CCCR - ldr r1, =CCCR - str r2, [r1] - - /* Turn on turbo mode */ - mrc p14, 0, r2, c6, c0, 0 - orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change */ - mcr p14, 0, r2, c6, c0, 0 - - /* Re-write MDREFR */ - ldr r1, =MDCNFG - ldr r2, [r1, #MDREFR_OFFSET] - str r2, [r1, #MDREFR_OFFSET] - - /* enable the 32Khz oscillator for RTC and PowerManager */ - ldr r1, =OSCC - mov r2, #OSCC_OON - str r2, [r1] - - /* Interrupt init: Mask all interrupts */ - ldr r0, =ICMR /* enable no sources */ - mov r1, #0 - str r1, [r0] - /* FIXME */ - -#ifdef NODEBUG - /* Disable software and data breakpoints */ - mov r0, #0 - mcr p15, 0, r0, c14, c8, 0 /* ibcr0 */ - mcr p15, 0, r0, c14, c9, 0 /* ibcr1 */ - mcr p15, 0, r0, c14, c4, 0 /* dbcon */ - - /* Enable all debug functionality */ - mov r0, #0x80000000 - mcr p14, 0, r0, c10, c0, 0 /* dcsr */ -#endif - - /* -------------------------------------------------------------------- */ - /* End lowlevel_init */ - /* -------------------------------------------------------------------- */ - -endlowlevel_init: - mov r0, #0xa0000000 - mov r1, #SZ_64M - mov r2, #0 - b barebox_arm_entry diff --git a/arch/arm/boards/sama5d3xek/Makefile b/arch/arm/boards/sama5d3xek/Makefile deleted file mode 100644 index 9691f07917..0000000000 --- a/arch/arm/boards/sama5d3xek/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += init.o -obj-$(CONFIG_W1) += hw_version.o -lwl-y += lowlevel.o -bbenv-$(CONFIG_DEFAULT_ENVIRONMENT_GENERIC) += defaultenv-sama5d3xek diff --git a/arch/arm/boards/sama5d3xek/defaultenv-sama5d3xek/bin/init_board b/arch/arm/boards/sama5d3xek/defaultenv-sama5d3xek/bin/init_board deleted file mode 100644 index f3d417e356..0000000000 --- a/arch/arm/boards/sama5d3xek/defaultenv-sama5d3xek/bin/init_board +++ /dev/null @@ -1,15 +0,0 @@ -#!/bin/sh - -PATH=/env/bin -export PATH - -. /env/config - -splash=/env/splash.png - -if [ -f ${splash} -a -e /dev/fb0 ]; then - splash -o ${splash} - fb0.enable=1 -fi - -exit 1 diff --git a/arch/arm/boards/sama5d3xek/defaultenv-sama5d3xek/config b/arch/arm/boards/sama5d3xek/defaultenv-sama5d3xek/config deleted file mode 100644 index a7fd930ed1..0000000000 --- a/arch/arm/boards/sama5d3xek/defaultenv-sama5d3xek/config +++ /dev/null @@ -1,44 +0,0 @@ -#!/bin/sh - -# use 'dhcp' to do dhcp in barebox and in kernel -# use 'none' if you want to skip kernel ip autoconfiguration -ip=dhcp-barebox -global.dhcp.vendor_id=barebox-sama5d3xek -global.dhcp.client_id="${sama5d3xcm.board}-${sama5d3xcm.vendor}" - -# or set your networking parameters here -#eth0.ipaddr=a.b.c.d -#eth0.netmask=a.b.c.d -#eth0.gateway=a.b.c.d -#eth0.serverip=a.b.c.d - -# can be either 'nfs', 'tftp', 'nor' or 'nand' -kernel_loc=nfs -# can be either 'net', 'nor', 'nand' or 'initrd' -rootfs_loc=net -# can be either 'nfs', 'tftp', 'nand' or empty -oftree_loc=nfs - -# can be either 'jffs2' or 'ubifs' -rootfs_type=ubifs -rootfsimage=root.$rootfs_type -ubiroot=rootfs - -# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo -kernelimage=zImage -#kernelimage=uImage -#kernelimage=Image -#kernelimage=Image.lzo - -nand_device=atmel_nand -nand_parts="256k(at91bootstrap),384k(barebox)ro,256k@768k(bareboxenv),256k(bareboxenv2),128k@1536k(oftree),5M@2M(kernel),-@8M(rootfs)" -rootfs_mtdblock_nand=6 - -m25p80_parts="64k(bootstrap),384k(barebox),256k(bareboxenv),256k(bareboxenv2),128k(oftree),-(updater)" - -autoboot_timeout=3 - -bootargs="console=ttyS0,115200" - -# set a fancy prompt (if support is compiled in) -PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m\n# " diff --git a/arch/arm/boards/sama5d3xek/hw_version.c b/arch/arm/boards/sama5d3xek/hw_version.c deleted file mode 100644 index c64d4566c6..0000000000 --- a/arch/arm/boards/sama5d3xek/hw_version.c +++ /dev/null @@ -1,236 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - -#include <common.h> -#include <fs.h> -#include <fcntl.h> -#include <libbb.h> -#include <libfile.h> -#include <asm/armlinux.h> -#include <of.h> - -#include "hw_version.h" - -enum board_type { - BOARD_TYPE_MB, - BOARD_TYPE_DM, - BOARD_TYPE_CPU, -}; - -static struct board_info { - char *name; - enum board_type type; - unsigned char id; -} board_list[] = { - {"SAMA5D3x-MB", BOARD_TYPE_MB, 0}, - {"SAMA5D3x-DM", BOARD_TYPE_DM, 1}, - {"SAMA5D31-CM", BOARD_TYPE_CPU, 2}, - {"SAMA5D33-CM", BOARD_TYPE_CPU, 3}, - {"SAMA5D34-CM", BOARD_TYPE_CPU, 4}, - {"SAMA5D35-CM", BOARD_TYPE_CPU, 5}, - {"PDA-DM", BOARD_TYPE_DM, 7}, -}; - -static struct board_info* get_board_info_by_name(const char *name) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(board_list); i++) { - char *bname = board_list[i].name; - if (strncmp(name, bname, strlen(bname)) == 0) - return &board_list[i]; - } - - return NULL; -} - -static struct vendor_info { - char *name; - enum vendor_id id; -} vendor_list[] = { - {"EMBEST", VENDOR_EMBEST}, - {"FLEX", VENDOR_FLEX}, - {"RONETIX", VENDOR_RONETIX}, - {"COGENT", VENDOR_COGENT}, - {"PDA", VENDOR_PDA}, -}; - -static struct vendor_info* get_vendor_info_by_name(const char *name) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(vendor_list); i++) { - char *vname = vendor_list[i].name; - if (strncmp(name, vname, strlen(vname)) == 0) - return &vendor_list[i]; - } - - return NULL; -} - -#define BOARD_NAME_LEN 12 -#define VENDOR_NAME_LEN 10 -#define VENDOR_COUNTRY_LEN 2 - -struct one_wire_info { - u8 total_bytes; - u8 vendor_name[VENDOR_NAME_LEN]; - u8 vendor_country[VENDOR_COUNTRY_LEN]; - u8 board_name[BOARD_NAME_LEN]; - u8 year; - u8 week; - u8 revision_board; - u8 revision_schema; - u8 revision_bom; - u8 checksum_l; - u8 checksum_h; -}__attribute__ ((packed)); - -static int at91sama5d3xek_read_w1(const char *file, struct one_wire_info *info) -{ - int fd; - int ret; - - fd = open(file, O_RDONLY); - if (fd < 0) { - ret = fd; - goto err; - } - - ret = read_full(fd, info, sizeof(*info)); - if (ret < 0) - goto err_open; - - if (ret < sizeof(*info)) { - ret = -EINVAL; - goto err_open; - } - - pr_debug("total_bytes = %d\n", info->total_bytes); - pr_debug("vendor_name = %s\n", info->vendor_name); - pr_debug("vendor_country = %.2s\n", info->vendor_country); - pr_debug("board_name = %s\n", info->board_name); - pr_debug("year = %d\n", info->year); - pr_debug("week = %d\n", info->week); - pr_debug("revision_board = %x\n", info->revision_board); - pr_debug("revision_schema = %x\n", info->revision_schema); - pr_debug("revision_bom = %x\n", info->revision_bom); - pr_debug("checksum_l = %x\n", info->checksum_l); - pr_debug("checksum_h = %x\n", info->checksum_h); - - ret = 0; - -err_open: - close(fd); -err: - if (ret) - pr_err("can not read 1-wire %s (%s)\n", file, strerror(ret)); - return ret; -} - -static u32 sn = 0; -static u32 rev = 0; - -bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid) -{ - return ((sn >> 5) & 0x1f) == vid; -} - -bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid) -{ - return ((sn >> 25) & 0x1f) == vid; -} - -bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid) -{ - return ((sn >> 15) & 0x1f) == vid; -} - -static void at91sama5d3xek_devices_detect_one(const char *name) -{ - struct one_wire_info info; - struct board_info* binfo; - struct vendor_info* vinfo; - struct device *dev = NULL; - char str[16]; - char *bname, *vname; - u8 vendor_id = 0; - - if (at91sama5d3xek_read_w1(name, &info)) - return; - - binfo = get_board_info_by_name(info.board_name); - - if (!binfo) { - pr_err("board %s no supported\n", info.board_name); - return; - } - bname = binfo->name; - - vinfo = get_vendor_info_by_name(info.vendor_name); - vname = info.vendor_name; - if (vinfo) { - vendor_id = vinfo->id; - vname = vinfo->name; - } - - switch (binfo->type) { - case BOARD_TYPE_CPU: - dev = add_generic_device_res("sama5d3xcm", DEVICE_ID_SINGLE, NULL, 0, NULL); - if (!dev) - return; - sn |= (binfo->id & 0x1f); - sn |= ((vendor_id & 0x1f) << 5); - rev |= (info.revision_board - 'A'); - rev |= (((info.revision_schema - '0') & 0x3) << 15); - pr_info("CM"); - break; - case BOARD_TYPE_MB: - dev = add_generic_device_res("sama5d3xmb", DEVICE_ID_SINGLE, NULL, 0, NULL); - if (!dev) - return; - sn |= ((binfo->id & 0x1f) << 20); - sn |= ((vendor_id & 0x1f) << 25); - rev |= ((info.revision_board - 'A') << 10); - rev |= (((info.revision_schema - '0') & 0x3) << 21); - pr_info("MB"); - break; - case BOARD_TYPE_DM: - dev = add_generic_device_res("sama5d3xdm", DEVICE_ID_SINGLE, NULL, 0, NULL); - if (!dev) - return; - sn |= ((binfo->id & 0x1f) << 10); - sn |= ((vendor_id & 0x1f) << 15); - rev |= ((info.revision_board - 'A') << 5); - rev |= (((info.revision_schema - '0') & 0x3) << 18); - pr_info("DM"); - break; - } - - pr_info(": %s [%c%c] from %s\n", - bname, info.revision_board, info.revision_schema, vname); - - dev_add_param_fixed(dev, "vendor", vname); - dev_add_param_fixed(dev, "board", bname); - sprintf(str, "%.2s", info.vendor_country); - dev_add_param_fixed(dev, "country", str); - dev_add_param_uint32_fixed(dev, "year", info.year, "%u"); - dev_add_param_uint32_fixed(dev, "week", info.week, "%u"); - sprintf(str, "%c", info.revision_board); - dev_add_param_fixed(dev, "revision_board", str); - sprintf(str, "%c", info.revision_schema); - dev_add_param_fixed(dev, "revision_schema", str); - sprintf(str, "%c", info.revision_bom); - dev_add_param_fixed(dev, "revision_bom", str); -} - -void at91sama5d3xek_devices_detect_hw(void) -{ - at91sama5d3xek_devices_detect_one("/dev/ds24310"); - at91sama5d3xek_devices_detect_one("/dev/ds28ec200"); - at91sama5d3xek_devices_detect_one("/dev/ds24330"); - - pr_info("sn: 0x%x, rev: 0x%x\n", sn, rev); - armlinux_set_revision(rev); - armlinux_set_serial(sn); -} diff --git a/arch/arm/boards/sama5d3xek/hw_version.h b/arch/arm/boards/sama5d3xek/hw_version.h deleted file mode 100644 index d90c751629..0000000000 --- a/arch/arm/boards/sama5d3xek/hw_version.h +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - -#ifndef __HW_REVISION_H__ -#define __HW_REVISION_H__ - -enum vendor_id { - VENDOR_UNKNOWN = 0, - VENDOR_EMBEST = 1, - VENDOR_FLEX = 2, - VENDOR_RONETIX = 3, - VENDOR_COGENT = 4, - VENDOR_PDA = 5, -}; - -#ifdef CONFIG_W1 -bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid); -bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid); -bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid); -void at91sama5d3xek_devices_detect_hw(void); -#else -bool at91sama5d3xek_cm_is_vendor(enum vendor_id vid) -{ - return false; -} - -bool at91sama5d3xek_ek_is_vendor(enum vendor_id vid) -{ - return false; -} - -bool at91sama5d3xek_dm_is_vendor(enum vendor_id vid) -{ - return false; -} - -void at91sama5d3xek_devices_detect_hw(void) {} -#endif - -#endif /* __HW_REVISION_H__ */ diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c deleted file mode 100644 index b75856198e..0000000000 --- a/arch/arm/boards/sama5d3xek/init.c +++ /dev/null @@ -1,475 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - -#include <common.h> -#include <net.h> -#include <init.h> -#include <environment.h> -#include <asm/armlinux.h> -#include <asm/mach-types.h> -#include <fs.h> -#include <fcntl.h> -#include <io.h> -#include <envfs.h> -#include <mach/at91/hardware.h> -#include <nand.h> -#include <linux/sizes.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/rawnand.h> -#include <mach/at91/board.h> -#include <mach/at91/at91sam9_smc.h> -#include <gpio.h> -#include <mach/at91/iomux.h> -#include <mach/at91/at91_pmc.h> -#include <mach/at91/at91_rstc.h> -#include <mach/at91/at91sam9x5_matrix.h> -#include <input/qt1070.h> -#include <readkey.h> -#include <poller.h> -#include <linux/w1-gpio.h> -#include <w1_mac_address.h> -#include <spi/spi.h> -#include <linux/clk.h> -#include <linux/phy.h> -#include <linux/micrel_phy.h> - -#include "hw_version.h" - -#ifdef CONFIG_W1_MASTER_GPIO -struct w1_gpio_platform_data w1_pdata = { - .pin = AT91_PIN_PE25, - .ext_pullup_enable_pin = -EINVAL, - .is_open_drain = 0, -}; -#endif - -#if defined(CONFIG_NAND_ATMEL) -static struct atmel_nand_data nand_pdata = { - .ale = 21, - .cle = 22, - .det_pin = -EINVAL, - .rdy_pin = -EINVAL, - .enable_pin = -EINVAL, - .ecc_mode = NAND_ECC_HW, - .has_pmecc = 1, - .pmecc_sector_size = 512, - .pmecc_corr_cap = 4, -#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) - .bus_width_16 = 1, -#endif - .on_flash_bbt = 1, -}; - -static struct sam9_smc_config cm_nand_smc_config = { - .ncs_read_setup = 1, - .nrd_setup = 2, - .ncs_write_setup = 1, - .nwe_setup = 2, - - .ncs_read_pulse = 5, - .nrd_pulse = 3, - .ncs_write_pulse = 5, - .nwe_pulse = 3, - - .read_cycle = 8, - .write_cycle = 8, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, - .tdf_cycles = 3, - - .tclr = 3, - .tadl = 10, - .tar = 3, - .ocms = 0, - .trr = 4, - .twb = 5, - .rbnsel = 3, - .nfsel = 1 -}; - -static void ek_add_device_nand(void) -{ - struct clk *clk = clk_get(NULL, "smc_clk"); - - clk_enable(clk); - - /* setup bus-width (8 or 16) */ - if (nand_pdata.bus_width_16) - cm_nand_smc_config.mode |= AT91_SMC_DBW_16; - else - cm_nand_smc_config.mode |= AT91_SMC_DBW_8; - - /* configure chip-select 3 (NAND) */ - sama5_smc_configure(0, 3, &cm_nand_smc_config); - - at91_add_device_nand(&nand_pdata); -} -#else -static void ek_add_device_nand(void) {} -#endif - -#if defined(CONFIG_DRIVER_NET_MACB) -static struct macb_platform_data gmac_pdata = { - .phy_interface = PHY_INTERFACE_MODE_RGMII, - .phy_addr = -1, -}; - -static struct macb_platform_data macb_pdata = { - .phy_interface = PHY_INTERFACE_MODE_RMII, - .phy_addr = -1, -}; - -static bool used_23 = false; -static bool used_43 = false; - -static int ek_register_mac_address_23(int id) -{ - if (used_23) - return -EBUSY; - - used_23 = true; - - return w1_local_mac_address_register(id, "tml", "w1-23-0"); -} - -static int ek_register_mac_address_43(int id) -{ - if (used_43) - return -EBUSY; - - used_43 = true; - - return w1_local_mac_address_register(id, "tml", "w1-43-0"); -} - -static int ksz9021rn_phy_fixup(struct phy_device *phy) -{ - int value; - -#define GMII_RCCPSR 260 -#define GMII_RRDPSR 261 -#define GMII_ERCR 11 -#define GMII_ERDWR 12 - - /* Set delay values */ - value = GMII_RCCPSR | 0x8000; - phy_write(phy, GMII_ERCR, value); - value = 0xF2F4; - phy_write(phy, GMII_ERDWR, value); - value = GMII_RRDPSR | 0x8000; - phy_write(phy, GMII_ERCR, value); - value = 0x2222; - phy_write(phy, GMII_ERDWR, value); - - return 0; -} - -static void ek_add_device_eth(void) -{ - if (w1_local_mac_address_register(0, "tml", "w1-2d-0")) - if (ek_register_mac_address_23(0)) - ek_register_mac_address_43(0); - - if (ek_register_mac_address_23(1)) - ek_register_mac_address_43(1); - - phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, - ksz9021rn_phy_fixup); - - at91_add_device_eth(0, &gmac_pdata); - at91_add_device_eth(1, &macb_pdata); -} -#else -static void ek_add_device_eth(void) {} -#endif - -#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) -/* - * LCD Controller - */ -static struct fb_videomode at91_tft_vga_modes[] = { - { - .name = "LG", - .refresh = 60, - .xres = 800, .yres = 480, - .pixclock = KHZ2PICOS(33260), - - .left_margin = 88, .right_margin = 168, - .upper_margin = 8, .lower_margin = 37, - .hsync_len = 128, .vsync_len = 2, - - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, -}; - -/* Default output mode is TFT 24 bit */ -#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_24BPP) - -/* Driver datas */ -static struct atmel_lcdfb_platform_data ek_lcdc_data = { - .lcdcon_is_backlight = true, - .default_bpp = 16, - .default_dmacon = ATMEL_LCDC_DMAEN, - .default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5, - .guard_time = 9, - .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, - .mode_list = at91_tft_vga_modes, - .num_modes = ARRAY_SIZE(at91_tft_vga_modes), -}; - -static void ek_add_device_lcdc(void) -{ - at91_add_device_lcdc(&ek_lcdc_data); -} - -#else -static void ek_add_device_lcdc(void) {} -#endif - -#if defined(CONFIG_MCI_ATMEL) -/* - * MCI (SD/MMC) - */ -static struct atmel_mci_platform_data mci0_data = { - .bus_width = 4, - .detect_pin = AT91_PIN_PD17, - .wp_pin = -EINVAL, -}; - -static struct atmel_mci_platform_data mci1_data = { - .bus_width = 4, - .detect_pin = AT91_PIN_PD18, - .wp_pin = -EINVAL, -}; - -static void ek_add_device_mci(void) -{ - /* MMC0 */ - at91_add_device_mci(0, &mci0_data); - /* MMC1 */ - at91_add_device_mci(1, &mci1_data); -} -#else -static void ek_add_device_mci(void) {} -#endif - -#if defined(CONFIG_I2C_GPIO) -struct qt1070_platform_data qt1070_pdata = { - .irq_pin = AT91_PIN_PE31, -}; - -static struct i2c_board_info i2c_devices[] = { - { - .platform_data = &qt1070_pdata, - I2C_BOARD_INFO("qt1070", 0x1b), - }, -}; - -static void ek_add_device_i2c(void) -{ - at91_set_gpio_input(qt1070_pdata.irq_pin, 0); - at91_set_deglitch(qt1070_pdata.irq_pin, 1); - at91_add_device_i2c(1, i2c_devices, ARRAY_SIZE(i2c_devices)); - at91_add_device_i2c(0, NULL, 0); -} -#else -static void ek_add_device_i2c(void) {} -#endif - -#if defined(CONFIG_DRIVER_SPI_ATMEL) -static const struct spi_board_info ek_spi_devices[] = { - { - .name = "m25p80", - .chip_select = 0, - .max_speed_hz = 30 * 1000 * 1000, - .bus_num = 0, - } -}; - -static unsigned spi0_standard_cs[] = { AT91_PIN_PD13 }; -static struct at91_spi_platform_data spi_pdata = { - .chipselect = spi0_standard_cs, - .num_chipselect = ARRAY_SIZE(spi0_standard_cs), -}; - -static void ek_add_device_spi(void) -{ - spi_register_board_info(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); - at91_add_device_spi(0, &spi_pdata); -} -#else -static void ek_add_device_spi(void) {} -#endif - -#ifdef CONFIG_LED_GPIO -struct gpio_led leds[] = { - { - .gpio = AT91_PIN_PE24, - .active_low = 1, - .led = { - .name = "d1", - }, - }, { -#ifndef CONFIG_W1_MASTER_GPIO - .gpio = AT91_PIN_PE25, - .active_low = 1, - .led = { - .name = "d2", - }, -#endif - }, -}; - -static void ek_add_led(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(leds); i++) { - at91_set_gpio_output(leds[i].gpio, leds[i].active_low); - led_gpio_register(&leds[i]); - } - led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); -} -#else -static void ek_add_led(void) {} -#endif - -static int at91sama5d3xek_mem_init(void) -{ - at91_add_device_sdram(0); - - return 0; -} -mem_initcall(at91sama5d3xek_mem_init); - -#ifdef CONFIG_W1_MASTER_GPIO -static void ek_add_device_w1(void) -{ - at91_set_gpio_input(w1_pdata.pin, 0); - at91_set_multi_drive(w1_pdata.pin, 1); - add_generic_device_res("w1-gpio", DEVICE_ID_SINGLE, NULL, 0, &w1_pdata); - - at91sama5d3xek_devices_detect_hw(); -} -#else -static void ek_add_device_w1(void) {} -#endif - -#ifdef CONFIG_POLLER -/* - * The SiI9022A (HDMI) and QT1070 share the same irq - * but if the SiI9022A is not reset the irq is pull down - * So do it. As the SiI9022A need 1s to reset (500ms up then 500ms down then up) - * do it poller to do not slow down the boot - */ -static int hdmi_reset_pin = AT91_PIN_PC31; -static uint64_t hdmi_reset_start; -struct poller_struct hdmi_poller; - -static void hdmi_on_poller(struct poller_struct *poller) -{ - if (!is_timeout_non_interruptible(hdmi_reset_start, 500 * MSECOND)) - return; - - gpio_set_value(hdmi_reset_pin, 1); - - poller_unregister(poller); - ek_add_device_i2c(); -} - -static void hdmi_off_poller(struct poller_struct *poller) -{ - if (!is_timeout_non_interruptible(hdmi_reset_start, 500 * MSECOND)) - return; - - gpio_set_value(hdmi_reset_pin, 0); - - hdmi_reset_start = get_time_ns(); - poller->func = hdmi_on_poller; -} - -static void ek_add_device_hdmi(void) -{ - at91_set_gpio_output(hdmi_reset_pin, 1); - hdmi_reset_start = get_time_ns(); - hdmi_poller.func = hdmi_off_poller; - - poller_register(&hdmi_poller, "hdmi-reset"); -} -#else -static void ek_add_device_hdmi(void) -{ - ek_add_device_i2c(); -} -#endif - -static const struct devfs_partition at91sama5d3xek_nand0_partitions[] = { - { - .offset = 0x00000, - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "at91bootstrap_raw", - .bbname = "at91bootstrap", - }, { - .offset = DEVFS_PARTITION_APPEND, /* 256 KiB */ - .size = SZ_256K + SZ_128K, - .flags = DEVFS_PARTITION_FIXED, - .name = "self_raw", - .bbname = "self0", - }, - /* hole of 128 KiB */ - { - .offset = SZ_512K + SZ_256K, - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "env_raw", - .bbname = "env0", - }, { - .offset = DEVFS_PARTITION_APPEND, /* 1 MiB */ - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "env_raw1", - .bbname = "env1", - }, { - /* sentinel */ - } -}; - -static int at91sama5d3xek_devices_init(void) -{ - ek_add_device_w1(); - ek_add_device_hdmi(); - ek_add_device_nand(); - ek_add_led(); - ek_add_device_eth(); - ek_add_device_spi(); - ek_add_device_mci(); - ek_add_device_lcdc(); - - devfs_create_partitions("nand0", at91sama5d3xek_nand0_partitions); - - if (IS_ENABLED(CONFIG_DEFAULT_ENVIRONMENT_GENERIC)) - defaultenv_append_directory(defaultenv_sama5d3xek); - - return 0; -} -device_initcall(at91sama5d3xek_devices_init); - -static int at91sama5d3xek_console_init(void) -{ - barebox_set_model("Atmel sama5d3x-ek"); - barebox_set_hostname("sama5d3x-ek"); - - at91_register_uart(0, 0); - at91_register_uart(2, 0); - return 0; -} -console_initcall(at91sama5d3xek_console_init); - -static int at91sama5d3xek_main_clock(void) -{ - at91_set_main_clock(12000000); - return 0; -} -pure_initcall(at91sama5d3xek_main_clock); diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c deleted file mode 100644 index fe5f172127..0000000000 --- a/arch/arm/boards/sama5d3xek/lowlevel.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 - */ - -#include <common.h> -#include <init.h> - -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> - -#include <mach/at91/at91_ddrsdrc.h> -#include <mach/at91/hardware.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - - arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE); - - barebox_arm_entry(SAMA5_DDRCS, at91sama5d3_get_ddram_size(), NULL); -} diff --git a/arch/arm/boards/sama5d4ek/Makefile b/arch/arm/boards/sama5d4ek/Makefile deleted file mode 100644 index 82ffe9771c..0000000000 --- a/arch/arm/boards/sama5d4ek/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += sama5d4ek.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/sama5d4ek/env/boot/nand b/arch/arm/boards/sama5d4ek/env/boot/nand deleted file mode 100644 index 29489bf613..0000000000 --- a/arch/arm/boards/sama5d4ek/env/boot/nand +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel.bb" -global.bootm.oftree="/dev/nand0.oftree.bb" - -global.linux.bootargs.dyn.root="root=ubi0:rootfs ubi.mtd=rootfs rootfstype=ubifs noinitrd" diff --git a/arch/arm/boards/sama5d4ek/env/init/mtdparts-nand b/arch/arm/boards/sama5d4ek/env/init/mtdparts-nand deleted file mode 100644 index c947910643..0000000000 --- a/arch/arm/boards/sama5d4ek/env/init/mtdparts-nand +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="256k(at91bootstrap),512k(barebox)ro,256k(bareboxenv),256k(bareboxenv2),256k(spare),512k(oftree),6M(kernel),-(rootfs)" -kernelname="atmel_nand" - -mtdparts-add -b -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/sama5d4ek/env/init/mtdparts-nor b/arch/arm/boards/sama5d4ek/env/init/mtdparts-nor deleted file mode 100644 index 01fa752c3c..0000000000 --- a/arch/arm/boards/sama5d4ek/env/init/mtdparts-nor +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="64k(bootstrap),64k(bareboxenv),512k(barebox),384k(oftree),-(kernel)" -kernelname="m25p800" - -mtdparts-add -d m25p0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/sama5d4ek/env/init/splash b/arch/arm/boards/sama5d4ek/env/init/splash deleted file mode 100644 index 190ef3149e..0000000000 --- a/arch/arm/boards/sama5d4ek/env/init/splash +++ /dev/null @@ -1,10 +0,0 @@ -#!/bin/sh - -splash=/env/splash.png - -if [ -f ${splash} -a -e /dev/fb0 ]; then - splash -o ${splash} - fb0.enable=1 -fi - -exit 1 diff --git a/arch/arm/boards/sama5d4ek/env/nv/boot.default b/arch/arm/boards/sama5d4ek/env/nv/boot.default deleted file mode 100644 index d287b22cbb..0000000000 --- a/arch/arm/boards/sama5d4ek/env/nv/boot.default +++ /dev/null @@ -1 +0,0 @@ -nand net diff --git a/arch/arm/boards/sama5d4ek/env/nv/hostname b/arch/arm/boards/sama5d4ek/env/nv/hostname deleted file mode 100644 index b74056d082..0000000000 --- a/arch/arm/boards/sama5d4ek/env/nv/hostname +++ /dev/null @@ -1 +0,0 @@ -sama5d4ek diff --git a/arch/arm/boards/sama5d4ek/env/nv/linux.bootargs.console b/arch/arm/boards/sama5d4ek/env/nv/linux.bootargs.console deleted file mode 100644 index 476b1fbe49..0000000000 --- a/arch/arm/boards/sama5d4ek/env/nv/linux.bootargs.console +++ /dev/null @@ -1 +0,0 @@ -console=ttyS0,115200 diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c deleted file mode 100644 index 183bd9c5a9..0000000000 --- a/arch/arm/boards/sama5d4ek/lowlevel.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2009-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * Under GPLv2 - */ - -#include <common.h> -#include <init.h> - -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> - -#include <mach/at91/at91_ddrsdrc.h> -#include <mach/at91/hardware.h> - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - - arm_setup_stack(SAMA5D4_SRAM_BASE + SAMA5D4_SRAM_SIZE); - - barebox_arm_entry(SAMA5_DDRCS, at91sama5d4_get_ddram_size(), NULL); -} diff --git a/arch/arm/boards/sama5d4ek/sama5d4ek.c b/arch/arm/boards/sama5d4ek/sama5d4ek.c deleted file mode 100644 index 0dda34614a..0000000000 --- a/arch/arm/boards/sama5d4ek/sama5d4ek.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * SAMA5D4EK board configuration. - * - * Copyright (C) 2014 Atmel Corporation, - * Bo Shen <voice.shen@atmel.com> - * - * Licensed under GPLv2 or later. - */ - -#include <common.h> -#include <net.h> -#include <init.h> -#include <environment.h> -#include <asm/armlinux.h> -#include <fs.h> -#include <fcntl.h> -#include <io.h> -#include <mach/at91/hardware.h> -#include <nand.h> -#include <linux/sizes.h> -#include <linux/mtd/nand.h> -#include <linux/mtd/rawnand.h> -#include <mach/at91/board.h> -#include <mach/at91/at91sam9_smc.h> -#include <gpio.h> -#include <mach/at91/iomux.h> -#include <mach/at91/at91_pmc.h> -#include <mach/at91/at91_rstc.h> -#include <mach/at91/at91sam9x5_matrix.h> -#include <input/qt1070.h> -#include <readkey.h> -#include <spi/spi.h> -#include <linux/clk.h> - -#if defined(CONFIG_NAND_ATMEL) -static struct atmel_nand_data nand_pdata = { - .ale = 21, - .cle = 22, - .det_pin = -EINVAL, - .rdy_pin = -EINVAL, - .enable_pin = -EINVAL, - .ecc_mode = NAND_ECC_HW, - .has_pmecc = 1, - .pmecc_sector_size = 512, - .pmecc_corr_cap = 8, - .on_flash_bbt = 1, -}; - -static struct sam9_smc_config cm_nand_smc_config = { - .ncs_read_setup = 1, - .nrd_setup = 1, - .ncs_write_setup = 1, - .nwe_setup = 1, - - .ncs_read_pulse = 3, - .nrd_pulse = 2, - .ncs_write_pulse = 3, - .nwe_pulse = 2, - - .read_cycle = 5, - .write_cycle = 5, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, - .tdf_cycles = 3, - - .tclr = 2, - .tadl = 7, - .tar = 2, - .ocms = 0, - .trr = 3, - .twb = 7, - .rbnsel = 3, - .nfsel = 1, -}; - -static void ek_add_device_nand(void) -{ - struct clk *clk = clk_get(NULL, "smc_clk"); - - clk_enable(clk); - - /* configure chip-select 3 (NAND) */ - sama5_smc_configure(0, 3, &cm_nand_smc_config); - - at91_add_device_nand(&nand_pdata); -} -#else -static void ek_add_device_nand(void) {} -#endif - -#if defined(CONFIG_DRIVER_NET_MACB) -static struct macb_platform_data macb0_pdata = { - .phy_interface = PHY_INTERFACE_MODE_RMII, - .phy_addr = 0, -}; - -static void ek_add_device_eth(void) -{ - at91_add_device_eth(0, &macb0_pdata); -} -#else -static void ek_add_device_eth(void) {} -#endif - -#if defined(CONFIG_DRIVER_VIDEO_ATMEL_HLCD) -static struct fb_videomode at91_tft_vga_modes[] = { - { - .name = "LG", - .refresh = 60, - .xres = 800, .yres = 480, - .pixclock = KHZ2PICOS(33260), - - .left_margin = 88, .right_margin = 168, - .upper_margin = 8, .lower_margin = 37, - .hsync_len = 128, .vsync_len = 2, - - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - }, -}; - -/* Output mode is TFT 18 bits */ -#define BPP_OUT_DEFAULT_LCDCFG5 (LCDC_LCDCFG5_MODE_OUTPUT_18BPP) - -static struct atmel_lcdfb_platform_data ek_lcdc_data = { - .lcdcon_is_backlight = true, - .default_bpp = 16, - .default_dmacon = ATMEL_LCDC_DMAEN, - .default_lcdcon2 = BPP_OUT_DEFAULT_LCDCFG5, - .guard_time = 9, - .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, - .mode_list = at91_tft_vga_modes, - .num_modes = ARRAY_SIZE(at91_tft_vga_modes), -}; - -static void ek_add_device_lcdc(void) -{ - at91_add_device_lcdc(&ek_lcdc_data); -} -#else -static void ek_add_device_lcdc(void) {} -#endif - -#if defined(CONFIG_MCI_ATMEL) -static struct atmel_mci_platform_data mci1_data = { - .bus_width = 4, - .detect_pin = AT91_PIN_PE6, - .wp_pin = -EINVAL, -}; - -static void ek_add_device_mci(void) -{ - /* MMC1 */ - at91_add_device_mci(1, &mci1_data); - - /* power on MCI1 */ - at91_set_gpio_output(AT91_PIN_PE15, 0); -} -#else -static void ek_add_device_mci(void) {} -#endif - -#if defined(CONFIG_I2C_GPIO) -struct qt1070_platform_data qt1070_pdata = { - .irq_pin = AT91_PIN_PE25, -}; - -static struct i2c_board_info i2c_devices[] = { - { - .platform_data = &qt1070_pdata, - I2C_BOARD_INFO("qt1070", 0x1b), - }, -}; - -static void ek_add_device_i2c(void) -{ - at91_set_gpio_input(qt1070_pdata.irq_pin, 0); - at91_set_deglitch(qt1070_pdata.irq_pin, 1); - at91_add_device_i2c(0, i2c_devices, ARRAY_SIZE(i2c_devices)); -} -#else -static void ek_add_device_i2c(void) {} -#endif - -#if defined(CONFIG_DRIVER_SPI_ATMEL) -static const struct spi_board_info ek_spi_devices[] = { - { - .name = "m25p80", - .chip_select = 0, - .max_speed_hz = 30 * 1000 * 1000, - .bus_num = 0, - } -}; - -static unsigned spi0_standard_cs[] = { AT91_PIN_PC3 }; -static struct at91_spi_platform_data spi_pdata = { - .chipselect = spi0_standard_cs, - .num_chipselect = ARRAY_SIZE(spi0_standard_cs), -}; - -static void ek_add_device_spi(void) -{ - spi_register_board_info(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); - at91_add_device_spi(0, &spi_pdata); -} -#else -static void ek_add_device_spi(void) {} -#endif - -#ifdef CONFIG_LED_GPIO -struct gpio_led leds[] = { - { - .gpio = AT91_PIN_PE28, - .active_low = 0, - .led = { - .name = "d8", - }, - }, { - .gpio = AT91_PIN_PE9, - .active_low = 1, - .led = { - .name = "d9", - }, - }, { - .gpio = AT91_PIN_PE8, - .active_low = 0, - .led = { - .name = "d10", - }, - }, -}; - -static void ek_add_led(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(leds); i++) { - at91_set_gpio_output(leds[i].gpio, leds[i].active_low); - led_gpio_register(&leds[i]); - } - led_set_trigger(LED_TRIGGER_HEARTBEAT, &leds[0].led); -} -#else -static void ek_add_led(void) {} -#endif - -static int sama5d4ek_mem_init(void) -{ - at91_add_device_sdram(0); - - return 0; -} -mem_initcall(sama5d4ek_mem_init); - -static const struct devfs_partition sama5d4ek_nand0_partitions[] = { - { - .offset = 0x00000, - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "at91bootstrap_raw", - .bbname = "at91bootstrap", - }, { - .offset = DEVFS_PARTITION_APPEND, - .size = SZ_512K, - .flags = DEVFS_PARTITION_FIXED, - .name = "bootloader_raw", - .bbname = "bootloader", - }, { - .offset = DEVFS_PARTITION_APPEND, - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "env_raw", - .bbname = "env0", - }, { - .offset = DEVFS_PARTITION_APPEND, - .size = SZ_256K, - .flags = DEVFS_PARTITION_FIXED, - .name = "env_raw1", - .bbname = "env1", - }, { - /* sentinel */ - } -}; - -static int sama5d4ek_devices_init(void) -{ - ek_add_device_i2c(); - ek_add_device_nand(); - ek_add_led(); - ek_add_device_eth(); - ek_add_device_spi(); - ek_add_device_mci(); - ek_add_device_lcdc(); - - devfs_create_partitions("nand0", sama5d4ek_nand0_partitions); - - return 0; -} -device_initcall(sama5d4ek_devices_init); - -static int sama5d4ek_console_init(void) -{ - barebox_set_model("Atmel sama5d4ek"); - barebox_set_hostname("sama5d4ek"); - - at91_register_uart(4, 0); - - return 0; -} -console_initcall(sama5d4ek_console_init); - -static int sama5d4ek_main_clock(void) -{ - at91_set_main_clock(12000000); - - return 0; -} -pure_initcall(sama5d4ek_main_clock); diff --git a/arch/arm/boards/versatile/Kconfig b/arch/arm/boards/versatile/Kconfig index 66492404e0..5cb3061635 100644 --- a/arch/arm/boards/versatile/Kconfig +++ b/arch/arm/boards/versatile/Kconfig @@ -2,8 +2,4 @@ if MACH_VERSATILEPB -config ARCH_TEXT_BASE - hex - default 0x01000000 - endif diff --git a/arch/arm/boards/virt2real/Makefile b/arch/arm/boards/virt2real/Makefile deleted file mode 100644 index da63d2625f..0000000000 --- a/arch/arm/boards/virt2real/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/virt2real/board.c b/arch/arm/boards/virt2real/board.c deleted file mode 100644 index caa2b53a68..0000000000 --- a/arch/arm/boards/virt2real/board.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> - -/* This file is part of barebox. */ - -#include <common.h> -#include <init.h> - -static int hostname_init(void) -{ - barebox_set_hostname("virt2real"); - - return 0; -} -core_initcall(hostname_init); diff --git a/arch/arm/boards/virt2real/lowlevel.c b/arch/arm/boards/virt2real/lowlevel.c deleted file mode 100644 index d14907b768..0000000000 --- a/arch/arm/boards/virt2real/lowlevel.c +++ /dev/null @@ -1,28 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -// SPDX-FileCopyrightText: 2014 Antony Pavlov <antonynpavlov@gmail.com> - -/* This file is part of barebox. */ - -#define __LOWLEVEL_INIT__ - -#include <common.h> -#include <asm/barebox-arm.h> -#include <asm/barebox-arm-head.h> -#include <init.h> -#include <linux/sizes.h> - -#define VIRT2REAL_SRAM_BASE 0x82000000 -#define VIRT2REAL_SRAM_SIZE SZ_16M - -extern char __dtb_virt2real_start[]; - -void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - void *fdt; - - arm_cpu_lowlevel_init(); - - fdt = __dtb_virt2real_start + get_runtime_offset(); - - barebox_arm_entry(VIRT2REAL_SRAM_BASE, VIRT2REAL_SRAM_SIZE, fdt); -} diff --git a/arch/arm/boards/zylonite/Makefile b/arch/arm/boards/zylonite/Makefile deleted file mode 100644 index da63d2625f..0000000000 --- a/arch/arm/boards/zylonite/Makefile +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -obj-y += board.o -lwl-y += lowlevel.o diff --git a/arch/arm/boards/zylonite/board.c b/arch/arm/boards/zylonite/board.c deleted file mode 100644 index 04cb34754c..0000000000 --- a/arch/arm/boards/zylonite/board.c +++ /dev/null @@ -1,93 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -// SPDX-FileCopyrightText: 2014 Robert Jarzmik <robert.jarzmik@free.fr> - -#include <common.h> - -#include <driver.h> -#include <environment.h> -#include <fs.h> -#include <gpio.h> -#include <init.h> -#include <led.h> -#include <platform_data/eth-smc91111.h> -#include <platform_data/mtd-nand-mrvl.h> -#include <pwm.h> -#include <linux/clk.h> -#include <linux/clkdev.h> -#include <linux/sizes.h> - -#include <mach/pxa/devices.h> -#include <mach/pxa/mfp-pxa3xx.h> -#include <mach/pxa/pxa-regs.h> - -#include <asm/armlinux.h> -#include <asm/io.h> -#include <asm/mmu.h> -#include <asm/mach-types.h> - -static struct smc91c111_pdata smsc91x_pdata; -static struct mrvl_nand_platform_data nand_pdata = { - .keep_config = 0, - .flash_bbt = 1, -}; - -static mfp_cfg_t pxa310_mfp_cfg[] = { - /* FFUART */ - MFP_CFG_LPM(GPIO99, AF1, FLOAT), /* GPIO99_UART1_RXD */ - MFP_CFG_LPM(GPIO100, AF1, FLOAT), /* GPIO100_UART1_RXD */ - MFP_CFG_LPM(GPIO101, AF1, FLOAT), /* GPIO101_UART1_CTS */ - MFP_CFG_LPM(GPIO106, AF1, FLOAT), /* GPIO106_UART1_CTS */ - - /* Ethernet */ - MFP_CFG(GPIO2, AF1), /* GPIO2_nCS3 */ -}; - -static int zylonite_devices_init(void) -{ - struct clk *clk; - - armlinux_set_architecture(MACH_TYPE_ZYLONITE); - pxa_add_uart((void *)0x40100000, 0); - add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, - 0x14000300, 0x100000, IORESOURCE_MEM, - &smsc91x_pdata); - clk = clk_get_sys("nand", NULL); - if (!IS_ERR(clk)) - clkdev_add_physbase(clk, 0x43100000, NULL); - add_generic_device("mrvl_nand", DEVICE_ID_DYNAMIC, NULL, - 0x43100000, 0x1000, IORESOURCE_MEM, &nand_pdata); - devfs_add_partition("nand0", SZ_1M, SZ_256K, DEVFS_PARTITION_FIXED, - "env0"); - return 0; -} -device_initcall(zylonite_devices_init); - -static int zylonite_coredevice_init(void) -{ - barebox_set_model("Zylonite"); - barebox_set_hostname("zylonite"); - - mfp_init(); - if (cpu_is_pxa310()) - pxa3xx_mfp_config(pxa310_mfp_cfg, ARRAY_SIZE(pxa310_mfp_cfg)); - CKENA |= CKEN_NAND | CKEN_SMC | CKEN_FFUART | CKEN_GPIO; - /* - * Configure Ethernet controller : - * MCS1: setup VLIO on nCS3, with 15 DF_SCLK cycles (max) for hold, - * setup and assertion times - * CSADRCFG3: DFI AA/D multiplexing VLIO, addr split at bit <16>, full - * latched mode, 7 DF_SCLK cycles (max) for nLUA and nLLA. - */ - MSC1 = 0x7ffc0000 | (MSC1 & 0x0000ffff); - CSADRCFG3 = 0x003e080b; - - return 0; -} -coredevice_initcall(zylonite_coredevice_init); - -static int zylonite_mem_init(void) -{ - arm_add_mem_device("ram0", 0x80000000, 64 * 1024 * 1024); - return 0; -} -mem_initcall(zylonite_mem_init); diff --git a/arch/arm/boards/zylonite/env/boot/nand-ubi b/arch/arm/boards/zylonite/env/boot/nand-ubi deleted file mode 100644 index 2231738224..0000000000 --- a/arch/arm/boards/zylonite/env/boot/nand-ubi +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -global.bootm.image="/dev/nand0.kernel" -#global.bootm.oftree="/env/oftree" -global.linux.bootargs.dyn.root="root=ubi0:linux_root ubi.mtd=nand.root rootfstype=ubifs" diff --git a/arch/arm/boards/zylonite/env/init/mtdparts-nand b/arch/arm/boards/zylonite/env/init/mtdparts-nand deleted file mode 100644 index 749318b59e..0000000000 --- a/arch/arm/boards/zylonite/env/init/mtdparts-nand +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/sh - -mtdparts="128k@0(TIMH)ro,128k@128k(OBMI)ro,768k@256k(barebox),256k@1024k(barebox-env),12M@1280k(kernel),38016k@13568k(root)" -kernelname="pxa3xx_nand-0" - -mtdparts-add -d nand0 -k ${kernelname} -p ${mtdparts} diff --git a/arch/arm/boards/zylonite/env/nv/hostname b/arch/arm/boards/zylonite/env/nv/hostname deleted file mode 100644 index 6e6d865eda..0000000000 --- a/arch/arm/boards/zylonite/env/nv/hostname +++ /dev/null @@ -1 +0,0 @@ -zylonite diff --git a/arch/arm/boards/zylonite/env/nv/linux.bootargs.base b/arch/arm/boards/zylonite/env/nv/linux.bootargs.base deleted file mode 100644 index 317f8b16a1..0000000000 --- a/arch/arm/boards/zylonite/env/nv/linux.bootargs.base +++ /dev/null @@ -1 +0,0 @@ -ram=64M diff --git a/arch/arm/boards/zylonite/env/nv/linux.bootargs.console b/arch/arm/boards/zylonite/env/nv/linux.bootargs.console deleted file mode 100644 index 476b1fbe49..0000000000 --- a/arch/arm/boards/zylonite/env/nv/linux.bootargs.console +++ /dev/null @@ -1 +0,0 @@ -console=ttyS0,115200 diff --git a/arch/arm/boards/zylonite/lowlevel.c b/arch/arm/boards/zylonite/lowlevel.c deleted file mode 100644 index 972fd34761..0000000000 --- a/arch/arm/boards/zylonite/lowlevel.c +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <common.h> -#include <linux/sizes.h> -#include <asm/barebox-arm-head.h> -#include <asm/barebox-arm.h> - -void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2) -{ - arm_cpu_lowlevel_init(); - barebox_arm_entry(0x80000000, SZ_64M, NULL); -} |