OSELAS.BSP-EnergyMicro-Gecko: enable framebuffer support

The hard work of adapting the bootloader to let it setup the framebuffer
was done by Alexandru Ciprian Iordan.

2 files changed, 263 insertions, 4 deletions

diff --git a/configs/ptxconfig b/configs/ptxconfig
index f600288..bd94e56 100644
--- a/configs/ptxconfig
+++ b/configs/ptxconfig
@@ -1380,7 +1380,7 @@ PTXCONF_BUSYBOX_FEATURE_SH_EXTRA_QUIET=y
 # PTXCONF_FBGRAB is not set
 # PTXCONF_FBSET is not set
 # PTXCONF_FBTERM is not set
-# PTXCONF_FBTEST is not set
+PTXCONF_FBTEST=y
 # PTXCONF_FBUTILS is not set
 # PTXCONF_FBV is not set
 # PTXCONF_SPLASHUTILS is not set
diff --git a/local_src/geckoboot-2013.01.0/geckoboot.S b/local_src/geckoboot-2013.01.0/geckoboot.S
index 3e7ae76..709996f 100644
--- a/local_src/geckoboot-2013.01.0/geckoboot.S
+++ b/local_src/geckoboot-2013.01.0/geckoboot.S
@@ -80,23 +80,25 @@ printch:
 reset:
 	/* init external RAM, serial port, EBI and stuff */
 	adr	r0, reginit
+	ldr 	r5, =(reginit_end)
 1:
 	ldr	r1, [r0]
 	ldr	r2, [r0, #4]
 	str	r2, [r1]
 	add	r0, r0, #8
-	cmp	r0, #(reginit_end)
+	cmp	r0, r5
 	blo	1b
 
 	/* init some BC registers */
 	adr	r0, bcinit
+	ldr 	r5, =(bcinit_end)
 1:
 	ldrh	r1, [r0]
 	ldrh	r2, [r0, #2]
 	add	r1, r1, #BC_REGISTER
 	strh	r2, [r1]
 	add	r0, r0, #4
-	cmp	r0, #(bcinit_end)
+	cmp	r0, r5
 	blo	1b
 
 	/* give mux some time to enable the level shifter */
@@ -123,6 +125,7 @@ reset:
 	beq	1b
 
 	adr	r0, swoinit
+	ldr	r5, =(swoinit_end)
 1:
 	ldmia	r0!, {r1, r2, r3} /* load addr, mask, value */
 	teq	r2, #0xffffffff
@@ -130,7 +133,7 @@ reset:
 	bicne	r4, r2
 	orrne	r3, r4
 	str	r3, [r1]
-	cmp	r0, #(swoinit_end)
+	cmp	r0, r5
 	blo	1b
 
 wait_boot_linux:
@@ -144,9 +147,164 @@ wait_boot_linux:
 #else
 	putc	#'c'
 #endif
+/*      TFT setup             */
+	/*wait for AEM button*/
+	ldr r0, =(BC_REGISTER)
+	putc	#'\r'
+	putc	#'\n'
+wait:
+        putc 	#'P'
+        putc 	#'r'
+        putc 	#'e'
+        putc 	#'s'
+        putc 	#'s'
+        putc 	#' '
+        putc 	#'t'
+        putc 	#'h'
+        putc 	#'e'
+        putc 	#' '
+        putc 	#'A'
+        putc 	#'E'
+        putc 	#'M'
+        putc 	#' '
+        putc 	#'b'
+        putc 	#'u'
+        putc 	#'t'
+        putc 	#'t'
+        putc 	#'o'
+        putc 	#'n'
+        putc 	#'!'
+	putc	#'\r'
+	putc	#'\n'
+	/*pause*/
+        ldr r1, =0x700000
+1:
+	ldrh 	r2, [r0, 0xe]
+	cmp 	r2, #1
+	beq 	aempress
+        subs 	r1, r1, #1
+	bne	1b
+	b 	wait
+	
+aempress:
+	putc	#'O'
+	putc	#'K'
+	putc	#'\r'
+	putc	#'\n'
+	adr 	r0, tft1
+	ldr	r5, =(tft1_end)
+1:
+        ldrh    r1, [r0]
+        ldrh    r2, [r0, #2]
+        add     r1, r1, #BC_REGISTER
+        strh    r2, [r1]
+        add     r0, r0, 4
+        cmp     r0, r5
+        blo     1b
+	/*pause*/
+	ldr     r0, =0x75400
+1:      subs    r0, r0, #1
+        bne     1b
+
+	adr r0, tft2
+	ldr	r5, =(tft2_end)
+1:
+        ldrh    r1, [r0]
+        ldrh    r2, [r0, #2]
+        add     r1, r1, #BC_REGISTER
+        strh    r2, [r1]
+        add     r0, r0, 4
+        cmp     r0, r5
+        blo     1b
+
+	adr 	r0, tft3
+	ldr	r5, =(tft3_end)
+1:
+        ldr     r1, [r0]
+        ldr     r2, [r0, #4]
+        str     r2, [r1]
+        add     r0, r0, #8
+        cmp     r0, r5
+        blo     1b
+
+        adr r0, tft4
+	ldr	r5, =(tft4_end)
+spi:
+        ldr r1, [r0]
+        ldr r2, [r0, #4]
+        /*start with a pause*/
+        ldr     r3, =0x20000
+1:	subs    r3, r3, #1
+        bne     1b
+        /*clear port D of GPIO to enable chip select*/
+        ldr r3, =0x40006080
+        ldr r4, =0x8
+        str r4, [r3]
+        /*select register*/
+        ldr r3, =0x4000C400
+        ldr r3, [r3]
+        bic r3, r3, #0x200000
+        ldr r4, =0x4000C400
+        str r3, [r4]
+        /*write register on Tx*/
+        str r1, [r4, #0x34]
+        /*check that transmit buffer is empty*/
+        bl checkt
+        /*read data from Rx*/
+        ldr r3, [r4, #0x1c]
+        /*check that read buffer is empty*/
+        bl checkr
+        /*write data*/
+        ldr r3, [r4]
+        orr r3, r3, #0x200000
+	str r3, [r4]
+        /*write data high on Tx*/
+        lsr r3, r2, #8
+        str r3, [r4, #0x34]
+        bl checkt
+        /*read data from Rx*/
+        ldr r3, [r4, #0x1c]
+        bl checkr
+        /*write data low on Tx*/
+        mov r3, r2
+        uxtb r3, r3
+        str r3, [r4, #0x34]
+        bl checkt
+        /*read data from Rx*/
+        ldr r3, [r4, #0x1c]
+        bl checkr
+        /*set port D of GPIO to enable chip select*/
+        ldr r3, =0x4000607C
+        ldr r4, =0x8
+        str r4, [r3]
+        add r0, r0, #8
+        cmp r0, r5
+        blo spi
+
+	adr r0, tft5
+	ldr	r5, =(tft5_end)
+1:
+        ldr     r1, [r0]
+        ldr     r2, [r0, #4]
+        str     r2, [r1]
+        add     r0, r0, #8
+        cmp     r0, r5
+        blo     1b
+
+	/*clear display*/
+	ldr r0, =0x883da000
+	ldr r1, =0x0000
+	ldr r2, =0x12C00
+1:
+        strh r1, [r0]
+        add r0, r0, #2
+        subs r2, r2, #1
+        bne 1b
 
 boot_linux:
 	putc	#'k'
+	putc	#'\r'
+	putc	#'\n'
 
 	/* Copy oftree to RAM */
 	ldr	r0, =(DTB_DST)
@@ -180,6 +338,20 @@ memcpy:
 	bhi	memcpy
 	bx	lr
 
+	/*check that transmit buffer is empty*/
+checkt:
+        ldr r3, [r4, #0x10]
+        tst r3, #0x40
+        beq checkt
+        bx lr
+
+        /*check that read buffer is empty*/
+checkr:
+        ldr r3, [r4, #0x10]
+        tst r3, #0x80
+        beq checkr
+        bx lr
+
 	.ltorg
 
 	.align 3
@@ -343,3 +515,90 @@ swoinit:
 	.int	0xe0000e80, 0xffffffff, 0x00010009	@ output data
 swoinit_end:
 	.size	swoinit, . - swoinit
+
+	.align 3
+        .type   tft1, %object
+tft1:
+	.short	0x001a, 0x0002		@ Enable SPI to SSD2119
+	.short	0x0018, 0x1701		@ enable UART mux, ETH and spi
+	.short	0x0016, 0x0001		@ BSP_DisplayControl(BSP_Display_EBI)
+	.short	0x0012, 0x0002		@ BSP_DisplayControl(BSP_Display_ResetAssert)
+tft1_end:
+	.size tft1, . - tft1
+
+	.align 3
+        .type   tft2, %object
+tft2:
+	.short  0x0012, 0x0006       	@ BSP_DisplayControl(BSP_Display_ModeGeneric)
+        .short  0x0012, 0x0007       	@ BSP_DisplayControl(BSP_Display_PowerEnable)
+        .short  0x0012, 0x0005       	@ BSP_DisplayControl(BSP_Display_ResetRelease)
+        .short  0x0012, 0x0005       	@ BSP_DisplayControl(BSP_Display_ResetRelease)
+tft2_end:
+	.size tft2, . - tft2
+
+	.align 3
+        .type   tft3, %object
+tft3:
+	.int    0x40006014, 0x00008f7f          @ GPIO_PA_DOUTCLR; EBI AD8..11 set dataout to 1
+	.int    0x40006008, 0x40004444          @ GPIO_PA_MODEH; EBI AD8..11 set mode=pushpull
+	/*CMU clock*/
+        .int    0x43900120, 0x00000001          @ CMU_ClockEnable(cmuClock_HFPER, true)
+	.int    0x43900884, 0x00000001          @ CMU_ClockEnable(cmuClock_USART1, true)
+	.int	0x439008B4, 0x00000001		@ CMU_ClockEnable(cmuClock_GPIO, true)
+	/*GPIO_PinModeSet(gpioPortD)*/
+	.int    0x40006080, 0x00000007          @ GPIO_PD_DOUTCLR, ETH_SPI_{TX, RX, CLK}
+	.int    0x4000607c, 0x0000fe08          @ GPIO_PD_DOUTSET, EBI CS0-3, spiconnect set dataout to 1; ETH_SPI_#CS (D3)
+	.int    0x40006070, 0x00004414          @ GPIO_PD_MODEL; ETH_SPI_
+	/*USART_Reset(USART1)*/
+	.int    0x4000C40C, 0x00000eaa          @ USART1->CMD = USART_CMD_RXDIS | USART_CMD_TXDIS | USART_CMD_MASTERDIS | USART_CMD_RXBLOCKDIS | USART_CMD_TXTRIDIS | USART_CMD_CLEARTX | USART_CMD_CLEARRX
+	.int    0x4000C400, 0x00000000          @ USART1->CTRL = _USART_CTRL_RESETVALUE
+	.int    0x4000C404, 0x00001005          @ USART1->FRAME = _USART_FRAME_RESETVALUE
+	.int    0x4000C408, 0x00000000          @ USART1->TRIGCTRL = _USART_TRIGCTRL_RESETVALUE
+	.int    0x4000C414, 0x00000000          @ USART1->CLKDIV = _USART_CLKDIV_RESETVALUE
+	.int    0x4000C44C, 0x00000000          @ USART1->IEN = _USART_IEN_RESETVALUE
+	.int    0x4000C448, 0x00001ff9          @ USART1->IFC = _USART_IFC_MASK
+	.int    0x4000C454, 0x00000000          @ USART1->ROUTE = _USART_ROUTE_RESETVALUE;
+        .int    0x4000C458, 0x00000000          @ USART1->INPUT = _USART_INPUT_RESETVALUE;
+        .int    0x4000C45C, 0x00000000          @ USART1->I2SCTRL = _USART_I2SCTRL_RESETVALUE
+	/*USART_InitSync(USART1, &inittft)*/
+	.int    0x4000C400, 0x00000701          @ USART1->CTRL |= (USART_CTRL_SYNC) | ((uint32_t)init->clockMode) | (init->msbf ? USART_CTRL_MSBF : 0)
+	.int    0x4000C404, 0x00001006          @ USART1->FRAME = ((uint32_t)(init->databits)) | (USART_FRAME_STOPBITS_DEFAULT) | (USART_FRAME_PARITY_DEFAULT)
+	.int    0x4000C414, 0x00001700          @ USART_BaudrateSyncSet(USART1, init->refFreq, init->baudrate)
+        .int    0x4000C40C, 0x00000015          @ USART1->CMD = USART_CMD_MASTEREN; USART1->CMD = (uint32_t)(init->enable)
+        .int    0x4000C454, 0x0000010b          @ USART1->ROUTE = USART_ROUTE_TXPEN | USART_ROUTE_RXPEN | USART_ROUTE_CLKPEN | USART_ROUTE_LOCATION_LOC1
+tft3_end:
+	.size tft3, . - tft3
+
+	.align 3
+        .type   tft4, %object
+tft4:
+	.int    0x00000028, 0x00000006     @ DMD_SSD2119_VCOM_OTP_1
+        .int    0x00000007, 0x00000023     @ DMD_SSD2119_DISPLAY_CONTROL
+        .int    0x00000010, 0x00000000     @ DMD_SSD2119_SLEEP_MODE_1
+        .int    0x00000007, 0x00000033     @ DMD_SSD2119_DISPLAY_CONTROL
+        .int    0x00000011, 0x00006730     @ DMD_SSD2119_ENTRY_MODE
+        .int    0x00000001, 0x000030ef     @ DMD_SSD2119_DRIVER_OUTPUT_CONTROL
+        .int    0x00000002, 0x00000600     @ DMD_SSD2119_LCD_AC_CONTROL
+        .int    0x00000022, 0x000000ff     @ DMD_SSD2119_ACCESS_DATA
+tft4_end:
+	.size tft4, . - tft4
+
+	.align 3
+        .type   tft5, %object
+tft5:
+	 /*Configure EBI TFT direct drive*/
+        .int    0x40008064, 0x003da000          @ EBI_TFTFrameBaseSet(ebiTFTInit->addressOffset)
+        .int    0x4000806C, 0x00EF013F          @ EBI_TFTSizeSet(ebiTFTInit->hsize, ebiTFTInit->vsize)
+        .int    0x40008070, 0x00780101          @ EBI_TFTHPorchSet(ebiTFTInit->hPorchFront, ebiTFTInit->hPorchBack, ebiTFTInit->hPulseWidth)
+        .int    0x40008074, 0x00100101          @ EBI_TFTVPorchSet(ebiTFTInit->vPorchFront, ebiTFTInit->vPorchBack, ebiTFTInit->vPulseWidth)
+        .int    0x40008078, 0x00000008          @ EBI_TFTTimingSet(ebiTFTInit->dclkPeriod, ebiTFTInit->startPosition, ebiTFTInit->setupCycles, ebiTFTInit->holdCycles)
+        .int    0x42100F80, 0x00000000          @ EBI_PolaritySet(ebiLineTFTCS, ebiTFTInit->csPolarity)
+        .int    0x42100F84, 0x00000001          @ EBI_PolaritySet(ebiLineTFTDClk, ebiTFTInit->dclkPolarity)
+        .int    0x42100F88, 0x00000000          @ EBI_PolaritySet(ebiLineTFTDataEn, ebiTFTInit->dataenPolarity)
+        .int    0x42100F90, 0x00000000          @ EBI_PolaritySet(ebiLineTFTVSync, ebiTFTInit->vsyncPolarity)
+        .int    0x42100F8C, 0x00000000          @ EBI_PolaritySet(ebiLineTFTHSync, ebiTFTInit->hsyncPolarity)
+        .int    0x4000805C, 0x00210002          @ EBI->TFTCTRL = ctrl modified
+	.int    0x40008014, 0x115e00bf          @ EBI->ROUTE |= (EBI_ROUTE_TFTPEN)
+        .int    0x40008068, 0x00000000          @ EBI_TFTHStrideSet((V_WIDTH - D_WIDTH) * 2)
+tft5_end:
+	.size tft5, . - tft5