diff options
| author | Juergen Beisert <jbe@pengutronix.de> | 2012-08-11 00:54:04 +0200 |
|---|---|---|
| committer | Juergen Beisert <jbe@pengutronix.de> | 2012-08-11 00:54:04 +0200 |
| commit | f1d7f9abcdd4f5b9a7c58c91458d69e25a3f8ec6 (patch) | |
| tree | 3cd19aeba78b4a21d384d044253c749b9bd9d254 | |
| parent | c36e5dfaaeea8a91c224c443342446dce9519063 (diff) | |
| download | OSELAS.BSP-Pengutronix-ChumbyOne-f1d7f9abcdd4f5b9a7c58c91458d69e25a3f8ec6.tar.gz OSELAS.BSP-Pengutronix-ChumbyOne-f1d7f9abcdd4f5b9a7c58c91458d69e25a3f8ec6.tar.xz | |
Platform: add the initial platform
Signed-off-by: Juergen Beisert <jbe@pengutronix.de>
79 files changed, 61287 insertions, 0 deletions
@@ -1,3 +1,7 @@ +2012-08-11 Juergen Beisert <jbe@pengutronix.de> + + * Platform: add initial platform + 2011-05-15 Juergen Beisert <jbe@pengutronix.de> * Board Support Package: Create initial revision diff --git a/configs/platform-chumby/Changelog b/configs/platform-chumby/Changelog new file mode 100644 index 0000000..f5c345d --- /dev/null +++ b/configs/platform-chumby/Changelog @@ -0,0 +1,15 @@ +2011-01-25 Juergen Beisert <jbe@pengutronix.de> + + * Platform: Release + +2010-10-07 Juergen Beisert <jbe@pengutronix.de> + + * Platform: Adding some local config files. Not all tested at runtime + yet + * barebox: working version added. Can boot from SD card and also store + all relevant data to it (environment) + +2010-09-09 Juergen Beisert <jbe@pengutronix.de> + + * kernel: Adding the 2.6.28 chumby kernel for reference only + * kernel: Starting development diff --git a/configs/platform-chumby/barebox-2010.11.0.config b/configs/platform-chumby/barebox-2010.11.0.config new file mode 100644 index 0000000..4f90e06 --- /dev/null +++ b/configs/platform-chumby/barebox-2010.11.0.config @@ -0,0 +1,264 @@ +# +# Automatically generated make config: don't edit +# Linux barebox version: 2010.11.0 +# +# CONFIG_BOARD_LINKER_SCRIPT is not set +CONFIG_GENERIC_LINKER_SCRIPT=y +CONFIG_ARM=y + +# +# System Type +# +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_IMX is not set +CONFIG_ARCH_STM=y +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_NOMADIK is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_S3C24xx is not set + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y + +# +# processor features +# +CONFIG_ARCH_TEXT_BASE=0x42000000 +CONFIG_BOARDINFO="Chumby Falconwing" + +# +# SigmaTel/Freescale i.MX System-on-Chip +# +CONFIG_ARCH_IMX23=y +# CONFIG_ARCH_IMX28 is not set +# CONFIG_MACH_MX23EVK is not set +CONFIG_MACH_CHUMBY=y + +# +# Board specific settings +# +# CONFIG_MACH_CHUMBY_RESERVE_VIDMEM is not set +CONFIG_AEABI=y + +# +# Arm specific settings +# +CONFIG_CMD_ARM_CPUINFO=y +CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y +CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG" +CONFIG_GREGORIAN_CALENDER=y +CONFIG_HAS_KALLSYMS=y +CONFIG_HAS_MODULES=y +CONFIG_CMD_MEMORY=y +CONFIG_ENV_HANDLING=y +CONFIG_GENERIC_GPIO=y + +# +# General Settings +# +CONFIG_LOCALVERSION_AUTO=y + +# +# memory layout +# +CONFIG_HAVE_MMU=y +# CONFIG_MMU is not set +CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y +CONFIG_TEXT_BASE=0x42000000 +CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y +CONFIG_MEMORY_LAYOUT_DEFAULT=y +# CONFIG_MEMORY_LAYOUT_FIXED is not set +CONFIG_STACK_SIZE=0x8000 +CONFIG_MALLOC_SIZE=0x400000 +CONFIG_BROKEN=y +# CONFIG_EXPERIMENTAL is not set +# CONFIG_KALLSYMS is not set +CONFIG_PROMPT="chumby:" +CONFIG_BAUDRATE=115200 +CONFIG_LONGHELP=y +CONFIG_CBSIZE=1024 +CONFIG_MAXARGS=16 +CONFIG_SHELL_HUSH=y +# CONFIG_SHELL_SIMPLE is not set +# CONFIG_GLOB is not set +CONFIG_PROMPT_HUSH_PS2="> " +# CONFIG_HUSH_FANCY_PROMPT is not set +# CONFIG_HUSH_GETOPT is not set +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +# CONFIG_MENU is not set +# CONFIG_PASSWORD is not set +CONFIG_DYNAMIC_CRC_TABLE=y +CONFIG_ERRNO_MESSAGES=y +CONFIG_TIMESTAMP=y +CONFIG_CONSOLE_FULL=y +CONFIG_CONSOLE_ACTIVATE_FIRST=y +# CONFIG_OF_FLAT_TREE is not set +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT=y +# CONFIG_DEFAULT_ENVIRONMENT_GENERIC is not set +CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/chumby_falconwing/env" + +# +# Debugging +# +CONFIG_DEBUG_INFO=y +# CONFIG_ENABLE_FLASH_NOISE is not set +# CONFIG_ENABLE_PARTITION_NOISE is not set +# CONFIG_ENABLE_DEVICE_NOISE is not set + +# +# Commands +# + +# +# scripting +# +CONFIG_CMD_EDIT=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TRUE=y +CONFIG_CMD_FALSE=y +# CONFIG_CMD_LOGIN is not set +# CONFIG_CMD_PASSWD is not set + +# +# file commands +# +CONFIG_CMD_LS=y +CONFIG_CMD_RM=y +CONFIG_CMD_CAT=y +CONFIG_CMD_MKDIR=y +CONFIG_CMD_RMDIR=y +CONFIG_CMD_CP=y +CONFIG_CMD_PWD=y +CONFIG_CMD_CD=y +CONFIG_CMD_MOUNT=y +CONFIG_CMD_UMOUNT=y + +# +# console +# +CONFIG_CMD_CLEAR=y +CONFIG_CMD_ECHO=y +CONFIG_CMD_ECHO_E=y + +# +# memory +# +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +# CONFIG_CMD_MEMINFO is not set +# CONFIG_CMD_CRC is not set +CONFIG_CMD_MTEST=y +CONFIG_CMD_MTEST_ALTERNATIVE=y + +# +# flash +# +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_UBI is not set + +# +# booting +# +CONFIG_CMD_BOOTM=y +# CONFIG_CMD_BOOTM_ZLIB is not set +# CONFIG_CMD_BOOTM_BZLIB is not set +# CONFIG_CMD_BOOTM_SHOW_TYPE is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_BOOTU=y +CONFIG_CMD_RESET=y +# CONFIG_CMD_GO is not set +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_TEST=y +CONFIG_CMD_VERSION=y +CONFIG_CMD_HELP=y +CONFIG_CMD_DEVINFO=y +CONFIG_CMD_BMP=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_UNLZO is not set +# CONFIG_NET is not set + +# +# Drivers +# + +# +# serial drivers +# +# CONFIG_DRIVER_SERIAL_ARM_DCC is not set +CONFIG_DRIVER_SERIAL_STM378X=y +# CONFIG_DRIVER_SERIAL_NS16550 is not set + +# +# SPI drivers +# +# CONFIG_SPI is not set +# CONFIG_I2C is not set + +# +# flash drivers +# +# CONFIG_DRIVER_CFI is not set +# CONFIG_MTD is not set +CONFIG_ATA=y + +# +# drive types +# +CONFIG_ATA_DISK=y + +# +# interface types +# +# CONFIG_USB is not set +# CONFIG_USB_GADGET is not set +CONFIG_VIDEO=y + +# +# runtime options +# +CONFIG_VIDEO_INFO_VERBOSE=y + +# +# drivers +# +CONFIG_DRIVER_VIDEO_STM=y +CONFIG_MCI=y + +# +# --- Feature list --- +# +CONFIG_MCI_STARTUP=y +CONFIG_MCI_INFO=y + +# +# --- MCI host drivers --- +# +CONFIG_MCI_STM378X=y + +# +# MFD +# + +# +# Filesystem support +# +# CONFIG_FS_CRAMFS is not set +CONFIG_FS_RAMFS=y +CONFIG_FS_DEVFS=y +CONFIG_CRC32=y +# CONFIG_DIGEST is not set +# CONFIG_GENERIC_FIND_NEXT_BIT is not set +CONFIG_PROCESS_ESCAPE_SEQUENCE=y diff --git a/configs/platform-chumby/barebox-defaultenv/bin/boot b/configs/platform-chumby/barebox-defaultenv/bin/boot new file mode 100644 index 0000000..b1d2e3e --- /dev/null +++ b/configs/platform-chumby/barebox-defaultenv/bin/boot @@ -0,0 +1,38 @@ +#!/bin/sh + +. /env/config + +if [ x$1 = xdisk ]; then + rootfs_loc=disk + kernel_loc=disk +elif [ x$1 = xnet ]; then + rootfs_loc=net + kernel_loc=net +fi + +if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" +elif [ x$ip = xnone ]; then + bootargs="$bootargs ip=none" +else + bootargs="$bootargs ip=$eth0.ipaddr::$eth0.gateway:$eth0.netmask:::" +fi + +if [ x$rootfs_loc = xdisk ]; then + bootargs="$bootargs noinitrd rootfstype=$rootfs_type root=/dev/$rootfs_part" +elif [ x$rootfs_loc = xnet ]; then + bootargs="$bootargs root=/dev/nfs nfsroot=$nfsroot,v3,tcp noinitrd" +elif [ x$rootfs_loc = xinitrd ]; then + bootargs="$bootargs root=/dev/ram0 rdinit=/sbin/init" +fi + +if [ x$kernelimage_type = xuimage ]; then + bootm -a 0x000006c5 /dev/$kernel_part +elif [ x$kernelimage_type = xzimage ]; then + bootz /dev/$kernel_part +else + echo "Booting failed. Correct setup of 'kernelimage_type'?" + exit +fi + +echo "Booting failed. Correct setup of 'kernel_part'?" diff --git a/configs/platform-chumby/barebox-defaultenv/bin/init b/configs/platform-chumby/barebox-defaultenv/bin/init new file mode 100644 index 0000000..76c8019 --- /dev/null +++ b/configs/platform-chumby/barebox-defaultenv/bin/init @@ -0,0 +1,31 @@ +#!/bin/sh + +PATH=/env/bin +export PATH + +. /env/config + +# enable the display on demand +if [ -e /dev/fb0 ]; then + # set its RESET# pin to high (activate the glass) + gpio_set_value 50 1 + # setup the mode to be used + framebuffer0.mode=NMA35 + # enable the video signals + framebuffer0.enable=1 + + if [ -e "$splash_image" ]; then + bmp -f /dev/fb0 $splash_image + fi + # activate the backlight (high is full brightness, low is off) + gpio_set_value 60 1 +fi + +echo +echo -n "Hit any key to stop autoboot: " +timeout -a $autoboot_timeout +if [ $? != 0 ]; then + exit +fi + +boot diff --git a/configs/platform-chumby/barebox-defaultenv/config.in b/configs/platform-chumby/barebox-defaultenv/config.in new file mode 100644 index 0000000..6cdd7d6 --- /dev/null +++ b/configs/platform-chumby/barebox-defaultenv/config.in @@ -0,0 +1,39 @@ +#!/bin/sh + +machine=falconwing + +# use 'dhcp' to do dhcp in barebox and in kernel +# use 'none' if you want to skip kernel ip autoconfiguration +ip=none + +# or set your networking parameters here (if a USB network adapter is attached) +#eth0.ipaddr=@PTXCONF_BOARDSETUP_TARGETIP@ +#eth0.netmask=@PTXCONF_BOARDSETUP_NETMASK@ +#eth0.gateway=@PTXCONF_BOARDSETUP_GATEWAY@ +#eth0.serverip=@PTXCONF_BOARDSETUP_SERVERIP@ + +# can be either 'net' or 'disk' +kernel_loc=disk +# can be either 'net', or 'disk' or 'initrd' +rootfs_loc=disk + +# can be any regular filesystem like ext2, ext3, reiserfs in case of 'rootfs_loc=disk' +rootfs_type=ext2 +# Where is the rootfs in case of 'rootfs_loc=disk' +rootfs_part=mmcblk0p4 + +# Where is the rootfs in case of 'rootfs_loc=net' +#nfsroot=@PTXCONF_BOARDSETUP_NFSROOT_PATH@ + +# The image type of the kernel. Can be uimage, zimage +kernelimage_type=uimage +# Where to get the kernel image in case of 'kernel_loc=disk' +kernel_part=disk0.2 + +# base kernel parameter +bootargs="console=ttyAM0,@PTXCONF_BOARDSETUP_SERIALBAUDRATE@ debug ro lcd_panel=lms350 ssp1=mmc line=1 sysrq_always_enabled rotary=1" + +autoboot_timeout=0 + +# what splash image should be used +splash_image=/env/splash.bmp diff --git a/configs/platform-chumby/kernelconfig-2.6.28 b/configs/platform-chumby/kernelconfig-2.6.28 new file mode 100644 index 0000000..d7a2874 --- /dev/null +++ b/configs/platform-chumby/kernelconfig-2.6.28 @@ -0,0 +1,1414 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.28 +# +CONFIG_ARM=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_GENERIC_GPIO=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_MMU=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_HARDIRQS=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_HAVE_LATENCYTOP_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_PANIC_TIMEOUT=0 +CONFIG_EMBEDDED=y +CONFIG_UID16=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_EXTRA_PASS=y +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_ASHMEM=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_KMOD=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +CONFIG_CLASSIC_RCU=y +CONFIG_FREEZER=y + +# +# System Type +# +# CONFIG_ARCH_AAEC2000 is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS7500 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_H720X is not set +# CONFIG_ARCH_IMX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP23XX is not set +# CONFIG_ARCH_IXP2000 is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_L7200 is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_NS9XXX is not set +# CONFIG_ARCH_LOKI is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_MXC is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_PNX4008 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C2410 is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_LH7A40X is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP is not set +# CONFIG_ARCH_MSM is not set +CONFIG_ARCH_STMP3XXX=y + +# +# Boot options +# + +# +# Power management +# + +# +# SigmaTel STMP3xxx implementations +# +# CONFIG_ARCH_STMP37XX is not set +CONFIG_ARCH_STMP378X=y +# CONFIG_MACH_STMP37XX is not set +CONFIG_MACH_STMP378X=y +# CONFIG_FB_STMP37XX_LMS350 is not set +# CONFIG_FB_STMP37XX_LMS430 is not set +# CONFIG_FB_STMP378X_TVENC is not set +CONFIG_STMP3XXX_UNIQUE_ID=y +CONFIG_STMP3XXX_UNIQUE_ID_OTP=y +CONFIG_STMP378X_RAM_FREQ_SCALING=y +# CONFIG_STMP378X_RAM_MDDR is not set +CONFIG_STMP378X_RAM_DDR=y + +# +# Processor Type +# +CONFIG_CPU_32=y +CONFIG_CPU_ARM926T=y +CONFIG_CPU_32v5=y +CONFIG_CPU_ABRT_EV5TJ=y +CONFIG_CPU_PABRT_NOIFAR=y +CONFIG_CPU_CACHE_VIVT=y +CONFIG_CPU_COPY_V4WB=y +CONFIG_CPU_TLB_V4WBI=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +CONFIG_ARM_THUMB=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_WRITETHROUGH is not set +# CONFIG_CPU_CACHE_ROUND_ROBIN is not set +# CONFIG_OUTER_CACHE is not set + +# +# Bus support +# +CONFIG_ISA=y +# CONFIG_PCI_SYSCALL is not set +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_VMSPLIT_3G=y +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PREEMPT=y +CONFIG_HZ=100 +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_ARCH_FLATMEM_HAS_HOLES=y +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4096 +# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_ALIGNMENT_TRAP=y + +# +# Boot options +# +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_CMDLINE="console=ttyAM0,115200 mem=64M root=/dev/mmcblk0p2 ro rootwait lcd_panel=lms350 init=/linuxrc" +# CONFIG_XIP_KERNEL is not set +# CONFIG_KEXEC is not set + +# +# CPU Power Management +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_MIN_TICKS=10 +CONFIG_CPU_FREQ_SAMPLING_LATENCY_MULTIPLIER=1000 +# CONFIG_CPU_IDLE is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_HAVE_AOUT=y +# CONFIG_BINFMT_AOUT is not set +# CONFIG_BINFMT_MISC is not set + +# +# Power management options +# +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HAS_WAKELOCK=y +CONFIG_HAS_EARLYSUSPEND=y +CONFIG_WAKELOCK=y +CONFIG_WAKELOCK_STAT=y +CONFIG_USER_WAKELOCK=y +CONFIG_EARLYSUSPEND=y +# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set +# CONFIG_CONSOLE_EARLYSUSPEND is not set +CONFIG_FB_EARLYSUSPEND=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_ANDROID_PARANOID_NETWORK is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +CONFIG_WIRELESS=y +CONFIG_CFG80211=y +CONFIG_NL80211=y +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +CONFIG_MAC80211=y + +# +# Rate control algorithm selection +# +CONFIG_MAC80211_RC_PID=y +# CONFIG_MAC80211_RC_MINSTREL is not set +CONFIG_MAC80211_RC_DEFAULT_PID=y +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set +CONFIG_MAC80211_RC_DEFAULT="pid" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_PNP is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_MISC_DEVICES=y +# CONFIG_ANDROID_PMEM is not set +# CONFIG_TIMED_OUTPUT is not set +# CONFIG_BINDER_IPC is not set +CONFIG_EEPROM_93CX6=m +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_KERNEL_DEBUGGER_CORE is not set +# CONFIG_LOW_MEMORY_KILLER is not set +# CONFIG_LOGGER is not set +# CONFIG_UID_STAT is not set +# CONFIG_ANDROID_RAM_CONSOLE is not set +# CONFIG_C2PORT is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_MII=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +CONFIG_WLAN_80211=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8187 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_P54_COMMON is not set +# CONFIG_IWLWIFI_LEDS is not set +# CONFIG_HOSTAP is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_ZD1211RW is not set +CONFIG_RT2X00=y +# CONFIG_RT2500USB is not set +CONFIG_RT73USB=y +CONFIG_RT2X00_LIB_USB=y +CONFIG_RT2X00_LIB=y +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +# CONFIG_RT2X00_DEBUG is not set + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=m +# CONFIG_USB_NET_CDCETHER is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set +# CONFIG_INPUT_KEYRESET is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_STMP3XXX is not set +CONFIG_KEYBOARD_CHUMBY_BEND=y +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +CONFIG_TOUCHSCREEN_STMP3XXX=y +# CONFIG_TOUCHSCREEN_HTCPEN is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_STMP3XXX_ROTDEC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +# CONFIG_INPUT_UINPUT is not set +# CONFIG_INPUT_GPIO is not set +# CONFIG_INPUT_KEYCHORD is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +CONFIG_DEVMEM=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_STMP_DBG=y +CONFIG_SERIAL_STMP_DBG_CONSOLE=y +# CONFIG_SERIAL_STMP_APP is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_NVRAM is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_DCC_TTY is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_STMP378X=y +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_ELEKTOR is not set +# CONFIG_I2C_PCA_ISA is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_AT24 is not set +# CONFIG_SENSORS_EEPROM is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +CONFIG_POWER_SUPPLY_DEBUG=y +# CONFIG_PDA_POWER is not set +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_BQ27x00 is not set +CONFIG_BATTERY_STMP3XXX=y +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_STMP3XXX_WATCHDOG=m + +# +# ISA-based Watchdog Cards +# +# CONFIG_PCWATCHDOG is not set +# CONFIG_MIXCOMWD is not set +# CONFIG_WDT is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +CONFIG_FB_PTXSTMP=y +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_STMP37XX is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_CHUMBYFBFW is not set +# CONFIG_FB_PRE_INIT_FB is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_CORGI is not set +CONFIG_BACKLIGHT_STMP37XX=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +# CONFIG_SND_SEQUENCER is not set +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=m +CONFIG_SND_STMP3XXX_SOC=m +# CONFIG_SND_STMP3XXX_SOC_STMP3780_DEVB is not set +# CONFIG_SND_STMP3XXX_SOC_STMP3780_DEVB_SPDIF is not set +# CONFIG_SND_SOC_ALL_CODECS is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=m +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# USB HID Boot Protocol drivers +# +# CONFIG_USB_KBD is not set +# CONFIG_USB_MOUSE is not set + +# +# Special HID drivers +# +# CONFIG_HID_COMPAT is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_BRIGHT is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DELL is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +# CONFIG_USB_ARCH_HAS_OHCI is not set +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ARC=y +CONFIG_USB_EHCI_ARC_OTG=y +# CONFIG_USB_STATIC_IRAM is not set +# CONFIG_USB_EHCI_FSL_MC13783 is not set +# CONFIG_USB_EHCI_FSL_1301 is not set +# CONFIG_USB_EHCI_FSL_1504 is not set +CONFIG_USB_EHCI_FSL_UTMI=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=y +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_DPCM is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set +CONFIG_MMC_STMP3XXX=y +# CONFIG_MEMSTICK is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_NEW_LEDS is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_INTF_ALARM is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set + +# +# SPI RTC drivers +# + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_STMP3XXX=y +# CONFIG_DMADEVICES is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_BQ24022 is not set +CONFIG_REGULATOR_STMP3XXX=y +# CONFIG_UIO is not set + +# +# File systems +# +# CONFIG_NILFS is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set + +# +# Layered filesystems +# +# CONFIG_UNION_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_HAVE_FUNCTION_TRACER=y + +# +# Tracers +# +# CONFIG_FUNCTION_TRACER is not set +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_STACK_TRACER is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_ERRORS=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_LL is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0001-Separate-framebuffer-platformdata-and-the-videomode.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0001-Separate-framebuffer-platformdata-and-the-videomode.patch new file mode 100644 index 0000000..6c2f650 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0001-Separate-framebuffer-platformdata-and-the-videomode.patch @@ -0,0 +1,262 @@ +From 9221d2ea8f5e53a884c7d8cc068e06ba7d9148f4 Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:15 +0100 +Subject: [PATCH 01/11] Separate framebuffer platformdata and the videomode + +This patch separates the imx platformdata and its videomode in two structures, +in order to support more than one defined videomode in the boardfile. This +is intended to support runtime videomode selection later on. It also uses +now the same videomode setup style than the imx-fpu based systems (like the +i.MX35). + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c | 28 +++++++++-------- + arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c | 28 +++++++++-------- + arch/arm/boards/guf-neso/board.c | 28 +++++++++-------- + arch/arm/boards/imx21ads/imx21ads.c | 34 +++++++++++---------- + arch/arm/boards/pcm038/pcm038.c | 28 +++++++++-------- + arch/arm/mach-imx/include/mach/imxfb.h | 2 +- + drivers/video/imx.c | 6 ++-- + 7 files changed, 82 insertions(+), 72 deletions(-) + +diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +index 3048c3f..2b53766 100644 +--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c ++++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +@@ -107,20 +107,22 @@ struct imx_nand_platform_data nand_info = { + .hw_ecc = 1, + }; + ++static struct fb_videomode cmo_display = { ++ .name = "CMO-QVGA", ++ .refresh = 60, ++ .xres = 320, ++ .yres = 240, ++ .pixclock = KHZ2PICOS(6500), ++ .hsync_len = 30, ++ .left_margin = 38, ++ .right_margin = 20, ++ .vsync_len = 3, ++ .upper_margin = 15, ++ .lower_margin = 4, ++}; ++ + static struct imx_fb_videomode imxfb_mode = { +- .mode = { +- .name = "CMO-QVGA", +- .refresh = 60, +- .xres = 320, +- .yres = 240, +- .pixclock = KHZ2PICOS(6500), +- .hsync_len = 30, +- .left_margin = 38, +- .right_margin = 20, +- .vsync_len = 3, +- .upper_margin = 15, +- .lower_margin = 4, +- }, ++ .mode = &cmo_display, + .pcr = 0xCAD08B80, + .bpp = 16, + }; +diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +index 4567cba..3ee1057 100644 +--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c ++++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +@@ -167,20 +167,22 @@ static void eukrea_cpuimx27_mmu_init(void) + #endif + + #ifdef CONFIG_DRIVER_VIDEO_IMX ++static struct fb_videomode cmo_display = { ++ .name = "CMO-QVGA", ++ .refresh = 60, ++ .xres = 320, ++ .yres = 240, ++ .pixclock = 156000, ++ .hsync_len = 30, ++ .left_margin = 38, ++ .right_margin = 20, ++ .vsync_len = 3, ++ .upper_margin = 15, ++ .lower_margin = 4, ++}; ++ + static struct imx_fb_videomode imxfb_mode = { +- .mode = { +- .name = "CMO-QVGA", +- .refresh = 60, +- .xres = 320, +- .yres = 240, +- .pixclock = 156000, +- .hsync_len = 30, +- .left_margin = 38, +- .right_margin = 20, +- .vsync_len = 3, +- .upper_margin = 15, +- .lower_margin = 4, +- }, ++ .mode = &cmo_display, + .pcr = 0xFAD08B80, + .bpp = 16,}; + +diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c +index d371dd6..fba43bb 100644 +--- a/arch/arm/boards/guf-neso/board.c ++++ b/arch/arm/boards/guf-neso/board.c +@@ -78,20 +78,22 @@ static struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + ++static struct fb_videomode cpt_display = { ++ .name = "CPT CLAA070LC0JCT", ++ .refresh = 60, ++ .xres = 800, ++ .yres = 480, ++ .pixclock = KHZ2PICOS(27000), ++ .hsync_len = 1, /* DE only sync */ ++ .left_margin = 50, ++ .right_margin = 50, ++ .vsync_len = 1, /* DE only sync */ ++ .upper_margin = 10, ++ .lower_margin = 10, ++}; ++ + static struct imx_fb_videomode imxfb_mode = { +- .mode = { +- .name = "CPT CLAA070LC0JCT", +- .refresh = 60, +- .xres = 800, +- .yres = 480, +- .pixclock = KHZ2PICOS(27000), +- .hsync_len = 1, /* DE only sync */ +- .left_margin = 50, +- .right_margin = 50, +- .vsync_len = 1, /* DE only sync */ +- .upper_margin = 10, +- .lower_margin = 10, +- }, ++ .mode = &cpt_display, + /* + * - TFT style panel + * - clk enabled while idle +diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c +index 3942581..8e145c7 100644 +--- a/arch/arm/boards/imx21ads/imx21ads.c ++++ b/arch/arm/boards/imx21ads/imx21ads.c +@@ -73,24 +73,26 @@ static struct device_d cs8900_dev = { + // IRQ is connected to UART3_RTS + }; + ++static struct fb_videomode sharp_display = { ++ .name = "Sharp-LQ035Q7", ++ .refresh = 60, ++ .xres = 240, ++ .yres = 320, ++ .pixclock = 188679, ++ .left_margin = 6, ++ .right_margin = 16, ++ .upper_margin = 8, ++ .lower_margin = 10, ++ .hsync_len = 2, ++ .vsync_len = 1, ++ .sync = 0, ++ .vmode = FB_VMODE_NONINTERLACED, ++ .flag = 0, ++}; ++ + /* Sharp LQ035Q7DB02 QVGA display */ + static struct imx_fb_videomode imx_fb_modedata = { +- .mode = { +- .name = "Sharp-LQ035Q7", +- .refresh = 60, +- .xres = 240, +- .yres = 320, +- .pixclock = 188679, +- .left_margin = 6, +- .right_margin = 16, +- .upper_margin = 8, +- .lower_margin = 10, +- .hsync_len = 2, +- .vsync_len = 1, +- .sync = 0, +- .vmode = FB_VMODE_NONINTERLACED, +- .flag = 0, +- }, ++ .mode = &sharp_display, + .pcr = 0xfb108bc7, + .bpp = 16, + }; +diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c +index 1dbc6b6..8cbb551 100644 +--- a/arch/arm/boards/pcm038/pcm038.c ++++ b/arch/arm/boards/pcm038/pcm038.c +@@ -107,20 +107,22 @@ static struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + ++static struct fb_videomode sharp_display = { ++ .name = "Sharp-LQ035Q7", ++ .refresh = 60, ++ .xres = 240, ++ .yres = 320, ++ .pixclock = 188679, /* in ps (5.3MHz) */ ++ .hsync_len = 7, ++ .left_margin = 5, ++ .right_margin = 16, ++ .vsync_len = 1, ++ .upper_margin = 7, ++ .lower_margin = 9, ++}; ++ + static struct imx_fb_videomode imxfb_mode = { +- .mode = { +- .name = "Sharp-LQ035Q7", +- .refresh = 60, +- .xres = 240, +- .yres = 320, +- .pixclock = 188679, /* in ps (5.3MHz) */ +- .hsync_len = 7, +- .left_margin = 5, +- .right_margin = 16, +- .vsync_len = 1, +- .upper_margin = 7, +- .lower_margin = 9, +- }, ++ .mode = &sharp_display, + /* + * - HSYNC active high + * - VSYNC active high +diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h +index b71b7f4..a75ad99 100644 +--- a/arch/arm/mach-imx/include/mach/imxfb.h ++++ b/arch/arm/mach-imx/include/mach/imxfb.h +@@ -53,7 +53,7 @@ + #define DMACR_TM(x) ((x) & 0xf) + + struct imx_fb_videomode { +- struct fb_videomode mode; ++ struct fb_videomode *mode; + u32 pcr; + unsigned char bpp; + }; +diff --git a/drivers/video/imx.c b/drivers/video/imx.c +index ac51858..6ccd77e 100644 +--- a/drivers/video/imx.c ++++ b/drivers/video/imx.c +@@ -555,9 +555,9 @@ static int imxfb_probe(struct device_d *dev) + fbi->enable = pdata->enable; + fbi->dev = dev; + info->priv = fbi; +- info->mode = &pdata->mode->mode; +- info->xres = pdata->mode->mode.xres; +- info->yres = pdata->mode->mode.yres; ++ info->mode = pdata->mode->mode; ++ info->xres = pdata->mode->mode->xres; ++ info->yres = pdata->mode->mode->yres; + info->bits_per_pixel = pdata->mode->bpp; + info->fbops = &imxfb_ops; + +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0002-Add-more-flags-for-sync-control.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0002-Add-more-flags-for-sync-control.patch new file mode 100644 index 0000000..072d6ef --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0002-Add-more-flags-for-sync-control.patch @@ -0,0 +1,48 @@ +From 7cf039eac7849535e2f1d4d28e718fc8432323ad Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:15 +0100 +Subject: [PATCH 02/11] Add more flags for sync control + +In order to make video mode setup and initializing a runtime job (currently +it is a compile time job) this patch tries to make the 'fb_videomode' structure +more generic. It should also carry special settings required only for some LC +displays. So, I add some additional sync flags to control the DE and CLCK to +the display (something a regular CRT do not know). Also the possibility to +stop the clock when outside active display data (required for (C)STN). + +Further suggestions for useful flags? + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + include/fb.h | 10 ++++++++++ + 1 files changed, 10 insertions(+), 0 deletions(-) + +diff --git a/include/fb.h b/include/fb.h +index 379f931..218b244 100644 +--- a/include/fb.h ++++ b/include/fb.h +@@ -17,11 +17,21 @@ + /* vtotal = 144d/288n/576i => PAL */ + /* vtotal = 121d/242n/484i => NTSC */ + #define FB_SYNC_ON_GREEN 32 /* sync on green */ ++/* LC display related settings */ ++#define FB_SYNC_DE_HIGH_ACT (1 << 6) ++#define FB_SYNC_CLK_INVERT (1 << 7) ++#define FB_SYNC_DATA_INVERT (1 << 8) ++#define FB_SYNC_CLK_IDLE_EN (1 << 9) ++#define FB_SYNC_SWAP_RGB (1 << 10) ++#define FB_SYNC_CLK_SEL_EN (1 << 11) ++#define FB_SYNC_SHARP_MODE (1 << 31) + + #define FB_VMODE_NONINTERLACED 0 /* non interlaced */ + #define FB_VMODE_INTERLACED 1 /* interlaced */ + #define FB_VMODE_DOUBLE 2 /* double scan */ + #define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */ ++/* LC display related settings */ ++#define FB_VMODE_DUAL_SCAN 8 + #define FB_VMODE_MASK 255 + + #define FB_VMODE_YWRAP 256 /* ywrap instead of panning */ +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0003-Bring-in-dynamic-videomode-selection-at-runtime.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0003-Bring-in-dynamic-videomode-selection-at-runtime.patch new file mode 100644 index 0000000..3c2867d --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0003-Bring-in-dynamic-videomode-selection-at-runtime.patch @@ -0,0 +1,355 @@ +From 328172c067d24a5bb8a08898decda268c83d0e77 Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 03/11] Bring in dynamic videomode selection at runtime + +This patch mostly rewrites all parts of /drivers/video/fb.c. As it changes +the API to the drivers, it must be done in one step to keep the repository +bisectable. But to do it in one step makes the patches itself unreadable. + +So, I decided to do it in a few steps, only for the review. All patches marked +with a "patch n of m" should be merged, prior the final commit onto the +repository. + +This step brings in the required function for dynamic videomode selection at +runtime. + +This is patch 1 of 4 to keep the repository bisectable. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + drivers/video/fb.c | 201 +++++++++++++++++++++++++++++++++++++++++++++------- + include/fb.h | 31 ++++---- + 2 files changed, 192 insertions(+), 40 deletions(-) + +diff --git a/drivers/video/fb.c b/drivers/video/fb.c +index ab2c5eb..5806dbe 100644 +--- a/drivers/video/fb.c ++++ b/drivers/video/fb.c +@@ -1,3 +1,4 @@ ++#include <init.h> + #include <common.h> + #include <fb.h> + #include <errno.h> +@@ -5,9 +6,14 @@ + #include <getopt.h> + #include <fcntl.h> + #include <fs.h> ++#include <malloc.h> ++#include <xfuncs.h> ++ ++#define to_fb_info(x) (container_of(x, struct fb_info, fb_dev)) + + static int fb_ioctl(struct cdev* cdev, int req, void *data) + { ++ struct fb_host *host = cdev->dev->platform_data; + struct fb_info *info = cdev->priv; + + switch (req) { +@@ -15,10 +21,10 @@ static int fb_ioctl(struct cdev* cdev, int req, void *data) + memcpy(data, info, sizeof(*info)); + break; + case FBIO_ENABLE: +- info->fbops->fb_enable(info); ++ host->fb_enable(cdev->priv); + break; + case FBIO_DISABLE: +- info->fbops->fb_disable(info); ++ host->fb_disable(cdev->priv); + break; + default: + return -ENOSYS; +@@ -27,15 +33,47 @@ static int fb_ioctl(struct cdev* cdev, int req, void *data) + return 0; + } + +-static int fb_enable_set(struct device_d *dev, struct param_d *param, +- const char *val) ++static int fb_check_if_already_initialized(struct device_d *fb_dev) ++{ ++ struct fb_info *info = to_fb_info(fb_dev); ++ ++ if (info->enabled) { ++ dev_err(&info->fb_dev, "Video output is active. Cannot change " ++ "until disabled\n"); ++ return -EPERM; ++ } ++ ++ return 0; ++} ++ ++static int fb_cdepth_set(struct device_d *fb_dev, struct param_d *param, const char *val) + { +- struct fb_info *info = dev->priv; ++ struct fb_info *info = to_fb_info(fb_dev); ++ unsigned cdepth; ++ int rc; ++ ++ rc = fb_check_if_already_initialized(fb_dev); ++ if (rc != 0) ++ return rc; ++ ++ cdepth = simple_strtoul(val, NULL, 0); ++ if (cdepth != 0) ++ info->bits_per_pixel = cdepth; ++ else ++ return -EINVAL; ++ ++ return dev_param_set_generic(fb_dev, param, val); ++} ++ ++static int fb_enable_set(struct device_d *fb_dev, struct param_d *param, const char *val) ++{ ++ struct fb_info *info = to_fb_info(fb_dev); ++ struct fb_host *host = info->host; + int enable; + char *new; + + if (!val) +- return dev_param_set_generic(dev, param, NULL); ++ return dev_param_set_generic(fb_dev, param, NULL); + + enable = simple_strtoul(val, NULL, 0); + +@@ -43,20 +81,79 @@ static int fb_enable_set(struct device_d *dev, struct param_d *param, + return 0; + + if (enable) { +- info->fbops->fb_enable(info); ++ host->fb_enable(info); + new = "1"; + } else { +- info->fbops->fb_disable(info); ++ host->fb_disable(info); + new = "0"; + } + +- dev_param_set_generic(dev, param, new); +- + info->enabled = !!enable; + ++ return dev_param_set_generic(fb_dev, param, new); ++} ++ ++static void fb_list_modes(struct fb_host *host) ++{ ++ unsigned u; ++ ++ printf(" Supported video mode(s):\n"); ++ for (u = 0; u < host->mode_cnt; u++) ++ printf(" '%s'\n", host->mode[u].name); ++} ++ ++static int fb_activate_mode(struct device_d *fb_dev, const struct fb_videomode *mode) ++{ ++ struct fb_info *info = to_fb_info(fb_dev); ++ struct fb_host *host = info->host; ++ int rc; ++ ++ rc = host->fb_mode(info, mode); ++ if (rc != 0) ++ return rc; ++ ++ info->active_mode = mode; ++ /* ++ * At this point of time we know the remaining information we need ++ * for the cdev and fb_info structure. ++ */ ++ info->cdev.size = fb_dev->size; ++ info->xres = mode->xres; ++ info->yres = mode->yres; ++ + return 0; + } + ++static int fb_mode_set(struct device_d *fb_dev, struct param_d *param, const char *name) ++{ ++ struct fb_host *host = fb_dev->platform_data; ++ unsigned u; ++ int rc; ++ ++ pr_debug("%s called\n", __func__); ++ ++ rc = fb_check_if_already_initialized(fb_dev); ++ if (rc != 0) ++ return rc; ++ ++ /* Search for the requested video mode by name */ ++ for (u = 0; u < host->mode_cnt; u++) { ++ if (!strcmp(host->mode[u].name, name)) ++ break; ++ } ++ if (u >= host->mode_cnt) { ++ fb_list_modes(host); /* no mode with 'name' found */ ++ return -ENODEV; ++ } else { ++ rc = fb_activate_mode(fb_dev, &host->mode[u]); ++ } ++ ++ if (rc == 0) ++ dev_param_set_generic(fb_dev, param, name); ++ ++ return rc; ++} ++ + static struct file_operations fb_ops = { + .read = mem_read, + .write = mem_write, +@@ -65,31 +162,85 @@ static struct file_operations fb_ops = { + .ioctl = fb_ioctl, + }; + +-int register_framebuffer(struct fb_info *info) ++static int add_fb_parameter(struct fb_info *info) ++{ ++ char cd[10]; ++ ++ /** @todo provide base address parameter for the user. Useful? */ ++ ++ dev_add_param(&info->fb_dev, "cdepth", fb_cdepth_set, NULL, 0); ++ if (info->bits_per_pixel == 0) { ++ dev_set_param(&info->fb_dev, "cdepth", "16"); ++ info->bits_per_pixel = 16; ++ } else { ++ sprintf(cd, "%u", info->bits_per_pixel); ++ dev_set_param(&info->fb_dev, "cdepth", cd); ++ } ++ ++ /* default is 'none' */ ++ dev_add_param(&info->fb_dev, "mode", fb_mode_set, NULL, 0); ++ ++ /* default is '0' for 'no output enabled' */ ++ dev_add_param(&info->fb_dev, "enable", fb_enable_set, NULL, 0); ++ ++ return 0; ++} ++ ++static int fb_probe(struct device_d *fb_dev) + { + int id = get_free_deviceid("fb"); +- struct device_d *dev; ++ struct fb_info *info = to_fb_info(fb_dev); ++ struct fb_host *host = info->host; ++ ++ fb_dev->priv = &info->cdev; /* pointer forward */ ++ info->cdev.dev = fb_dev; /* pointer backward */ ++ info->cdev.priv = info; /* pointer backward */ + + info->cdev.ops = &fb_ops; + info->cdev.name = asprintf("fb%d", id); +- info->cdev.size = info->xres * info->yres * (info->bits_per_pixel >> 3); +- info->cdev.dev = &info->dev; +- info->cdev.priv = info; +- info->cdev.dev->map_base = (unsigned long)info->screen_base; +- info->cdev.dev->size = info->cdev.size; + +- dev = &info->dev; +- dev->priv = info; +- dev->id = id; ++ info->host = host; + +- sprintf(dev->name, "fb"); ++ /* setup defaults */ ++ if (host->bits_per_pixel != 0) ++ info->bits_per_pixel = host->bits_per_pixel; ++ else ++ info->bits_per_pixel = 16; + +- register_device(&info->dev); +- dev_add_param(dev, "enable", fb_enable_set, NULL, 0); +- dev_set_param(dev, "enable", "0"); ++ add_fb_parameter(info); + + devfs_create(&info->cdev); +- + return 0; + } + ++static struct driver_d fb_driver = { ++ .name = "framebuffer", ++ .probe = fb_probe, ++}; ++ ++static int framebuffer_init(void) ++{ ++ return register_driver(&fb_driver); ++} ++ ++device_initcall(framebuffer_init); ++ ++struct device_d *register_framebuffer(struct fb_host *host) ++{ ++ struct fb_info *fb_info; ++ int rc; ++ ++ fb_info = xzalloc(sizeof(struct fb_info)); ++ ++ strcpy(fb_info->fb_dev.name, fb_driver.name); ++ fb_info->host = fb_info->fb_dev.platform_data = (void*)host; ++ ++ rc = register_device(&fb_info->fb_dev); ++ if (rc != 0) { ++ pr_debug("Cannot register framebuffer device\n"); ++ free(fb_info); ++ return NULL; ++ } ++ ++ return &fb_info->fb_dev; ++} +diff --git a/include/fb.h b/include/fb.h +index 218b244..36b2a74 100644 +--- a/include/fb.h ++++ b/include/fb.h +@@ -77,25 +77,26 @@ struct fb_bitfield { + + struct fb_info; + +-struct fb_ops { +- /* set color register */ +- int (*fb_setcolreg)(unsigned regno, unsigned red, unsigned green, +- unsigned blue, unsigned transp, struct fb_info *info); +- void (*fb_enable)(struct fb_info *info); +- void (*fb_disable)(struct fb_info *info); +-}; +- +-struct fb_info { +- struct fb_videomode *mode; ++struct fb_host { ++ const struct fb_videomode *mode; ++ unsigned mode_cnt; + +- struct fb_ops *fbops; +- struct device_d dev; /* This is this fb device */ ++ struct device_d *hw_dev; + +- void *screen_base; ++ /* callbacks into the video hardware driver */ ++ int (*fb_setcolreg)(struct fb_info*, unsigned, unsigned, unsigned, unsigned, unsigned); ++ int (*fb_mode)(struct fb_info*, const struct fb_videomode*); ++ void (*fb_enable)(struct fb_info*); ++ void (*fb_disable)(struct fb_info*); + +- void *priv; ++ unsigned bits_per_pixel; ++}; + ++struct fb_info { ++ struct fb_host *host; ++ struct device_d fb_dev; + struct cdev cdev; ++ const struct fb_videomode *active_mode; + + u32 xres; /* visible resolution */ + u32 yres; +@@ -111,7 +112,7 @@ struct fb_info { + int enabled; + }; + +-int register_framebuffer(struct fb_info *info); ++struct device_d *register_framebuffer(struct fb_host*); + + #define FBIOGET_SCREENINFO _IOR('F', 1, loff_t) + #define FBIO_ENABLE _IO('F', 2) +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0004-Add-verbose-framebuffer-device-info.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0004-Add-verbose-framebuffer-device-info.patch new file mode 100644 index 0000000..7466437 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0004-Add-verbose-framebuffer-device-info.patch @@ -0,0 +1,104 @@ +From 2f070b1194a68d997b8d9661192c97cc7e0a200b Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 04/11] Add verbose framebuffer device info + +This is patch 2 of 4 to keep the repository bisectable. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + drivers/video/Kconfig | 10 ++++++++++ + drivers/video/fb.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 59 insertions(+), 0 deletions(-) + +diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig +index 7a89a3f..b600444 100644 +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -5,6 +5,16 @@ menuconfig VIDEO + + if VIDEO + ++comment "runtime options" ++ ++config VIDEO_INFO_VERBOSE ++ bool "Verbose video info" ++ help ++ Say 'y' here to be more verbose when running the 'devinfo' command ++ on the framebuffer device. ++ ++comment "drivers" ++ + config DRIVER_VIDEO_IMX + bool "i.MX framebuffer driver" + depends on ARCH_IMX1 || ARCH_IMX21 || ARCH_IMX25 || ARCH_IMX27 +diff --git a/drivers/video/fb.c b/drivers/video/fb.c +index 5806dbe..d1ba85a 100644 +--- a/drivers/video/fb.c ++++ b/drivers/video/fb.c +@@ -162,6 +162,54 @@ static struct file_operations fb_ops = { + .ioctl = fb_ioctl, + }; + ++static void fb_info(struct device_d *fb_dev) ++{ ++ struct fb_info *info = to_fb_info(fb_dev); ++ ++ printf(" Video/Mode info:\n"); ++ printf(" Video output %senabled\n", info->enabled != 0 ? "" : "not "); ++ printf(" Current video mode:\n"); ++ if (info->active_mode != NULL) { ++ printf(" Name: %s\n", info->active_mode->name); ++#ifdef CONFIG_VIDEO_INFO_VERBOSE ++ if (info->active_mode->refresh == 0) ++ printf(" Refresh rate: undefined\n"); ++ else ++ printf(" Refresh rate: %u Hz\n", ++ info->active_mode->refresh); ++ printf(" Horizontal active pixel: %u\n", ++ info->active_mode->xres); ++ printf(" Vertical active lines: %u\n", ++ info->active_mode->yres); ++ printf(" Pixel clock: %u kHz\n", ++ PICOS2KHZ(info->active_mode->pixclock)); ++ printf(" Left/Right margin (pixel): %u/%u\n", ++ info->active_mode->left_margin, ++ info->active_mode->right_margin); ++ printf(" Upper/Lower margin (lines): %u/%u\n", ++ info->active_mode->upper_margin, ++ info->active_mode->lower_margin); ++ printf(" HSYNC length in pixel: %u, polarity: %s\n", ++ info->active_mode->hsync_len, ++ (info->active_mode->sync & FB_SYNC_HOR_HIGH_ACT) ? ++ "high" : "low"); ++ printf(" VSYNC length in lines: %u, polarity: %s\n", ++ info->active_mode->vsync_len, ++ (info->active_mode->sync & FB_SYNC_VERT_HIGH_ACT) ? ++ "high" : "low"); ++ printf(" Colour depth: %u bpp\n", info->bits_per_pixel); ++ printf(" Framebuffer size is: %u bytes\n", info->cdev.size); ++ /** @todo Add the remaining information from fb_videomode. ++ * How valuable they are? ++ */ ++#endif ++ } else { ++ printf (" No video mode selected yet\n"); ++ } ++ ++ fb_list_modes(info->host); ++} ++ + static int add_fb_parameter(struct fb_info *info) + { + char cd[10]; +@@ -216,6 +264,7 @@ static int fb_probe(struct device_d *fb_dev) + static struct driver_d fb_driver = { + .name = "framebuffer", + .probe = fb_probe, ++ .info = fb_info, + }; + + static int framebuffer_init(void) +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0005-Adapt-the-existing-imx-fb-driver-to-support-runtime-.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0005-Adapt-the-existing-imx-fb-driver-to-support-runtime-.patch new file mode 100644 index 0000000..d0f782b --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0005-Adapt-the-existing-imx-fb-driver-to-support-runtime-.patch @@ -0,0 +1,402 @@ +From 92604a443fcc81f77a0bc571a739af4041beaa20 Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 05/11] Adapt the existing imx fb driver to support runtime videomode selection + +Adapt the API to the new framebuffer videomode selection at runtime. + +NOTE: Due to the lack of hardware, this is compile time tested only. + +This is patch 3 of 4 to keep the repository bisectable. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/mach-imx/include/mach/imxfb.h | 1 + + drivers/video/imx.c | 209 ++++++++++++++++++------------- + 2 files changed, 122 insertions(+), 88 deletions(-) + +diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h +index a75ad99..4a890a7 100644 +--- a/arch/arm/mach-imx/include/mach/imxfb.h ++++ b/arch/arm/mach-imx/include/mach/imxfb.h +@@ -63,6 +63,7 @@ struct imx_fb_videomode { + */ + struct imx_fb_platform_data { + struct imx_fb_videomode *mode; ++ unsigned mode_cnt; /**< number of entries in 'mode' */ + + u_int cmap_greyscale:1, + cmap_inverse:1, +diff --git a/drivers/video/imx.c b/drivers/video/imx.c +index 6ccd77e..b13f39d 100644 +--- a/drivers/video/imx.c ++++ b/drivers/video/imx.c +@@ -125,6 +125,9 @@ + + #define LCDC_LGWDCR 0x68 + ++#define MAIN_FBUFFER 0 ++#define OVRLY_FBUFFER 1 ++ + /* + * These are the bitfields for each + * display depth that we support. +@@ -137,6 +140,7 @@ struct imxfb_rgb { + }; + + struct imxfb_info { ++ struct fb_host fb_host; /**< myself */ + void __iomem *regs; + + u_int pcr; +@@ -147,16 +151,17 @@ struct imxfb_info { + cmap_static:1, + unused:30; + +- struct imx_fb_videomode *mode; +- +- struct fb_info info; +- struct device_d *dev; +- + void (*enable)(int enable); + +- struct fb_info overlay; ++ struct fb_host fb_overlay; + }; + ++#define fb_overlay_to_imxfb_info(x) \ ++ (container_of((struct fb_host*)(x->host), struct imxfb_info, fb_overlay)) ++#define fb_overlay_dev_to_imxfb_info(x) \ ++ (container_of((struct fb_host*)(x->platform_data), struct imxfb_info, fb_overlay)) ++#define fb_info_to_imxfb_info(x) ((struct imxfb_info*)((x)->host)) ++ + #define IMX_NAME "IMX" + + /* +@@ -204,11 +209,10 @@ static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) + return chan << bf->offset; + } + +- +-static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, +- u_int trans, struct fb_info *info) ++static int imxfb_setcolreg(struct fb_info *info, u_int regno, u_int red, ++ u_int green, u_int blue, u_int trans) + { +- struct imxfb_info *fbi = info->priv; ++ struct imxfb_info *fbi = fb_info_to_imxfb_info(info); + int ret = 1; + u32 val; + +@@ -247,7 +251,7 @@ static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, + + static void imxfb_enable_controller(struct fb_info *info) + { +- struct imxfb_info *fbi = info->priv; ++ struct imxfb_info *fbi = fb_info_to_imxfb_info(info); + + writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR); + #ifdef CONFIG_ARCH_IMX21 +@@ -269,7 +273,7 @@ static void imxfb_enable_controller(struct fb_info *info) + + static void imxfb_disable_controller(struct fb_info *info) + { +- struct imxfb_info *fbi = info->priv; ++ struct imxfb_info *fbi = fb_info_to_imxfb_info(info); + + if (fbi->enable) + fbi->enable(0); +@@ -290,19 +294,53 @@ static void imxfb_disable_controller(struct fb_info *info) + #endif + } + ++static void imxfb_memory_mmgt(struct fb_info *info, unsigned size, int buf) ++{ ++ struct imx_fb_platform_data *pdata = ++ info->host->hw_dev->platform_data; ++ void *base_address = buf == MAIN_FBUFFER ? ++ pdata->framebuffer : pdata->framebuffer_ovl; ++ ++ if (base_address != NULL) { ++ /* fixed memory location */ ++ info->fb_dev.map_base = (resource_size_t)base_address; ++ /** @todo how large is this space? */ ++ info->fb_dev.size = size; ++ } else { ++ /* dynamic memory location */ ++ if ((info->fb_dev.size < size) && (info->fb_dev.size != 0)) { ++ free((void*)info->fb_dev.map_base); ++ info->fb_dev.map_base = 0; ++ info->fb_dev.size = 0; ++ } ++ if (info->fb_dev.size == 0) { ++ info->fb_dev.map_base = (resource_size_t)xzalloc(size); ++ info->fb_dev.size = size; ++ } ++ } ++} ++ + /* + * imxfb_activate_var(): + * Configures LCD Controller based on entries in var parameter. Settings are + * only written to the controller if changes were made. + */ +-static int imxfb_activate_var(struct fb_info *info) ++static int imxfb_initialize_mode(struct fb_info *info, ++ const struct fb_videomode *mode) + { +- struct fb_videomode *mode = info->mode; + struct imxfb_rgb *rgb; + unsigned long lcd_clk; + unsigned long long tmp; +- struct imxfb_info *fbi = info->priv; ++ struct imxfb_info *fbi = fb_info_to_imxfb_info(info); + u32 pcr; ++ unsigned size; ++ ++ /* ++ * we need at least this amount of memory for the framebuffer ++ */ ++ size = mode->xres * mode->yres * (info->bits_per_pixel >> 3); ++ ++ imxfb_memory_mmgt(info, size, MAIN_FBUFFER); + + /* physical screen start address */ + writel(VPW_VPW(mode->xres * info->bits_per_pixel / 8 / 4), +@@ -318,13 +356,13 @@ static int imxfb_activate_var(struct fb_info *info) + VCR_V_WAIT_2(mode->upper_margin), + fbi->regs + LCDC_VCR); + +- writel(SIZE_XMAX(info->xres) | SIZE_YMAX(info->yres), ++ writel(SIZE_XMAX(mode->xres) | SIZE_YMAX(mode->yres), + fbi->regs + LCDC_SIZE); + + writel(fbi->pwmr, fbi->regs + LCDC_PWMR); + writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); + writel(fbi->dmacr, fbi->regs + LCDC_DMACR); +- writel((unsigned long)fbi->info.screen_base, fbi->regs + LCDC_SSA); ++ writel((uint32_t)info->fb_dev.map_base, fbi->regs + LCDC_SSA); + + /* panning offset 0 (0 pixel offset) */ + writel(0x0, fbi->regs + LCDC_POS); +@@ -386,16 +424,10 @@ static int imxfb_activate_var(struct fb_info *info) + return 0; + } + +-static struct fb_ops imxfb_ops = { +- .fb_setcolreg = imxfb_setcolreg, +- .fb_enable = imxfb_enable_controller, +- .fb_disable = imxfb_disable_controller, +-}; +- + #ifdef CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY + static void imxfb_overlay_enable_controller(struct fb_info *overlay) + { +- struct imxfb_info *fbi = overlay->priv; ++ struct imxfb_info *fbi = fb_overlay_to_imxfb_info(overlay); + unsigned int tmp; + + tmp = readl(fbi->regs + LCDC_LGWCR); +@@ -405,7 +437,7 @@ static void imxfb_overlay_enable_controller(struct fb_info *overlay) + + static void imxfb_overlay_disable_controller(struct fb_info *overlay) + { +- struct imxfb_info *fbi = overlay->priv; ++ struct imxfb_info *fbi = fb_overlay_to_imxfb_info(overlay); + unsigned int tmp; + + tmp = readl(fbi->regs + LCDC_LGWCR); +@@ -413,23 +445,16 @@ static void imxfb_overlay_disable_controller(struct fb_info *overlay) + writel(tmp , fbi->regs + LCDC_LGWCR); + } + +-static int imxfb_overlay_setcolreg(u_int regno, u_int red, u_int green, u_int blue, +- u_int trans, struct fb_info *info) ++static int imxfb_overlay_setcolreg(struct fb_info *overlay, u_int regno, ++ u_int red, u_int green, u_int blue, u_int trans) + { + return 0; + } + +-static struct fb_ops imxfb_overlay_ops = { +- .fb_setcolreg = imxfb_overlay_setcolreg, +- .fb_enable = imxfb_overlay_enable_controller, +- .fb_disable = imxfb_overlay_disable_controller, +-}; +- + static int imxfb_alpha_set(struct device_d *dev, struct param_d *param, + const char *val) + { +- struct fb_info *overlay = dev->priv; +- struct imxfb_info *fbi = overlay->priv; ++ struct imxfb_info *fbi = fb_overlay_dev_to_imxfb_info(dev); + int alpha; + char alphastr[16]; + unsigned int tmp; +@@ -452,32 +477,23 @@ static int imxfb_alpha_set(struct device_d *dev, struct param_d *param, + return 0; + } + +-static int imxfb_register_overlay(struct imxfb_info *fbi, void *fb) ++static int imxfb_overlay_mode(struct fb_info *overlay, ++ const struct fb_videomode *mode) + { +- struct fb_info *overlay; ++ struct imxfb_info *fbi = fb_overlay_to_imxfb_info(overlay); + struct imxfb_rgb *rgb; +- int ret; ++ unsigned size; + +- overlay = &fbi->overlay; ++ /* we need at least this amount of memory for the framebuffer */ ++ size = mode->xres * mode->yres * (overlay->bits_per_pixel >> 3); + +- overlay->priv = fbi; +- overlay->mode = fbi->info.mode; +- overlay->xres = fbi->info.xres; +- overlay->yres = fbi->info.yres; +- overlay->bits_per_pixel = fbi->info.bits_per_pixel; +- overlay->fbops = &imxfb_overlay_ops; ++ imxfb_memory_mmgt(overlay, size, OVRLY_FBUFFER); + +- if (fb) +- overlay->screen_base = fb; +- else +- overlay->screen_base = xzalloc(overlay->xres * overlay->yres * +- (overlay->bits_per_pixel >> 3)); +- +- writel((unsigned long)overlay->screen_base, fbi->regs + LCDC_LGWSAR); +- writel(SIZE_XMAX(overlay->xres) | SIZE_YMAX(overlay->yres), ++ writel((uint32_t)overlay->fb_dev.map_base, fbi->regs + LCDC_LGWSAR); ++ writel(SIZE_XMAX(mode->xres) | SIZE_YMAX(mode->yres), + fbi->regs + LCDC_LGWSR); +- writel(VPW_VPW(overlay->xres * overlay->bits_per_pixel / 8 / 4), +- fbi->regs + LCDC_LGWVPWR); ++ writel(VPW_VPW(mode->xres * overlay->bits_per_pixel / 8 / 4), ++ fbi->regs + LCDC_LGWVPWR); + writel(0, fbi->regs + LCDC_LGWPR); + writel(LGWCR_GWAV(0x0), fbi->regs + LCDC_LGWCR); + +@@ -506,14 +522,36 @@ static int imxfb_register_overlay(struct imxfb_info *fbi, void *fb) + overlay->blue = rgb->blue; + overlay->transp = rgb->transp; + +- ret = register_framebuffer(overlay); +- if (ret < 0) { +- dev_err(fbi->dev, "failed to register framebuffer\n"); +- return ret; ++ return 0; ++} ++ ++static int imxfb_register_overlay(struct imxfb_info *fbi, ++ struct device_d *hw_dev, struct imx_fb_platform_data *pdata) ++{ ++ struct fb_host *overlay; ++ struct device_d *overlay_dev; ++ ++ overlay = &fbi->fb_overlay; ++ ++ /* add runtime hardware info */ ++ overlay->hw_dev = hw_dev; /* same as the master device */ ++ overlay->fb_mode = imxfb_overlay_mode; ++ overlay->fb_enable = imxfb_overlay_enable_controller; ++ overlay->fb_disable = imxfb_overlay_disable_controller; ++ overlay->fb_setcolreg = imxfb_overlay_setcolreg; ++ ++ /* add runtime video info */ ++ overlay->mode = pdata->mode->mode; ++ overlay->mode_cnt = 1; /* no choice */ ++ ++ overlay_dev = register_framebuffer(overlay); ++ if (overlay_dev == NULL) { ++ dev_err(hw_dev, "failed to register overlay framebuffer\n"); ++ return -EINVAL; + } + +- dev_add_param(&overlay->dev, "alpha", imxfb_alpha_set, NULL, 0); +- dev_set_param(&overlay->dev, "alpha", "0"); ++ dev_add_param(overlay_dev, "alpha", imxfb_alpha_set, NULL, 0); ++ dev_set_param(overlay_dev, "alpha", "0"); + + return 0; + } +@@ -522,13 +560,13 @@ static int imxfb_register_overlay(struct imxfb_info *fbi, void *fb) + static int imxfb_probe(struct device_d *dev) + { + struct imxfb_info *fbi; +- struct fb_info *info; ++ struct device_d *fb_dev; + struct imx_fb_platform_data *pdata = dev->platform_data; +- int ret; + + if (!pdata) + return -ENODEV; + ++ /* TODO should be done when enabling the video output */ + #ifdef CONFIG_ARCH_IMX21 + PCCR0 &= ~(PCCR0_PERCLK3_EN | PCCR0_HCLK_LCDC_EN); + #endif +@@ -544,40 +582,35 @@ static int imxfb_probe(struct device_d *dev) + #endif + + fbi = xzalloc(sizeof(*fbi)); +- info = &fbi->info; + +- fbi->mode = pdata->mode; +- fbi->regs = (void *)dev->map_base; ++ /* add runtime hardware info */ ++ fbi->fb_host.hw_dev = dev; ++ fbi->fb_host.fb_mode = imxfb_initialize_mode; ++ fbi->fb_host.fb_enable = imxfb_enable_controller; ++ fbi->fb_host.fb_disable = imxfb_disable_controller; ++ fbi->fb_host.fb_setcolreg = imxfb_setcolreg; ++ ++ fbi->regs = (void*)dev->map_base; + fbi->pcr = pdata->mode->pcr; + fbi->pwmr = pdata->pwmr; + fbi->lscr1 = pdata->lscr1; + fbi->dmacr = pdata->dmacr; + fbi->enable = pdata->enable; +- fbi->dev = dev; +- info->priv = fbi; +- info->mode = pdata->mode->mode; +- info->xres = pdata->mode->mode->xres; +- info->yres = pdata->mode->mode->yres; +- info->bits_per_pixel = pdata->mode->bpp; +- info->fbops = &imxfb_ops; +- +- dev_info(dev, "i.MX Framebuffer driver\n"); +- +- if (pdata->framebuffer) +- fbi->info.screen_base = pdata->framebuffer; +- else +- fbi->info.screen_base = xzalloc(info->xres * info->yres * +- (info->bits_per_pixel >> 3)); +- +- imxfb_activate_var(&fbi->info); +- +- ret = register_framebuffer(&fbi->info); +- if (ret < 0) { ++ ++ /* add runtime video info */ ++ fbi->fb_host.mode = pdata->mode->mode; ++ /* to be backward compatible */ ++ fbi->fb_host.mode_cnt = pdata->mode_cnt == 0 ? 1 : pdata->mode_cnt; ++ fbi->fb_host.bits_per_pixel = 16; /* RGB565, the default */ ++ ++ fb_dev = register_framebuffer(&fbi->fb_host); ++ if (dev == NULL) { + dev_err(dev, "failed to register framebuffer\n"); +- return ret; ++ return -EINVAL; + } ++ + #ifdef CONFIG_IMXFB_DRIVER_VIDEO_IMX_OVERLAY +- imxfb_register_overlay(fbi, pdata->framebuffer_ovl); ++ imxfb_register_overlay(fbi, fb_dev, pdata); + #endif + return 0; + } +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0006-Adapt-the-existing-imx-ipu-fb-driver-to-support-runt.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0006-Adapt-the-existing-imx-ipu-fb-driver-to-support-runt.patch new file mode 100644 index 0000000..cb353e0 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0006-Adapt-the-existing-imx-ipu-fb-driver-to-support-runt.patch @@ -0,0 +1,477 @@ +From 0d06ecdc01cb10e14596ec4d1bbdada24ac0a47d Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 06/11] Adapt the existing imx-ipu fb driver to support runtime videomode selection + +Adapt the API to the new framebuffer videomode selection at runtime. + +NOTE: Due to the lack of hardware, this is compile time tested only. + +This is patch 4 of 4 to keep the repository bisectable. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/boards/freescale-mx35-3-stack/3stack.c | 2 +- + arch/arm/boards/pcm043/pcm043.c | 2 +- + arch/arm/mach-imx/include/mach/imx-ipu-fb.h | 12 +- + drivers/video/imx-ipu-fb.c | 217 +++++++++++++---------- + 4 files changed, 125 insertions(+), 108 deletions(-) + +diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c +index 127bfb4..d2b8262 100644 +--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c ++++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c +@@ -126,7 +126,7 @@ static struct fb_videomode CTP_CLAA070LC0ACW = { + .lower_margin = 10, /* whole frame should have 500 lines */ + .hsync_len = 1, /* note: DE only display */ + .vsync_len = 1, /* note: DE only display */ +- .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH, ++ .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_DE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }; +diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c +index 2191bc8..c504440 100644 +--- a/arch/arm/boards/pcm043/pcm043.c ++++ b/arch/arm/boards/pcm043/pcm043.c +@@ -111,7 +111,7 @@ static struct fb_videomode pcm043_fb_mode = { + .lower_margin = 40, + .hsync_len = 96, + .vsync_len = 1, +- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, ++ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_DE_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + }; +diff --git a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h +index 8e1cc87..ce95243 100644 +--- a/arch/arm/mach-imx/include/mach/imx-ipu-fb.h ++++ b/arch/arm/mach-imx/include/mach/imx-ipu-fb.h +@@ -12,20 +12,12 @@ + + #include <fb.h> + +-/* Proprietary FB_SYNC_ flags */ +-#define FB_SYNC_OE_ACT_HIGH 0x80000000 +-#define FB_SYNC_CLK_INVERT 0x40000000 +-#define FB_SYNC_DATA_INVERT 0x20000000 +-#define FB_SYNC_CLK_IDLE_EN 0x10000000 +-#define FB_SYNC_SHARP_MODE 0x08000000 +-#define FB_SYNC_SWAP_RGB 0x04000000 +-#define FB_SYNC_CLK_SEL_EN 0x02000000 +- + /* +- * struct mx3fb_platform_data - mx3fb platform data ++ * struct imx_ipu_fb_platform_data - imx-ipu-fb's platform data + */ + struct imx_ipu_fb_platform_data { + struct fb_videomode *mode; ++ unsigned mode_cnt; /**< number of entries in 'mode' */ + unsigned char bpp; + void __iomem *framebuffer; + /** hook to enable backlight and stuff */ +diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c +index c38082d..866d711 100644 +--- a/drivers/video/imx-ipu-fb.c ++++ b/drivers/video/imx-ipu-fb.c +@@ -34,12 +34,12 @@ + #include <mach/clock.h> + + struct ipu_fb_info { ++ struct fb_host fb_host; /**< myself */ + void __iomem *regs; + + void (*enable)(int enable); + +- struct fb_info info; +- struct device_d *dev; ++ const struct fb_videomode *mode; /**< requested videomodue */ + }; + + /* IPU DMA Controller channel definitions. */ +@@ -413,29 +413,30 @@ static inline void reg_write(struct ipu_fb_info *fbi, u32 value, + writel(value, fbi->regs + reg); + } + ++#define fb_info_to_imxfb_info(x) ((struct ipu_fb_info*)((x)->host)) ++ + /* + * sdc_init_panel() - initialize a synchronous LCD panel. +- * @width: width of panel in pixels. +- * @height: height of panel in pixels. +- * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. ++ * @param info The framebuffer to work on ++ * @param pixel_fmt pixel format of buffer as FOURCC ASCII code. + * @return: 0 on success or negative error code on failure. + */ +-static int sdc_init_panel(struct fb_info *info, enum pixel_fmt pixel_fmt) ++static int sdc_init_panel(struct fb_info *fb_info, enum pixel_fmt pixel_fmt) + { +- struct ipu_fb_info *fbi = info->priv; +- struct fb_videomode *mode = info->mode; ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); ++ const struct fb_videomode *mode = fbi->mode; + u32 reg, old_conf, div; + enum ipu_panel panel = IPU_PANEL_TFT; + unsigned long pixel_clk; + + /* Init panel size and blanking periods */ + reg = ((mode->hsync_len - 1) << 26) | +- ((info->xres + mode->left_margin + mode->right_margin + ++ ((mode->xres + mode->left_margin + mode->right_margin + + mode->hsync_len - 1) << 16); + reg_write(fbi, reg, SDC_HOR_CONF); + + reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | +- ((info->yres + mode->upper_margin + mode->lower_margin + ++ ((mode->yres + mode->upper_margin + mode->lower_margin + + mode->vsync_len - 1) << 16); + reg_write(fbi, reg, SDC_VER_CONF); + +@@ -448,7 +449,7 @@ static int sdc_init_panel(struct fb_info *info, enum pixel_fmt pixel_fmt) + old_conf |= DI_D3_CLK_POL; + if (mode->sync & FB_SYNC_DATA_INVERT) + old_conf |= DI_D3_DATA_POL; +- if (mode->sync & FB_SYNC_OE_ACT_HIGH) ++ if (mode->sync & FB_SYNC_DE_HIGH_ACT) + old_conf |= DI_D3_DRDY_SHARP_POL; + reg_write(fbi, old_conf, DI_DISP_SIG_POL); + +@@ -483,12 +484,12 @@ static int sdc_init_panel(struct fb_info *info, enum pixel_fmt pixel_fmt) + div = imx_get_lcdclk() * 16 / pixel_clk; + + if (div < 0x40) { /* Divider less than 4 */ +- dev_dbg(&info->dev, ++ dev_dbg(fbi->fb_host.hw_dev, + "InitPanel() - Pixel clock divider less than 4\n"); + div = 0x40; + } + +- dev_dbg(&info->dev, "pixel clk = %u, divider %u.%u\n", ++ dev_dbg(fbi->fb_host.hw_dev, "pixel clk = %u, divider %u.%u\n", + pixel_clk, div >> 4, (div & 7) * 125); + + /* +@@ -588,19 +589,20 @@ static u32 dma_param_addr(enum ipu_channel channel) + return 0x10000 | (channel << 4); + } + +-static void ipu_init_channel_buffer(struct ipu_fb_info *fbi, ++static void ipu_init_channel_buffer(struct fb_info *fb_info, + enum ipu_channel channel, void *fbmem) + { ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); + union chan_param_mem params = {}; + u32 reg; + u32 stride_bytes; + +- stride_bytes = fbi->info.xres * ((fbi->info.bits_per_pixel + 7) / 8); ++ stride_bytes = fbi->mode->xres * ((fb_info->bits_per_pixel + 7) / 8); + stride_bytes = (stride_bytes + 3) & ~3; + + /* Build parameter memory data for DMA channel */ +- ipu_ch_param_set_size(¶ms, bpp_to_pixfmt(fbi->info.bits_per_pixel), +- fbi->info.xres, fbi->info.yres, stride_bytes); ++ ipu_ch_param_set_size(¶ms, bpp_to_pixfmt(fb_info->bits_per_pixel), ++ fbi->mode->xres, fbi->mode->yres, stride_bytes); + ipu_ch_param_set_buffer(¶ms, fbmem, NULL); + params.pp.bam = 0; + /* Some channels (rotation) have restriction on burst length */ +@@ -622,9 +624,10 @@ static void ipu_init_channel_buffer(struct ipu_fb_info *fbi, + reg_write(fbi, reg, IPU_CHA_DB_MODE_SEL); + } + +-static void ipu_channel_set_priority(struct ipu_fb_info *fbi, ++static void ipu_channel_set_priority(struct fb_info *fb_info, + enum ipu_channel channel, int prio) + { ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); + u32 reg; + + reg = reg_read(fbi, IDMAC_CHA_PRI); +@@ -639,11 +642,13 @@ static void ipu_channel_set_priority(struct ipu_fb_info *fbi, + + /* + * ipu_enable_channel() - enable an IPU channel. ++ * @param fb_info The framebuffer to work on + * @channel: channel ID. + * @return: 0 on success or negative error code on failure. + */ +-static int ipu_enable_channel(struct ipu_fb_info *fbi, enum ipu_channel channel) ++static int ipu_enable_channel(struct fb_info *fb_info, enum ipu_channel channel) + { ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); + u32 reg; + + /* Reset to buffer 0 */ +@@ -651,7 +656,7 @@ static int ipu_enable_channel(struct ipu_fb_info *fbi, enum ipu_channel channel) + + switch (channel) { + case IDMAC_SDC_0: +- ipu_channel_set_priority(fbi, channel, 1); ++ ipu_channel_set_priority(fb_info, channel, 1); + break; + default: + break; +@@ -663,9 +668,10 @@ static int ipu_enable_channel(struct ipu_fb_info *fbi, enum ipu_channel channel) + return 0; + } + +-static int ipu_update_channel_buffer(struct ipu_fb_info *fbi, ++static int ipu_update_channel_buffer(struct fb_info *fb_info, + enum ipu_channel channel, void *buf) + { ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); + u32 reg; + + reg = reg_read(fbi, IPU_CHA_BUF0_RDY); +@@ -679,16 +685,17 @@ static int ipu_update_channel_buffer(struct ipu_fb_info *fbi, + return 0; + } + +-static int idmac_tx_submit(struct ipu_fb_info *fbi, enum ipu_channel channel, ++static int idmac_tx_submit(struct fb_info *fb_info, enum ipu_channel channel, + void *buf) + { ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); + int ret; + +- ipu_init_channel_buffer(fbi, channel, buf); ++ ipu_init_channel_buffer(fb_info, channel, buf); + + + /* ipu_idmac.c::ipu_submit_channel_buffers() */ +- ret = ipu_update_channel_buffer(fbi, channel, buf); ++ ret = ipu_update_channel_buffer(fb_info, channel, buf); + if (ret < 0) + return ret; + +@@ -697,16 +704,17 @@ static int idmac_tx_submit(struct ipu_fb_info *fbi, enum ipu_channel channel, + reg_write(fbi, 1UL << channel, IPU_CHA_BUF0_RDY); + + +- ret = ipu_enable_channel(fbi, channel); ++ ret = ipu_enable_channel(fb_info, channel); + return ret; + } + +-static void sdc_enable_channel(struct ipu_fb_info *fbi, void *fbmem) ++static void sdc_enable_channel(struct fb_info *fb_info, void *fbmem) + { ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); + int ret; + u32 reg; + +- ret = idmac_tx_submit(fbi, IDMAC_SDC_0, fbmem); ++ ret = idmac_tx_submit(fb_info, IDMAC_SDC_0, fbmem); + + /* mx3fb.c::sdc_fb_init() */ + if (ret >= 0) { +@@ -722,11 +730,75 @@ static void sdc_enable_channel(struct ipu_fb_info *fbi, void *fbmem) + mdelay(2); + } + ++static void imxfb_init_info(struct fb_info *fb_info, ++ const struct fb_videomode *mode) ++{ ++ struct imx_ipu_fb_rgb *rgb; ++ ++ fb_info->xres = mode->xres; ++ fb_info->yres = mode->yres; ++ ++ switch (fb_info->bits_per_pixel) { ++ case 32: ++ rgb = &def_rgb_32; ++ break; ++ case 24: ++ rgb = &def_rgb_24; ++ break; ++ case 16: ++ default: ++ rgb = &def_rgb_16; ++ break; ++ } ++ ++ /* ++ * Copy the RGB parameters for this display ++ * from the machine specific parameters. ++ */ ++ fb_info->red = rgb->red; ++ fb_info->green = rgb->green; ++ fb_info->blue = rgb->blue; ++ fb_info->transp = rgb->transp; ++} ++ ++static void imxfb_memory_mmgt(struct fb_info *fb_info, unsigned size) ++{ ++ if ((fb_info->fb_dev.size < size) && (fb_info->fb_dev.size != 0)) { ++ free((void*)fb_info->fb_dev.map_base); ++ fb_info->fb_dev.map_base = 0; ++ fb_info->fb_dev.size = 0; ++ } ++ if (fb_info->fb_dev.size == 0) { ++ fb_info->fb_dev.map_base = (resource_size_t)xzalloc(size); ++ fb_info->fb_dev.size = size; ++ } ++} ++ ++static int ipu_fb_initialize_mode(struct fb_info *fb_info, ++ const struct fb_videomode *mode) ++{ ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); ++ unsigned size; ++ ++ /* ++ * we need at least this amount of memory for the framebuffer ++ */ ++ size = mode->xres * mode->yres * (fb_info->bits_per_pixel >> 3); ++ ++ imxfb_memory_mmgt(fb_info, size); ++ ++ fbi->mode = mode; ++ ++ imxfb_init_info(fb_info, mode); ++ ++ return 0; ++} ++ + /* References in this function refer to respective Linux kernel sources */ +-static void ipu_fb_enable(struct fb_info *info) ++static void ipu_fb_enable(struct fb_info *fb_info) + { +- struct ipu_fb_info *fbi = info->priv; +- struct fb_videomode *mode = info->mode; ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(fb_info); ++ const struct fb_videomode *mode = fbi->mode; + u32 reg; + + /* pcm037.c::mxc_board_init() */ +@@ -779,12 +851,12 @@ static void ipu_fb_enable(struct fb_info *info) + ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); + reg_write(fbi, reg, SDC_COM_CONF); + +- sdc_init_panel(info, IPU_PIX_FMT_RGB666); ++ sdc_init_panel(fb_info, IPU_PIX_FMT_RGB666); + + reg_write(fbi, (mode->left_margin << 16) | mode->upper_margin, + SDC_BG_POS); + +- sdc_enable_channel(fbi, info->screen_base); ++ sdc_enable_channel(fb_info, (void*)fb_info->fb_dev.map_base); + + /* + * Linux driver calls sdc_set_brightness() here again, +@@ -796,7 +868,7 @@ static void ipu_fb_enable(struct fb_info *info) + + static void ipu_fb_disable(struct fb_info *info) + { +- struct ipu_fb_info *fbi = info->priv; ++ struct ipu_fb_info *fbi = fb_info_to_imxfb_info(info); + u32 reg; + + if (fbi->enable) +@@ -807,85 +879,38 @@ static void ipu_fb_disable(struct fb_info *info) + reg_write(fbi, reg, SDC_COM_CONF); + } + +-static struct fb_ops imxfb_ops = { +- .fb_enable = ipu_fb_enable, +- .fb_disable = ipu_fb_disable, +-}; +- +-static void imxfb_init_info(struct fb_info *info, struct fb_videomode *mode, +- int bpp) +-{ +- struct imx_ipu_fb_rgb *rgb; +- +- info->mode = mode; +- info->xres = mode->xres; +- info->yres = mode->yres; +- info->bits_per_pixel = bpp; +- +- switch (info->bits_per_pixel) { +- case 32: +- rgb = &def_rgb_32; +- break; +- case 24: +- rgb = &def_rgb_24; +- break; +- case 16: +- default: +- rgb = &def_rgb_16; +- break; +- } +- +- /* +- * Copy the RGB parameters for this display +- * from the machine specific parameters. +- */ +- info->red = rgb->red; +- info->green = rgb->green; +- info->blue = rgb->blue; +- info->transp = rgb->transp; +-} +- + static int imxfb_probe(struct device_d *dev) + { + struct ipu_fb_info *fbi; +- struct fb_info *info; ++ struct device_d *fb_dev; + const struct imx_ipu_fb_platform_data *pdata = dev->platform_data; +- int ret; + + if (!pdata) + return -ENODEV; + + fbi = xzalloc(sizeof(*fbi)); +- info = &fbi->info; ++ ++ /* add runtime hardware info */ ++ fbi->fb_host.hw_dev = dev; ++ fbi->fb_host.fb_mode = ipu_fb_initialize_mode; ++ fbi->fb_host.fb_enable = ipu_fb_enable; ++ fbi->fb_host.fb_disable = ipu_fb_disable; ++ fbi->fb_host.fb_setcolreg = NULL; + + fbi->regs = (void *)dev->map_base; +- fbi->dev = dev; +- info->priv = fbi; +- info->fbops = &imxfb_ops; +- fbi->enable = pdata->enable; + +- imxfb_init_info(info, pdata->mode, pdata->bpp); ++ /* add runtime video info */ ++ fbi->fb_host.mode = pdata->mode; ++ /* to be backward compatible */ ++ fbi->fb_host.mode_cnt = pdata->mode_cnt == 0 ? 1 : pdata->mode_cnt; ++ fbi->fb_host.bits_per_pixel = pdata->bpp; + + dev_info(dev, "i.MX Framebuffer driver\n"); + +- /* +- * Use a given frambuffer or reserve some +- * memory for screen usage +- */ +- fbi->info.screen_base = pdata->framebuffer; +- if (fbi->info.screen_base == NULL) { +- fbi->info.screen_base = malloc(info->xres * info->yres * +- (info->bits_per_pixel >> 3)); +- if (!fbi->info.screen_base) +- return -ENOMEM; +- } +- +- sdc_enable_channel(fbi, info->screen_base); +- +- ret = register_framebuffer(&fbi->info); +- if (ret < 0) { ++ fb_dev = register_framebuffer(&fbi->fb_host); ++ if (fb_dev == NULL) { + dev_err(dev, "failed to register framebuffer\n"); +- return ret; ++ return -EINVAL; + } + + return 0; +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0007-Remove-variable-size-restrictions.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0007-Remove-variable-size-restrictions.patch new file mode 100644 index 0000000..cd7e60c --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0007-Remove-variable-size-restrictions.patch @@ -0,0 +1,83 @@ +From 7cb0e3264abec7ca5722fa1dc0cb90377248b6ed Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 07/11] Remove variable size restrictions + +There is no really need for restricted variable types in these structures. +Replace them by standard C types with the same behaviour. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + include/fb.h | 41 ++++++++++++++++++++--------------------- + 1 files changed, 20 insertions(+), 21 deletions(-) + +diff --git a/include/fb.h b/include/fb.h +index 36b2a74..a1bd147 100644 +--- a/include/fb.h ++++ b/include/fb.h +@@ -43,19 +43,19 @@ + + struct fb_videomode { + const char *name; /* optional */ +- u32 refresh; /* optional */ +- u32 xres; +- u32 yres; +- u32 pixclock; +- u32 left_margin; +- u32 right_margin; +- u32 upper_margin; +- u32 lower_margin; +- u32 hsync_len; +- u32 vsync_len; +- u32 sync; +- u32 vmode; +- u32 flag; ++ unsigned refresh; /* optional */ ++ unsigned xres; ++ unsigned yres; ++ unsigned pixclock; ++ unsigned left_margin; ++ unsigned right_margin; ++ unsigned upper_margin; ++ unsigned lower_margin; ++ unsigned hsync_len; ++ unsigned vsync_len; ++ unsigned sync; ++ unsigned vmode; ++ unsigned flag; + }; + + /* Interpretation of offset for color fields: All offsets are from the right, +@@ -69,10 +69,9 @@ struct fb_videomode { + * of available palette entries (i.e. # of entries = 1 << length). + */ + struct fb_bitfield { +- u32 offset; /* beginning of bitfield */ +- u32 length; /* length of bitfield */ +- u32 msb_right; /* != 0 : Most significant bit is */ +- /* right */ ++ unsigned offset; /* beginning of bitfield */ ++ unsigned length; /* length of bitfield */ ++ int msb_right; /* != 0 : Most significant bit is right */ + }; + + struct fb_info; +@@ -98,11 +97,11 @@ struct fb_info { + struct cdev cdev; + const struct fb_videomode *active_mode; + +- u32 xres; /* visible resolution */ +- u32 yres; +- u32 bits_per_pixel; /* guess what */ ++ unsigned xres; /* visible resolution */ ++ unsigned yres; ++ unsigned bits_per_pixel; /* guess what */ + +- u32 grayscale; /* != 0 Graylevels instead of colors */ ++ int grayscale; /* != 0 Graylevels instead of colors */ + + struct fb_bitfield red; /* bitfield in fb mem if true color, */ + struct fb_bitfield green; /* else only length is significant */ +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0008-Add-doxygen-documentation-to-the-framebfuffer-code.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0008-Add-doxygen-documentation-to-the-framebfuffer-code.patch new file mode 100644 index 0000000..811913b --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0008-Add-doxygen-documentation-to-the-framebfuffer-code.patch @@ -0,0 +1,457 @@ +From 4cf620b396465e32e32da6058f3274b3e8852f12 Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 08/11] Add doxygen documentation to the framebfuffer code + +Add some (hopefully) helpful documentation to the source code. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + Documentation/developers_manual.dox | 1 + Documentation/users_manual.dox | 1 + drivers/video/fb.c | 202 ++++++++++++++++++++++++++++++++++++ + include/fb.h | 97 +++++++++++------ + 4 files changed, 269 insertions(+), 32 deletions(-) + +Index: barebox-2010.11.0/Documentation/developers_manual.dox +=================================================================== +--- barebox-2010.11.0.orig/Documentation/developers_manual.dox ++++ barebox-2010.11.0/Documentation/developers_manual.dox +@@ -21,5 +21,6 @@ This part of the documentation is intend + @li @subpage mci_for_developers + @li @subpage io_access_functions + @li @subpage mcfv4e_MCDlib ++@li @subpage fb_for_developers + + */ +Index: barebox-2010.11.0/Documentation/users_manual.dox +=================================================================== +--- barebox-2010.11.0.orig/Documentation/users_manual.dox ++++ barebox-2010.11.0/Documentation/users_manual.dox +@@ -15,5 +15,6 @@ you find a lot of nice tricks on these p + @li @subpage readline_parser + @li @subpage x86_bootloader + @li @subpage net_netconsole ++@li @subpage fb_for_users + + */ +Index: barebox-2010.11.0/drivers/video/fb.c +=================================================================== +--- barebox-2010.11.0.orig/drivers/video/fb.c ++++ barebox-2010.11.0/drivers/video/fb.c +@@ -33,6 +33,11 @@ static int fb_ioctl(struct cdev* cdev, i + return 0; + } + ++/** ++ * Check if the video output is already enabled ++ * @param fb_dev The framebuffer device to check ++ * @return 0 if the video output is still disabled, -EPERM if enabled ++ */ + static int fb_check_if_already_initialized(struct device_d *fb_dev) + { + struct fb_info *info = to_fb_info(fb_dev); +@@ -46,6 +51,9 @@ static int fb_check_if_already_initializ + return 0; + } + ++/** ++ * Change colour depth via device parameter ++ */ + static int fb_cdepth_set(struct device_d *fb_dev, struct param_d *param, const char *val) + { + struct fb_info *info = to_fb_info(fb_dev); +@@ -65,6 +73,9 @@ static int fb_cdepth_set(struct device_d + return dev_param_set_generic(fb_dev, param, val); + } + ++/** ++ * Enable/disable video output via device parameter ++ */ + static int fb_enable_set(struct device_d *fb_dev, struct param_d *param, const char *val) + { + struct fb_info *info = to_fb_info(fb_dev); +@@ -93,6 +104,10 @@ static int fb_enable_set(struct device_d + return dev_param_set_generic(fb_dev, param, new); + } + ++/** ++ * Output the list of supported video modes in this framebuffer ++ * @param host Platformdata of the hardware video device ++ */ + static void fb_list_modes(struct fb_host *host) + { + unsigned u; +@@ -102,6 +117,14 @@ static void fb_list_modes(struct fb_host + printf(" '%s'\n", host->mode[u].name); + } + ++/** ++ * Call the video hardware driver to initialize the given video mode ++ * @param fb_dev Framebuffer device ++ * @param mode Mode description to initialize ++ * @return 0 on success ++ * ++ * @note This call does not imply enabling the video output device! ++ */ + static int fb_activate_mode(struct device_d *fb_dev, const struct fb_videomode *mode) + { + struct fb_info *info = to_fb_info(fb_dev); +@@ -124,6 +147,13 @@ static int fb_activate_mode(struct devic + return 0; + } + ++/** ++ * Setup the requested video mode via device parameter ++ * @param dev Device instance ++ * @param param FIXME ++ * @param name Video mode name to activate ++ * @return 0 on success ++ */ + static int fb_mode_set(struct device_d *fb_dev, struct param_d *param, const char *name) + { + struct fb_host *host = fb_dev->platform_data; +@@ -210,6 +240,11 @@ static void fb_info(struct device_d *fb_ + fb_list_modes(info->host); + } + ++/** ++ * Add controlling parameters to the framebuffer device ++ * @param dev Device instance ++ * @return 0 on success ++ */ + static int add_fb_parameter(struct fb_info *info) + { + char cd[10]; +@@ -274,6 +309,11 @@ static int framebuffer_init(void) + + device_initcall(framebuffer_init); + ++/** ++ * Create a new framebuffer device ++ * @param pinfo Video device's platform data for this framebuffer device ++ * @return Pointer to the newly created device or NULL on failure ++ */ + struct device_d *register_framebuffer(struct fb_host *host) + { + struct fb_info *fb_info; +@@ -293,3 +333,165 @@ struct device_d *register_framebuffer(st + + return &fb_info->fb_dev; + } ++ ++/** ++@page fb_for_users Framebuffer handling for users ++ ++@section delayed_fb Framebuffer setup ++ ++If the platform supports more than one video output device, its possible to select ++one of the supported ones at runtime. To do so, no videomode setup happens when ++the graphics driver gets registered. The device offers the 'mode' parameter to ++support specifiying the correct output device. But keep in mind that there will ++be also no framebuffer memory until the output video hardware and its videomode ++get specified. This is important to know, if you want to paint some nice splash ++screen. ++ ++Running the @b devinfo command on the framebuffer0 device will output: ++@verbatim ++barebox:/ devinfo framebuffer0 ++base : 0x00000000 ++size : 0x00000000 ++driver: framebuffer ++ ++ Video/Mode info: ++ Video output not enabled ++ Current video mode: ++ No video mode selected yet ++ Supported video mode(s): ++ 'QVGA' ++ 'VGA' ++Parameters: ++ cdepth = 16 ++ mode = <NULL> ++ enable = <NULL> ++@endverbatim ++ ++@note As long @b devinfo reports a @b base or @b size of zero there is ++@b no framebuffer memory yet! ++ ++This framebuffer device is not initialized yet. As shown in the list, it ++supports two video modes: 'QVGA' and 'VGA'. ++ ++So, the user can first specifiy the video output device with (for example) ++@verbatim ++barebox:/ framebuffer0.mode="QVGA" ++@endverbatim ++ ++After this the @b devinfo command's output changes to: ++@verbatim ++barebox:/ devinfo framebuffer0 ++base : 0x31fc0000 ++size : 0x00040000 ++driver: framebuffer ++ ++ Video/Mode info: ++ Video output not enabled ++ Current video mode: ++ Name: QVGA ++ Refresh rate: 60 Hz ++ Horizontal active pixel: 320 ++ Vertical active lines: 240 ++ Pixel clock: 6500 kHz ++ Left/Right margin (pixel): 20/20 ++ Upper/Lower margin (lines): 10/10 ++ HSYNC length in pixel: 10, polarity: high ++ VSYNC length in lines: 5, polarity: high ++ Colour depth: 16 bpp ++ Supported video mode(s): ++ 'QVGA' ++ 'VGA' ++Parameters: ++ cdepth = 16 ++ mode = QVGA ++ enable = <NULL> ++@endverbatim ++As one can see, the framebuffer has a @b base, a @b size and a @b mode ++configuration now. ++@note Take care if setting a video mode fails. In this case @b base and @b size ++will kept at zero! ++ ++With this setting its possible to paint some kind of image into the framebuffer ++memory and enabling the video output as the final step at runtime ++@verbatim ++barebox:/ framebuffer0.enable=1 ++@endverbatim ++The video output is fully enabled now: ++@verbatim ++barebox:/ devinfo framebuffer0 ++base : 0x31fc0000 ++size : 0x00040000 ++driver: framebuffer ++ ++ Video/Mode info: ++ Video output enabled ++ Current video mode: ++ Name: QVGA ++ Refresh rate: 60 Hz ++ Horizontal active pixel: 320 ++ Vertical active lines: 240 ++ Pixel clock: 6500 kHz ++ Left/Right margin (pixel): 20/20 ++ Upper/Lower margin (lines): 10/10 ++ HSYNC length in pixel: 10, polarity: high ++ VSYNC length in lines: 5, polarity: high ++ Colour depth: 16 bpp ++ Supported video mode(s): ++ 'QVGA' ++ 'VGA' ++Parameters: ++ cdepth = 16 ++ mode = QVGA ++ enable = 1 ++@endverbatim ++ ++@section other_fb_params Other framebuffer parameter ++@verbatim ++framebuffer0.cdepth=[1 | 4 | 8 | 16 | 24 | 32] ++@endverbatim ++ ++Colour depth to be used with the framebuffer. Its unit is "bit per pixel" and ++the default value is 16 bits per pixel (means "RGB565" format). This value can ++only be changed if the video output is disabled. ++ ++@note The possible values from the list above are hardware dependend. ++ ++@note The default colour depth value may also depend on the hardware ++*/ ++ ++/** ++@page fb_for_developers Framebuffer handling for developers ++ ++@section fb_platform_dev For the platform developer ++ ++If you provide more than one video output device description use an array of ++this type. In this case the 'mode_cnt' entry must contain the count of existing ++array entries (> 1). Give each video output device description entry an unique ++name, because a user will select the required output device by this name ++at runtime. ++ ++@section fb_driver_dev For the video hardware driver developer: ++ ++Don't initialize a special video mode in your probe function (e.g. don't ++allocate any framebuffer memory and so on). The framework will call back your ++exported fb_mode() function to do so (immediately or delayed). ++ ++Don't enable video output in your probe or exported fb_mode() function. Also ++do not switch on any LCD or backlight if any. The framework will call your ++exported fb_enable() function to do so. ++ ++If your hardware cannot handle the default 16 bit colour depth, change the ++'bits_per_pixel' field prior registering your framebuffer. ++ ++When your exported fb_mode() function is called, calculate the amount of memory ++you need for the requested video mode and colour depth, save this value to ++framebuffer's info struct in field 'fb_dev->size' and allocate the memory with ++this size for the framebuffer. Store the basepointer to this area into ++framebuffer's info struct in field 'fb_dev->map_base'. ++ ++@note To support flickerless splash screen into the Linux kernel, your driver ++should support a fixed framebuffer memory. Fixed in location and size. The platform ++should hold the Linux kernel to not touch this memory in any way. Instead the ++kernel based video hardware driver should inherit the fixed settings. ++ ++*/ +Index: barebox-2010.11.0/include/fb.h +=================================================================== +--- barebox-2010.11.0.orig/include/fb.h ++++ barebox-2010.11.0/include/fb.h +@@ -18,19 +18,27 @@ + /* vtotal = 121d/242n/484i => NTSC */ + #define FB_SYNC_ON_GREEN 32 /* sync on green */ + /* LC display related settings */ ++/** LC display uses active high data enable signal */ + #define FB_SYNC_DE_HIGH_ACT (1 << 6) ++/** LC display will latch its data at clock's rising edge */ + #define FB_SYNC_CLK_INVERT (1 << 7) ++/** output RGB data inverted */ + #define FB_SYNC_DATA_INVERT (1 << 8) ++/** Stop clock if no data is sent (required for passive displays) */ + #define FB_SYNC_CLK_IDLE_EN (1 << 9) ++/** swap RGB to BGR */ + #define FB_SYNC_SWAP_RGB (1 << 10) ++/** FIXME */ + #define FB_SYNC_CLK_SEL_EN (1 << 11) ++/** enable special signals for SHARP displays (_very_ hardware specific) */ + #define FB_SYNC_SHARP_MODE (1 << 31) + +-#define FB_VMODE_NONINTERLACED 0 /* non interlaced */ +-#define FB_VMODE_INTERLACED 1 /* interlaced */ ++#define FB_VMODE_NONINTERLACED 0 /** non interlaced */ ++#define FB_VMODE_INTERLACED 1 /** interlaced */ + #define FB_VMODE_DOUBLE 2 /* double scan */ +-#define FB_VMODE_ODD_FLD_FIRST 4 /* interlaced: top line first */ ++#define FB_VMODE_ODD_FLD_FIRST 4 /** interlaced: top line first */ + /* LC display related settings */ ++/** output two screen parts at once (required for passive displays) */ + #define FB_VMODE_DUAL_SCAN 8 + #define FB_VMODE_MASK 255 + +@@ -42,19 +50,24 @@ + #define KHZ2PICOS(a) (1000000000UL/(a)) + + struct fb_videomode { +- const char *name; /* optional */ +- unsigned refresh; /* optional */ +- unsigned xres; +- unsigned yres; +- unsigned pixclock; +- unsigned left_margin; +- unsigned right_margin; +- unsigned upper_margin; +- unsigned lower_margin; +- unsigned hsync_len; +- unsigned vsync_len; +- unsigned sync; +- unsigned vmode; ++ const char *name; /**< always required and must be unique */ ++ unsigned refresh; /**< frame refresh rate in [Hz] (optional) */ ++ unsigned xres; /**< visible horizontal pixel */ ++ unsigned yres; /**< visible vertical pixel */ ++ unsigned pixclock; /**< pixel clock period in [ps]. Refer ++ PICOS2KHZ/KHZ2PICOS macros */ ++ unsigned left_margin; /**< distance in pixels between ending active HSYNC ++ and starting visible line content */ ++ unsigned right_margin; /**< distance in pixels between ending visible line ++ content and starting active HSYNC */ ++ unsigned upper_margin; /**< distance in lines between ending active VSYNC ++ and the first line with visible content */ ++ unsigned lower_margin; /**< distance in lines between last line with ++ visible content and starting active VSYNC */ ++ unsigned hsync_len; /**< HSYNC's active length in pixels */ ++ unsigned vsync_len; /**< VSYNC's active lenght in lines */ ++ unsigned sync; /**< sync information, refer FB_SYNC_* macros */ ++ unsigned vmode; /**< video mode information, refer FB_VMODE_* macros */ + unsigned flag; + }; + +@@ -69,18 +82,33 @@ struct fb_videomode { + * of available palette entries (i.e. # of entries = 1 << length). + */ + struct fb_bitfield { +- unsigned offset; /* beginning of bitfield */ +- unsigned length; /* length of bitfield */ +- int msb_right; /* != 0 : Most significant bit is right */ ++ unsigned offset; /**< beginning of bitfield */ ++ unsigned length; /**< length of bitfield */ ++ int msb_right; /**< != 0 : Most significant bit is right */ + }; + + struct fb_info; + ++/** ++ * Framebuffer device's platform information ++ * ++ * The video hardware driver must set the following fields: ++ * - 'fb_mode' function to setup a specific video mode ++ * - 'fb_enable' function to activate the video output ++ * - 'fb_disable' function to deactivate the video output ++ * - 'fb_setcolreg' function to ???????? FIXME ++ * ++ * The video hardware driver can set default values for the following fields: ++ * - 'mode' if the driver supports only specific video modes. ++ * - 'mode_cnt' must be set, if 'mode_list' is given ++ * - 'bits_per_pixel' if the video hardware driver defaults to another bpp than 16 ++ */ + struct fb_host { +- const struct fb_videomode *mode; +- unsigned mode_cnt; ++ /* information about possible video mode(s) */ ++ const struct fb_videomode *mode; /**< Array of modes */ ++ unsigned mode_cnt; /**< count of entries in 'mode'. */ + +- struct device_d *hw_dev; ++ struct device_d *hw_dev; /**< the host device */ + + /* callbacks into the video hardware driver */ + int (*fb_setcolreg)(struct fb_info*, unsigned, unsigned, unsigned, unsigned, unsigned); +@@ -88,25 +116,30 @@ struct fb_host { + void (*fb_enable)(struct fb_info*); + void (*fb_disable)(struct fb_info*); + +- unsigned bits_per_pixel; ++ unsigned bits_per_pixel; /**< default bpp, 0 = use framebuffer's default */ + }; + ++/** ++ * Framebuffer's runtime information ++ */ + struct fb_info { +- struct fb_host *host; +- struct device_d fb_dev; ++ struct fb_host *host; /**< host data this fb is based on */ ++ struct device_d fb_dev; /**< the framebuffer device */ + struct cdev cdev; ++ /* information about current video mode */ ++ /** the currently active video mode if set. Can be NULL = no video mode set yet */ + const struct fb_videomode *active_mode; + +- unsigned xres; /* visible resolution */ +- unsigned yres; +- unsigned bits_per_pixel; /* guess what */ ++ unsigned xres; /**< visible horizontal pixel count */ ++ unsigned yres; /**< visible vertical line count */ ++ unsigned bits_per_pixel; /**< visible colour depth */ + +- int grayscale; /* != 0 Graylevels instead of colors */ ++ int grayscale; /**< != 0 Graylevels instead of colors */ + +- struct fb_bitfield red; /* bitfield in fb mem if true color, */ +- struct fb_bitfield green; /* else only length is significant */ ++ struct fb_bitfield red; /**< bitfield in fb mem if true color, */ ++ struct fb_bitfield green; /**< else only length is significant */ + struct fb_bitfield blue; +- struct fb_bitfield transp; /* transparency */ ++ struct fb_bitfield transp; /**< transparency */ + + int enabled; + }; diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0009-Provide-more-driver-specific-data-in-a-videomode.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0009-Provide-more-driver-specific-data-in-a-videomode.patch new file mode 100644 index 0000000..6ebd6e4 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0009-Provide-more-driver-specific-data-in-a-videomode.patch @@ -0,0 +1,404 @@ +From f80a4bc4de53f677ad1aa11f6f5f19ae1f42d169 Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 09/11] Provide more driver specific data in a videomode + +In order to support more than one videomode in a binary barebox, some drivers +need more specific data to setup the requested video mode in a correct manner. +This patch adds the 'priv' field to the generic videomode description to give +any platform a chance to forward some video hardware specific information on +a per videomode base. + +This is currently i.MX21/i.MX25/i.MX27 specific. + +BTW: At least the 'pcr' value could be generated at runtime from the 'sync' +field in 'struct fb_videomode'. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c | 21 +++++----- + arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c | 21 +++++----- + arch/arm/boards/guf-neso/board.c | 45 +++++++++++---------- + arch/arm/boards/imx21ads/imx21ads.c | 24 ++++++------ + arch/arm/boards/pcm038/pcm038.c | 40 +++++++++--------- + arch/arm/mach-imx/include/mach/imxfb.h | 20 +++++---- + drivers/video/imx.c | 19 +++++---- + include/fb.h | 2 + + 8 files changed, 99 insertions(+), 93 deletions(-) + +diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +index 2b53766..a2bbaa3 100644 +--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c ++++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +@@ -107,7 +107,14 @@ struct imx_nand_platform_data nand_info = { + .hw_ecc = 1, + }; + +-static struct fb_videomode cmo_display = { ++static const struct imx_fb_driver_data driver_data = { ++ .pwmr = 0x00A903FF, ++ .lscr1 = 0x00120300, ++ .dmacr = 0x80040060, ++ .pcr = 0xCAD08B80, ++}; ++ ++static const struct fb_videomode cmo_display = { + .name = "CMO-QVGA", + .refresh = 60, + .xres = 320, +@@ -121,17 +128,9 @@ static struct fb_videomode cmo_display = { + .lower_margin = 4, + }; + +-static struct imx_fb_videomode imxfb_mode = { +- .mode = &cmo_display, +- .pcr = 0xCAD08B80, +- .bpp = 16, +-}; +- + static struct imx_fb_platform_data eukrea_cpuimx25_fb_data = { +- .mode = &imxfb_mode, +- .pwmr = 0x00A903FF, +- .lscr1 = 0x00120300, +- .dmacr = 0x80040060, ++ .mode = &cmo_display, ++ .mode_cnt = 1, + }; + + #ifdef CONFIG_USB +diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +index 3ee1057..b162611 100644 +--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c ++++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +@@ -167,7 +167,14 @@ static void eukrea_cpuimx27_mmu_init(void) + #endif + + #ifdef CONFIG_DRIVER_VIDEO_IMX +-static struct fb_videomode cmo_display = { ++static const struct imx_fb_driver_data driver_data = { ++ .pwmr = 0x00A903FF, ++ .lscr1 = 0x00120300, ++ .dmacr = 0x00020010, ++ .pcr = 0xFAD08B80, ++}; ++ ++static const struct fb_videomode cmo_display = { + .name = "CMO-QVGA", + .refresh = 60, + .xres = 320, +@@ -179,18 +186,12 @@ static struct fb_videomode cmo_display = { + .vsync_len = 3, + .upper_margin = 15, + .lower_margin = 4, ++ .priv = &driver_data, + }; + +-static struct imx_fb_videomode imxfb_mode = { +- .mode = &cmo_display, +- .pcr = 0xFAD08B80, +- .bpp = 16,}; +- + static struct imx_fb_platform_data eukrea_cpuimx27_fb_data = { +- .mode = &imxfb_mode, +- .pwmr = 0x00A903FF, +- .lscr1 = 0x00120300, +- .dmacr = 0x00020010, ++ .mode = &cmo_display, ++ .mode_cnt = 1, + }; + + static struct device_d imxfb_dev = { +diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c +index fba43bb..0c7a9fa 100644 +--- a/arch/arm/boards/guf-neso/board.c ++++ b/arch/arm/boards/guf-neso/board.c +@@ -78,22 +78,11 @@ static struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + +-static struct fb_videomode cpt_display = { +- .name = "CPT CLAA070LC0JCT", +- .refresh = 60, +- .xres = 800, +- .yres = 480, +- .pixclock = KHZ2PICOS(27000), +- .hsync_len = 1, /* DE only sync */ +- .left_margin = 50, +- .right_margin = 50, +- .vsync_len = 1, /* DE only sync */ +- .upper_margin = 10, +- .lower_margin = 10, +-}; +- +-static struct imx_fb_videomode imxfb_mode = { +- .mode = &cpt_display, ++static const struct imx_fb_driver_data driver_data = { ++ .pwmr = 0x00000000, /* doesn't matter */ ++ .lscr1 = 0x00120300, /* doesn't matter */ ++ /* dynamic mode -> using the reset values (as recommended in the datasheet) */ ++ .dmacr = (0 << 31) | (4 << 16) | 96, + /* + * - TFT style panel + * - clk enabled while idle +@@ -109,7 +98,21 @@ static struct imx_fb_videomode imxfb_mode = { + PCR_SCLK_SEL | + PCR_LPPOL | + PCR_FLMPOL, +- .bpp = 16, /* TODO 32 bit does not work: The 'green' component is lacking in this mode */ ++}; ++ ++static struct fb_videomode cpt_display = { ++ .name = "CPT CLAA070LC0JCT", ++ .refresh = 60, ++ .xres = 800, ++ .yres = 480, ++ .pixclock = KHZ2PICOS(27000), ++ .hsync_len = 1, /* DE only sync */ ++ .left_margin = 50, ++ .right_margin = 50, ++ .vsync_len = 1, /* DE only sync */ ++ .upper_margin = 10, ++ .lower_margin = 10, ++ .priv = &driver_data, + }; + + static void neso_fb_enable(int enable) +@@ -119,12 +122,10 @@ static void neso_fb_enable(int enable) + } + + static struct imx_fb_platform_data neso_fb_data = { +- .mode = &imxfb_mode, +- .pwmr = 0x00000000, /* doesn't matter */ +- .lscr1 = 0x00120300, /* doesn't matter */ +- /* dynamic mode -> using the reset values (as recommended in the datasheet) */ +- .dmacr = (0 << 31) | (4 << 16) | 96, ++ .mode = &cpt_display, ++ .mode_cnt = 1, + .enable = neso_fb_enable, ++ .bpp = 16, /* TODO 32 bit does not work: The 'green' component is lacking in this mode */ + .framebuffer_ovl = (void *)0xa7f00000, + }; + +diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c +index 8e145c7..299a3cd 100644 +--- a/arch/arm/boards/imx21ads/imx21ads.c ++++ b/arch/arm/boards/imx21ads/imx21ads.c +@@ -73,7 +73,14 @@ static struct device_d cs8900_dev = { + // IRQ is connected to UART3_RTS + }; + +-static struct fb_videomode sharp_display = { ++static const struct imx_fb_driver_data driver_data = { ++ .pwmr = 0x00a903ff, ++ .lscr1 = 0x00120300, ++ .dmacr = 0x00020008, ++ .pcr = 0xfb108bc7, ++}; ++ ++static const struct fb_videomode sharp_display = { + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, +@@ -88,23 +95,16 @@ static struct fb_videomode sharp_display = { + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +-}; +- +-/* Sharp LQ035Q7DB02 QVGA display */ +-static struct imx_fb_videomode imx_fb_modedata = { +- .mode = &sharp_display, +- .pcr = 0xfb108bc7, +- .bpp = 16, ++ .priv = &driver_data, + }; + + static struct imx_fb_platform_data imx_fb_data = { +- .mode = &imx_fb_modedata, ++/* Sharp LQ035Q7DB02 QVGA display */ ++ .mode = &sharp_display, ++ .mode_cnt = 1, + .cmap_greyscale = 0, + .cmap_inverse = 0, + .cmap_static = 0, +- .pwmr = 0x00a903ff, +- .lscr1 = 0x00120300, +- .dmacr = 0x00020008, + }; + + static int imx21ads_timing_init(void) +diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c +index 8cbb551..d5269f1 100644 +--- a/arch/arm/boards/pcm038/pcm038.c ++++ b/arch/arm/boards/pcm038/pcm038.c +@@ -107,7 +107,23 @@ static struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + +-static struct fb_videomode sharp_display = { ++static const struct imx_fb_driver_data driver_data = { ++ /* ++ * - HSYNC active high ++ * - VSYNC active high ++ * - clk notenabled while idle ++ * - clock not inverted ++ * - data not inverted ++ * - data enable low active ++ * - enable sharp mode ++ */ ++ .pwmr = 0x00A903FF, ++ .lscr1 = 0x00120300, ++ .dmacr = 0x00020010, ++ .pcr = 0xF00080C0, ++}; ++ ++static const struct fb_videomode sharp_display = { + .name = "Sharp-LQ035Q7", + .refresh = 60, + .xres = 240, +@@ -119,28 +135,12 @@ static struct fb_videomode sharp_display = { + .vsync_len = 1, + .upper_margin = 7, + .lower_margin = 9, +-}; +- +-static struct imx_fb_videomode imxfb_mode = { +- .mode = &sharp_display, +- /* +- * - HSYNC active high +- * - VSYNC active high +- * - clk notenabled while idle +- * - clock not inverted +- * - data not inverted +- * - data enable low active +- * - enable sharp mode +- */ +- .pcr = 0xF00080C0, +- .bpp = 16, ++ .priv = &driver_data, + }; + + static struct imx_fb_platform_data pcm038_fb_data = { +- .mode = &imxfb_mode, +- .pwmr = 0x00A903FF, +- .lscr1 = 0x00120300, +- .dmacr = 0x00020010, ++ .mode = &sharp_display, ++ .mode_cnt = 1, + }; + + #ifdef CONFIG_USB +diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h +index 4a890a7..f2083c4 100644 +--- a/arch/arm/mach-imx/include/mach/imxfb.h ++++ b/arch/arm/mach-imx/include/mach/imxfb.h +@@ -52,28 +52,30 @@ + #define DMACR_HM(x) (((x) & 0xf) << 16) + #define DMACR_TM(x) ((x) & 0xf) + +-struct imx_fb_videomode { +- struct fb_videomode *mode; +- u32 pcr; +- unsigned char bpp; ++/** ++ * Videomode dependent, but driver specific data ++ */ ++struct imx_fb_driver_data { ++ uint32_t pwmr; /**< refer datasheet: LPCCR register */ ++ uint32_t lscr1; /**< refer datasheet: LSCR register */ ++ uint32_t dmacr; /**< refer datasheet: LDCR register */ ++ uint32_t pcr; /**< refer datasheet: LPCR register */ + }; + + /** + * Define relevant framebuffer information + */ + struct imx_fb_platform_data { +- struct imx_fb_videomode *mode; ++ const struct fb_videomode *mode; + unsigned mode_cnt; /**< number of entries in 'mode' */ + ++ unsigned char bpp; /**< preferred colour depth for this device */ ++ + u_int cmap_greyscale:1, + cmap_inverse:1, + cmap_static:1, + unused:29; + +- u_int pwmr; +- u_int lscr1; +- u_int dmacr; +- + /** force a memory area to be used, else NULL for dynamic allocation */ + void *framebuffer; + /** force a memory area to be used, else NULL for dynamic allocation */ +diff --git a/drivers/video/imx.c b/drivers/video/imx.c +index b13f39d..69ba3e7 100644 +--- a/drivers/video/imx.c ++++ b/drivers/video/imx.c +@@ -332,6 +332,7 @@ static int imxfb_initialize_mode(struct fb_info *info, + unsigned long lcd_clk; + unsigned long long tmp; + struct imxfb_info *fbi = fb_info_to_imxfb_info(info); ++ const struct imx_fb_driver_data *drv_data = mode->priv; + u32 pcr; + unsigned size; + +@@ -342,6 +343,11 @@ static int imxfb_initialize_mode(struct fb_info *info, + + imxfb_memory_mmgt(info, size, MAIN_FBUFFER); + ++ fbi->pcr = drv_data->pcr; ++ fbi->pwmr = drv_data->pwmr; ++ fbi->lscr1 = drv_data->lscr1; ++ fbi->dmacr = drv_data->dmacr; ++ + /* physical screen start address */ + writel(VPW_VPW(mode->xres * info->bits_per_pixel / 8 / 4), + fbi->regs + LCDC_VPW); +@@ -541,7 +547,7 @@ static int imxfb_register_overlay(struct imxfb_info *fbi, + overlay->fb_setcolreg = imxfb_overlay_setcolreg; + + /* add runtime video info */ +- overlay->mode = pdata->mode->mode; ++ overlay->mode = pdata->mode; + overlay->mode_cnt = 1; /* no choice */ + + overlay_dev = register_framebuffer(overlay); +@@ -591,17 +597,12 @@ static int imxfb_probe(struct device_d *dev) + fbi->fb_host.fb_setcolreg = imxfb_setcolreg; + + fbi->regs = (void*)dev->map_base; +- fbi->pcr = pdata->mode->pcr; +- fbi->pwmr = pdata->pwmr; +- fbi->lscr1 = pdata->lscr1; +- fbi->dmacr = pdata->dmacr; + fbi->enable = pdata->enable; + + /* add runtime video info */ +- fbi->fb_host.mode = pdata->mode->mode; +- /* to be backward compatible */ +- fbi->fb_host.mode_cnt = pdata->mode_cnt == 0 ? 1 : pdata->mode_cnt; +- fbi->fb_host.bits_per_pixel = 16; /* RGB565, the default */ ++ fbi->fb_host.mode = pdata->mode; ++ fbi->fb_host.mode_cnt = pdata->mode_cnt; ++ fbi->fb_host.bits_per_pixel = pdata->bpp; + + fb_dev = register_framebuffer(&fbi->fb_host); + if (dev == NULL) { +diff --git a/include/fb.h b/include/fb.h +index 7e01e87..a9ad447 100644 +--- a/include/fb.h ++++ b/include/fb.h +@@ -69,6 +69,8 @@ struct fb_videomode { + unsigned sync; /**< sync information, refer FB_SYNC_* macros */ + unsigned vmode; /**< video mode information, refer FB_VMODE_* macros */ + unsigned flag; ++ ++ const void *priv; /**< video driver related information */ + }; + + /* Interpretation of offset for color fields: All offsets are from the right, +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0010-Add-a-video-driver-for-S3C2440-bases-platforms.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0010-Add-a-video-driver-for-S3C2440-bases-platforms.patch new file mode 100644 index 0000000..112e4aa --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0010-Add-a-video-driver-for-S3C2440-bases-platforms.patch @@ -0,0 +1,568 @@ +From fc905290d304e2d598bbdef723026a62fdc6759c Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <juergen@kreuzholzen.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 10/11] Add a video driver for S3C2440 bases platforms + +Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de> +--- + arch/arm/mach-s3c24xx/include/mach/fb.h | 40 +++ + drivers/video/Kconfig | 6 + + drivers/video/Makefile | 1 + + drivers/video/s3c.c | 474 +++++++++++++++++++++++++++++++ + 4 files changed, 521 insertions(+), 0 deletions(-) + create mode 100644 arch/arm/mach-s3c24xx/include/mach/fb.h + create mode 100644 drivers/video/s3c.c + +diff --git a/arch/arm/mach-s3c24xx/include/mach/fb.h b/arch/arm/mach-s3c24xx/include/mach/fb.h +new file mode 100644 +index 0000000..eec6164 +--- /dev/null ++++ b/arch/arm/mach-s3c24xx/include/mach/fb.h +@@ -0,0 +1,40 @@ ++/* ++ * Copyright (C) 2010 Juergen Beisert ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#ifndef __MACH_FB_H_ ++# define __MACH_FB_H_ ++ ++#include <fb.h> ++ ++struct s3c_fb_platform_data { ++ ++ const struct fb_videomode *mode_list; ++ unsigned mode_cnt; ++ ++ int passive_display; /**< enable support for STN or CSTN displays */ ++ ++ void *framebuffer; /**< force framebuffer base address */ ++ unsigned size; /**< force framebuffer size */ ++ ++ /** hook to enable backlight and stuff */ ++ void (*enable)(int); ++}; ++ ++#endif /* __MACH_FB_H_ */ +diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig +index b600444..f43c100 100644 +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -30,4 +30,10 @@ config DRIVER_VIDEO_IMX_IPU + Add support for the IPU framebuffer device found on + i.MX31 and i.MX35 CPUs. + ++config S3C_VIDEO ++ bool "S3C244x framebuffer driver" ++ depends on ARCH_S3C24xx ++ help ++ Add support for the S3C244x LCD controller. ++ + endif +diff --git a/drivers/video/Makefile b/drivers/video/Makefile +index 179f0c4..4287fc8 100644 +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -2,3 +2,4 @@ obj-$(CONFIG_VIDEO) += fb.o + + obj-$(CONFIG_DRIVER_VIDEO_IMX) += imx.o + obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o ++obj-$(CONFIG_S3C_VIDEO) += s3c.o +diff --git a/drivers/video/s3c.c b/drivers/video/s3c.c +new file mode 100644 +index 0000000..c831ebd +--- /dev/null ++++ b/drivers/video/s3c.c +@@ -0,0 +1,474 @@ ++/* ++ * Copyright (C) 2010 Juergen Beisert ++ * ++ * This driver is based on a patch found in the web: ++ * (C) Copyright 2006 by OpenMoko, Inc. ++ * Author: Harald Welte <laforge at openmoko.org> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <fb.h> ++#include <driver.h> ++#include <malloc.h> ++#include <errno.h> ++#include <asm/io.h> ++#include <mach/gpio.h> ++#include <mach/s3c24xx-generic.h> ++#include <mach/s3c24x0-clocks.h> ++#include <mach/fb.h> ++ ++#define LCDCON1 0x00 ++# define PNRMODE(x) (((x) & 3) << 5) ++# define BPPMODE(x) (((x) & 0xf) << 1) ++# define SET_CLKVAL(x) (((x) & 0x3ff) << 8) ++# define GET_CLKVAL(x) (((x) >> 8) & 0x3ff) ++# define ENVID (1 << 0) ++ ++#define LCDCON2 0x04 ++# define SET_VBPD(x) (((x) & 0xff) << 24) ++# define SET_LINEVAL(x) (((x) & 0x3ff) << 14) ++# define SET_VFPD(x) (((x) & 0xff) << 6) ++# define SET_VSPW(x) ((x) & 0x3f) ++ ++#define LCDCON3 0x08 ++# define SET_HBPD(x) (((x) & 0x7f) << 19) ++# define SET_HOZVAL(x) (((x) & 0x7ff) << 8) ++# define SET_HFPD(x) ((x) & 0xff) ++ ++#define LCDCON4 0x0c ++# define SET_HSPW(x) ((x) & 0xff) ++ ++#define LCDCON5 0x10 ++# define BPP24BL (1 << 12) ++# define FRM565 (1 << 11) ++# define INV_CLK (1 << 10) ++# define INV_HS (1 << 9) ++# define INV_VS (1 << 8) ++# define INV_DTA (1 << 7) ++# define INV_DE (1 << 6) ++# define INV_PWREN (1 << 5) ++# define INV_LEND (1 << 4) /* FIXME */ ++# define ENA_PWREN (1 << 3) ++# define ENA_LEND (1 << 2) /* FIXME */ ++# define BSWP (1 << 1) ++# define HWSWP (1 << 0) ++ ++#define LCDSADDR1 0x14 ++# define SET_LCDBANK(x) (((x) & 0x1ff) << 21) ++# define GET_LCDBANK(x) (((x) >> 21) & 0x1ff) ++# define SET_LCDBASEU(x) ((x) & 0x1fffff) ++# define GET_LCDBASEU(x) ((x) & 0x1fffff) ++ ++#define LCDSADDR2 0x18 ++# define SET_LCDBASEL(x) ((x) & 0x1fffff) ++# define GET_LCDBASEL(x) ((x) & 0x1fffff) ++ ++#define LCDSADDR3 0x1c ++# define SET_OFFSIZE(x) (((x) & 0x7ff) << 11) ++# define GET_OFFSIZE(x) (((x) >> 11) & 0x7ff) ++# define SET_PAGE_WIDTH(x) ((x) & 0x3ff) ++# define GET_PAGE_WIDTH(x) ((x) & 0x3ff) ++ ++#define RED_LUT 0x20 ++#define GREEN_LUT 0x24 ++#define BLUE_LUT 0x28 ++ ++#define DITHMODE 0x4c ++ ++#define TPAL 0x50 ++ ++#define LCDINTPND 0x54 ++ ++#define LCDSRCPND 0x58 ++ ++#define LCDINTMSK 0x5c ++# define FIWSEL (1 << 2) ++ ++#define TCONSEL 0x60 ++ ++#define RED 0 ++#define GREEN 1 ++#define BLUE 2 ++#define TRANSP 3 ++ ++struct s3cfb_host { ++ struct fb_host fb_data; ++ struct device_d *hw_dev; ++ struct s3c_fb_platform_data *pdata; /* shortcut to hw_dev->platform_data */ ++ void __iomem *base; ++}; ++ ++#define fb_info_to_s3cfb_host(x) ((struct s3cfb_host*)((x)->host)) ++ ++/* the RGB565 true colour mode */ ++static const struct fb_bitfield def_rgb565[] = { ++ [RED] = { ++ .offset = 11, ++ .length = 5, ++ }, ++ [GREEN] = { ++ .offset = 5, ++ .length = 6, ++ }, ++ [BLUE] = { ++ .offset = 0, ++ .length = 5, ++ }, ++ [TRANSP] = { /* no support for transparency */ ++ .length = 0, ++ } ++}; ++ ++/* the RGB888 true colour mode */ ++static const struct fb_bitfield def_rgb888[] = { ++ [RED] = { ++ .offset = 16, ++ .length = 8, ++ }, ++ [GREEN] = { ++ .offset = 8, ++ .length = 8, ++ }, ++ [BLUE] = { ++ .offset = 0, ++ .length = 8, ++ }, ++ [TRANSP] = { /* no support for transparency */ ++ .length = 0, ++ } ++}; ++ ++/** ++ * @param fb_info Framebuffer information ++ */ ++static void s3cfb_enable_controller(struct fb_info *fb_info) ++{ ++ struct s3cfb_host *fbh = fb_info_to_s3cfb_host(fb_info); ++ struct s3c_fb_platform_data *pdata = fbh->pdata; ++ uint32_t con1; ++ ++ con1 = readl(fbh->base + LCDCON1); ++ ++ con1 |= ENVID; ++ ++ writel(con1, fbh->base + LCDCON1); ++ ++ if (pdata->enable) ++ pdata->enable(1); ++} ++ ++/** ++ * @param fb_info Framebuffer information ++ */ ++static void s3cfb_disable_controller(struct fb_info *fb_info) ++{ ++ struct s3cfb_host *fbh = fb_info_to_s3cfb_host(fb_info); ++ struct s3c_fb_platform_data *pdata = fbh->pdata; ++ uint32_t con1; ++ ++ if (pdata->enable) ++ pdata->enable(0); ++ ++ con1 = readl(fbh->base + LCDCON1); ++ ++ con1 &= ~ENVID; ++ ++ writel(con1, fbh->base + LCDCON1); ++} ++ ++/** ++ * Framebuffer memory management ++ * @param fb_info Framebuffer information ++ * @param size Requested framebuffer size in bytes ++ * @return 0 on success ++ * ++ * If the user forces a fixed memory location, try to map the framebuffer into ++ * it. If it does not match, report an error. If no fixed memory location ++ * exists do memory allocation in a dynamic manner. ++ */ ++static int s3cfb_memory_mmgt(struct fb_info *fb_info, unsigned size) ++{ ++ struct s3cfb_host *fbh = fb_info_to_s3cfb_host(fb_info); ++ struct s3c_fb_platform_data *pdata = fbh->pdata; ++ ++ if (pdata->framebuffer != NULL) { ++ /* fixed memory location */ ++ if (pdata->size < size) ++ return -EINVAL; ++ fb_info->fb_dev.map_base = (resource_size_t)pdata->framebuffer; ++ fb_info->fb_dev.size = size; ++ } else { ++ /* dynamic memory location */ ++ if ((fb_info->fb_dev.size < size) && ++ (fb_info->fb_dev.size != 0)) { ++ free((void*)fb_info->fb_dev.map_base); ++ fb_info->fb_dev.map_base = 0; ++ fb_info->fb_dev.size = 0; ++ } ++ if (fb_info->fb_dev.size == 0) { ++ /* allocate more space on platform request */ ++ if (pdata->size > size) ++ size = pdata->size; ++ fb_info->fb_dev.map_base = ++ (resource_size_t)xzalloc(size); ++ fb_info->fb_dev.size = size; ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * Prepare the video hardware for a specified video mode ++ * @param fb_info Framebuffer information ++ * @param mode The video mode description to setup ++ * @return 0 on success ++ */ ++static int s3cfb_initialize_mode(struct fb_info *fb_info, ++ const struct fb_videomode *mode) ++{ ++ struct s3cfb_host *fbh = fb_info_to_s3cfb_host(fb_info); ++ struct s3c_fb_platform_data *pdata = fbh->pdata; ++ unsigned size, hclk, div; ++ int rc; ++ uint32_t con1, con2, con3, con4, con5 = 0; ++ ++ if (pdata->passive_display != 0) { ++ dev_err(fbh->hw_dev, ++ "Passive displays are currently not supported\n"); ++ return -EINVAL; ++ } ++ ++ /* ++ * we need at least this amount of memory for the framebuffer ++ */ ++ size = mode->xres * mode->yres * (fb_info->bits_per_pixel >> 3); ++ ++ rc = s3cfb_memory_mmgt(fb_info, size); ++ if (rc != 0) { ++ dev_err(fbh->hw_dev, "Cannot allocate framebuffer memory\n"); ++ return rc; ++ } ++ ++ /* its useful to enable the unit's clock */ ++ s3c244x_mod_clock(CLK_LCDC, 1); ++ ++ /* ensure video output is _off_ */ ++ writel(0x00000000, fbh->base + LCDCON1); ++ ++ hclk = s3c24xx_get_hclk() / 1000U; /* hclk in kHz */ ++ div = hclk / PICOS2KHZ(mode->pixclock); ++ if (div < 3) ++ div = 3; ++ /* pixel clock is: (hclk) / ((div + 1) * 2) */ ++ div += 1; ++ div >>= 1; ++ div -= 1; ++ ++ con1 = PNRMODE(3) | SET_CLKVAL(div); /* PNRMODE=3 is TFT */ ++ ++ switch (fb_info->bits_per_pixel) { ++#if 0 ++ /** @todo S3C2440: Add CLUT based videomodes */ ++ case 1: ++ con1 |= BPPMODE(8); ++ break; ++ case 2: ++ con1 |= BPPMODE(9); ++ break; ++ case 4: ++ con1 |= BPPMODE(10); ++ break; ++ case 8: ++ con1 |= BPPMODE(11); ++ break; ++#endif ++ case 16: ++ con1 |= BPPMODE(12); ++ con5 |= FRM565; ++ fb_info->red = def_rgb565[RED]; ++ fb_info->green = def_rgb565[GREEN]; ++ fb_info->blue = def_rgb565[BLUE]; ++ fb_info->transp = def_rgb565[TRANSP]; ++ break; ++ case 24: ++ con1 |= BPPMODE(13); ++ /** @todo S3C2440: Define the correct byte order ++ * for 24 bpp in memory (BPP24BL) ++ */ ++ con5 |= BPP24BL; ++ fb_info->red = def_rgb888[RED]; ++ fb_info->green = def_rgb888[GREEN]; ++ fb_info->blue = def_rgb888[BLUE]; ++ fb_info->transp = def_rgb888[TRANSP]; ++ break; ++ default: ++ dev_err(fbh->hw_dev, "Invalid bits per pixel value: %u\n", ++ fb_info->bits_per_pixel); ++ return -EINVAL; ++ } ++ ++ /* 'normal' in register description means positive logic */ ++ if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) ++ con5 |= INV_HS; ++ if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) ++ con5 |= INV_VS; ++ if (!(mode->sync & FB_SYNC_DE_HIGH_ACT)) ++ con5 |= INV_DE; ++ if (mode->sync & FB_SYNC_CLK_INVERT) ++ con5 |= INV_CLK; /* display should latch at the rising edge */ ++ if (mode->sync & FB_SYNC_SWAP_RGB) ++ con5 |= HWSWP; ++ ++ /** @todo S3C2440: LCD power enable via platform data */ ++ ++ /* vertical timing */ ++ con2 = SET_VBPD(mode->upper_margin - 1) | ++ SET_LINEVAL(mode->yres - 1) | ++ SET_VFPD(mode->lower_margin - 1) | ++ SET_VSPW(mode->vsync_len - 1); ++ ++ /* horizontal timing */ ++ con3 = SET_HBPD(mode->left_margin - 1) | ++ SET_HOZVAL(mode->xres - 1) | ++ SET_HFPD(mode->right_margin - 1); ++ con4 = SET_HSPW(mode->hsync_len - 1); ++ ++ /* basic timing setup */ ++ writel(con1, fbh->base + LCDCON1); ++ writel(con2, fbh->base + LCDCON2); ++ writel(con3, fbh->base + LCDCON3); ++ writel(con4, fbh->base + LCDCON4); ++ writel(con5, fbh->base + LCDCON5); ++ ++ /* framebuffer memory setup */ ++ writel(((uint32_t)fb_info->fb_dev.map_base) >> 1, ++ fbh->base + LCDSADDR1); ++ ++ writel(SET_LCDBASEL(((uint32_t)fb_info->fb_dev.map_base + size) >> 1), ++ fbh->base + LCDSADDR2); ++ ++ writel(SET_OFFSIZE(0) | ++ SET_PAGE_WIDTH((mode->xres * fb_info->bits_per_pixel) >> 4), ++ fbh->base + LCDSADDR3); ++ ++ writel(FIWSEL, fbh->base + LCDINTMSK); ++ ++ return 0; ++} ++ ++/** ++ * Print some information about the current hardware state ++ * @param hw_dev S3C video device ++ */ ++#ifdef CONFIG_VIDEO_INFO_VERBOSE ++static void s3cfb_info(struct device_d *hw_dev) ++{ ++ uint32_t con1, addr1, addr2, addr3; ++ ++ con1 = readl(hw_dev->map_base + LCDCON1); ++ addr1 = readl(hw_dev->map_base + LCDSADDR1); ++ addr2 = readl(hw_dev->map_base + LCDSADDR2); ++ addr3 = readl(hw_dev->map_base + LCDSADDR3); ++ ++ printf(" Video hardware info:\n"); ++ printf(" Video clock is running at %u Hz\n", ++ s3c24xx_get_hclk() / ((GET_CLKVAL(con1) + 1) * 2)); ++ printf(" Video memory bank starts at 0x%08X\n", ++ GET_LCDBANK(addr1) << 22); ++ printf(" Video memory bank offset: 0x%08X\n", ++ GET_LCDBASEU(addr1)); ++ printf(" Video memory end: 0x%08X\n", ++ GET_LCDBASEU(addr2)); ++ printf(" Virtual screen offset size: %u half words\n", ++ GET_OFFSIZE(addr3)); ++ printf(" Virtual screen page width: %u half words\n", ++ GET_PAGE_WIDTH(addr3)); ++} ++#endif ++ ++/* ++ * There is only one video hardware instance available. ++ * It makes no sense to dynamically allocate this data ++ */ ++static struct s3cfb_host host_data = { ++ .fb_data.fb_mode = s3cfb_initialize_mode, ++ .fb_data.fb_enable = s3cfb_enable_controller, ++ .fb_data.fb_disable = s3cfb_disable_controller, ++}; ++ ++static int s3cfb_probe(struct device_d *hw_dev) ++{ ++ struct s3c_fb_platform_data *pdata = hw_dev->platform_data; ++ struct device_d *fb_dev; ++ ++ if (pdata == NULL) { ++ dev_err(hw_dev, "Framebuffer driver missing platform data"); ++ return -ENODEV; ++ } ++ ++ /* enable unit's clock */ ++ s3c244x_mod_clock(CLK_LCDC, 1); ++ ++ writel(0, hw_dev->map_base + LCDCON1); ++ ++ /** @todo S3C2440: LCD power disable via platform data */ ++ writel(0, hw_dev->map_base + LCDCON5); ++ ++ /* disable it again until user request */ ++ s3c244x_mod_clock(CLK_LCDC, 0); ++ ++ /* add runtime hardware info */ ++ host_data.hw_dev = hw_dev; ++ host_data.base = (void*)hw_dev->map_base; ++ ++ /* add runtime video info */ ++ host_data.fb_data.mode = pdata->mode_list; ++ host_data.fb_data.mode_cnt = pdata->mode_cnt; ++ ++ fb_dev = register_framebuffer(&host_data.fb_data); ++ if (fb_dev == NULL) { ++ dev_err(hw_dev, "Failed to register framebuffer\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static struct driver_d s3cfb_driver = { ++ .name = "s3cfb", ++ .probe = s3cfb_probe, ++#ifdef CONFIG_VIDEO_INFO_VERBOSE ++ .info = s3cfb_info, ++#endif ++}; ++ ++static int s3cfb_init(void) ++{ ++ return register_driver(&s3cfb_driver); ++} ++ ++device_initcall(s3cfb_init); ++ ++/** ++ * The S3C244x LCD controller supports passive (CSTN/STN) and active (TFT) ++ * LC displays ++ * ++ * The driver itself currently supports only active TFT LC displays in the ++ * follwing manner: ++ * ++ * * True colours ++ * - 16 bpp ++ * - 24 bpp ++ */ +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/0011-STM378x-Add-video-driver-for-this-platform.patch b/configs/platform-chumby/patches/barebox-2010.11.0/0011-STM378x-Add-video-driver-for-this-platform.patch new file mode 100644 index 0000000..dc5f7ac --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/0011-STM378x-Add-video-driver-for-this-platform.patch @@ -0,0 +1,736 @@ +From 42aa785dba2fa66770b85607152f5b3438942edf Mon Sep 17 00:00:00 2001 +From: Juergen Beisert <jbe@pengutronix.de> +Date: Fri, 19 Nov 2010 12:53:16 +0100 +Subject: [PATCH 11/11] STM378x: Add video driver for this platform + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/mach-stm/include/mach/fb.h | 33 ++ + drivers/video/Kconfig | 7 + + drivers/video/Makefile | 1 + + drivers/video/stm.c | 646 +++++++++++++++++++++++++++++++++++ + 4 files changed, 687 insertions(+), 0 deletions(-) + create mode 100644 arch/arm/mach-stm/include/mach/fb.h + create mode 100644 drivers/video/stm.c + +diff --git a/arch/arm/mach-stm/include/mach/fb.h b/arch/arm/mach-stm/include/mach/fb.h +new file mode 100644 +index 0000000..6def0c1 +--- /dev/null ++++ b/arch/arm/mach-stm/include/mach/fb.h +@@ -0,0 +1,33 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#ifndef __MACH_FB_H ++# define __MACH_FB_H ++ ++#include <fb.h> ++ ++#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ ++#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ ++#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ ++#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ ++ ++struct imx_fb_videomode { ++ struct fb_videomode *mode_list; ++ unsigned mode_count; ++ void *framebuffer; /**< force fixed framebuffer address if != NULL */ ++ unsigned size; /**< force fixed size if != NULL */ ++ ++ unsigned dotclk_delay; /**< refer manual HW_LCDIF_VDCTRL4 register */ ++ unsigned ld_intf_width; /**< refer STMLCDIF_* macros */ ++}; ++ ++#endif /* __MACH_FB_H */ ++ +diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig +index f43c100..7174451 100644 +--- a/drivers/video/Kconfig ++++ b/drivers/video/Kconfig +@@ -36,4 +36,11 @@ config S3C_VIDEO + help + Add support for the S3C244x LCD controller. + ++config DRIVER_VIDEO_STM ++ bool "i.MX23/28 framebuffer driver" ++ depends on ARCH_STM ++ help ++ Say 'Y' here to enable framebuffer and spash screen support for ++ i.MX23 and i.MX28 based systems. ++ + endif +diff --git a/drivers/video/Makefile b/drivers/video/Makefile +index 4287fc8..0ddb81e 100644 +--- a/drivers/video/Makefile ++++ b/drivers/video/Makefile +@@ -1,5 +1,6 @@ + obj-$(CONFIG_VIDEO) += fb.o + ++obj-$(CONFIG_DRIVER_VIDEO_STM) += stm.o + obj-$(CONFIG_DRIVER_VIDEO_IMX) += imx.o + obj-$(CONFIG_DRIVER_VIDEO_IMX_IPU) += imx-ipu-fb.o + obj-$(CONFIG_S3C_VIDEO) += s3c.o +diff --git a/drivers/video/stm.c b/drivers/video/stm.c +new file mode 100644 +index 0000000..747dc04 +--- /dev/null ++++ b/drivers/video/stm.c +@@ -0,0 +1,646 @@ ++/* ++ * Copyright (C) 2010 Juergen Beisert, Pengutronix ++ * ++ * This code is based on: ++ * Author: Vitaly Wool <vital@embeddedalley.com> ++ * ++ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++/** ++ * @file ++ * @brief LCDIF driver for i.MX23 and i.MX28 (i.MX23 untested yet) ++ * ++ * The LCDIF support four modes of operation ++ * - MPU interface (to drive smart displays) -> not supported yet ++ * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet ++ * - Dotclock interface (to drive LC displays with RGB data and sync signals) ++ * - DVI (to drive ITU-R BT656) -> not supported yet ++ * ++ * This driver depends on a correct setup of the pins used for this purpose ++ * (platform specific). ++ * ++ * For the developer: Don't forget to set the data bus width to the display ++ * in the imx_fb_videomode structure. You will else end up with ugly colours. ++ * If you fight against jitter you can vary the clock delay. This is a feature ++ * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give ++ * the required value in the imx_fb_videomode structure. ++ */ ++ ++/* #define DEBUG */ ++ ++#include <common.h> ++#include <init.h> ++#include <driver.h> ++#include <malloc.h> ++#include <errno.h> ++#include <xfuncs.h> ++#include <asm/io.h> ++#include <mach/clock.h> ++#include <mach/fb.h> ++ ++#define HW_LCDIF_CTRL 0x00 ++# define CTRL_SFTRST (1 << 31) ++# define CTRL_CLKGATE (1 << 30) ++# define CTRL_BYPASS_COUNT (1 << 19) ++# define CTRL_VSYNC_MODE (1 << 18) ++# define CTRL_DOTCLK_MODE (1 << 17) ++# define CTRL_DATA_SELECT (1 << 16) ++# define SET_BUS_WIDTH(x) (((x) & 0x3) << 10) ++# define SET_WORD_LENGTH(x) (((x) & 0x3) << 8) ++# define GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) ++# define CTRL_MASTER (1 << 5) ++# define CTRL_DF16 (1 << 3) ++# define CTRL_DF18 (1 << 2) ++# define CTRL_DF24 (1 << 1) ++# define CTRL_RUN (1 << 0) ++ ++#define HW_LCDIF_CTRL1 0x10 ++# define CTRL1_FIFO_CLEAR (1 << 21) ++# define SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) ++# define GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) ++ ++#ifdef CONFIG_ARCH_IMX28 ++#define HW_LCDIF_CTRL2 0x20 ++#define HW_LCDIF_TRANSFER_COUNT 0x30 ++#endif ++#ifdef CONFIG_ARCH_IMX23 ++#define HW_LCDIF_TRANSFER_COUNT 0x20 ++#endif ++# define SET_VCOUNT(x) (((x) & 0xffff) << 16) ++# define SET_HCOUNT(x) ((x) & 0xffff) ++ ++#ifdef CONFIG_ARCH_IMX28 ++#define HW_LCDIF_CUR_BUF 0x40 ++#define HW_LCDIF_NEXT_BUF 0x50 ++#endif ++#ifdef CONFIG_ARCH_IMX23 ++#define HW_LCDIF_CUR_BUF 0x30 ++#define HW_LCDIF_NEXT_BUF 0x40 ++#endif ++ ++#define HW_LCDIF_TIMING 0x60 ++# define SET_CMD_HOLD(x) (((x) & 0xff) << 24) ++# define SET_CMD_SETUP(x) (((x) & 0xff) << 16) ++# define SET_DATA_HOLD(x) (((x) & 0xff) << 8) ++# define SET_DATA_SETUP(x) ((x) & 0xff)) ++ ++#define HW_LCDIF_VDCTRL0 0x70 ++# define VDCTRL0_ENABLE_PRESENT (1 << 28) ++# define VDCTRL0_VSYNC_POL (1 << 27) /* 0 = low active, 1 = high active */ ++# define VDCTRL0_HSYNC_POL (1 << 26) /* 0 = low active, 1 = high active */ ++# define VDCTRL0_DOTCLK_POL (1 << 25) /* 0 = output@falling, capturing@rising edge */ ++# define VDCTRL0_ENABLE_POL (1 << 24) /* 0 = low active, 1 = high active */ ++# define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) ++# define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) ++# define VDCTRL0_HALF_LINE (1 << 19) ++# define VDCTRL0_HALF_LINE_MODE (1 << 18) ++# define SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) ++ ++#define HW_LCDIF_VDCTRL1 0x80 ++ ++#define HW_LCDIF_VDCTRL2 0x90 ++#ifdef CONFIG_ARCH_IMX28 ++# define SET_HSYNC_PULSE_WIDTH(x) (((x) & 0x3fff) << 18) ++#endif ++#ifdef CONFIG_ARCH_IMX23 ++# define SET_HSYNC_PULSE_WIDTH(x) (((x) & 0xff) << 24) ++#endif ++# define SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) ++ ++#define HW_LCDIF_VDCTRL3 0xa0 ++# define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) ++# define VDCTRL3_VSYNC_ONLY (1 << 28) ++# define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) ++# define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) ++ ++#define HW_LCDIF_VDCTRL4 0xb0 ++#ifdef CONFIG_ARCH_IMX28 ++# define SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) ++#endif ++# define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) ++# define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) ++ ++#define HW_LCDIF_DVICTRL0 0xc0 ++#define HW_LCDIF_DVICTRL1 0xd0 ++#define HW_LCDIF_DVICTRL2 0xe0 ++#define HW_LCDIF_DVICTRL3 0xf0 ++#define HW_LCDIF_DVICTRL4 0x100 ++ ++#ifdef CONFIG_ARCH_IMX28 ++#define HW_LCDIF_DATA 0x180 ++#endif ++#ifdef CONFIG_ARCH_IMX23 ++#define HW_LCDIF_DATA 0x1b0 ++#endif ++ ++#ifdef CONFIG_ARCH_IMX28 ++#define HW_LCDIF_DEBUG0 0x1d0 ++#endif ++#ifdef CONFIG_ARCH_IMX23 ++#define HW_LCDIF_DEBUG0 0x1f0 ++#endif ++# define DEBUG_HSYNC (1 < 26) ++# define DEBUG_VSYNC (1 < 25) ++ ++#define RED 0 ++#define GREEN 1 ++#define BLUE 2 ++#define TRANSP 3 ++ ++struct imxfb_host { ++ struct fb_host fb_data; ++ struct device_d *hw_dev; ++ struct imx_fb_videomode *pdata; ++ void __iomem *base; ++}; ++ ++#define fb_info_to_imxfb_host(x) ((struct imxfb_host*)((x)->host)) ++ ++/* the RGB565 true colour mode */ ++static const struct fb_bitfield def_rgb565[] = { ++ [RED] = { ++ .offset = 11, ++ .length = 5, ++ }, ++ [GREEN] = { ++ .offset = 5, ++ .length = 6, ++ }, ++ [BLUE] = { ++ .offset = 0, ++ .length = 5, ++ }, ++ [TRANSP] = { /* no support for transparency */ ++ .length = 0, ++ } ++}; ++ ++/* the RGB666 true colour mode */ ++static const struct fb_bitfield def_rgb666[] = { ++ [RED] = { ++ .offset = 16, ++ .length = 6, ++ }, ++ [GREEN] = { ++ .offset = 8, ++ .length = 6, ++ }, ++ [BLUE] = { ++ .offset = 0, ++ .length = 6, ++ }, ++ [TRANSP] = { /* no support for transparency */ ++ .length = 0, ++ } ++}; ++ ++/* the RGB888 true colour mode */ ++static const struct fb_bitfield def_rgb888[] = { ++ [RED] = { ++ .offset = 16, ++ .length = 8, ++ }, ++ [GREEN] = { ++ .offset = 8, ++ .length = 8, ++ }, ++ [BLUE] = { ++ .offset = 0, ++ .length = 8, ++ }, ++ [TRANSP] = { /* no support for transparency */ ++ .length = 0, ++ } ++}; ++ ++/** ++ * Just calculate the amount of required bytes per line ++ * @param ppl Used pixel per line ++ * @param bpp Bits per pixel ++ * @return Byte count ++ * ++ * @note This routine expects a non packed pixel mode ++ * (e.g. four bytes per pixel in 24 bpp mode). ++ */ ++static inline unsigned calc_line_length(unsigned ppl, unsigned bpp) ++{ ++ if (bpp == 24) ++ bpp = 32; ++ return (ppl * bpp) >> 3; ++} ++ ++/** ++ * Framebuffer memory management ++ * @param fb_info Framebuffer information ++ * @param size Requested framebuffer size in bytes ++ * @return 0 on success ++ * ++ * If the user forces a fixed memory location, try to map the framebuffer into ++ * it. If it does not match, report an error. If no fixed memory location ++ * exists do memory allocation in a dynamic manner. ++ */ ++static int stmfb_memory_mmgt(struct fb_info *fb_info, unsigned size) ++{ ++ struct imxfb_host *fbh = fb_info_to_imxfb_host(fb_info); ++ struct imx_fb_videomode *pdata = fbh->pdata; ++ ++ if (pdata->framebuffer != NULL) { ++ /* fixed memory location */ ++ if (pdata->size < size) ++ return -EINVAL; ++ fb_info->fb_dev.map_base = (resource_size_t)pdata->framebuffer; ++ fb_info->fb_dev.size = size; ++ } else { ++ /* dynamic memory location */ ++ if ((fb_info->fb_dev.size < size) && ++ (fb_info->fb_dev.size != 0)) { ++ free((void*)fb_info->fb_dev.map_base); ++ fb_info->fb_dev.map_base = 0; ++ fb_info->fb_dev.size = 0; ++ } ++ if (fb_info->fb_dev.size == 0) { ++ /* allocate more space on platform request */ ++ if (pdata->size > size) ++ size = pdata->size; ++ fb_info->fb_dev.map_base = ++ (resource_size_t)xzalloc(size); ++ fb_info->fb_dev.size = size; ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * Prepare the video hardware for a specified video mode ++ * @param fb_info Framebuffer information ++ * @param mode The video mode description to initialize ++ * @return 0 on success ++ * ++ * Dotclock mode: ++ * One line of pixels or one frame in the i.MX23/i.MX28 is defined to: ++ * @verbatim ++ * |<---------------------- one line period -------------------------------->| ++ * |<- HSync length ->| ++ * |<----- Start of line --->| ++ * |<-------- active line data ------>| ++ * ++ * |<------------------------ frame period --------------------------------->| ++ * |<- VSync length ->| ++ * |<--- Start of 1. line -->| ++ * |<---------- active lines -------->| ++ * @endverbatim ++ * Based on the values from struct fb_videomode: ++ * - "one line period" = left_margin + xres + right_margin + hsync_len ++ * - "HSync length" = hsync_len ++ * - "Start of line" = hsync_len + left_margin ++ * - "active line data" = xres ++ */ ++static int stmfb_initialize_mode(struct fb_info *fb_info, ++ const struct fb_videomode *mode) ++{ ++ struct imxfb_host *fbh = fb_info_to_imxfb_host(fb_info); ++ struct imx_fb_videomode *pdata = fbh->pdata; ++ uint32_t reg; ++ int rc; ++ unsigned size; ++ ++ /* ++ * we need at least this amount of memory for the framebuffer ++ */ ++ size = calc_line_length(mode->xres, fb_info->bits_per_pixel) * ++ mode->yres; ++ ++ rc = stmfb_memory_mmgt(fb_info, size); ++ if (rc != 0) { ++ dev_err(fbh->hw_dev, "Cannot allocate framebuffer memory\n"); ++ return rc; ++ } ++ ++ /** @todo ensure HCLK is active at this point of time! */ ++ ++ size = imx_set_lcdifclk(PICOS2KHZ(mode->pixclock)); ++ if (size == 0) { ++ dev_dbg(fbh->hw_dev, "Unable to set a valid pixel clock\n"); ++ return -EINVAL; ++ } ++ ++ /* ++ * bring the controller out of reset and ++ * configure it into DOTCLOCK mode ++ */ ++ reg = CTRL_BYPASS_COUNT | /* always in DOTCLOCK mode */ ++ CTRL_DOTCLK_MODE; ++ writel(reg, fbh->base + HW_LCDIF_CTRL); ++ ++ /* master mode only */ ++ reg |= CTRL_MASTER; ++ ++ /* ++ * Configure videomode and interface mode ++ */ ++ reg |= SET_BUS_WIDTH(pdata->ld_intf_width); ++ switch (fb_info->bits_per_pixel) { ++ case 8: ++ reg |= SET_WORD_LENGTH(1); ++ /** @todo refer manual page 2046 for 8 bpp modes */ ++ dev_dbg(fbh->hw_dev, "8 bpp mode not supported yet\n"); ++ break; ++ case 16: ++ pr_debug("Setting up an RGB565 mode\n"); ++ reg |= SET_WORD_LENGTH(0); ++ reg &= ~CTRL_DF16; /* we assume RGB565 */ ++ writel(SET_BYTE_PACKAGING(0xf), fbh->base + HW_LCDIF_CTRL1); ++ fb_info->red = def_rgb565[RED]; ++ fb_info->green = def_rgb565[GREEN]; ++ fb_info->blue = def_rgb565[BLUE]; ++ fb_info->transp = def_rgb565[TRANSP]; ++ break; ++ case 24: ++ case 32: ++ pr_debug("Setting up an RGB888/666 mode\n"); ++ reg |= SET_WORD_LENGTH(3); ++ switch (pdata->ld_intf_width) { ++ case STMLCDIF_8BIT: ++ dev_dbg(fbh->hw_dev, ++ "Unsupported LCD bus width mapping\n"); ++ break; ++ case STMLCDIF_16BIT: ++ case STMLCDIF_18BIT: ++ /* 24 bit to 18 bit mapping ++ * which means: ignore the upper 2 bits in ++ * each colour component ++ */ ++ reg |= CTRL_DF24; ++ fb_info->red = def_rgb666[RED]; ++ fb_info->green = def_rgb666[GREEN]; ++ fb_info->blue = def_rgb666[BLUE]; ++ fb_info->transp = def_rgb666[TRANSP]; ++ break; ++ case STMLCDIF_24BIT: ++ /* real 24 bit */ ++ fb_info->red = def_rgb888[RED]; ++ fb_info->green = def_rgb888[GREEN]; ++ fb_info->blue = def_rgb888[BLUE]; ++ fb_info->transp = def_rgb888[TRANSP]; ++ break; ++ } ++ /* do not use packed pixels = one pixel per word instead */ ++ writel(SET_BYTE_PACKAGING(0x7), fbh->base + HW_LCDIF_CTRL1); ++ break; ++ default: ++ dev_dbg(fbh->hw_dev, "Unhandled colour depth of %u\n", ++ fb_info->bits_per_pixel); ++ return -EINVAL; ++ } ++ writel(reg, fbh->base + HW_LCDIF_CTRL); ++ pr_debug("Setting up CTRL to %08X\n", reg); ++ ++ writel(SET_VCOUNT(mode->yres) | ++ SET_HCOUNT(mode->xres), fbh->base + HW_LCDIF_TRANSFER_COUNT); ++ ++ reg = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ ++ VDCTRL0_VSYNC_PERIOD_UNIT | ++ VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; ++ if (mode->sync & FB_SYNC_HOR_HIGH_ACT) ++ reg |= VDCTRL0_HSYNC_POL; ++ if (mode->sync & FB_SYNC_VERT_HIGH_ACT) ++ reg |= VDCTRL0_VSYNC_POL; ++ if (mode->sync & FB_SYNC_DE_HIGH_ACT) ++ reg |= VDCTRL0_ENABLE_POL; ++ if (mode->sync & FB_SYNC_CLK_INVERT) ++ reg |= VDCTRL0_DOTCLK_POL; ++ ++ reg |= SET_VSYNC_PULSE_WIDTH(mode->vsync_len); ++ writel(reg, fbh->base + HW_LCDIF_VDCTRL0); ++ pr_debug("Setting up VDCTRL0 to %08X\n", reg); ++ ++ /* frame length in lines */ ++ writel(mode->upper_margin + mode->vsync_len + mode->lower_margin + ++ mode->yres, ++ fbh->base + HW_LCDIF_VDCTRL1); ++ ++ /* line length in units of clocks or pixels */ ++ writel(SET_HSYNC_PULSE_WIDTH(mode->hsync_len) | ++ SET_HSYNC_PERIOD(mode->left_margin + mode->hsync_len + ++ mode->right_margin + mode->xres), ++ fbh->base + HW_LCDIF_VDCTRL2); ++ ++ writel(SET_HOR_WAIT_CNT(mode->left_margin + mode->hsync_len) | ++ SET_VERT_WAIT_CNT(mode->upper_margin + mode->vsync_len), ++ fbh->base + HW_LCDIF_VDCTRL3); ++ ++ writel( ++#ifdef CONFIG_ARCH_IMX28 ++ SET_DOTCLK_DLY(pdata->dotclk_delay) | ++#endif ++ SET_DOTCLK_H_VALID_DATA_CNT(mode->xres), ++ fbh->base + HW_LCDIF_VDCTRL4); ++ ++ writel((uint32_t)fb_info->fb_dev.map_base, ++ fbh->base + HW_LCDIF_CUR_BUF); ++ /* always show one framebuffer only */ ++ writel((uint32_t)fb_info->fb_dev.map_base, ++ fbh->base + HW_LCDIF_NEXT_BUF); ++ ++ return 0; ++} ++ ++/** ++ * @param fb_info Framebuffer information ++ */ ++static void stmfb_enable_controller(struct fb_info *fb_info) ++{ ++ struct imxfb_host *fbh = fb_info_to_imxfb_host(fb_info); ++ uint32_t reg, last_reg; ++ unsigned loop, edges; ++ ++ /* ++ * Sometimes some data is still present in the FIFO. This leads into ++ * a correct but shifted picture. Clearing the FIFO helps ++ */ ++ writel(CTRL1_FIFO_CLEAR, fbh->base + HW_LCDIF_CTRL1 + 4); ++ ++ /* if it was disabled, re-enable the mode again */ ++ reg = readl(fbh->base + HW_LCDIF_CTRL); ++ reg |= CTRL_DOTCLK_MODE; ++ writel(reg, fbh->base + HW_LCDIF_CTRL); ++ ++ /* enable the SYNC signals first, then the DMA enginge */ ++ reg = readl(fbh->base + HW_LCDIF_VDCTRL4); ++ reg |= VDCTRL4_SYNC_SIGNALS_ON; ++ writel(reg, fbh->base + HW_LCDIF_VDCTRL4); ++ ++ /* ++ * Give the attached LC display or monitor a chance to sync into ++ * our signals. ++ * Wait for at least 2 VSYNCs = four VSYNC edges ++ */ ++ edges = 4; ++ ++ while (edges != 0) { ++ loop = 800; ++ last_reg = readl(fbh->base + HW_LCDIF_DEBUG0) & DEBUG_VSYNC; ++ do { ++ reg = readl(fbh->base + HW_LCDIF_DEBUG0) & DEBUG_VSYNC; ++ if (reg != last_reg); ++ break; ++ last_reg = reg; ++ loop--; ++ } while (loop != 0); ++ edges--; ++ } ++ ++ /* stop FIFO reset */ ++ writel(CTRL1_FIFO_CLEAR, fbh->base + HW_LCDIF_CTRL1 + 8); ++ /* start the engine right now */ ++ writel(CTRL_RUN, fbh->base + HW_LCDIF_CTRL + 4); ++} ++ ++/** ++ * @param fb_info Framebuffer information ++ */ ++static void stmfb_disable_controller(struct fb_info *fb_info) ++{ ++ struct imxfb_host *fbh = fb_info_to_imxfb_host(fb_info); ++ unsigned loop; ++ uint32_t reg; ++ ++ /* ++ * Even if we disable the controller here, it will still continue ++ * until its FIFOs are running out of data ++ */ ++ reg = readl(fbh->base + HW_LCDIF_CTRL); ++ reg &= ~CTRL_DOTCLK_MODE; ++ writel(reg, fbh->base + HW_LCDIF_CTRL); ++ ++ loop = 1000; ++ while (loop) { ++ reg = readl(fbh->base + HW_LCDIF_CTRL); ++ if (!(reg & CTRL_RUN)) ++ break; ++ loop--; ++ } ++ ++ reg = readl(fbh->base + HW_LCDIF_VDCTRL4); ++ reg &= ~VDCTRL4_SYNC_SIGNALS_ON; ++ writel(reg, fbh->base + HW_LCDIF_VDCTRL4); ++} ++ ++/** ++ * Print some information about the current hardware state ++ * @param hw_dev STM video device ++ */ ++static void stmfb_info(struct device_d *hw_dev) ++{ ++ uint32_t reg; ++ ++ printf(" STM video hardware:\n"); ++ printf(" Pixel clock: %u kHz\n", imx_get_lcdifclk()); ++ ++ reg = readl(hw_dev->map_base + HW_LCDIF_CTRL); ++ switch (GET_WORD_LENGTH(reg)) { ++ case 0: ++ printf(" 16 bpp mode with %s colour scheme\n", ++ reg & CTRL_DF16 ? "ARGB1555" : "RGB565"); ++ switch (GET_BYTE_PACKAGING(readl(hw_dev->map_base + ++ HW_LCDIF_CTRL1))) { ++ case 0xf: ++ printf(" One pixel per halfword\n"); ++ break; ++ case 0x3: ++ printf(" One pixel per word\n"); ++ break; ++ default: ++ printf("Unknown pixel packaging: %u\n", ++ GET_BYTE_PACKAGING(readl(hw_dev->map_base + ++ HW_LCDIF_CTRL1))); ++ } ++ break; ++ case 1: ++ case 2: ++ printf("Unsupported bpp mode yet!\n"); ++ break; ++ case 3: ++ printf(" 24 bpp mode with %s colour scheme\n", ++ reg & CTRL_DF24 ? "RGB666" : "RGB888"); ++ switch (GET_BYTE_PACKAGING(readl(hw_dev->map_base + ++ HW_LCDIF_CTRL1))) { ++ case 0x7: ++ printf(" One pixel per word (xRGB xRGB xRGB ...)\n"); ++ break; ++ case 0xf: ++ printf("Packed pixel format per word " ++ "(RGBR GBRG BRGB ...)\n"); ++ break; ++ default: ++ printf("Unknown pixel packaging: %u\n", ++ GET_BYTE_PACKAGING(readl(hw_dev->map_base + ++ HW_LCDIF_CTRL1))); ++ } ++ break; ++ } ++} ++ ++/* ++ * There is only one video hardware instance available. ++ * It makes no sense to dynamically allocate this data ++ */ ++static struct imxfb_host host_data = { ++ .fb_data.fb_mode = stmfb_initialize_mode, ++ .fb_data.fb_enable = stmfb_enable_controller, ++ .fb_data.fb_disable = stmfb_disable_controller, ++ .fb_data.bits_per_pixel = 16, ++}; ++ ++static int stmfb_probe(struct device_d *hw_dev) ++{ ++ struct imx_fb_videomode *pdata = hw_dev->platform_data; ++ struct device_d *fb_dev; ++ ++ if (pdata == NULL) { ++ dev_err(hw_dev, "No platform data. Giving up\n"); ++ return -ENODEV; ++ } ++ ++ /* add runtime hardware info */ ++ host_data.hw_dev = hw_dev; ++ host_data.pdata = pdata; ++ host_data.base = (void*)hw_dev->map_base; ++ ++ /* add runtime video info */ ++ host_data.fb_data.mode = pdata->mode_list; ++ host_data.fb_data.mode_cnt = pdata->mode_count; ++ ++ fb_dev = register_framebuffer(&host_data.fb_data); ++ if (fb_dev == NULL) { ++ dev_err(hw_dev, "Failed to register framebuffer\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static struct driver_d stmfb_driver = { ++ .name = "stmfb", ++ .probe = stmfb_probe, ++ .info = stmfb_info, ++}; ++ ++static int stmfb_init(void) ++{ ++ return register_driver(&stmfb_driver); ++} ++ ++device_initcall(stmfb_init); +-- +1.7.3.2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/2010.11_2_next.diff b/configs/platform-chumby/patches/barebox-2010.11.0/2010.11_2_next.diff new file mode 100644 index 0000000..fad5226 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/2010.11_2_next.diff @@ -0,0 +1,48796 @@ +diff --git a/.gitignore b/.gitignore +index 2c580c6..4a45113 100644 +--- a/.gitignore ++++ b/.gitignore +@@ -48,6 +48,9 @@ include/config + include/linux/compile.h + include/generated + ++# Generated files ++Doxyfile.version ++ + # stgit generated dirs + patches-* + +diff --git a/Documentation/barebox-main.dox b/Documentation/barebox-main.dox +index fb780e6..90fce8e 100644 +--- a/Documentation/barebox-main.dox ++++ b/Documentation/barebox-main.dox +@@ -1,166 +1,74 @@ +-/** @mainpage Universal Bootloader +- +-@section barebox_intro Introduction +- +-@a Barebox is a bootloader which follows the tradition of U-Boot. U-Boot +-offers an excellent choice as a bootloader for today's embedded systems, +-seen from a user's point of view. Nevertheless, there are quite some +-design flaws which turned out over the last years and we think that they +-cannot be solved in a production tree. So this tree tries to do several +-things right - without caring about losing support for old boards. +- +-@par General features include: +- +-- A posix based file API +- - inside @a barebox the usual open/close/read/write/lseek functions are used. +- This makes it familiar to everyone who has programmed under unix systems. +- +-- usual shell commands like ls/cd/mkdir/echo/cat,... +- +-- The environment is not a variable store anymore, but a file store. It has +- currently some limitations, of course. The environment is not a real +- read/write filesystem, it is more like a tar archive, or even more like +- an ar archive, because it cannot handle directories. The saveenv command +- saves the files under a certain directory (by default /env) in persistent +- storage (by default /dev/env0). There is a counterpart called loadenv, too. ++/** @mainpage Barebox ++ ++Barebox is a bootloader that initializes a hardware and boots Linux and ++maybe other operating systems or bare metal code on a variety of ++processors. It was initialy derived from U-Boot and captures up with ++several of it's ideas, so users being familiar with U-Boot should come ++into production quickly with Barebox. ++ ++However, as the Barebox developers are highly addicted to the Linux ++kernel, it's coding style and code quality, we try to stick as closely ++as possible to the methodologies and techniques developed in Linux. In ++addition we have a strong background in POSIX, so you'll find several ++good old Unix traditions realized in Barebox as well. ++ ++@par Highlights: ++ ++- <b>POSIX File API:</b><br> ++ @a Barebox uses the the well known open/close/read/write/lseek access ++ functions, together with a model of representing devices by files. This ++ makes the APIs familiar to everyone who has experience with Unix ++ systems. ++ ++- <b>Shell:</b><br> ++ We have the standard shell commands like ls/cd/mkdir/echo/cat,... ++ ++- <b>Environment Filesystem:</b><br> ++ In contrast to U-Boot, Barebox doesn't misuse the environment for ++ scripting. If you start the bootloader, it gives you a shell and ++ something that looks like a filesystem. In fact it isn't: it is a very ++ simple ar archive being extracted from flash into a ramdisk with 'loadenv' ++ and stored back with 'saveenv'. ++ ++- <b>Filesystem Support:</b><br> ++ When starting up, the environment is mounted to /, followed by a ++ device filesytem being mounted to /dev in order to make it possible to ++ access devices. Other filesystems can be mounted on demand. ++ ++- <b>Driver Model (borrowed from Linux):</b><br> ++ Barebox follows the Linux driver model: devices can be specified in a ++ hardware specific file, and drivers feel responsible for these devices ++ if they have the same name. ++ ++- <b>Clocksource:</b><br> ++ We use the clocksource API knwon from Linux. ++ ++- <b>Kconfig/Kbuild:</b><br> ++ This gives us parallel builds and removes the need for lots of ifdefs. ++ ++- <b>Sandbox:</b><br> ++ If you develop features for @a Barebox, you can use the 'sandbox' ++ target which compiles @a Barebox as a POSIX application in the Linux ++ userspace: it can be started like a normal command and even has ++ network access (tun/tap). Files from the local filesytem can be used ++ to simulate devices. ++ ++- <b>Device Parameters:</b><br> ++ There is a parameter model in @a Barebox: each device can specify it's ++ own parameters, which do exist for every instance. Parameters can be ++ changed on the command line with \<devid\>.\<param\>="...". For ++ example, if you want to access the IPv4 address for eth0, this is done ++ with 'eth0.ip=192.168.0.7' and 'echo $eth0.ip'. ++ ++- <b>Getopt:</b><br> ++ @a Barebox has a lightweight getopt() implementation. This makes it ++ unnecessary to use positional parameters, which can be hard to read. ++ ++- <b>Integrated Editor:</b><br> ++ Scripts can be edited with a small integrated fullscreen editor. ++ This editor has no features except the ones really needed: moving ++ the cursor around, typing characters, exiting and saving. + +-- Real filesystem support +- - The loader starts up with mounting a ramdisk on /. Then a devfs is mounted +- on /dev allowing the user (or shell commands) to access devices. Apart from +- these two filesystems there is currently one filesystem ported: cramfs. One +- can mount it with the usual mount command. +- +-- device/driver model +- - Devices are no longer described by defines in the config file. Instead +- there are devices which can be registered in the board .c file or +- dynamically allocated. Drivers will match upon the devices automatically. +- +-- clocksource support +- - Timekeeping has been simplified by the use of the Linux clocksource API. +- Only one function is needed for a new board, no [gs]et_timer[masked]() or +- reset_timer[masked]() functions. +- +-- Kconfig and Kernel build system +- - Only targets which are really needed get recompiled. Parallel builds are +- no problem anymore. This also removes the need for many many ifdefs in +- the code. +- +-- simulation target +- - @a barebox can be compiled to run under Linux. While this is rather useless +- in real world this is a great debugging and development aid. New features +- can be easily developed and tested on long train journeys and started +- under gdb. There is a console driver for linux which emulates a serial +- device and a tap based ethernet driver. Linux files can be mapped to +- devices under @a barebox to emulate storage devices. +- +-- device parameter support +- - Each device can have a unlimited number of parameters. They can be accessed +- on the command line with \<devid\>.\<param\>="...", for example +- 'eth0.ip=192.168.0.7' or 'echo $eth0.ip' +- +-- initcalls +- - hooks in the startup process can be achieved with *_initcall() directives +- in each file. +- +-- getopt +- - There is a small getopt implementation. Some commands got really +- complicated (both in code and in usage) due to the fact that @a U-Boot only +- allowed positional parameters. +- +-- editor +- - Scripts can be edited with a small editor. This editor has no features +- except the ones really needed: moving the cursor and typing characters. +- +-@par Building barebox +- +-@a Barebox uses the Linux kernel's build system. It consists of two parts: +-the makefile infrastructure (kbuild), plus a configuration system +-(kconfig). So building @a barebox is very similar to building the Linux +-kernel. +- +-For the examples below, we use the User Mode @a barebox implementation, which +-is a port of @a barebox to the Linux userspace. This makes it possible to +-test drive the code without having real hardware. So for this test +-scenario, @p ARCH=sandbox is the valid architecture selection. This currently +-only works on ia32 hosts and partly on x86-64. +- +-Selection of the architecture and the cross compiler can be done in two +-ways. You can either specify it using the environment variables @p ARCH +-and @p CROSS_COMPILE, or you can create the soft links cross_arch and +-cross_compile pointing to your architecture and compiler. For @p ARCH=sandbox +-we do not need a cross compiler so it is sufficient to specify the +-architecture: +- +-@code # ln -s arch/sandbox cross_arch @endcode +- +-In order to configure the various aspects of @a barebox, start the @a barebox +-configuration system: +- +-@code # make menuconfig @endcode +- +-This command starts a menu box and lets you select all the different +-options available for your architecture. Once the configuration was +-finished (you can simulate this by using the standard demo config file +-with 'make sandbox_defconfig'), there is a .config file in the toplevel +-directory of the sourcecode. +- +-Once @a barebox is configured, we can start the compilation +- +-@code # make @endcode +- +-If everything goes well, the result is a file called @p barebox: +- +-@code +- # ls -l barebox +- -rwxr-xr-x 1 rsc ptx 114073 Jun 26 22:34 barebox +-@endcode +- +-@a barebox usually needs an environment for storing the configuration data. +-You can generate an environment using the example environment contained +-in arch/sanbox/board/env: +- +-@code # ./scripts/bareboxenv -s -p 0x10000 arch/sanbox/board/env/ env.bin @endcode +- +-To get some files to play with you can generate a cramfs image: +- +-@code # mkcramfs somedir/ cramfs.bin @endcode +- +-The @a barebox image is a normal Linux executable, so it can be started +-just like every other program: +- +-@code +- # ./barebox -e env.bin -i cramfs.bin +- +- barebox 2.0.0-trunk (Jun 26 2007 - 22:34:38) +- +- loading environment from /dev/env0 +- barebox\> / +-@endcode +- +-Specifying -[ie] \<file\> tells @a barebox to map the file as a device +-under @p /dev. Files given with '-e' will appear as @p /dev/env[n]. Files +-given with '-i' will appear as @p /dev/fd[n]. +-If @a barebox finds a valid configuration sector on @p /dev/env0 it will +-load it to @p /env. It then executes @p /env/init if it exists. If you have +-loaded the example environment @a barebox will show you a menu asking for +-your settings. +- +-If you have started @a barebox as root you will find a new tap device on your +-host which you can configure using ifconfig. Once you configured the +-network settings accordingly you can do a ping or tftpboot. +- +-If you have mapped a cramfs image try mounting it with +- +-@code +- # mkdir /cram +- # mount /dev/fd0 cramfs /cram +-@endcode +- +-Memory can be examined as usual using @p md/mw commands. They both understand +-the -f \<file\> option to tell the commands that they should work on the +-specified files instead of @p /dev/mem which holds the complete address space. +-Note that if you call 'md /dev/fd0' (without -f) @a barebox will segfault on +-the host, because it will interpret @p /dev/fd0 as a number. + + @par Directory layout + +diff --git a/Documentation/boards.dox b/Documentation/boards.dox +index 3eb79b2..c04e06b 100644 +--- a/Documentation/boards.dox ++++ b/Documentation/boards.dox +@@ -8,18 +8,23 @@ PowerPC type: + + ARM type: + ++ + @li @subpage pcm037 + @li @subpage pcm038 + @li @subpage pcm043 + @li @subpage imx21ads + @li @subpage imx27ads + @li @subpage the3stack ++@li @subpage mx23_evk ++@li @subpage board_babage ++@li @subpage chumbyone + @li @subpage scb9328 + @li @subpage netx + @li @subpage dev_omap_arch + @li @subpage a9m2440 + @li @subpage a9m2410 + @li @subpage eukrea_cpuimx27 ++@li @subpage eukrea_cpuimx35 + @li @subpage edb9301 + @li @subpage edb9302 + @li @subpage edb9302a +@@ -28,6 +33,7 @@ ARM type: + @li @subpage edb9312 + @li @subpage edb9315 + @li @subpage edb9315a ++@li @subpage board_cupid + + Blackfin type: + +@@ -37,11 +43,6 @@ x86 type: + + @li @subpage generic_pc + +-coldfire/m68k type: +- +-@li @subpage phycore_mcf54xx +-@li @subpage kp_ukd_r1 +- + */ + + /* TODO +diff --git a/Documentation/building.dox b/Documentation/building.dox +new file mode 100644 +index 0000000..527ca45 +--- /dev/null ++++ b/Documentation/building.dox +@@ -0,0 +1,60 @@ ++/** @page building Building ++ ++<i>This section describes how to build the Barebox bootloader.</i> ++ ++@a Barebox uses Kconfig/Kbuild from the Linux kernel to build it's ++sources. It consists of two parts: the makefile infrastructure (kbuild) ++and a configuration system (kconfig). So building @a barebox is very ++similar to building the Linux kernel. ++ ++In the examples below we use the "sandbox" configuration, which is a ++port of @a Barebox to the Linux userspace. This makes it possible to ++test the code without having real hardware or even qemu. Note that the ++sandbox architecture does only work well on x86 and has some issues on ++x86_64. ++ ++\todo Find out about issues on x86_64. ++ ++Selecting the architecture and the corresponding cross compiler is done ++by setting the following environment variables: ++ ++- ARCH=\<architecture> ++- CROSS_COMPILE=\<compiler-prefix> ++ ++For @p ARCH=sandbox we do not need a cross compiler, so it is sufficient ++to specify the architecture: ++ ++@code ++# export ARCH=sandbox ++@endcode ++ ++In order to configure the various aspects of @a barebox, start the ++@a barebox configuration system: ++ ++@code ++# make menuconfig ++@endcode ++ ++This command starts a menu box and lets you select all the different ++options available for the selected architecture. Once the configuration ++is finished (you can simulate this by using the default config file with ++'make sandbox_defconfig'), there is a .config file in the toplevel ++directory of the sourcecode. ++ ++After @a barebox is configured, we can start the compilation: ++ ++@code ++# make ++@endcode ++ ++You can use '-j \<n\>' in order to do a parallel build if you have more ++than one cpus. ++ ++If everything goes well, the result is a file called @p barebox: ++ ++@code ++# ls -l barebox ++-rwxr-xr-x 1 rsc ptx 114073 Jun 26 22:34 barebox ++@endcode ++ ++*/ +diff --git a/Documentation/commands.dox b/Documentation/commands.dox +index a8850b1..5ef7829 100644 +--- a/Documentation/commands.dox ++++ b/Documentation/commands.dox +@@ -1,24 +1,111 @@ + /** +- * @page command_reference Supported Shell Commands ++ * @page command_reference Shell Commands + ++<i>This section describes the commands which are available on the @a ++Barebox shell. </i> ++ ++@a Barebox, as a bootloader, usually shall start the Linux kernel right ++away. However, there are several use cases around which make it ++necessary to have some (customizable) logic and interactive scripting ++possibilities. In order to achieve this, @a Barebox offers several ++commands on it's integrated commandline shell. ++ ++The following alphabetically sorted list documents all commands ++available in @a Barebox: ++ ++\todo Sort this by functionality? ++ ++@li @subpage _name + @li @subpage addpart_command ++@li @subpage alternate ++@li @subpage bmp_command ++@li @subpage bootm_command ++@li @subpage bootu ++@li @subpage bootz + @li @subpage cat_command + @li @subpage cd_command ++@li @subpage clear_command ++@li @subpage clko + @li @subpage cp_command ++@li @subpage cpufreq ++@li @subpage cpuinfo ++@li @subpage crc_command ++@li @subpage crc32 + @li @subpage delpart_command + @li @subpage devinfo_command ++@li @subpage dfu_command ++@li @subpage dhcp ++@li @subpage dump_clocks ++@li @subpage echo_command + @li @subpage edit_command + @li @subpage erase_command ++@li @subpage ethact ++@li @subpage exec ++@li @subpage exit + @li @subpage export_command +-@li @subpage tftp_command ++@li @subpage false ++@li @subpage getopt ++@li @subpage gpio_get_value_command ++@li @subpage gpio_set_value_command ++@li @subpage gpio_direction_input_command ++@li @subpage gpio_direction_output_command ++@li @subpage go ++@li @subpage help ++@li @subpage host ++@li @subpage i2c_probe ++@li @subpage i2c_read ++@li @subpage i2c_write ++@li @subpage icache ++@li @subpage iminfo ++@li @subpage insmod ++@li @subpage linux16_command + @li @subpage loadenv_command ++@li @subpage loadb ++@li @subpage loady ++@li @subpage loadxc ++@li @subpage login ++@li @subpage ls_command ++@li @subpage lsmod ++@li @subpage md ++@li @subpage memcmp ++@li @subpage meminfo ++@li @subpage memset ++@li @subpage menu ++@li @subpage mkdir + @li @subpage mount_command ++@li @subpage mtest ++@li @subpage mw ++@li @subpage mycdev ++@li @subpage nand ++@li @subpage nand_boot_test ++@li @subpage nfs ++@li @subpage passwd ++@li @subpage ping + @li @subpage printenv_command + @li @subpage protect_command +-@li @subpage rarp_command ++@li @subpage pwd ++@li @subpage readline ++@li @subpage reset ++@li @subpage rarpboot ++@li @subpage reginfo ++@li @subpage rm ++@li @subpage rmdir + @li @subpage saveenv_command + @li @subpage setenv_command +-@li @subpage sh_command ++@li @subpage sh ++@li @subpage sleep ++@li @subpage source ++@li @subpage test ++@li @subpage timeout ++@li @subpage true ++@li @subpage tftp_command ++@li @subpage ubiattach ++@li @subpage ubimkvol ++@li @subpage ubirmvol ++@li @subpage umount ++@li @subpage unlzo + @li @subpage unprotect_command +-@li @subpage linux16_command ++@li @subpage usb ++@li @subpage version ++ + */ +diff --git a/Documentation/developers_manual.dox b/Documentation/developers_manual.dox +index 620905e..2f7d360 100644 +--- a/Documentation/developers_manual.dox ++++ b/Documentation/developers_manual.dox +@@ -20,6 +20,5 @@ This part of the documentation is intended for developers of @a barebox. + @li @subpage barebox_simul + @li @subpage io_access_functions + @li @subpage mcfv4e_MCDlib +-@li @subpage x86_runtime + + */ +diff --git a/Documentation/first_steps.dox b/Documentation/first_steps.dox +new file mode 100644 +index 0000000..edc612f +--- /dev/null ++++ b/Documentation/first_steps.dox +@@ -0,0 +1,61 @@ ++/** @page first_steps First Steps ++ ++<i>This section demonstrates the first steps with the 'sandbox' ++platform. </i> ++ ++@a barebox usually needs an environment for storing it's configuration. ++You can generate an environment using the example-environment contained ++in arch/sanbox/board/env: ++ ++@code ++# ./scripts/bareboxenv -s -p 0x10000 arch/sanbox/board/env/ env.bin ++@endcode ++ ++To get some files to play with you can generate a cramfs image: ++ ++@code ++# mkcramfs somedir/ cramfs.bin ++@endcode ++ ++The @a barebox image is a normal Linux executable, so it can be started ++just like every other program: ++ ++@code ++# ./barebox -e env.bin -i cramfs.bin ++ ++barebox 2010.10.0 (Oct 29 2010 - 13:47:17) ++ ++loading environment from /dev/env0 ++barebox\> / ++@endcode ++ ++Specifying -[ie] \<file\> tells @a barebox to map the file as a device ++under @p /dev. Files given with '-e' will appear as @p /dev/env[n]. Files ++given with '-i' will appear as @p /dev/fd[n]. ++ ++If @a barebox finds a valid configuration sector on @p /dev/env0, it ++will be loaded into @p /env and executes @p /env/init if existing. ++The default environment from the example above will show up a menu ++asking for the relevant settings. ++ ++If you have started @a barebox as root you will find a new tap device on ++your host which you can configure using ifconfig. Once configured with ++valid network addresses, barebox can be used to ping the host machine or ++to fetch files with tftp. ++ ++\todo Add more about tun/tap configuration ++ ++If you have mapped a cramfs image, try mounting it with ++ ++@code ++# mkdir /cram ++# mount /dev/fd0 cramfs /cram ++@endcode ++ ++Memory can be examined using @p md/mw commands. They both understand the ++-f \<file\> option to tell the commands that they should work on the ++specified files instead of @p /dev/mem (which holds the complete address ++space). Note that if you call 'md /dev/fd0' (without -f), @a barebox will ++segfault on the host, because it will interpret @p /dev/fd0 as a number. ++ ++*/ +diff --git a/Documentation/users_manual.dox b/Documentation/users_manual.dox +index cd2b99c..ea47b18 100644 +--- a/Documentation/users_manual.dox ++++ b/Documentation/users_manual.dox +@@ -1,15 +1,17 @@ + /** @page users_manual User's Manual + +-Who should read this part? ++This manual provides help for working with @a Barebox from the user's ++point of view. So if you want to use @a Barebox for booting your target, ++you find a lot of nice tricks on these pages to make your life easier. + +-Mostly everyone. The user needs it to find help for his daily work to manage +-his targets. The developer to find out all the new features that make his +-work easier. ++@li @subpage building ++@li @subpage first_steps ++@li @subpage command_reference ++@li @subpage gpio_for_users + ++\todo Rework the following sections + @li @subpage shell_notes + @li @subpage readline_parser +-@li @subpage command_reference +-@li @subpage partitions + @li @subpage x86_bootloader + @li @subpage net_netconsole + +diff --git a/Doxyfile b/Doxyfile +index 40bcb2f..89151e3 100644 +--- a/Doxyfile ++++ b/Doxyfile +@@ -31,7 +31,7 @@ PROJECT_NAME = barebox + # This could be handy for archiving the generated documentation or + # if some version control system is used. + +-PROJECT_NUMBER = 1 ++@INCLUDE = Doxyfile.version + + # The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) + # base path where the generated documentation will be put. +@@ -424,7 +424,7 @@ FILE_VERSION_FILTER = + # The QUIET tag can be used to turn on/off the messages that are generated + # by doxygen. Possible values are YES and NO. If left blank NO is used. + +-QUIET = NO ++QUIET = YES + + # The WARNINGS tag can be used to turn on/off the warning messages that are + # generated by doxygen. Possible values are YES and NO. If left blank +@@ -483,7 +483,6 @@ INPUT = Documentation \ + drivers \ + commands \ + common \ +- board \ + lib \ + scripts/setupmbr \ + net +@@ -504,6 +503,7 @@ INPUT_ENCODING = UTF-8 + + FILE_PATTERNS = *.c \ + *.h \ ++ *.S \ + *.dox + + # The RECURSIVE tag can be used to turn specify whether or not subdirectories +@@ -516,7 +516,9 @@ RECURSIVE = YES + # excluded from the INPUT source files. This way you can easily exclude a + # subdirectory from a directory tree whose root is specified with the INPUT tag. + +-EXCLUDE = ++EXCLUDE = drivers/mtd/ubi \ ++ include/mtd \ ++ include/linux/mtd + + # The EXCLUDE_SYMLINKS tag can be used select whether or not files or + # directories that are symbolic links (a Unix filesystem feature) are excluded +@@ -543,7 +545,7 @@ EXCLUDE_SYMBOLS = + # directories that contain example code fragments that are included (see + # the \include command). + +-EXAMPLE_PATH = Documentation/examples/ ++EXAMPLE_PATH = + + # If the value of the EXAMPLE_PATH tag contains directories, you can use the + # EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +@@ -563,7 +565,7 @@ EXAMPLE_RECURSIVE = NO + # directories that contain image that are included in the documentation (see + # the \image command). + +-IMAGE_PATH = Documentation/images/ ++IMAGE_PATH = + + # The INPUT_FILTER tag can be used to specify a program that doxygen should + # invoke to filter for each input file. Doxygen will invoke the filter program +@@ -573,7 +575,7 @@ IMAGE_PATH = Documentation/images/ + # to standard output. If FILTER_PATTERNS is specified, this tag will be + # ignored. + +-INPUT_FILTER = ++INPUT_FILTER = "awk -f scripts/doxy_filter.awk" + + # The FILTER_PATTERNS tag can be used to specify filters on a per file pattern + # basis. Doxygen will compare the file name with each pattern and apply the +@@ -1065,7 +1067,10 @@ INCLUDE_FILE_PATTERNS = + # undefined via #undef or recursively expanded use the := operator + # instead of the = operator. + +-PREDEFINED = DOXYGEN_SHOULD_SKIP_THIS ++PREDEFINED = \ ++ DOXYGEN_SHOULD_SKIP_THIS \ ++ CONFIG_CMD_DEVINFO \ ++ CONFIG_NET_TFTP_PUSH + + # If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then + # this tag can be used to specify a list of macro names that should be expanded. +@@ -1209,7 +1214,7 @@ INCLUDED_BY_GRAPH = NO + # So in most cases it will be better to enable call graphs for selected + # functions only using the \callgraph command. + +-CALL_GRAPH = YES ++CALL_GRAPH = NO + + # If the CALLER_GRAPH, SOURCE_BROWSER and HAVE_DOT tags are set to YES then doxygen will + # generate a caller dependency graph for every global function or class method. +@@ -1217,19 +1222,19 @@ CALL_GRAPH = YES + # So in most cases it will be better to enable caller graphs for selected + # functions only using the \callergraph command. + +-CALLER_GRAPH = YES ++CALLER_GRAPH = NO + + # If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen + # will graphical hierarchy of all classes instead of a textual one. + +-GRAPHICAL_HIERARCHY = YES ++GRAPHICAL_HIERARCHY = NO + + # If the DIRECTORY_GRAPH, SHOW_DIRECTORIES and HAVE_DOT tags are set to YES + # then doxygen will show the dependencies a directory has on other directories + # in a graphical way. The dependency relations are determined by the #include + # relations between the files in the directories. + +-DIRECTORY_GRAPH = YES ++DIRECTORY_GRAPH = NO + + # The DOT_IMAGE_FORMAT tag can be used to set the image format of the images + # generated by dot. Possible values are png, jpg, or gif +diff --git a/Makefile b/Makefile +index ae32b50..4e1c011 100644 +--- a/Makefile ++++ b/Makefile +@@ -762,6 +762,9 @@ include/config/kernel.release: include/config/auto.conf FORCE + $(Q)rm -f $@ + $(Q)echo $(kernelrelease) > $@ + ++Doxyfile.version: include/config/auto.conf FORCE ++ $(Q)rm -f $@ ++ $(Q)echo "PROJECT_NUMBER = $(KERNELRELEASE)" > $@ + + # Things we need to do before we recursively start building the kernel + # or the modules are listed in "prepare". +@@ -973,7 +976,7 @@ endif # CONFIG_MODULES + CLEAN_DIRS += $(MODVERDIR) + CLEAN_FILES += barebox System.map include/generated/barebox_default_env.h \ + .tmp_version .tmp_barebox* barebox.bin barebox.S \ +- .tmp_kallsyms* barebox_default_env barebox.ldr ++ .tmp_kallsyms* barebox_default_env barebox.ldr Doxyfile.version + + # Directories & files removed with 'make mrproper' + MRPROPER_DIRS += include/config include2 usr/include +@@ -1098,7 +1101,7 @@ help: + + docs : htmldocs + +-htmldocs: ++htmldocs: Doxyfile.version + @echo 'Running doxygen with local Doxyfile' + $(Q)doxygen Doxyfile + +diff --git a/arch/architecture.dox b/arch/architecture.dox +index ea00dcd..67e2c38 100644 +--- a/arch/architecture.dox ++++ b/arch/architecture.dox +@@ -87,7 +87,6 @@ TODO + @li @subpage dev_arm_mach + @li @subpage dev_bf_mach + @li @subpage dev_ppc_mach +-@li @subpage dev_m68k_mach + @li @subpage dev_x86_mach + + */ +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index fa37036..8cb86cb 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -39,6 +39,10 @@ config ARCH_IMX + bool "Freescale iMX-based" + select GENERIC_GPIO + ++config ARCH_STM ++ bool "SigmaTel/FSL iMX-based" ++ select GENERIC_GPIO ++ + config ARCH_NETX + bool "Hilscher NetX based" + select CPU_ARM926T +@@ -55,6 +59,7 @@ config ARCH_OMAP + config ARCH_S3C24xx + bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443" + select CPU_ARM920T ++ select GENERIC_GPIO + + endchoice + +@@ -62,6 +67,7 @@ source arch/arm/cpu/Kconfig + source arch/arm/mach-at91/Kconfig + source arch/arm/mach-ep93xx/Kconfig + source arch/arm/mach-imx/Kconfig ++source arch/arm/mach-stm/Kconfig + source arch/arm/mach-netx/Kconfig + source arch/arm/mach-nomadik/Kconfig + source arch/arm/mach-omap/Kconfig +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index 77b6cf4..9729c23 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -41,6 +41,7 @@ CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y) + machine-$(CONFIG_ARCH_AT91) := at91 + machine-$(CONFIG_ARCH_EP93XX) := ep93xx + machine-$(CONFIG_ARCH_IMX) := imx ++machine-$(CONFIG_ARCH_STM) := stm + machine-$(CONFIG_ARCH_NOMADIK) := nomadik + machine-$(CONFIG_ARCH_NETX) := netx + machine-$(CONFIG_ARCH_OMAP) := omap +@@ -51,8 +52,11 @@ machine-$(CONFIG_ARCH_S3C24xx) := s3c24xx + board-$(CONFIG_MACH_A9M2410) := a9m2410 + board-$(CONFIG_MACH_A9M2440) := a9m2440 + board-$(CONFIG_MACH_AT91SAM9260EK) := at91sam9260ek ++board-$(CONFIG_MACH_AT91SAM9261EK) := at91sam9261ek + board-$(CONFIG_MACH_AT91SAM9263EK) := at91sam9263ek ++board-$(CONFIG_MACH_AT91SAM9G10EK) := at91sam9261ek + board-$(CONFIG_MACH_AT91SAM9G20EK) := at91sam9260ek ++board-$(CONFIG_MACH_AT91SAM9M10G45EK) := at91sam9m10g45ek + board-$(CONFIG_MACH_EDB9301) := edb93xx + board-$(CONFIG_MACH_EDB9302) := edb93xx + board-$(CONFIG_MACH_EDB9302A) := edb93xx +@@ -77,9 +81,16 @@ board-$(CONFIG_MACH_PCA100) := phycard-i.MX27 + board-$(CONFIG_MACH_PCM037) := pcm037 + board-$(CONFIG_MACH_PCM038) := pcm038 + board-$(CONFIG_MACH_PCM043) := pcm043 ++board-$(CONFIG_MACH_PM9261) := pm9261 + board-$(CONFIG_MACH_PM9263) := pm9263 ++board-$(CONFIG_MACH_PM9G45) := pm9g45 + board-$(CONFIG_MACH_SCB9328) := scb9328 + board-$(CONFIG_MACH_NESO) := guf-neso ++board-$(CONFIG_MACH_MX23EVK) := freescale-mx23-evk ++board-$(CONFIG_MACH_CHUMBY) := chumby_falconwing ++board-$(CONFIG_MACH_FREESCALE_MX51_PDK) := freescale-mx51-pdk ++board-$(CONFIG_MACH_GUF_CUPID) := guf-cupid ++board-$(CONFIG_MACH_MINI2440) := mini2440 + + machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) + +diff --git a/arch/arm/boards/at91sam9261ek/Makefile b/arch/arm/boards/at91sam9261ek/Makefile +new file mode 100644 +index 0000000..eb072c0 +--- /dev/null ++++ b/arch/arm/boards/at91sam9261ek/Makefile +@@ -0,0 +1 @@ ++obj-y += init.o +diff --git a/arch/arm/boards/at91sam9261ek/config.h b/arch/arm/boards/at91sam9261ek/config.h +new file mode 100644 +index 0000000..006820c +--- /dev/null ++++ b/arch/arm/boards/at91sam9261ek/config.h +@@ -0,0 +1,6 @@ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ ++ ++#endif /* __CONFIG_H */ +diff --git a/arch/arm/boards/at91sam9261ek/env/config b/arch/arm/boards/at91sam9261ek/env/config +new file mode 100644 +index 0000000..3b92233 +--- /dev/null ++++ b/arch/arm/boards/at91sam9261ek/env/config +@@ -0,0 +1,41 @@ ++#!/bin/sh ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration ++ip=dhcp ++ ++# or set your networking parameters here ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'net' or 'nand' ++kernel_loc=net ++# can be either 'net', 'nand' or 'initrd' ++rootfs_loc=net ++ ++# can be either 'jffs2' or 'ubifs' ++rootfs_type=ubifs ++rootfsimage=root.$rootfs_type ++ ++# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo ++#kernelimage_type=zimage ++#kernelimage=zImage ++kernelimage_type=uimage ++kernelimage=uImage ++#kernelimage_type=raw ++#kernelimage=Image ++#kernelimage_type=raw_lzo ++#kernelimage=Image.lzo ++ ++nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" ++rootfs_mtdblock_nand=3 ++ ++autoboot_timeout=3 ++ ++bootargs="console=ttyS0,115200" ++ ++# set a fancy prompt (if support is compiled in) ++PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " ++ +diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c +new file mode 100644 +index 0000000..576a022 +--- /dev/null ++++ b/arch/arm/boards/at91sam9261ek/init.c +@@ -0,0 +1,174 @@ ++/* ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <net.h> ++#include <init.h> ++#include <environment.h> ++#include <asm/armlinux.h> ++#include <generated/mach-types.h> ++#include <partition.h> ++#include <fs.h> ++#include <fcntl.h> ++#include <asm/io.h> ++#include <asm/hardware.h> ++#include <nand.h> ++#include <linux/mtd/nand.h> ++#include <mach/at91_pmc.h> ++#include <mach/board.h> ++#include <mach/gpio.h> ++#include <mach/io.h> ++#include <mach/at91sam9_smc.h> ++#include <mach/sam9_smc.h> ++#include <dm9000.h> ++ ++static struct atmel_nand_data nand_pdata = { ++ .ale = 22, ++ .cle = 21, ++/* .det_pin = ... not connected */ ++ .rdy_pin = AT91_PIN_PC15, ++ .enable_pin = AT91_PIN_PC14, ++#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) ++ .bus_width_16 = 1, ++#else ++ .bus_width_16 = 0, ++#endif ++}; ++ ++static struct sam9_smc_config ek_nand_smc_config = { ++ .ncs_read_setup = 0, ++ .nrd_setup = 1, ++ .ncs_write_setup = 0, ++ .nwe_setup = 1, ++ ++ .ncs_read_pulse = 3, ++ .nrd_pulse = 3, ++ .ncs_write_pulse = 3, ++ .nwe_pulse = 3, ++ ++ .read_cycle = 5, ++ .write_cycle = 5, ++ ++ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, ++ .tdf_cycles = 2, ++}; ++ ++static void ek_add_device_nand(void) ++{ ++ /* setup bus-width (8 or 16) */ ++ if (nand_pdata.bus_width_16) ++ ek_nand_smc_config.mode |= AT91_SMC_DBW_16; ++ else ++ ek_nand_smc_config.mode |= AT91_SMC_DBW_8; ++ ++ /* configure chip-select 3 (NAND) */ ++ sam9_smc_configure(3, &ek_nand_smc_config); ++ ++ at91_add_device_nand(&nand_pdata); ++} ++ ++/* ++ * DM9000 ethernet device ++ */ ++#if defined(CONFIG_DRIVER_NET_DM9000) ++static struct dm9000_platform_data dm9000_data = { ++ .iobase = AT91_CHIPSELECT_2, ++ .iodata = AT91_CHIPSELECT_2 + 4, ++ .buswidth = DM9000_WIDTH_16, ++ .srom = 0, ++}; ++ ++static struct device_d dm9000_dev = { ++ .id = 0, ++ .name = "dm9000", ++ .map_base = AT91_CHIPSELECT_2, ++ .size = 8, ++ .platform_data = &dm9000_data, ++}; ++ ++/* ++ * SMC timings for the DM9000. ++ * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings. ++ */ ++static struct sam9_smc_config __initdata dm9000_smc_config = { ++ .ncs_read_setup = 0, ++ .nrd_setup = 2, ++ .ncs_write_setup = 0, ++ .nwe_setup = 2, ++ ++ .ncs_read_pulse = 8, ++ .nrd_pulse = 4, ++ .ncs_write_pulse = 8, ++ .nwe_pulse = 4, ++ ++ .read_cycle = 16, ++ .write_cycle = 16, ++ ++ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16, ++ .tdf_cycles = 1, ++}; ++ ++static void __init ek_add_device_dm9000(void) ++{ ++ /* Configure chip-select 2 (DM9000) */ ++ sam9_smc_configure(2, &dm9000_smc_config); ++ ++ /* Configure Reset signal as output */ ++ at91_set_gpio_output(AT91_PIN_PC10, 0); ++ ++ /* Configure Interrupt pin as input, no pull-up */ ++ at91_set_gpio_input(AT91_PIN_PC11, 0); ++ ++ register_device(&dm9000_dev); ++} ++#else ++static void __init ek_add_device_dm9000(void) {} ++#endif /* CONFIG_DRIVER_NET_DM9000 */ ++ ++static int at91sam9261ek_devices_init(void) ++{ ++ ++ at91_add_device_sdram(64 * 1024 * 1024); ++ ek_add_device_nand(); ++ ek_add_device_dm9000(); ++ ++ devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw"); ++ dev_add_bb_dev("self_raw", "self0"); ++ devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw"); ++ dev_add_bb_dev("env_raw", "env0"); ++ ++ armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); ++ if (machine_is_at91sam9g10ek()) ++ armlinux_set_architecture(MACH_TYPE_AT91SAM9G10EK); ++ else ++ armlinux_set_architecture(MACH_TYPE_AT91SAM9261EK); ++ ++ return 0; ++} ++ ++device_initcall(at91sam9261ek_devices_init); ++ ++static int at91sam9261ek_console_init(void) ++{ ++ at91_register_uart(0, 0); ++ return 0; ++} ++ ++console_initcall(at91sam9261ek_console_init); +diff --git a/arch/arm/boards/at91sam9m10g45ek/Makefile b/arch/arm/boards/at91sam9m10g45ek/Makefile +new file mode 100644 +index 0000000..eb072c0 +--- /dev/null ++++ b/arch/arm/boards/at91sam9m10g45ek/Makefile +@@ -0,0 +1 @@ ++obj-y += init.o +diff --git a/arch/arm/boards/at91sam9m10g45ek/config.h b/arch/arm/boards/at91sam9m10g45ek/config.h +new file mode 100644 +index 0000000..ac3114d +--- /dev/null ++++ b/arch/arm/boards/at91sam9m10g45ek/config.h +@@ -0,0 +1,6 @@ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ ++ ++#endif /* __CONFIG_H */ +diff --git a/arch/arm/boards/at91sam9m10g45ek/env/config b/arch/arm/boards/at91sam9m10g45ek/env/config +new file mode 100644 +index 0000000..3b92233 +--- /dev/null ++++ b/arch/arm/boards/at91sam9m10g45ek/env/config +@@ -0,0 +1,41 @@ ++#!/bin/sh ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration ++ip=dhcp ++ ++# or set your networking parameters here ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'net' or 'nand' ++kernel_loc=net ++# can be either 'net', 'nand' or 'initrd' ++rootfs_loc=net ++ ++# can be either 'jffs2' or 'ubifs' ++rootfs_type=ubifs ++rootfsimage=root.$rootfs_type ++ ++# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo ++#kernelimage_type=zimage ++#kernelimage=zImage ++kernelimage_type=uimage ++kernelimage=uImage ++#kernelimage_type=raw ++#kernelimage=Image ++#kernelimage_type=raw_lzo ++#kernelimage=Image.lzo ++ ++nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" ++rootfs_mtdblock_nand=3 ++ ++autoboot_timeout=3 ++ ++bootargs="console=ttyS0,115200" ++ ++# set a fancy prompt (if support is compiled in) ++PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " ++ +diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c +new file mode 100644 +index 0000000..bb8b7ba +--- /dev/null ++++ b/arch/arm/boards/at91sam9m10g45ek/init.c +@@ -0,0 +1,116 @@ ++/* ++ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> ++ * ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <net.h> ++#include <init.h> ++#include <environment.h> ++#include <asm/armlinux.h> ++#include <generated/mach-types.h> ++#include <partition.h> ++#include <fs.h> ++#include <fcntl.h> ++#include <asm/io.h> ++#include <asm/hardware.h> ++#include <nand.h> ++#include <linux/mtd/nand.h> ++#include <mach/at91_pmc.h> ++#include <mach/board.h> ++#include <mach/gpio.h> ++#include <mach/io.h> ++#include <mach/at91sam9_smc.h> ++#include <mach/sam9_smc.h> ++ ++static struct atmel_nand_data nand_pdata = { ++ .ale = 21, ++ .cle = 22, ++/* .det_pin = ... not connected */ ++ .rdy_pin = AT91_PIN_PC8, ++ .enable_pin = AT91_PIN_PC14, ++#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) ++ .bus_width_16 = 1, ++#else ++ .bus_width_16 = 0, ++#endif ++}; ++ ++static struct sam9_smc_config ek_nand_smc_config = { ++ .ncs_read_setup = 0, ++ .nrd_setup = 2, ++ .ncs_write_setup = 0, ++ .nwe_setup = 2, ++ ++ .ncs_read_pulse = 4, ++ .nrd_pulse = 4, ++ .ncs_write_pulse = 4, ++ .nwe_pulse = 4, ++ ++ .read_cycle = 7, ++ .write_cycle = 7, ++ ++ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, ++ .tdf_cycles = 3, ++}; ++ ++static void ek_add_device_nand(void) ++{ ++ /* setup bus-width (8 or 16) */ ++ if (nand_pdata.bus_width_16) ++ ek_nand_smc_config.mode |= AT91_SMC_DBW_16; ++ else ++ ek_nand_smc_config.mode |= AT91_SMC_DBW_8; ++ ++ /* configure chip-select 3 (NAND) */ ++ sam9_smc_configure(3, &ek_nand_smc_config); ++ ++ at91_add_device_nand(&nand_pdata); ++} ++ ++static struct at91_ether_platform_data macb_pdata = { ++ .flags = AT91SAM_ETHER_RMII, ++ .phy_addr = 0, ++}; ++ ++static int at91sam9m10g45ek_devices_init(void) ++{ ++ at91_add_device_sdram(128 * 1024 * 1024); ++ ek_add_device_nand(); ++ at91_add_device_eth(&macb_pdata); ++ ++ devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw"); ++ dev_add_bb_dev("self_raw", "self0"); ++ devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw"); ++ dev_add_bb_dev("env_raw", "env0"); ++ ++ armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100)); ++ armlinux_set_architecture(MACH_TYPE_AT91SAM9M10G45EK); ++ ++ return 0; ++} ++device_initcall(at91sam9m10g45ek_devices_init); ++ ++static int at91sam9m10g45ek_console_init(void) ++{ ++ at91_register_uart(0, 0); ++ return 0; ++} ++console_initcall(at91sam9m10g45ek_console_init); +diff --git a/arch/arm/boards/chumby_falconwing/Makefile b/arch/arm/boards/chumby_falconwing/Makefile +new file mode 100644 +index 0000000..0bc79d9 +--- /dev/null ++++ b/arch/arm/boards/chumby_falconwing/Makefile +@@ -0,0 +1 @@ ++obj-y = falconwing.o +diff --git a/arch/arm/boards/chumby_falconwing/config.h b/arch/arm/boards/chumby_falconwing/config.h +new file mode 100644 +index 0000000..87d9e2f +--- /dev/null ++++ b/arch/arm/boards/chumby_falconwing/config.h +@@ -0,0 +1,21 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef _CONFIG_H_ ++# define _CONFIG_H_ ++ ++#endif /* _CONFIG_H_ */ +diff --git a/arch/arm/boards/chumby_falconwing/env/bin/boot b/arch/arm/boards/chumby_falconwing/env/bin/boot +new file mode 100644 +index 0000000..981a387 +--- /dev/null ++++ b/arch/arm/boards/chumby_falconwing/env/bin/boot +@@ -0,0 +1,38 @@ ++#!/bin/sh ++ ++. /env/config ++ ++if [ x$1 = xdisk ]; then ++ rootfs_loc=disk ++ kernel_loc=disk ++elif [ x$1 = xnet ]; then ++ rootfs_loc=net ++ kernel_loc=net ++fi ++ ++if [ x$ip = xdhcp ]; then ++ bootargs="$bootargs ip=dhcp" ++elif [ x$ip = xnone ]; then ++ bootargs="$bootargs ip=none" ++else ++ bootargs="$bootargs ip=$eth0.ipaddr::$eth0.gateway:$eth0.netmask:::" ++fi ++ ++if [ x$rootfs_loc = xdisk ]; then ++ bootargs="$bootargs noinitrd rootfstype=$rootfs_type root=/dev/$rootfs_part" ++elif [ x$rootfs_loc = xnet ]; then ++ bootargs="$bootargs root=/dev/nfs nfsroot=$nfsroot,v3,tcp noinitrd" ++elif [ x$rootfs_loc = xinitrd ]; then ++ bootargs="$bootargs root=/dev/ram0 rdinit=/sbin/init" ++fi ++ ++if [ x$kernelimage_type = xuimage ]; then ++ bootm /dev/$kernel_part ++elif [ x$kernelimage_type = xzimage ]; then ++ bootz /dev/$kernel_part ++else ++ echo "Booting failed. Correct setup of 'kernelimage_type'?" ++ exit ++fi ++ ++echo "Booting failed. Correct setup of 'kernel_part'?" +diff --git a/arch/arm/boards/chumby_falconwing/env/bin/init b/arch/arm/boards/chumby_falconwing/env/bin/init +new file mode 100644 +index 0000000..3ed68f7 +--- /dev/null ++++ b/arch/arm/boards/chumby_falconwing/env/bin/init +@@ -0,0 +1,15 @@ ++#!/bin/sh ++ ++PATH=/env/bin ++export PATH ++ ++. /env/config ++ ++echo ++echo -n "Hit any key to stop autoboot: " ++timeout -a $autoboot_timeout ++if [ $? != 0 ]; then ++ exit ++fi ++ ++boot +diff --git a/arch/arm/boards/chumby_falconwing/env/config b/arch/arm/boards/chumby_falconwing/env/config +new file mode 100644 +index 0000000..1e61dce +--- /dev/null ++++ b/arch/arm/boards/chumby_falconwing/env/config +@@ -0,0 +1,36 @@ ++#!/bin/sh ++ ++machine=falconwing ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration ++ip=none ++ ++# or set your networking parameters here (if a USB network adapter is attached) ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'net' or 'disk' ++kernel_loc=disk ++# can be either 'net', or 'disk' or 'initrd' ++rootfs_loc=disk ++ ++# can be any regular filesystem like ext2, ext3, reiserfs in case of 'rootfs_loc=disk' ++rootfs_type=ext2 ++# Where is the rootfs in case of 'rootfs_loc=disk' ++rootfs_part=mmcblk0p4 ++ ++# Where is the rootfs in case of 'rootfs_loc=net' ++nfsroot=FIXME ++ ++# The image type of the kernel. Can be uimage, zimage ++kernelimage_type=uimage ++# Where to get the kernel image in case of 'kernel_loc=disk' ++kernel_part=disk0.2 ++ ++# base kernel parameter ++bootargs="console=ttyAM0,115200 debug ro lcd_panel=lms350 ssp1=mmc line=1 sysrq_always_enabled rotary=1" ++ ++autoboot_timeout=2 +diff --git a/arch/arm/boards/chumby_falconwing/falconwing.c b/arch/arm/boards/chumby_falconwing/falconwing.c +new file mode 100644 +index 0000000..952a384 +--- /dev/null ++++ b/arch/arm/boards/chumby_falconwing/falconwing.c +@@ -0,0 +1,350 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include <common.h> ++#include <init.h> ++#include <gpio.h> ++#include <environment.h> ++#include <errno.h> ++#include <mci.h> ++#include <asm/armlinux.h> ++#include <asm/io.h> ++#include <generated/mach-types.h> ++#include <mach/imx-regs.h> ++#include <mach/clock.h> ++#include <mach/mci.h> ++ ++static struct memory_platform_data ram_pdata = { ++ .name = "ram0", ++ .flags = DEVFS_RDWR, ++}; ++ ++static struct device_d sdram_dev = { ++ .name = "mem", ++ .map_base = IMX_MEMORY_BASE, ++ .size = 64 * 1024 * 1024, ++ .platform_data = &ram_pdata, ++}; ++ ++static struct stm_mci_platform_data mci_pdata = { ++ .caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz, ++ .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, /* fixed to 3.3 V */ ++}; ++ ++static struct device_d mci_dev = { ++ .name = "stm_mci", ++ .map_base = IMX_SSP1_BASE, ++ .platform_data = &mci_pdata, ++}; ++ ++static const uint32_t pad_setup[] = { ++ /* may be not required as already done by the bootlet code */ ++#if 0 ++ /* SDRAM data signals */ ++ EMI_D15 | STRENGTH(0) | VE_2_5V, ++ EMI_D14 | STRENGTH(0) | VE_2_5V, ++ EMI_D13 | STRENGTH(0) | VE_2_5V, ++ EMI_D12 | STRENGTH(0) | VE_2_5V, ++ EMI_D11 | STRENGTH(0) | VE_2_5V, ++ EMI_D10 | STRENGTH(0) | VE_2_5V, ++ EMI_D9 | STRENGTH(0) | VE_2_5V, ++ EMI_D8 | STRENGTH(0) | VE_2_5V, ++ EMI_D7 | STRENGTH(0) | VE_2_5V, ++ EMI_D6 | STRENGTH(0) | VE_2_5V, ++ EMI_D5 | STRENGTH(0) | VE_2_5V, ++ EMI_D4 | STRENGTH(0) | VE_2_5V, ++ EMI_D3 | STRENGTH(0) | VE_2_5V, ++ EMI_D2 | STRENGTH(0) | VE_2_5V, ++ EMI_D1 | STRENGTH(0) | VE_2_5V, ++ EMI_D0 | STRENGTH(0) | VE_2_5V, ++ ++ /* SDRAM data control signals */ ++ EMI_DQM0 | STRENGTH(0) | VE_2_5V, /* LDM */ ++ EMI_DQM1 | STRENGTH(0) | VE_2_5V, /* UDM */ ++ ++ /* SDRAM address signals */ ++ EMI_A0 | STRENGTH(0) | VE_2_5V, ++ EMI_A1 | STRENGTH(0) | VE_2_5V, ++ EMI_A2 | STRENGTH(0) | VE_2_5V, ++ EMI_A3 | STRENGTH(0) | VE_2_5V, ++ EMI_A4 | STRENGTH(0) | VE_2_5V, ++ EMI_A5 | STRENGTH(0) | VE_2_5V, ++ EMI_A6 | STRENGTH(0) | VE_2_5V, ++ EMI_A7 | STRENGTH(0) | VE_2_5V, ++ EMI_A8 | STRENGTH(0) | VE_2_5V, ++ EMI_A9 | STRENGTH(0) | VE_2_5V, ++ EMI_A10 | STRENGTH(0) | VE_2_5V, ++ EMI_A11 | STRENGTH(0) | VE_2_5V, ++ EMI_A12 | STRENGTH(0) | VE_2_5V, ++ ++ /* SDRAM address control signals */ ++ EMI_RASN | STRENGTH(0) | VE_2_5V, ++ EMI_CASN | STRENGTH(0) | VE_2_5V, ++ ++ /* SDRAM control signals */ ++ EMI_CE0N | STRENGTH(0) | VE_2_5V, ++ EMI_CLK | STRENGTH(0) | VE_2_5V, ++ EMI_CLKN | STRENGTH(0) | VE_2_5V, ++ EMI_CKE | STRENGTH(0) | VE_2_5V, ++ EMI_WEN | STRENGTH(0) | VE_2_5V, ++ EMI_BA0 | STRENGTH(0) | VE_2_5V, ++ EMI_BA1 | STRENGTH(0) | VE_2_5V, ++ EMI_DQS0 | STRENGTH(0) | VE_2_5V, ++ EMI_DQS1 | STRENGTH(0) | VE_2_5V, ++#endif ++ /* debug port */ ++ PWM1_DUART_TX | STRENGTH(S4MA), /* strength is TBD */ ++ PWM0_DUART_RX | STRENGTH(S4MA), /* strength is TBD */ ++ ++ /* lcd */ ++ LCD_VSYNC, /* kernel tries with 12 mA for all LCD related pins */ ++ LCD_HSYNC, ++ LCD_ENABE, ++ LCD_DOTCLOCK, ++ LCD_D17, ++ LCD_D16, ++ LCD_D15, ++ LCD_D14, ++ LCD_D13, ++ LCD_D12, ++ LCD_D11, ++ LCD_D10, ++ LCD_D9, ++ LCD_D8, ++ LCD_D7, ++ LCD_D6, ++ LCD_D5, ++ LCD_D4, ++ LCD_D3, ++ LCD_D2, ++ LCD_D1, ++ LCD_D0, ++ ++ /* LCD usage currently unknown */ ++ LCD_CS, /* used as SPI SS */ ++ LCD_RS, /* used as SPI CLK */ ++ LCD_RESET, ++ LCD_WR, /* used as SPI MOSI */ ++ ++ /* I2C to the MMA7455L, KXTE9, AT24C08 (DCID), AT24C128B (ID EEPROM) and QN8005B */ ++ I2C_SDA, ++ I2C_CLK, ++ ++ /* Rotary decoder (external pull ups) */ ++ ROTARYA, ++ ROTARYB, ++ ++ /* the chumby bend (external pull up) */ ++ PWM4_GPIO | GPIO_IN, ++ ++ /* backlight control, to be controled by PWM, here we only want to disable it */ ++ PWM2_GPIO | GPIO_OUT | GPIO_VALUE(0), /* 1 enables, 0 disables the backlight */ ++ ++ /* send a reset signal to the USB hub */ ++ AUART1_TX_GPIO | GPIO_OUT | GPIO_VALUE(0), ++ ++ /* USB power disable (FIXME what level to be switched off) */ ++ AUART1_CTS_GPIO | GPIO_OUT | GPIO_VALUE(0), ++ ++ /* Detecting if a display is connected (0 = display attached) (external pull up) */ ++ AUART1_RTS_GPIO | GPIO_IN, ++ ++ /* disable the audio amplifier */ ++ GPMI_D08_GPIO | GPIO_OUT | GPIO_VALUE(0), ++ ++ /* Head Phone detection (FIXME what level when plugged in) (external pull up) */ ++ GPMI_D11_GPIO | GPIO_IN, ++ ++#if 0 ++ /* Enable the local 5V (FIXME what to do when the bootloader runs) */ ++ GPMI_D12_GPIO | GPIO_OUT | GPIO_VALUE(1), ++#endif ++ ++ /* not used pins */ ++ GPMI_D09_GPIO | GPIO_IN | PULLUP(1), ++ GPMI_D10_GPIO | GPIO_IN | PULLUP(1), ++ GPMI_D13_GPIO | GPIO_IN | PULLUP(1), ++ ++ /* unknown. Not connected to anything than test pin J113 */ ++ GPMI_D14_GPIO | GPIO_IN | PULLUP(1), ++ ++ /* unknown. Not connected to anything than test pin J114 */ ++ GPMI_D15_GPIO | GPIO_IN | PULLUP(1), ++ ++ /* NAND controller (Note: There is no NAND device on the board) */ ++ GPMI_D00 | PULLUP(1), ++ GPMI_D01 | PULLUP(1), ++ GPMI_D02 | PULLUP(1), ++ GPMI_D03 | PULLUP(1), ++ GPMI_D04 | PULLUP(1), ++ GPMI_D05 | PULLUP(1), ++ GPMI_D06 | PULLUP(1), ++ GPMI_D07 | PULLUP(1), ++ GPMI_CE0N, ++ GPMI_RDY0 | PULLUP(1), ++ GPMI_WRN, /* kernel tries here with 12 mA */ ++ GPMI_RDN, /* kernel tries here with 12 mA */ ++ GPMI_WPM, /* kernel tries here with 12 mA */ ++ GPMI_CLE, ++ GPMI_ALE, ++ ++ /* SD card interface */ ++ SSP1_DATA0 | PULLUP(1), /* available at J201 */ ++ SSP1_DATA1 | PULLUP(1), /* available at J200 */ ++ SSP1_DATA2 | PULLUP(1), /* available at J205 */ ++ SSP1_DATA3 | PULLUP(1), /* available at J204 */ ++ SSP1_SCK, /* available at J202 */ ++ SSP1_CMD | PULLUP(1), /* available at J203 */ ++ SSP1_DETECT | PULLUP(1), /* only connected to test pin J115 */ ++ ++ /* other not used pins */ ++ GPMI_CE1N_GPIO | GPIO_IN | PULLUP(1), ++ GPMI_CE2N_GPIO | GPIO_IN | PULLUP(1), ++ GPMI_RDY1_GPIO | GPIO_IN | PULLUP(1), ++ GPMI_RDY2_GPIO | GPIO_IN | PULLUP(1), ++ GPMI_RDY3_GPIO | GPIO_IN | PULLUP(1), ++}; ++ ++/** ++ * Try to register an environment storage on the attached MCI card ++ * @return 0 on success ++ * ++ * We relay on the existance of a useable SD card, already attached to ++ * our system, to get someting like a persistant memory for our environment. ++ * If this SD card is also the boot media, we can use the second partition ++ * for our environment purpose (if present!). ++ */ ++static int register_persistant_environment(void) ++{ ++ struct cdev *cdev; ++ ++ /* ++ * The chumby one only has one MCI card socket. ++ * So, we expect its name as "disk0". ++ */ ++ cdev = cdev_by_name("disk0"); ++ if (cdev == NULL) { ++ pr_err("No MCI card preset\n"); ++ return -ENODEV; ++ } ++ ++ /* MCI card is present, also a useable partition on it? */ ++ cdev = cdev_by_name("disk0.1"); ++ if (cdev == NULL) { ++ pr_err("No second partition available\n"); ++ pr_info("Please create at least a second partition with" ++ " 256 kiB...512 kiB in size (your choice)\n"); ++ return -ENODEV; ++ } ++ ++ /* use the full partition as our persistant environment storage */ ++ return devfs_add_partition("disk0.1", 0, cdev->size, DEVFS_PARTITION_FIXED, "env0"); ++} ++ ++static int falconwing_devices_init(void) ++{ ++ int i, rc; ++ ++ /* initizalize gpios */ ++ for (i = 0; i < ARRAY_SIZE(pad_setup); i++) ++ imx_gpio_mode(pad_setup[i]); ++ ++ register_device(&sdram_dev); ++ imx_set_ioclk(480U * 1000U); /* enable IOCLK to run at the PLL frequency */ ++ /* run the SSP unit clock at 100,000 kHz */ ++ imx_set_sspclk(0, 100U * 1000U, 1); ++ register_device(&mci_dev); ++ ++ armlinux_add_dram(&sdram_dev); ++ armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100)); ++ armlinux_set_architecture(MACH_TYPE_CHUMBY); ++ ++ rc = register_persistant_environment(); ++ if (rc != 0) ++ printf("Cannot create the 'env0' persistant environment storage (%d)\n", rc); ++ ++ return 0; ++} ++ ++device_initcall(falconwing_devices_init); ++ ++static struct device_d falconwing_serial_device = { ++ .name = "stm_serial", ++ .map_base = IMX_DBGUART_BASE, ++ .size = 8192, ++}; ++ ++static int falconwing_console_init(void) ++{ ++ return register_device(&falconwing_serial_device); ++} ++ ++console_initcall(falconwing_console_init); ++ ++/** @page chumbyone Chumby Industrie's Falconwing ++ ++This device is also known as "chumby one" (http://www.chumby.com/) ++ ++This CPU card is based on a Freescale i.MX23 CPU. The card is shipped with: ++ ++- 64 MiB synchronous dynamic RAM (DDR type) ++ ++Memory layout when @b barebox is running: ++ ++- 0x40000000 start of SDRAM ++- 0x40000100 start of kernel's boot parameters ++ - below malloc area: stack area ++ - below barebox: malloc area ++- 0x42000000 start of @b barebox ++ ++@section get_falconwing_binary How to get the bootloader binary image: ++ ++Using the default configuration: ++ ++@verbatim ++make ARCH=arm chumbyone_defconfig ++@endverbatim ++ ++Build the bootloader binary image: ++ ++@verbatim ++make ARCH=arm CROSS_COMPILE=armv5compiler ++@endverbatim ++ ++@note replace the armv5compiler with your ARM v5 cross compiler. ++ ++@section setup_falconwing How to prepare an MCI card to boot the "chumby one" with barebox ++ ++- Create four primary partitions on the MCI card ++ - the first one for the bootlets (about 256 kiB) ++ - the second one for the persistant environment (size is up to you, at least 256k) ++ - the third one for the kernel (2 MiB ... 4 MiB in size) ++ - the 4th one for the root filesystem which can fill the rest of the available space ++ ++- Mark the first partition with the partition ID "53" and copy the bootlets ++ into this partition (currently not part of @b barebox!). ++ ++- Copy the default @b barebox environment into the second partition (no filesystem required). ++ ++- Copy the kernel into the third partition (no filesystem required). ++ ++- Create the root filesystem in the 4th partition. You may copy an image into this ++ partition or you can do it in the classic way: mkfs on it, mount it and copy ++ all required data and programs into it. ++ ++*/ +diff --git a/arch/arm/boards/eukrea_cpuimx25/env/bin/init b/arch/arm/boards/eukrea_cpuimx25/env/bin/init +index 335d7ae..4732875 100644 +--- a/arch/arm/boards/eukrea_cpuimx25/env/bin/init ++++ b/arch/arm/boards/eukrea_cpuimx25/env/bin/init +@@ -14,9 +14,11 @@ fi + + if [ -f /env/logo.bmp ]; then + bmp /env/logo.bmp ++ fb0.enable=1 + elif [ -f /env/logo.bmp.lzo ]; then + unlzo /env/logo.bmp.lzo /logo.bmp + bmp /logo.bmp ++ fb0.enable=1 + fi + + if [ -z $eth0.ethaddr ]; then +diff --git a/arch/arm/boards/eukrea_cpuimx25/env/config b/arch/arm/boards/eukrea_cpuimx25/env/config +index 9217ca1..3e41ec8 100644 +--- a/arch/arm/boards/eukrea_cpuimx25/env/config ++++ b/arch/arm/boards/eukrea_cpuimx25/env/config +@@ -13,7 +13,7 @@ autoboot_timeout=1 + nfsroot="" + bootargs="console=ttymxc0,115200" + +-nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)" ++nand_parts="256k(barebox)ro,128k(bareboxenv),2432k(kernel),-(root)" + rootpartnum_nand=3 + ubiroot="eukrea-cpuimx25-rootfs" + +diff --git a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +index 7fd1031..3048c3f 100644 +--- a/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c ++++ b/arch/arm/boards/eukrea_cpuimx25/eukrea_cpuimx25.c +@@ -40,6 +40,10 @@ + #include <nand.h> + #include <mach/imx-flash-header.h> + #include <mach/iomux-mx25.h> ++#include <i2c/i2c.h> ++#include <usb/fsl_usb2.h> ++#include <mach/usb.h> ++#include <mach/devices-imx25.h> + + extern unsigned long _stext; + extern void exception_vectors(void); +@@ -85,13 +89,6 @@ static struct fec_platform_data fec_info = { + .phy_addr = 1, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = IMX_FEC_BASE, +- .platform_data = &fec_info, +-}; +- + static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +@@ -110,13 +107,6 @@ struct imx_nand_platform_data nand_info = { + .hw_ecc = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = IMX_NFC_BASE, +- .platform_data = &nand_info, +-}; +- + static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "CMO-QVGA", +@@ -142,13 +132,47 @@ static struct imx_fb_platform_data eukrea_cpuimx25_fb_data = { + .dmacr = 0x80040060, + }; + ++#ifdef CONFIG_USB ++static void imx25_usb_init(void) ++{ ++ unsigned int tmp; ++ ++ /* Host 1 */ ++ tmp = readl(IMX_OTG_BASE + 0x600); ++ tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | ++ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); ++ tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; ++ tmp |= MX35_H1_USBTE_BIT; ++ tmp |= MX35_H1_IPPUE_DOWN_BIT; ++ writel(tmp, IMX_OTG_BASE + 0x600); ++ ++ tmp = readl(IMX_OTG_BASE + 0x584); ++ tmp |= 3 << 30; ++ writel(tmp, IMX_OTG_BASE + 0x584); ++ ++ /* Set to Host mode */ ++ tmp = readl(IMX_OTG_BASE + 0x5a8); ++ writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); ++} ++ ++static struct device_d usbh2_dev = { ++ .id = -1, ++ .name = "ehci", ++ .map_base = IMX_OTG_BASE + 0x400, ++ .size = 0x200, ++}; ++#endif + +-static struct device_d imxfb_dev = { +- .id = -1, +- .name = "imxfb", +- .map_base = 0x53fbc000, +- .size = 0x1000, +- .platform_data = &eukrea_cpuimx25_fb_data, ++static struct fsl_usb2_platform_data usb_pdata = { ++ .operating_mode = FSL_USB2_DR_DEVICE, ++ .phy_mode = FSL_USB2_PHY_UTMI, ++}; ++ ++static struct device_d usbotg_dev = { ++ .name = "fsl-udc", ++ .map_base = IMX_OTG_BASE, ++ .size = 0x200, ++ .platform_data = &usb_pdata, + }; + + #ifdef CONFIG_MMU +@@ -209,6 +233,16 @@ static struct pad_desc eukrea_cpuimx25_pads[] = { + MX25_PAD_HSYNC__LCDC_HSYN, + /* BACKLIGHT CONTROL */ + MX25_PAD_PWM__GPIO26, ++ /* I2C */ ++ MX25_PAD_I2C1_CLK__SCL, ++ MX25_PAD_I2C1_DAT__SDA, ++ /* SDCard */ ++ MX25_PAD_SD1_CLK__CLK, ++ MX25_PAD_SD1_CMD__CMD, ++ MX25_PAD_SD1_DATA0__DAT0, ++ MX25_PAD_SD1_DATA1__DAT1, ++ MX25_PAD_SD1_DATA2__DAT2, ++ MX25_PAD_SD1_DATA3__DAT3, + }; + + static int eukrea_cpuimx25_devices_init(void) +@@ -217,10 +251,11 @@ static int eukrea_cpuimx25_devices_init(void) + + mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads, + ARRAY_SIZE(eukrea_cpuimx25_pads)); +- register_device(&fec_dev); ++ ++ imx25_add_fec(&fec_info); + + nand_info.width = 1; +- register_device(&nand_dev); ++ imx25_add_nand(&nand_info); + + devfs_add_partition("nand0", 0x00000, 0x40000, + PARTITION_FIXED, "self_raw"); +@@ -236,7 +271,16 @@ static int eukrea_cpuimx25_devices_init(void) + gpio_direction_output(26, 1); + gpio_set_value(26, 1); + +- register_device(&imxfb_dev); ++ imx25_add_fb(&eukrea_cpuimx25_fb_data); ++ ++ imx25_add_i2c0(NULL); ++ imx25_add_mmc0(NULL); ++ ++#ifdef CONFIG_USB ++ imx25_usb_init(); ++ register_device(&usbh2_dev); ++#endif ++ register_device(&usbotg_dev); + + armlinux_add_dram(&sdram0_dev); + armlinux_set_bootparams((void *)0x80000100); +@@ -247,17 +291,9 @@ static int eukrea_cpuimx25_devices_init(void) + + device_initcall(eukrea_cpuimx25_devices_init); + +-static struct device_d eukrea_cpuimx25_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 16 * 1024, +-}; +- + static int eukrea_cpuimx25_console_init(void) + { +- writel(0x03010101, IMX_CCM_BASE + CCM_PCDR3); +- register_device(&eukrea_cpuimx25_serial_device); ++ imx25_add_uart0(); + return 0; + } + +@@ -270,10 +306,17 @@ void __bare_init nand_boot(void) + } + #endif + +-static int eukrea_cpuimx25_core_setup(void) +-{ +- writel(0x01010103, IMX_CCM_BASE + CCM_PCDR2); +- return 0; ++static int eukrea_cpuimx25_core_init(void) { ++ /* enable UART1, FEC, SDHC, USB & I2C clock */ ++ writel(readl(IMX_CCM_BASE + CCM_CGCR0) | (1 << 6) | (1 << 23) ++ | (1 << 15) | (1 << 21) | (1 << 3) | (1 << 28), ++ IMX_CCM_BASE + CCM_CGCR0); ++ writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 23) | (1 << 15) ++ | (1 << 13), IMX_CCM_BASE + CCM_CGCR1); ++ writel(readl(IMX_CCM_BASE + CCM_CGCR2) | (1 << 14), ++ IMX_CCM_BASE + CCM_CGCR2); + ++ return 0; + } +-core_initcall(eukrea_cpuimx25_core_setup); ++ ++core_initcall(eukrea_cpuimx25_core_init); +diff --git a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +index b9d3ce5..4ebf247 100644 +--- a/arch/arm/boards/eukrea_cpuimx25/lowlevel.c ++++ b/arch/arm/boards/eukrea_cpuimx25/lowlevel.c +@@ -26,13 +26,13 @@ + #include <mach/imx-regs.h> + #include <mach/imx-pll.h> + #include <mach/esdctl.h> +-#include <asm/cache-l2x0.h> + #include <asm/io.h> + #include <mach/imx-nand.h> + #include <asm/barebox-arm.h> + #include <asm-generic/memory_layout.h> + #include <asm/system.h> + ++#ifdef CONFIG_NAND_IMX_BOOT + static void __bare_init __naked insdram(void) + { + uint32_t r; +@@ -45,17 +45,32 @@ static void __bare_init __naked insdram(void) + + board_init_lowlevel_return(); + } +- +-#define MX25_CCM_MCR 0x64 +-#define MX25_CCM_CGR0 0x0c +-#define MX25_CCM_CGR1 0x10 +-#define MX25_CCM_CGR2 0x14 ++#endif + + void __bare_init __naked board_init_lowlevel(void) + { + uint32_t r; ++#ifdef CONFIG_NAND_IMX_BOOT + unsigned int *trg, *src; + int i; ++#endif ++ register uint32_t loops = 0x20000; ++ ++ /* restart the MPLL and wait until it's stable */ ++ writel(readl(IMX_CCM_BASE + CCM_CCTL) | (1 << 27), ++ IMX_CCM_BASE + CCM_CCTL); ++ while (readl(IMX_CCM_BASE + CCM_CCTL) & (1 << 27)) {}; ++ ++ /* Configure dividers and ARM clock source ++ * ARM @ 400 MHz ++ * AHB @ 133 MHz ++ */ ++ writel(0x20034000, IMX_CCM_BASE + CCM_CCTL); ++ ++ /* Enable UART1 / FEC / */ ++/* writel(0x1FFFFFFF, IMX_CCM_BASE + CCM_CGCR0); ++ writel(0xFFFFFFFF, IMX_CCM_BASE + CCM_CGCR1); ++ writel(0x000FDFFF, IMX_CCM_BASE + CCM_CGCR2);*/ + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good. + * Set all MPROTx to be non-bufferable, trusted for R/W, +@@ -102,23 +117,46 @@ void __bare_init __naked board_init_lowlevel(void) + */ + writel(0x1, 0xb8003000); + +- /* enable all the clocks */ +- writel(0x038A81A2, IMX_CCM_BASE + MX25_CCM_CGR0); +- writel(0x24788F00, IMX_CCM_BASE + MX25_CCM_CGR1); +- writel(0x00004438, IMX_CCM_BASE + MX25_CCM_CGR2); +- writel(0x00, IMX_CCM_BASE + MX25_CCM_MCR); ++ /* Speed up NAND controller by adjusting the NFC divider */ ++ r = readl(IMX_CCM_BASE + CCM_PCDR2); ++ r &= ~0xf; ++ r |= 0x1; ++ writel(r, IMX_CCM_BASE + CCM_PCDR2); ++ ++ /* Skip SDRAM initialization if we run from RAM */ ++ r = get_pc(); ++ if (r > 0x80000000 && r < 0x90000000) ++ board_init_lowlevel_return(); ++ ++ /* Init Mobile DDR */ ++ writel(0x0000000E, ESDMISC); ++ writel(0x00000004, ESDMISC); ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++ ++ writel(0x0029572B, ESDCFG0); ++ writel(0x92210000, ESDCTL0); ++ writeb(0xda, IMX_SDRAM_CS0 + 0x400); ++ writel(0xA2210000, ESDCTL0); ++ writeb(0xda, IMX_SDRAM_CS0); ++ writeb(0xda, IMX_SDRAM_CS0); ++ writel(0xB2210000, ESDCTL0); ++ writeb(0xda, IMX_SDRAM_CS0 + 0x33); ++ writeb(0xda, IMX_SDRAM_CS0 + 0x1000000); ++ writel(0x82216080, ESDCTL0); + + #ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); +- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000) ++ if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ +- for (i = 0; i < 0x1000 / sizeof(int); i++) ++ for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ +diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot +index 7272e56..0e1c80a 100644 +--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/boot ++++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/boot +@@ -27,12 +27,14 @@ else + bootargs="$bootargs ip=off" + fi + +-if [ x$root = xnand ]; then +- bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" +-elif [ x$root = xnor ]; then +- bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" ++if [ x$rootfstype = xubifs ]; then ++ bootargs="$bootargs root=ubi0:$ubiroot ubi.mtd=$rootpartnum rootfstype=ubifs" + else +- bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" ++ if [ x$root = xnand ]; then ++ bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" ++ elif [ x$root = xnor ]; then ++ bootargs="$bootargs root=$rootpart_nor rootfstype=jffs2" ++ fi + fi + + bootargs="$bootargs mtdparts=physmap-flash.0:$nor_parts;mxc_nand:$nand_parts" +diff --git a/arch/arm/boards/eukrea_cpuimx27/env/bin/init b/arch/arm/boards/eukrea_cpuimx27/env/bin/init +index 3bfd194..aefd67c 100644 +--- a/arch/arm/boards/eukrea_cpuimx27/env/bin/init ++++ b/arch/arm/boards/eukrea_cpuimx27/env/bin/init +@@ -16,11 +16,21 @@ if [ -e /dev/nand0 ]; then + source /env/bin/hush_hack + fi + ++if [ -f /env/logo.bmp ]; then ++ bmp /env/logo.bmp ++ fb0.enable=1 ++elif [ -f /env/logo.bmp.lzo ]; then ++ unlzo /env/logo.bmp.lzo /logo.bmp ++ bmp /logo.bmp ++ fb0.enable=1 ++fi ++ + if [ -z $eth0.ethaddr ]; then + while [ -z $eth0.ethaddr ]; do + readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr + done + echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" ++ saveenv + fi + + echo +diff --git a/arch/arm/boards/eukrea_cpuimx27/env/config b/arch/arm/boards/eukrea_cpuimx27/env/config +index 505ada3..7f56003 100644 +--- a/arch/arm/boards/eukrea_cpuimx27/env/config ++++ b/arch/arm/boards/eukrea_cpuimx27/env/config +@@ -3,9 +3,11 @@ + # can be either 'net', 'nor' or 'nand'' + kernel=nor + root=nor ++rootfstype=ubifs + +-uimage=mx27/uImage +-jffs2=mx27/rootfs.jffs2 ++basedir=cpuimx27 ++uimage=$basedir/uImage ++rootfs=$basedir/rootfs + + autoboot_timeout=1 + +@@ -13,12 +15,15 @@ autoboot_timeout=1 + video="CMO-QVGA" + bootargs="console=ttymxc0,115200 fec_mac=$eth0.ethaddr video=mxcfb:$video" + +-nor_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)" ++nor_parts="256k(barebox)ro,128k(bareboxenv),2432k(kernel),-(root)" + rootpart_nor="/dev/mtdblock3" + + nand_parts="-(nand)" + rootpart_nand="" + ++rootpartnum=3 ++ubiroot="eukrea-cpuimx27-rootfs" ++ + nfsroot="" + + # use 'dhcp' to do dhcp in barebox and in kernel +diff --git a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +index 4d1797b..4567cba 100644 +--- a/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c ++++ b/arch/arm/boards/eukrea_cpuimx27/eukrea_cpuimx27.c +@@ -44,8 +44,9 @@ + #include <ns16550.h> + #include <asm/mmu.h> + #include <i2c/i2c.h> +-#include <i2c/lp3972.h> ++#include <mfd/lp3972.h> + #include <mach/iomux-mx27.h> ++#include <mach/devices-imx27.h> + + static struct device_d cfi_dev = { + .id = -1, +@@ -86,26 +87,12 @@ static struct fec_platform_data fec_info = { + .phy_addr = 1, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = 0x1002b000, +- .platform_data = &fec_info, +-}; +- + struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = 0xd8000000, +- .platform_data = &nand_info, +-}; +- + #ifdef CONFIG_DRIVER_SERIAL_NS16550 + unsigned int quad_uart_read(unsigned long base, unsigned char reg_idx) + { +@@ -156,12 +143,6 @@ static struct i2c_board_info i2c_devices[] = { + }, + }; + +-static struct device_d i2c_dev = { +- .id = -1, +- .name = "i2c-imx", +- .map_base = IMX_I2C1_BASE, +-}; +- + #ifdef CONFIG_MMU + static void eukrea_cpuimx27_mmu_init(void) + { +@@ -275,6 +256,7 @@ static int eukrea_cpuimx27_devices_init(void) + PA29_PF_VSYNC, + PA31_PF_OE_ACD, + GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT, ++ GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT, + #endif + }; + +@@ -293,12 +275,12 @@ static int eukrea_cpuimx27_devices_init(void) + #ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB + register_device(&cfi_dev1); + #endif +- register_device(&nand_dev); ++ imx27_add_nand(&nand_info); + register_device(&sdram_dev); + + PCCR0 |= PCCR0_I2C1_EN; + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); +- register_device(&i2c_dev); ++ imx27_add_i2c0(NULL); + + devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); +@@ -311,6 +293,8 @@ static int eukrea_cpuimx27_devices_init(void) + register_device(&imxfb_dev); + gpio_direction_output(GPIO_PORTE | 5, 0); + gpio_set_value(GPIO_PORTE | 5, 1); ++ gpio_direction_output(GPIO_PORTA | 25, 0); ++ gpio_set_value(GPIO_PORTA | 25, 1); + #endif + + armlinux_add_dram(&sdram_dev); +@@ -356,7 +340,7 @@ static int eukrea_cpuimx27_late_init(void) + u8 reg[1]; + #endif + console_flush(); +- register_device(&fec_dev); ++ imx27_add_fec(&fec_info); + + #ifdef CONFIG_I2C_LP3972 + client = lp3972_get_client(); +diff --git a/arch/arm/boards/eukrea_cpuimx35/env/bin/init b/arch/arm/boards/eukrea_cpuimx35/env/bin/init +index 90007cd..b56d7b5 100644 +--- a/arch/arm/boards/eukrea_cpuimx35/env/bin/init ++++ b/arch/arm/boards/eukrea_cpuimx35/env/bin/init +@@ -15,12 +15,12 @@ fi + if [ -f /env/logo.bmp ]; then + fb0.enable=1 + bmp /env/logo.bmp +- gpio_direction_out 1 1 ++ gpio_set_value 1 1 + elif [ -f /env/logo.bmp.lzo ]; then + unlzo /env/logo.bmp.lzo /logo.bmp + fb0.enable=1 + bmp /logo.bmp +- gpio_direction_out 1 1 ++ gpio_set_value 1 1 + fi + + if [ -z $eth0.ethaddr ]; then +diff --git a/arch/arm/boards/eukrea_cpuimx35/env/config b/arch/arm/boards/eukrea_cpuimx35/env/config +index df2079f..fc99e51 100644 +--- a/arch/arm/boards/eukrea_cpuimx35/env/config ++++ b/arch/arm/boards/eukrea_cpuimx35/env/config +@@ -13,7 +13,7 @@ autoboot_timeout=1 + nfsroot="" + bootargs="console=ttymxc0,115200" + +-nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)" ++nand_parts="256k(barebox)ro,128k(bareboxenv),2432k(kernel),-(root)" + rootpartnum_nand=3 + ubiroot="eukrea-cpuimx35-rootfs" + +diff --git a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +index 63d019a..07f320b 100644 +--- a/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c ++++ b/arch/arm/boards/eukrea_cpuimx35/eukrea_cpuimx35.c +@@ -51,19 +51,16 @@ + #include <mach/pmic.h> + #include <mach/imx-ipu-fb.h> + #include <mach/imx-pll.h> ++#include <i2c/i2c.h> ++#include <usb/fsl_usb2.h> ++#include <mach/usb.h> ++#include <mach/devices-imx35.h> + + static struct fec_platform_data fec_info = { + .xcv_type = MII100, + .phy_addr = 0x1F, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = IMX_FEC_BASE, +- .platform_data = &fec_info, +-}; +- + static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +@@ -83,13 +80,6 @@ struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = IMX_NFC_BASE, +- .platform_data = &nand_info, +-}; +- + static struct fb_videomode imxfb_mode = { + .name = "CMO_QVGA", + .refresh = 60, +@@ -118,12 +108,47 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = { + .enable = eukrea_cpuimx35_enable_display, + }; + +-static struct device_d imxfb_dev = { +- .id = -1, +- .name = "imx-ipu-fb", +- .map_base = 0x53fc0000, +- .size = 0x1000, +- .platform_data = &ipu_fb_data, ++#ifdef CONFIG_USB ++static void imx35_usb_init(void) ++{ ++ unsigned int tmp; ++ ++ /* Host 1 */ ++ tmp = readl(IMX_OTG_BASE + 0x600); ++ tmp &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT | ++ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT); ++ tmp |= (MXC_EHCI_INTERFACE_SINGLE_UNI) << MX35_H1_SIC_SHIFT; ++ tmp |= MX35_H1_USBTE_BIT; ++ tmp |= MX35_H1_IPPUE_DOWN_BIT; ++ writel(tmp, IMX_OTG_BASE + 0x600); ++ ++ tmp = readl(IMX_OTG_BASE + 0x584); ++ tmp |= 3 << 30; ++ writel(tmp, IMX_OTG_BASE + 0x584); ++ ++ /* Set to Host mode */ ++ tmp = readl(IMX_OTG_BASE + 0x5a8); ++ writel(tmp | 0x3, IMX_OTG_BASE + 0x5a8); ++} ++ ++static struct device_d usbh2_dev = { ++ .id = -1, ++ .name = "ehci", ++ .map_base = IMX_OTG_BASE + 0x400, ++ .size = 0x200, ++}; ++#endif ++ ++static struct fsl_usb2_platform_data usb_pdata = { ++ .operating_mode = FSL_USB2_DR_DEVICE, ++ .phy_mode = FSL_USB2_PHY_UTMI, ++}; ++ ++static struct device_d usbotg_dev = { ++ .name = "fsl-udc", ++ .map_base = IMX_OTG_BASE, ++ .size = 0x200, ++ .platform_data = &usb_pdata, + }; + + #ifdef CONFIG_MMU +@@ -153,17 +178,31 @@ postcore_initcall(eukrea_cpuimx35_mmu_init); + + static int eukrea_cpuimx35_devices_init(void) + { +- register_device(&nand_dev); ++ unsigned int tmp; ++ ++ imx35_add_nand(&nand_info); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); + devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); + dev_add_bb_dev("env_raw", "env0"); + +- register_device(&fec_dev); ++ imx35_add_fec(&fec_info); + + register_device(&sdram_dev); +- register_device(&imxfb_dev); ++ imx35_add_fb(&ipu_fb_data); ++ ++ imx35_add_i2c0(NULL); ++ imx35_add_mmc0(NULL); ++ ++#ifdef CONFIG_USB ++ imx35_usb_init(); ++ register_device(&usbh2_dev); ++#endif ++ /* Workaround ENGcm09152 */ ++ tmp = readl(IMX_OTG_BASE + 0x608); ++ writel(tmp | (1 << 23), IMX_OTG_BASE + 0x608); ++ register_device(&usbotg_dev); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0x80000100); +@@ -174,13 +213,6 @@ static int eukrea_cpuimx35_devices_init(void) + + device_initcall(eukrea_cpuimx35_devices_init); + +-static struct device_d eukrea_cpuimx35_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 4096, +-}; +- + static struct pad_desc eukrea_cpuimx35_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, +@@ -211,6 +243,16 @@ static struct pad_desc eukrea_cpuimx35_pads[] = { + MX35_PAD_LD23__GPIO3_29, + MX35_PAD_CONTRAST__GPIO1_1, + MX35_PAD_D3_CLS__GPIO1_4, ++ ++ MX35_PAD_I2C1_CLK__I2C1_SCL, ++ MX35_PAD_I2C1_DAT__I2C1_SDA, ++ ++ MX35_PAD_SD1_CMD__ESDHC1_CMD, ++ MX35_PAD_SD1_CLK__ESDHC1_CLK, ++ MX35_PAD_SD1_DATA0__ESDHC1_DAT0, ++ MX35_PAD_SD1_DATA1__ESDHC1_DAT1, ++ MX35_PAD_SD1_DATA2__ESDHC1_DAT2, ++ MX35_PAD_SD1_DATA3__ESDHC1_DAT3, + }; + + static int eukrea_cpuimx35_console_init(void) +@@ -219,13 +261,13 @@ static int eukrea_cpuimx35_console_init(void) + ARRAY_SIZE(eukrea_cpuimx35_pads)); + + /* screen default on to prevent flicker */ +- gpio_direction_output(4, 1); ++ gpio_direction_output(4, 0); + /* backlight default off */ + gpio_direction_output(1, 0); + /* led default off */ + gpio_direction_output(32 * 2 + 29, 1); + +- register_device(&eukrea_cpuimx35_serial_device); ++ imx35_add_uart0(); + return 0; + } + +@@ -235,10 +277,15 @@ static int eukrea_cpuimx35_core_init(void) + { + u32 reg; + +- /* enable clock for I2C1 and FEC */ ++ /* enable clock for I2C1, SDHC1, USB and FEC */ + reg = readl(IMX_CCM_BASE + CCM_CGR1); + reg |= 0x3 << CCM_CGR1_FEC_SHIFT; ++ reg |= 0x3 << CCM_CGR1_SDHC1_SHIFT; ++ reg |= 0x3 << CCM_CGR1_I2C1_SHIFT, + reg = writel(reg, IMX_CCM_BASE + CCM_CGR1); ++ reg = readl(IMX_CCM_BASE + CCM_CGR2); ++ reg |= 0x3 << CCM_CGR2_USB_SHIFT; ++ reg = writel(reg, IMX_CCM_BASE + CCM_CGR2); + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + /* +diff --git a/arch/arm/boards/eukrea_cpuimx35/flash_header.c b/arch/arm/boards/eukrea_cpuimx35/flash_header.c +index 285a2d4..93c8348 100644 +--- a/arch/arm/boards/eukrea_cpuimx35/flash_header.c ++++ b/arch/arm/boards/eukrea_cpuimx35/flash_header.c +@@ -12,30 +12,31 @@ void __naked __flash_header_start go(void) + struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { + { .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, }, + { .ptr_type = 4, .addr = 0x53F80004, .val = 0x00821000, }, +- { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, + { .ptr_type = 4, .addr = 0xB8001010, .val = 0x0000000C, }, +- { .ptr_type = 4, .addr = 0xB8001004, .val = 0x0009572B, }, +- { .ptr_type = 4, .addr = 0xB8001000, .val = 0x92220000, }, ++ { .ptr_type = 4, .addr = 0xb8001004, .val = 0x0009572B, }, ++ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x92220000, }, + { .ptr_type = 1, .addr = 0x80000400, .val = 0xda, }, +- { .ptr_type = 4, .addr = 0xB8001000, .val = 0xA2220000, }, +- { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, }, +- { .ptr_type = 1, .addr = 0x80000000, .val = 0x87654321, }, +- { .ptr_type = 4, .addr = 0xB8001000, .val = 0xB2220000, }, ++ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xa2220000, }, ++ { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, ++ { .ptr_type = 4, .addr = 0x80000000, .val = 0x12344321, }, ++ { .ptr_type = 4, .addr = 0xb8001000, .val = 0xb2220000, }, + { .ptr_type = 1, .addr = 0x80000033, .val = 0xda, }, + { .ptr_type = 1, .addr = 0x82000000, .val = 0xda, }, +- { .ptr_type = 4, .addr = 0xB8001000, .val = 0x82224080, }, +- { .ptr_type = 4, .addr = 0xB8001010, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0xb8001000, .val = 0x82224080, }, ++ { .ptr_type = 4, .addr = 0xb8001010, .val = 0x00000004, }, + }; + +- ++#define CPUIMX35_DEST_BASE 0x80000000 ++#define CPUIMX35_FLASH_HEADER_BASE (CPUIMX35_DEST_BASE + FLASH_HEADER_OFFSET) + struct imx_flash_header __flash_header_section flash_header = { +- .app_code_jump_vector = DEST_BASE + ((unsigned int)&exception_vectors - TEXT_BASE), ++ .app_code_jump_vector = CPUIMX35_DEST_BASE + 0x1000, + .app_code_barker = APP_CODE_BARKER, + .app_code_csf = 0, +- .dcd_ptr_ptr = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd), ++ .dcd_ptr_ptr = CPUIMX35_FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd), + .super_root_key = 0, +- .dcd = FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker), +- .app_dest = DEST_BASE, ++ .dcd = CPUIMX35_FLASH_HEADER_BASE + offsetof(struct imx_flash_header, dcd_barker), ++ .app_dest = CPUIMX35_DEST_BASE, + .dcd_barker = DCD_BARKER, + .dcd_block_len = sizeof(dcd_entry), + }; +diff --git a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +index aad334d..6c0e106 100644 +--- a/arch/arm/boards/eukrea_cpuimx35/lowlevel.c ++++ b/arch/arm/boards/eukrea_cpuimx35/lowlevel.c +@@ -66,6 +66,7 @@ void __bare_init __naked board_init_lowlevel(void) + unsigned int *trg, *src; + int i; + #endif ++ register uint32_t loops = 0x20000; + + r = get_cr(); + r |= CR_Z; /* Flow prediction (Z) */ +@@ -118,7 +119,7 @@ void __bare_init __naked board_init_lowlevel(void) + writel(r, ccm_base + CCM_CGR0); + + r = readl(ccm_base + CCM_CGR1); +- r |= 0x00000C00; ++ r |= 0x00030C00; + r |= 0x00000003; + writel(r, ccm_base + CCM_CGR1); + +@@ -132,31 +133,34 @@ void __bare_init __naked board_init_lowlevel(void) + board_init_lowlevel_return(); + + /* Init Mobile DDR */ ++ writel(0x0000000E, ESDMISC); + writel(0x00000004, ESDMISC); +- writel(0x0000000C, ESDMISC); ++ __asm__ volatile ("1:\n" ++ "subs %0, %1, #1\n" ++ "bne 1b":"=r" (loops):"0" (loops)); ++ + writel(0x0009572B, ESDCFG0); + writel(0x92220000, ESDCTL0); + writeb(0xda, IMX_SDRAM_CS0 + 0x400); + writel(0xA2220000, ESDCTL0); +- writel(0x87654321, IMX_SDRAM_CS0); +- writel(0x87654321, IMX_SDRAM_CS0); ++ writeb(0xda, IMX_SDRAM_CS0); ++ writeb(0xda, IMX_SDRAM_CS0); + writel(0xB2220000, ESDCTL0); + writeb(0xda, IMX_SDRAM_CS0 + 0x33); + writeb(0xda, IMX_SDRAM_CS0 + 0x2000000); +- writel(0x82224080, ESDCTL0); +- writel(0x00000004, ESDMISC); ++ writel(0x82228080, ESDCTL0); + + #ifdef CONFIG_NAND_IMX_BOOT + /* skip NAND boot if not running from NFC space */ + r = get_pc(); +- if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x1000) ++ if (r < IMX_NFC_BASE || r > IMX_NFC_BASE + 0x800) + board_init_lowlevel_return(); + + src = (unsigned int *)IMX_NFC_BASE; + trg = (unsigned int *)TEXT_BASE; + + /* Move ourselves out of NFC SRAM */ +- for (i = 0; i < 0x1000 / sizeof(int); i++) ++ for (i = 0; i < 0x800 / sizeof(int); i++) + *trg++ = *src++; + + /* Jump to SDRAM */ +diff --git a/arch/arm/boards/freescale-mx23-evk/Makefile b/arch/arm/boards/freescale-mx23-evk/Makefile +new file mode 100644 +index 0000000..cffb561 +--- /dev/null ++++ b/arch/arm/boards/freescale-mx23-evk/Makefile +@@ -0,0 +1,2 @@ ++# ++obj-y := mx23-evk.o +diff --git a/arch/arm/boards/freescale-mx23-evk/config.h b/arch/arm/boards/freescale-mx23-evk/config.h +new file mode 100644 +index 0000000..4b3da8f +--- /dev/null ++++ b/arch/arm/boards/freescale-mx23-evk/config.h +@@ -0,0 +1,16 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ +diff --git a/arch/arm/boards/freescale-mx23-evk/mx23-evk.c b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c +new file mode 100644 +index 0000000..1ce72be +--- /dev/null ++++ b/arch/arm/boards/freescale-mx23-evk/mx23-evk.c +@@ -0,0 +1,96 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <gpio.h> ++#include <environment.h> ++#include <asm/armlinux.h> ++#include <generated/mach-types.h> ++#include <mach/imx-regs.h> ++ ++static struct memory_platform_data ram_pdata = { ++ .name = "ram0", ++ .flags = DEVFS_RDWR, ++}; ++ ++static struct device_d sdram_dev = { ++ .name = "mem", ++ .map_base = IMX_MEMORY_BASE, ++ .size = 32 * 1024 * 1024, ++ .platform_data = &ram_pdata, ++}; ++ ++static int mx23_evk_devices_init(void) ++{ ++ register_device(&sdram_dev); ++ ++ armlinux_add_dram(&sdram_dev); ++ armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100)); ++ armlinux_set_architecture(MACH_TYPE_MX23EVK); ++ ++ return 0; ++} ++ ++device_initcall(mx23_evk_devices_init); ++ ++static struct device_d mx23_evk_serial_device = { ++ .name = "stm_serial", ++ .map_base = IMX_DBGUART_BASE, ++ .size = 8192, ++}; ++ ++static int mx23_evk_console_init(void) ++{ ++ return register_device(&mx23_evk_serial_device); ++} ++ ++console_initcall(mx23_evk_console_init); ++ ++/** @page mx23_evk Freescale's i.MX23 evaluation kit ++ ++This CPU card is based on an i.MX23 CPU. The card is shipped with: ++ ++- 32 MiB synchronous dynamic RAM (mobile DDR type) ++- ENC28j60 based network (over SPI) ++ ++Memory layout when @b barebox is running: ++ ++- 0x40000000 start of SDRAM ++- 0x40000100 start of kernel's boot parameters ++ - below malloc area: stack area ++ - below barebox: malloc area ++- 0x41000000 start of @b barebox ++ ++@section get_imx23evk_binary How to get the bootloader binary image: ++ ++Using the default configuration: ++ ++@verbatim ++make ARCH=arm imx23evk_defconfig ++@endverbatim ++ ++Build the bootloader binary image: ++ ++@verbatim ++make ARCH=arm CROSS_COMPILE=armv5compiler ++@endverbatim ++ ++@note replace the armv5compiler with your ARM v5 cross compiler. ++*/ +diff --git a/arch/arm/boards/freescale-mx25-3-stack/3stack.c b/arch/arm/boards/freescale-mx25-3-stack/3stack.c +index 70de7958..49b7f5c 100644 +--- a/arch/arm/boards/freescale-mx25-3-stack/3stack.c ++++ b/arch/arm/boards/freescale-mx25-3-stack/3stack.c +@@ -39,7 +39,8 @@ + #include <mach/generic.h> + #include <linux/err.h> + #include <i2c/i2c.h> +-#include <i2c/mc34704.h> ++#include <mfd/mc34704.h> ++#include <mach/devices-imx25.h> + + extern unsigned long _stext; + extern void exception_vectors(void); +@@ -112,13 +113,6 @@ static struct fec_platform_data fec_info = { + .phy_addr = 1, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = IMX_FEC_BASE, +- .platform_data = &fec_info, +-}; +- + static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +@@ -156,13 +150,6 @@ struct imx_nand_platform_data nand_info = { + .hw_ecc = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = IMX_NFC_BASE, +- .platform_data = &nand_info, +-}; +- + #ifdef CONFIG_USB + static void imx25_usb_init(void) + { +@@ -197,12 +184,6 @@ static struct i2c_board_info i2c_devices[] = { + }, + }; + +-static struct device_d i2c_dev = { +- .id = -1, +- .name = "i2c-imx", +- .map_base = IMX_I2C1_BASE, +-}; +- + static int imx25_3ds_pmic_init(void) + { + struct mc34704 *pmic; +@@ -259,12 +240,12 @@ static int imx25_devices_init(void) + register_device(&usbh2_dev); + #endif + +- register_device(&fec_dev); ++ imx25_add_fec(&fec_info); + + if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 14)) + nand_info.width = 2; + +- register_device(&nand_dev); ++ imx25_add_nand(&nand_info); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); +@@ -276,7 +257,7 @@ static int imx25_devices_init(void) + register_device(&sram0_dev); + + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); +- register_device(&i2c_dev); ++ imx25_add_i2c0(NULL); + + armlinux_add_dram(&sdram0_dev); + armlinux_set_bootparams((void *)0x80000100); +@@ -288,13 +269,6 @@ static int imx25_devices_init(void) + + device_initcall(imx25_devices_init); + +-static struct device_d imx25_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 16 * 1024, +-}; +- + static struct pad_desc imx25_pads[] = { + MX25_PAD_FEC_MDC__MDC, + MX25_PAD_FEC_MDIO__MDIO, +@@ -339,7 +313,7 @@ static int imx25_console_init(void) + + writel(0x03010101, 0x53f80024); + +- register_device(&imx25_serial_device); ++ imx25_add_uart0(); + return 0; + } + +diff --git a/arch/arm/boards/freescale-mx35-3-stack/3stack.c b/arch/arm/boards/freescale-mx35-3-stack/3stack.c +index 71aaa92..127bfb4 100644 +--- a/arch/arm/boards/freescale-mx35-3-stack/3stack.c ++++ b/arch/arm/boards/freescale-mx35-3-stack/3stack.c +@@ -48,10 +48,11 @@ + #include <mach/pmic.h> + #include <mach/imx-ipu-fb.h> + #include <mach/generic.h> ++#include <mach/devices-imx35.h> + + #include <i2c/i2c.h> +-#include <i2c/mc13892.h> +-#include <i2c/mc9sdz60.h> ++#include <mfd/mc13892.h> ++#include <mfd/mc9sdz60.h> + + + /* Board rev for the PDK 3stack */ +@@ -70,13 +71,6 @@ static struct fec_platform_data fec_info = { + .phy_addr = 0x1F, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = IMX_FEC_BASE, +- .platform_data = &fec_info, +-}; +- + static struct memory_platform_data sdram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +@@ -95,13 +89,6 @@ struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = IMX_NFC_BASE, +- .platform_data = &nand_info, +-}; +- + static struct device_d smc911x_dev = { + .id = -1, + .name = "smc911x", +@@ -111,7 +98,7 @@ static struct device_d smc911x_dev = { + + static struct i2c_board_info i2c_devices[] = { + { +- I2C_BOARD_INFO("mc13892", 0x08), ++ I2C_BOARD_INFO("mc13892-i2c", 0x08), + }, { + I2C_BOARD_INFO("mc9sdz60", 0x69), + }, +@@ -149,14 +136,6 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = { + .bpp = 16, + }; + +-static struct device_d imxfb_dev = { +- .id = -1, +- .name = "imx-ipu-fb", +- .map_base = 0x53fc0000, +- .size = 0x1000, +- .platform_data = &ipu_fb_data, +-}; +- + /* + * Revision to be passed to kernel. The kernel provided + * by freescale relies on this. +@@ -202,7 +181,7 @@ static int f3s_devices_init(void) + /* + * This platform supports NOR and NAND + */ +- register_device(&nand_dev); ++ imx35_add_nand(&nand_info); + register_device(&cfi_dev); + + switch ((reg >> 25) & 0x3) { +@@ -225,11 +204,11 @@ static int f3s_devices_init(void) + i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices)); + register_device(&i2c_dev); + +- register_device(&fec_dev); ++ imx35_add_fec(&fec_info); + register_device(&smc911x_dev); + + register_device(&sdram_dev); +- register_device(&imxfb_dev); ++ imx35_add_fb(&ipu_fb_data); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0x80000100); +@@ -250,13 +229,6 @@ static int f3s_enable_display(void) + + late_initcall(f3s_enable_display); + +-static struct device_d f3s_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 4096, +-}; +- + static struct pad_desc f3s_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, +@@ -322,7 +294,7 @@ static int f3s_console_init(void) + { + mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); + +- register_device(&f3s_serial_device); ++ imx35_add_uart0(); + return 0; + } + +diff --git a/arch/arm/boards/freescale-mx51-pdk/Makefile b/arch/arm/boards/freescale-mx51-pdk/Makefile +new file mode 100644 +index 0000000..8e0c87c +--- /dev/null ++++ b/arch/arm/boards/freescale-mx51-pdk/Makefile +@@ -0,0 +1,3 @@ ++obj-y += lowlevel_init.o ++obj-y += board.o ++obj-y += flash_header.o +diff --git a/arch/arm/boards/freescale-mx51-pdk/board.c b/arch/arm/boards/freescale-mx51-pdk/board.c +new file mode 100644 +index 0000000..ff779ca +--- /dev/null ++++ b/arch/arm/boards/freescale-mx51-pdk/board.c +@@ -0,0 +1,295 @@ ++/* ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <net.h> ++#include <init.h> ++#include <environment.h> ++#include <mach/imx-regs.h> ++#include <fec.h> ++#include <mach/gpio.h> ++#include <asm/armlinux.h> ++#include <generated/mach-types.h> ++#include <partition.h> ++#include <fs.h> ++#include <fcntl.h> ++#include <nand.h> ++#include <spi/spi.h> ++#include <mfd/mc13892.h> ++#include <asm/io.h> ++#include <asm/mmu.h> ++#include <mach/imx-nand.h> ++#include <mach/spi.h> ++#include <mach/generic.h> ++#include <mach/iomux-mx51.h> ++#include <mach/devices-imx51.h> ++ ++static struct memory_platform_data ram_pdata = { ++ .name = "ram0", ++ .flags = DEVFS_RDWR, ++}; ++ ++static struct device_d sdram_dev = { ++ .id = -1, ++ .name = "mem", ++ .map_base = 0x90000000, ++ .size = 512 * 1024 * 1024, ++ .platform_data = &ram_pdata, ++}; ++ ++static struct fec_platform_data fec_info = { ++ .xcv_type = MII100, ++}; ++ ++static struct pad_desc f3s_pads[] = { ++ MX51_PAD_EIM_EB2__FEC_MDIO, ++ MX51_PAD_EIM_EB3__FEC_RDATA1, ++ MX51_PAD_EIM_CS2__FEC_RDATA2, ++ MX51_PAD_EIM_CS3__FEC_RDATA3, ++ MX51_PAD_EIM_CS4__FEC_RX_ER, ++ MX51_PAD_EIM_CS5__FEC_CRS, ++ MX51_PAD_NANDF_RB2__FEC_COL, ++ MX51_PAD_NANDF_RB3__FEC_RX_CLK, ++ MX51_PAD_NANDF_RB7__FEC_TX_ER, ++ MX51_PAD_NANDF_CS3__FEC_MDC, ++ MX51_PAD_NANDF_CS4__FEC_TDATA1, ++ MX51_PAD_NANDF_CS5__FEC_TDATA2, ++ MX51_PAD_NANDF_CS6__FEC_TDATA3, ++ MX51_PAD_NANDF_CS7__FEC_TX_EN, ++ MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, ++ MX51_PAD_NANDF_D11__FEC_RX_DV, ++ MX51_PAD_NANDF_RB6__FEC_RDATA0, ++ MX51_PAD_NANDF_D8__FEC_TDATA0, ++ MX51_PAD_CSPI1_SS0__CSPI1_SS0, ++ MX51_PAD_CSPI1_MOSI__CSPI1_MOSI, ++ MX51_PAD_CSPI1_MISO__CSPI1_MISO, ++ MX51_PAD_CSPI1_RDY__CSPI1_RDY, ++ MX51_PAD_CSPI1_SCLK__CSPI1_SCLK, ++ MX51_PAD_EIM_A20__GPIO2_14, /* LAN8700 reset pin */ ++ IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, 0x85), /* FIXME: needed? */ ++}; ++ ++#ifdef CONFIG_MMU ++static void babbage_mmu_init(void) ++{ ++ mmu_init(); ++ ++ arm_create_section(0x90000000, 0x90000000, 512, PMD_SECT_DEF_CACHED); ++ arm_create_section(0xb0000000, 0x90000000, 512, PMD_SECT_DEF_UNCACHED); ++ ++ setup_dma_coherent(0x20000000); ++ ++#if TEXT_BASE & (0x100000 - 1) ++#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary ++#else ++ arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); ++#endif ++ ++ mmu_enable(); ++} ++#else ++static void babbage_mmu_init(void) ++{ ++} ++#endif ++ ++//extern int babbage_power_init(void); ++ ++#define BABBAGE_ECSPI1_CS0 (3 * 32 + 24) ++static int spi_0_cs[] = {BABBAGE_ECSPI1_CS0}; ++ ++static struct spi_imx_master spi_0_data = { ++ .chipselect = spi_0_cs, ++ .num_chipselect = ARRAY_SIZE(spi_0_cs), ++}; ++ ++static const struct spi_board_info mx51_babbage_spi_board_info[] = { ++ { ++ .name = "mc13892-spi", ++ .max_speed_hz = 300000, ++ .bus_num = 0, ++ .chip_select = 0, ++ }, ++}; ++ ++#define MX51_CCM_CACRR 0x10 ++ ++static void babbage_power_init(void) ++{ ++ struct mc13892 *mc13892; ++ u32 val; ++ ++ mc13892 = mc13892_get(); ++ if (!mc13892) { ++ printf("could not get mc13892\n"); ++ return; ++ } ++ ++ /* Write needed to Power Gate 2 register */ ++ mc13892_reg_read(mc13892, 34, &val); ++ val &= ~0x10000; ++ mc13892_reg_write(mc13892, 34, val); ++ ++ /* Write needed to update Charger 0 */ ++ mc13892_reg_write(mc13892, 48, 0x0023807F); ++ ++ /* power up the system first */ ++ mc13892_reg_write(mc13892, 34, 0x00200000); ++ ++ if (imx_silicon_revision() < MX51_CHIP_REV_3_0) { ++ /* Set core voltage to 1.1V */ ++ mc13892_reg_read(mc13892, 24, &val); ++ val &= ~0x1f; ++ val |= 0x14; ++ mc13892_reg_write(mc13892, 24, val); ++ ++ /* Setup VCC (SW2) to 1.25 */ ++ mc13892_reg_read(mc13892, 25, &val); ++ val &= ~0x1f; ++ val |= 0x1a; ++ mc13892_reg_write(mc13892, 25, val); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.25 */ ++ mc13892_reg_read(mc13892, 26, &val); ++ val &= ~0x1f; ++ val |= 0x1a; ++ mc13892_reg_write(mc13892, 26, val); ++ udelay(50); ++ /* Raise the core frequency to 800MHz */ ++ writel(0x0, MX51_CCM_BASE_ADDR + MX51_CCM_CACRR); ++ } else { ++ /* Setup VCC (SW2) to 1.225 */ ++ mc13892_reg_read(mc13892, 25, &val); ++ val &= ~0x1f; ++ val |= 0x19; ++ mc13892_reg_write(mc13892, 25, val); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.2 */ ++ mc13892_reg_read(mc13892, 26, &val); ++ val &= ~0x1f; ++ val |= 0x18; ++ mc13892_reg_write(mc13892, 26, val); ++ } ++ ++ if (mc13892_get_revision(mc13892) < MC13892_REVISION_2_0) { ++ /* Set switchers in PWM mode for Atlas 2.0 and lower */ ++ /* Setup the switcher mode for SW1 & SW2*/ ++ mc13892_reg_read(mc13892, 28, &val); ++ val &= ~0x3c0f; ++ val |= 0x1405; ++ mc13892_reg_write(mc13892, 28, val); ++ ++ /* Setup the switcher mode for SW3 & SW4 */ ++ mc13892_reg_read(mc13892, 29, &val); ++ val &= ~0xf0f; ++ val |= 0x505; ++ mc13892_reg_write(mc13892, 29, val); ++ } else { ++ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ ++ /* Setup the switcher mode for SW1 & SW2*/ ++ mc13892_reg_read(mc13892, 28, &val); ++ val &= ~0x3c0f; ++ val |= 0x2008; ++ mc13892_reg_write(mc13892, 28, val); ++ ++ /* Setup the switcher mode for SW3 & SW4 */ ++ mc13892_reg_read(mc13892, 29, &val); ++ val &= ~0xf0f; ++ val |= 0x808; ++ mc13892_reg_write(mc13892, 29, val); ++ } ++ ++ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ ++ mc13892_reg_read(mc13892, 30, &val); ++ val &= ~0x34030; ++ val |= 0x10020; ++ mc13892_reg_write(mc13892, 30, val); ++ ++ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ ++ mc13892_reg_read(mc13892, 31, &val); ++ val &= ~0x1FC; ++ val |= 0x1F4; ++ mc13892_reg_write(mc13892, 31, val); ++ ++ /* Configure VGEN3 and VCAM regulators to use external PNP */ ++ val = 0x208; ++ mc13892_reg_write(mc13892, 33, val); ++ udelay(200); ++#define GPIO_LAN8700_RESET (1 * 32 + 14) ++ ++ /* Reset the ethernet controller over GPIO */ ++ gpio_direction_output(GPIO_LAN8700_RESET, 0); ++ ++ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ ++ val = 0x49249; ++ mc13892_reg_write(mc13892, 33, val); ++ ++ udelay(500); ++ ++ gpio_set_value(GPIO_LAN8700_RESET, 1); ++} ++ ++static int f3s_devices_init(void) ++{ ++ babbage_mmu_init(); ++ ++ register_device(&sdram_dev); ++ imx51_add_fec(&fec_info); ++ imx51_add_mmc0(NULL); ++ ++ spi_register_board_info(mx51_babbage_spi_board_info, ++ ARRAY_SIZE(mx51_babbage_spi_board_info)); ++ imx51_add_spi0(&spi_0_data); ++ ++ babbage_power_init(); ++ ++ armlinux_add_dram(&sdram_dev); ++ armlinux_set_bootparams((void *)0x90000100); ++ armlinux_set_architecture(MACH_TYPE_MX51_BABBAGE); ++ ++ return 0; ++} ++ ++device_initcall(f3s_devices_init); ++ ++static int f3s_part_init(void) ++{ ++ devfs_add_partition("disk0", 0x00000, 0x40000, PARTITION_FIXED, "self0"); ++ devfs_add_partition("disk0", 0x40000, 0x20000, PARTITION_FIXED, "env0"); ++ ++ return 0; ++} ++late_initcall(f3s_part_init); ++ ++static int f3s_console_init(void) ++{ ++ mxc_iomux_v3_setup_multiple_pads(f3s_pads, ARRAY_SIZE(f3s_pads)); ++ ++ writel(0, 0x73fa8228); ++ writel(0, 0x73fa822c); ++ writel(0, 0x73fa8230); ++ writel(0, 0x73fa8234); ++ ++ imx51_add_uart0(); ++ return 0; ++} ++ ++console_initcall(f3s_console_init); ++ +diff --git a/arch/arm/boards/freescale-mx51-pdk/config.h b/arch/arm/boards/freescale-mx51-pdk/config.h +new file mode 100644 +index 0000000..b7effe5 +--- /dev/null ++++ b/arch/arm/boards/freescale-mx51-pdk/config.h +@@ -0,0 +1,24 @@ ++/** ++ * @file ++ * @brief Global defintions for the ARM i.MX51 based babbage board ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#endif /* __CONFIG_H */ +diff --git a/arch/arm/boards/freescale-mx51-pdk/env/config b/arch/arm/boards/freescale-mx51-pdk/env/config +new file mode 100644 +index 0000000..d9b8407 +--- /dev/null ++++ b/arch/arm/boards/freescale-mx51-pdk/env/config +@@ -0,0 +1,52 @@ ++#!/bin/sh ++ ++machine=babbage ++eth0.serverip= ++user= ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration ++ip=dhcp ++ ++# or set your networking parameters here ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'net', 'nor' or 'nand' ++kernel_loc=net ++# can be either 'net', 'nor', 'nand' or 'initrd' ++rootfs_loc=net ++ ++# can be either 'jffs2' or 'ubifs' ++rootfs_type=ubifs ++rootfsimage=root-$machine.$rootfs_type ++ ++# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo ++kernelimage_type=zimage ++kernelimage=zImage-$machine ++#kernelimage_type=uimage ++#kernelimage=uImage-$machine ++#kernelimage_type=raw ++#kernelimage=Image-$machine ++#kernelimage_type=raw_lzo ++#kernelimage=Image-$machine.lzo ++ ++if [ -n $user ]; then ++ kernelimage="$user"-"$kernelimage" ++ nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine" ++ rootfsimage="$user"-"$rootfsimage" ++else ++ nfsroot="$eth0.serverip:/path/to/nfs/root" ++fi ++ ++autoboot_timeout=3 ++ ++bootargs="console=ttymxc0,115200" ++ ++disk_parts="256k(barebox)ro,128k(bareboxenv),4M(kernel),-(root)" ++ ++# set a fancy prompt (if support is compiled in) ++PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " ++ +diff --git a/arch/arm/boards/freescale-mx51-pdk/flash_header.c b/arch/arm/boards/freescale-mx51-pdk/flash_header.c +new file mode 100644 +index 0000000..5f94506 +--- /dev/null ++++ b/arch/arm/boards/freescale-mx51-pdk/flash_header.c +@@ -0,0 +1,85 @@ ++#include <common.h> ++#include <mach/imx-flash-header.h> ++ ++extern unsigned long _stext; ++ ++void __naked __flash_header_start go(void) ++{ ++ __asm__ __volatile__("b exception_vectors\n"); ++} ++ ++struct imx_dcd_entry __dcd_entry_section dcd_entry[] = { ++ { .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, }, ++ { .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, }, ++ { .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, }, ++ { .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, }, ++ { .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, }, ++ { .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, }, ++ { .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, }, ++ { .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, }, ++ { .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, }, ++ { .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, }, ++ { .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, }, ++ { .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, }, ++ { .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, }, ++ { .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, }, ++ { .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, }, ++ { .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, }, ++ { .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, }, ++ { .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, }, ++ { .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, }, ++ { .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, }, ++ { .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, }, ++ { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, }, ++ { .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, }, ++ { .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, }, ++ { .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, }, ++ { .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, }, ++ { .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, }, ++ { .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, }, ++ { .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, }, ++}; ++ ++#define APP_DEST 0x90000000 ++ ++struct imx_flash_header __flash_header_section flash_header = { ++ .app_code_jump_vector = APP_DEST + 0x1000, ++ .app_code_barker = APP_CODE_BARKER, ++ .app_code_csf = 0, ++ .dcd_ptr_ptr = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd), ++ .super_root_key = 0, ++ .dcd = APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker), ++ .app_dest = APP_DEST, ++ .dcd_barker = DCD_BARKER, ++ .dcd_block_len = sizeof (dcd_entry), ++}; ++ ++unsigned long __image_len_section barebox_len = 0x40000; ++ +diff --git a/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S b/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S +new file mode 100644 +index 0000000..793104c +--- /dev/null ++++ b/arch/arm/boards/freescale-mx51-pdk/lowlevel_init.S +@@ -0,0 +1,216 @@ ++/* ++ * This code is based on the ecos babbage startup code ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <config.h> ++#include <mach/imx-regs.h> ++#include <mach/clock-imx51.h> ++ ++#define ROM_SI_REV_OFFSET 0x48 ++ ++.macro setup_pll pll, freq ++ ldr r2, =\pll ++ ldr r1, =0x00001232 ++ str r1, [r2, #MX51_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ ++ mov r1, #0x2 ++ str r1, [r2, #MX51_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ ++ ++ str r3, [r2, #MX51_PLL_DP_OP] ++ str r3, [r2, #MX51_PLL_DP_HFS_OP] ++ ++ str r4, [r2, #MX51_PLL_DP_MFD] ++ str r4, [r2, #MX51_PLL_DP_HFS_MFD] ++ ++ str r5, [r2, #MX51_PLL_DP_MFN] ++ str r5, [r2, #MX51_PLL_DP_HFS_MFN] ++ ++ ldr r1, =0x00001232 ++ str r1, [r2, #MX51_PLL_DP_CTL] ++1: ldr r1, [r2, #MX51_PLL_DP_CTL] ++ ands r1, r1, #0x1 ++ beq 1b ++.endm ++ ++#define writel(val, reg) \ ++ ldr r0, =reg; \ ++ ldr r1, =val; \ ++ str r1, [r0]; ++ ++#define IMX51_TO_2 ++ ++.globl board_init_lowlevel ++board_init_lowlevel: ++ mov r10, lr ++ ++ /* explicitly disable L2 cache */ ++ mrc 15, 0, r0, c1, c0, 1 ++ bic r0, r0, #0x2 ++ mcr 15, 0, r0, c1, c0, 1 ++ ++ /* reconfigure L2 cache aux control reg */ ++ mov r0, #0xC0 /* tag RAM */ ++ add r0, r0, #0x4 /* data RAM */ ++ orr r0, r0, #(1 << 24) /* disable write allocate delay */ ++ orr r0, r0, #(1 << 23) /* disable write allocate combine */ ++ orr r0, r0, #(1 << 22) /* disable write allocate */ ++ ++ ldr r1, =MX51_IROM_BASE_ADDR ++ ldr r3, [r1, #ROM_SI_REV_OFFSET] ++ cmp r3, #0x10 ++ orrls r0, r0, #(1 << 25) /* disable write combine for TO 2 and lower revs */ ++ ++ mcr 15, 1, r0, c9, c0, 2 ++ ++ ldr r0, =MX51_CCM_BASE_ADDR ++ ++ /* Gate of clocks to the peripherals first */ ++ ldr r1, =0x3FFFFFFF ++ str r1, [r0, #MX51_CCM_CCGR0] ++ ldr r1, =0x0 ++ str r1, [r0, #MX51_CCM_CCGR1] ++ str r1, [r0, #MX51_CCM_CCGR2] ++ str r1, [r0, #MX51_CCM_CCGR3] ++ ++ ldr r1, =0x00030000 ++ str r1, [r0, #MX51_CCM_CCGR4] ++ ldr r1, =0x00FFF030 ++ str r1, [r0, #MX51_CCM_CCGR5] ++ ldr r1, =0x00000300 ++ str r1, [r0, #MX51_CCM_CCGR6] ++ ++ /* Disable IPU and HSC dividers */ ++ mov r1, #0x60000 ++ str r1, [r0, #MX51_CCM_CCDR] ++ ++#ifdef IMX51_TO_2 ++ /* Make sure to switch the DDR away from PLL 1 */ ++ ldr r1, =0x19239145 ++ str r1, [r0, #MX51_CCM_CBCDR] ++ /* make sure divider effective */ ++1: ldr r1, [r0, #MX51_CCM_CDHIPR] ++ cmp r1, #0x0 ++ bne 1b ++#endif ++ ++ /* Switch ARM to step clock */ ++ mov r1, #0x4 ++ str r1, [r0, #MX51_CCM_CCSR] ++ ++ mov r3, #MX51_PLL_DP_OP_800 ++ mov r4, #MX51_PLL_DP_MFD_800 ++ mov r5, #MX51_PLL_DP_MFN_800 ++ setup_pll MX51_PLL1_BASE_ADDR ++ ++ mov r3, #MX51_PLL_DP_OP_665 ++ mov r4, #MX51_PLL_DP_MFD_665 ++ mov r5, #MX51_PLL_DP_MFN_665 ++ setup_pll MX51_PLL3_BASE_ADDR ++ ++ /* Switch peripheral to PLL 3 */ ++ ldr r1, =0x000010C0 ++ str r1, [r0, #MX51_CCM_CBCMR] ++ ldr r1, =0x13239145 ++ str r1, [r0, #MX51_CCM_CBCDR] ++ ++ mov r3, #MX51_PLL_DP_OP_665 ++ mov r4, #MX51_PLL_DP_MFD_665 ++ mov r5, #MX51_PLL_DP_MFN_665 ++ setup_pll MX51_PLL2_BASE_ADDR ++ ++ /* Switch peripheral to PLL2 */ ++ ldr r1, =0x19239145 ++ str r1, [r0, #MX51_CCM_CBCDR] ++ ldr r1, =0x000020C0 ++ str r1, [r0, #MX51_CCM_CBCMR] ++ ++ mov r3, #MX51_PLL_DP_OP_216 ++ mov r4, #MX51_PLL_DP_MFD_216 ++ mov r5, #MX51_PLL_DP_MFN_216 ++ setup_pll MX51_PLL3_BASE_ADDR ++ ++ /* Set the platform clock dividers */ ++ ldr r2, =MX51_ARM_BASE_ADDR ++ ldr r1, =0x00000124 ++ str r1, [r2, #0x14] ++ ++ /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ++ ldr r1, =MX51_IROM_BASE_ADDR ++ ldr r3, [r1, #ROM_SI_REV_OFFSET] ++ cmp r3, #0x10 ++ movls r1, #0x1 ++ movhi r1, #0 ++ str r1, [r0, #MX51_CCM_CACRR] ++ ++ /* Switch ARM back to PLL 1 */ ++ mov r1, #0 ++ str r1, [r0, #MX51_CCM_CCSR] ++ ++ /* setup the rest */ ++ /* Use lp_apm (24MHz) source for perclk */ ++#ifdef IMX51_TO_2 ++ ldr r1, =0x000020C2 ++ str r1, [r0, #MX51_CCM_CBCMR] ++ // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz ++ ldr r1, =0x59239100 ++ str r1, [r0, #MX51_CCM_CBCDR] ++#else ++ ldr r1, =0x0000E3C2 ++ str r1, [r0, #MX51_CCM_CBCMR] ++ // emi=ahb, all perclk dividers are 1 since using 24MHz ++ // DDR divider=6 to have 665/6=110MHz ++ ldr r1, =0x013B9100 ++ str r1, [r0, #MX51_CCM_CBCDR] ++#endif ++ ++ /* Restore the default values in the Gate registers */ ++ ldr r1, =0xFFFFFFFF ++ str r1, [r0, #MX51_CCM_CCGR0] ++ str r1, [r0, #MX51_CCM_CCGR1] ++ str r1, [r0, #MX51_CCM_CCGR2] ++ str r1, [r0, #MX51_CCM_CCGR3] ++ str r1, [r0, #MX51_CCM_CCGR4] ++ str r1, [r0, #MX51_CCM_CCGR5] ++ str r1, [r0, #MX51_CCM_CCGR6] ++ ++ /* Use PLL 2 for UART's, get 66.5MHz from it */ ++ ldr r1, =0xA5A2A020 ++ str r1, [r0, #MX51_CCM_CSCMR1] ++ ldr r1, =0x00C30321 ++ str r1, [r0, #MX51_CCM_CSCDR1] ++ ++ /* make sure divider effective */ ++ 1: ldr r1, [r0, #MX51_CCM_CDHIPR] ++ cmp r1, #0x0 ++ bne 1b ++ ++ mov r1, #0x0 ++ str r1, [r0, #MX51_CCM_CCDR] ++ ++ writel(0x1, 0x73fa8074) ++ ldr r0, =0x73f88000 ++ ldr r1, [r0] ++ orr r1, #0x40 ++ str r1, [r0] ++ ++ ldr r0, =0x73f88004 ++ ldr r1, [r0] ++ orr r1, #0x40 ++ str r1, [r0] ++ ++ mov pc, r10 ++ +diff --git a/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox b/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox +new file mode 100644 +index 0000000..d9ea823 +--- /dev/null ++++ b/arch/arm/boards/freescale-mx51-pdk/mx51-pdk.dox +@@ -0,0 +1,4 @@ ++/** @page board_babage Freescale i.MX51 PDK (Babbage) Board ++ ++ ++*/ +diff --git a/arch/arm/boards/freescale-mx51-pdk/spi.c b/arch/arm/boards/freescale-mx51-pdk/spi.c +new file mode 100644 +index 0000000..8eabe81 +--- /dev/null ++++ b/arch/arm/boards/freescale-mx51-pdk/spi.c +@@ -0,0 +1,340 @@ ++#include <common.h> ++#include <init.h> ++#include <asm/io.h> ++#include <mach/imx-regs.h> ++#include <gpio.h> ++ ++#define IMX_SPI_ACTIVE_HIGH 1 ++#define SPI_RETRY_TIMES 100 ++#define CLKCTL_CACRR 0x10 ++#define REV_ATLAS_LITE_2_0 0x10 ++ ++/* Only for SPI master support */ ++struct imx_spi_dev { ++ unsigned int base; // base address of SPI module the device is connected to ++ unsigned int freq; // desired clock freq in Hz for this device ++ unsigned int ss_pol; // ss polarity: 1=active high; 0=active low ++ unsigned int ss; // slave select ++ unsigned int in_sctl; // inactive sclk ctl: 1=stay low; 0=stay high ++ unsigned int in_dctl; // inactive data ctl: 1=stay low; 0=stay high ++ unsigned int ssctl; // single burst mode vs multiple: 0=single; 1=multi ++ unsigned int sclkpol; // sclk polarity: active high=0; active low=1 ++ unsigned int sclkpha; // sclk phase: 0=phase 0; 1=phase1 ++ unsigned int fifo_sz; // fifo size in bytes for either tx or rx. Don't add them up! ++ unsigned int ctrl_reg; ++ unsigned int cfg_reg; ++}; ++ ++struct imx_spi_dev imx_spi_pmic = { ++ .base = MX51_CSPI1_BASE_ADDR, ++ .freq = 25000000, ++ .ss_pol = IMX_SPI_ACTIVE_HIGH, ++ .ss = 0, /* slave select 0 */ ++ .fifo_sz = 32, ++}; ++ ++/* ++ * Initialization function for a spi slave device. It must be called BEFORE ++ * any spi operations. The SPI module will be -disabled- after this call. ++ */ ++static int imx_spi_init(struct imx_spi_dev *dev) ++{ ++ unsigned int clk_src = 66500000; ++ unsigned int pre_div = 0, post_div = 0, i, reg_ctrl = 0, reg_config = 0; ++ ++ if (dev->freq == 0) { ++ printf("Error: desired clock is 0\n"); ++ return -1; ++ } ++ ++ /* control register setup */ ++ if (clk_src > dev->freq) { ++ pre_div = clk_src / dev->freq; ++ if (pre_div > 16) { ++ post_div = pre_div / 16; ++ pre_div = 15; ++ } ++ if (post_div != 0) { ++ for (i = 0; i < 16; i++) { ++ if ((1 << i) >= post_div) ++ break; ++ } ++ if (i == 16) { ++ printf ++ ("Error: no divider can meet the freq: %d\n", ++ dev->freq); ++ return -1; ++ } ++ post_div = i; ++ } ++ } ++ debug("pre_div = %d, post_div=%d\n", pre_div, post_div); ++ reg_ctrl |= pre_div << 12; ++ reg_ctrl |= post_div << 8; ++ reg_ctrl |= 1 << (dev->ss + 4); /* always set to master mode */ ++ ++ /* configuration register setup */ ++ reg_config |= dev->ss_pol << (dev->ss + 12); ++ reg_config |= dev->in_sctl << (dev->ss + 20); ++ reg_config |= dev->in_dctl << (dev->ss + 16); ++ reg_config |= dev->ssctl << (dev->ss + 8); ++ reg_config |= dev->sclkpol << (dev->ss + 4); ++ reg_config |= dev->sclkpha << (dev->ss + 0); ++ ++ debug("reg_ctrl = 0x%x\n", reg_ctrl); ++ /* reset the spi */ ++ writel(0, dev->base + 0x8); ++ writel(reg_ctrl, dev->base + 0x8); ++ debug("reg_config = 0x%x\n", reg_config); ++ writel(reg_config, dev->base + 0xC); ++ /* save control register */ ++ dev->cfg_reg = reg_config; ++ dev->ctrl_reg = reg_ctrl; ++ ++ /* clear interrupt reg */ ++ writel(0, dev->base + 0x10); ++ writel(3 << 6, dev->base + 0x18); ++ ++ return 0; ++} ++ ++static int imx_spi_xfer(struct imx_spi_dev *dev, /* spi device pointer */ ++ void *tx_buf, /* tx buffer (has to be 4-byte aligned) */ ++ void *rx_buf, /* rx buffer (has to be 4-byte aligned) */ ++ int burst_bits /* total number of bits in one burst (or xfer) */ ++ ) ++{ ++ int val = SPI_RETRY_TIMES; ++ unsigned int *p_buf; ++ unsigned int reg; ++ int len, ret_val = 0; ++ int burst_bytes = burst_bits / 8; ++ ++ /* Account for rounding of non-byte aligned burst sizes */ ++ if ((burst_bits % 8) != 0) ++ burst_bytes++; ++ ++ if (burst_bytes > dev->fifo_sz) { ++ printf("Error: maximum burst size is 0x%x bytes, asking 0x%x\n", ++ dev->fifo_sz, burst_bytes); ++ return -1; ++ } ++ ++ dev->ctrl_reg = (dev->ctrl_reg & ~0xFFF00000) | ((burst_bits - 1) << 20); ++ writel(dev->ctrl_reg | 0x1, dev->base + 0x8); ++ writel(dev->cfg_reg, dev->base + 0xC); ++ debug("ctrl_reg=0x%x, cfg_reg=0x%x\n", ++ readl(dev->base + 0x8), readl(dev->base + 0xC)); ++ ++ /* move data to the tx fifo */ ++ len = burst_bytes; ++ for (p_buf = tx_buf; len > 0; p_buf++, len -= 4) ++ writel(*p_buf, dev->base + 0x4); ++ ++ reg = readl(dev->base + 0x8); ++ reg |= (1 << 2); /* set xch bit */ ++ writel(reg, dev->base + 0x8); ++ ++ /* poll on the TC bit (transfer complete) */ ++ while ((val-- > 0) && (readl(dev->base + 0x18) & (1 << 7)) == 0); ++ ++ /* clear the TC bit */ ++ writel(3 << 6, dev->base + 0x18); ++ ++ if (val == 0) { ++ printf("Error: re-tried %d times without response. Give up\n", ++ SPI_RETRY_TIMES); ++ ret_val = -1; ++ goto error; ++ } ++ ++ /* move data in the rx buf */ ++ len = burst_bytes; ++ for (p_buf = rx_buf; len > 0; p_buf++, len -= 4) ++ *p_buf = readl(dev->base + 0x0); ++ ++error: ++ writel(0, dev->base + 0x8); ++ return ret_val; ++} ++ ++/* ++ * To read/write to a PMIC register. For write, it does another read for the ++ * actual register value. ++ * ++ * @param reg register number inside the PMIC ++ * @param val data to be written to the register; don't care for read ++ * @param write 0 for read; 1 for write ++ * ++ * @return the actual data in the PMIC register ++ */ ++static unsigned int ++pmic_reg(unsigned int reg, unsigned int val, unsigned int write) ++{ ++ static unsigned int pmic_tx, pmic_rx; ++ ++ if (reg > 63 || write > 1) { ++ printf("<reg num> = %d is invalid. Should be less then 63\n", ++ reg); ++ return 0; ++ } ++ pmic_tx = (write << 31) | (reg << 25) | (val & 0x00FFFFFF); ++ debug("reg=0x%x, val=0x%08x\n", reg, pmic_tx); ++ ++ imx_spi_xfer(&imx_spi_pmic, (unsigned char *) &pmic_tx, ++ (unsigned char *) &pmic_rx, (4 * 8)); ++ ++ if (write) { ++ pmic_tx &= ~(1 << 31); ++ imx_spi_xfer(&imx_spi_pmic, (unsigned char *) &pmic_tx, ++ (unsigned char *) &pmic_rx, (4 * 8)); ++ } ++ ++ return pmic_rx; ++} ++ ++static void show_pmic_info(void) ++{ ++ unsigned int rev_id; ++ char *rev; ++ ++ rev_id = pmic_reg(7, 0, 0); ++ ++ switch (rev_id & 0x1F) { ++ case 0x1: rev = "1.0"; break; ++ case 0x9: rev = "1.1"; break; ++ case 0xa: rev = "1.2"; break; ++ case 0x10: ++ if (((rev_id >> 9) & 0x3) == 0) ++ rev = "2.0"; ++ else ++ rev = "2.0a"; ++ break; ++ case 0x11: rev = "2.1"; break; ++ case 0x18: rev = "3.0"; break; ++ case 0x19: rev = "3.1"; break; ++ case 0x1a: rev = "3.2"; break; ++ case 0x2: rev = "3.2a"; break; ++ case 0x1b: rev = "3.3"; break; ++ case 0x1d: rev = "3.5"; break; ++ default: rev = "unknown"; break; ++ } ++ ++ printf("PMIC ID: 0x%08x [Rev: %s]\n", rev_id, rev); ++} ++ ++int babbage_power_init(void) ++{ ++ unsigned int val; ++ unsigned int reg; ++ ++ imx_spi_init(&imx_spi_pmic); ++ ++ show_pmic_info(); ++ ++ /* Write needed to Power Gate 2 register */ ++ val = pmic_reg(34, 0, 0); ++ val &= ~0x10000; ++ pmic_reg(34, val, 1); ++ ++ /* Write needed to update Charger 0 */ ++ pmic_reg(48, 0x0023807F, 1); ++ ++ /* power up the system first */ ++ pmic_reg(34, 0x00200000, 1); ++ ++ if (1) { ++ /* Set core voltage to 1.1V */ ++ val = pmic_reg(24, 0, 0); ++ val &= ~0x1f; ++ val |= 0x14; ++ pmic_reg(24, val, 1); ++ ++ /* Setup VCC (SW2) to 1.25 */ ++ val = pmic_reg(25, 0, 0); ++ val &= ~0x1f; ++ val |= 0x1a; ++ pmic_reg(25, val, 1); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.25 */ ++ val = pmic_reg(26, 0, 0); ++ val &= ~0x1f; ++ val |= 0x1a; ++ pmic_reg(26, val, 1); ++ udelay(50); ++ /* Raise the core frequency to 800MHz */ ++ writel(0x0, MX51_CCM_BASE_ADDR + CLKCTL_CACRR); ++ } else { ++ /* TO 3.0 */ ++ /* Setup VCC (SW2) to 1.225 */ ++ val = pmic_reg(25, 0, 0); ++ val &= ~0x1f; ++ val |= 0x19; ++ pmic_reg(25, val, 1); ++ ++ /* Setup 1V2_DIG1 (SW3) to 1.2 */ ++ val = pmic_reg(26, 0, 0); ++ val &= ~0x1f; ++ val |= 0x18; ++ pmic_reg(26, val, 1); ++ } ++ ++ if (((pmic_reg(7, 0, 0) & 0x1F) < REV_ATLAS_LITE_2_0) ++ || (((pmic_reg(7, 0, 0) >> 9) & 0x3) == 0)) { ++ /* Set switchers in PWM mode for Atlas 2.0 and lower */ ++ /* Setup the switcher mode for SW1 & SW2 */ ++ val = pmic_reg(28, 0, 0); ++ val &= ~0x3c0f; ++ val |= 0x1405; ++ pmic_reg(28, val, 1); ++ ++ /* Setup the switcher mode for SW3 & SW4 */ ++ val = pmic_reg(29, 0, 0); ++ val &= ~0xf0f; ++ val |= 0x505; ++ pmic_reg(29, val, 1); ++ } else { ++ /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */ ++ /* Setup the switcher mode for SW1 & SW2 */ ++ val = pmic_reg(28, 0, 0); ++ val &= ~0x3c0f; ++ val |= 0x2008; ++ pmic_reg(28, val, 1); ++ ++ /* Setup the switcher mode for SW3 & SW4 */ ++ val = pmic_reg(29, 0, 0); ++ val &= ~0xf0f; ++ val |= 0x808; ++ pmic_reg(29, val, 1); ++ } ++ ++ /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.5V */ ++ val = pmic_reg(30, 0, 0); ++ val &= ~0x34030; ++ val |= 0x10020; ++ pmic_reg(30, val, 1); ++ ++ /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ ++ val = pmic_reg(31, 0, 0); ++ val &= ~0x1FC; ++ val |= 0x1F4; ++ pmic_reg(31, val, 1); ++ ++ /* Configure VGEN3 and VCAM regulators to use external PNP */ ++ val = 0x208; ++ pmic_reg(33, val, 1); ++ udelay(200); ++ ++ gpio_direction_output(32 + 14, 0); /* Lower reset line */ ++ ++ /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ ++ val = 0x49249; ++ pmic_reg(33, val, 1); ++ ++ udelay(500); ++ ++ gpio_set_value(32 + 14, 1); ++ ++ return 0; ++} ++ +diff --git a/arch/arm/boards/guf-cupid/Makefile b/arch/arm/boards/guf-cupid/Makefile +new file mode 100644 +index 0000000..3a06cf4 +--- /dev/null ++++ b/arch/arm/boards/guf-cupid/Makefile +@@ -0,0 +1,24 @@ ++# ++# (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> ++# ++# See file CREDITS for list of people who contributed to this ++# project. ++# ++# This program is free software; you can redistribute it and/or ++# modify it under the terms of the GNU General Public License as ++# published by the Free Software Foundation; either version 2 of ++# the License, or (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++# MA 02111-1307 USA ++# ++ ++obj-y += lowlevel.o ++obj-y += board.o +diff --git a/arch/arm/boards/guf-cupid/board.c b/arch/arm/boards/guf-cupid/board.c +new file mode 100644 +index 0000000..6d7a99b +--- /dev/null ++++ b/arch/arm/boards/guf-cupid/board.c +@@ -0,0 +1,426 @@ ++/* ++ * (C) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> ++ * (C) 2009 Pengutronix, Juergen Beisert <kernel@pengutronix.de> ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Board support for the Garz+Fricke Cupid board ++ */ ++ ++#include <common.h> ++#include <command.h> ++#include <init.h> ++#include <driver.h> ++#include <environment.h> ++#include <fs.h> ++#include <mach/imx-regs.h> ++#include <asm/armlinux.h> ++#include <mach/gpio.h> ++#include <asm/io.h> ++#include <partition.h> ++#include <nand.h> ++#include <generated/mach-types.h> ++#include <mach/imx-nand.h> ++#include <fec.h> ++#include <fb.h> ++#include <asm/mmu.h> ++#include <mach/imx-ipu-fb.h> ++#include <mach/imx-pll.h> ++#include <mach/iomux-mx35.h> ++ ++static struct fec_platform_data fec_info = { ++ .xcv_type = MII100, ++}; ++ ++static struct device_d fec_dev = { ++ .id = -1, ++ .name = "fec_imx", ++ .map_base = IMX_FEC_BASE, ++ .platform_data = &fec_info, ++}; ++ ++static struct memory_platform_data ram_pdata = { ++ .name = "ram0", ++ .flags = DEVFS_RDWR, ++}; ++ ++static struct device_d sdram0_dev = { ++ .id = -1, ++ .name = "mem", ++ .map_base = IMX_SDRAM_CS0, ++ .size = 128 * 1024 * 1024, ++ .platform_data = &ram_pdata, ++}; ++ ++struct imx_nand_platform_data nand_info = { ++ .width = 1, ++ .hw_ecc = 1, ++ .flash_bbt = 1, ++}; ++ ++static struct device_d nand_dev = { ++ .id = -1, ++ .name = "imx_nand", ++ .map_base = IMX_NFC_BASE, ++ .platform_data = &nand_info, ++}; ++ ++static struct fb_videomode guf_cupid_fb_mode = { ++ /* 800x480 @ 70 Hz */ ++ .name = "CPT CLAA070LC0JCT", ++ .refresh = 70, ++ .xres = 800, ++ .yres = 480, ++ .pixclock = 30761, ++ .left_margin = 24, ++ .right_margin = 47, ++ .upper_margin = 5, ++ .lower_margin = 3, ++ .hsync_len = 24, ++ .vsync_len = 3, ++ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_CLK_INVERT | ++ FB_SYNC_OE_ACT_HIGH, ++ .vmode = FB_VMODE_NONINTERLACED, ++ .flag = 0, ++}; ++ ++#define GPIO_LCD_ENABLE (2 * 32 + 24) ++#define GPIO_LCD_BACKLIGHT (0 * 32 + 19) ++ ++static void cupid_fb_enable(int enable) ++{ ++ if (enable) { ++ gpio_direction_output(GPIO_LCD_ENABLE, 1); ++ mdelay(100); ++ gpio_direction_output(GPIO_LCD_BACKLIGHT, 1); ++ } else { ++ gpio_direction_output(GPIO_LCD_BACKLIGHT, 0); ++ mdelay(100); ++ gpio_direction_output(GPIO_LCD_ENABLE, 0); ++ } ++} ++ ++static struct imx_ipu_fb_platform_data ipu_fb_data = { ++ .mode = &guf_cupid_fb_mode, ++ .bpp = 16, ++ .enable = cupid_fb_enable, ++}; ++ ++static struct device_d imx_ipu_fb_dev = { ++ .id = -1, ++ .name = "imx-ipu-fb", ++ .map_base = 0x53fc0000, ++ .size = 0x1000, ++ .platform_data = &ipu_fb_data, ++}; ++ ++static struct device_d esdhc_dev = { ++ .name = "imx-esdhc", ++ .map_base = IMX_SDHC1_BASE, ++}; ++ ++#ifdef CONFIG_MMU ++static int cupid_mmu_init(void) ++{ ++ mmu_init(); ++ ++ arm_create_section(0x80000000, 0x80000000, 128, PMD_SECT_DEF_CACHED); ++ arm_create_section(0x90000000, 0x80000000, 128, PMD_SECT_DEF_UNCACHED); ++ ++ setup_dma_coherent(0x10000000); ++ ++#if TEXT_BASE & (0x100000 - 1) ++#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary ++#else ++ arm_create_section(0x0, TEXT_BASE, 1, PMD_SECT_DEF_UNCACHED); ++#endif ++ ++ mmu_enable(); ++ ++#ifdef CONFIG_CACHE_L2X0 ++ l2x0_init((void __iomem *)0x30000000, 0x00030024, 0x00000000); ++#endif ++ return 0; ++} ++postcore_initcall(cupid_mmu_init); ++#endif ++ ++static int cupid_devices_init(void) ++{ ++ uint32_t reg; ++ ++ gpio_direction_output(GPIO_LCD_ENABLE, 0); ++ gpio_direction_output(GPIO_LCD_BACKLIGHT, 0); ++ ++ reg = readl(IMX_CCM_BASE + CCM_RCSR); ++ /* some fuses provide us vital information about connected hardware */ ++ if (reg & 0x20000000) ++ nand_info.width = 2; /* 16 bit */ ++ else ++ nand_info.width = 1; /* 8 bit */ ++ ++ register_device(&fec_dev); ++ register_device(&nand_dev); ++ ++ devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); ++ dev_add_bb_dev("self_raw", "self0"); ++ devfs_add_partition("nand0", 0x40000, 0x80000, PARTITION_FIXED, "env_raw"); ++ dev_add_bb_dev("env_raw", "env0"); ++ ++ register_device(&sdram0_dev); ++ register_device(&imx_ipu_fb_dev); ++ register_device(&esdhc_dev); ++ ++ armlinux_add_dram(&sdram0_dev); ++ armlinux_set_bootparams((void *)0x80000100); ++ armlinux_set_architecture(MACH_TYPE_GUF_CUPID); ++ ++ return 0; ++} ++ ++device_initcall(cupid_devices_init); ++ ++static struct device_d cupid_serial_device = { ++ .id = -1, ++ .name = "imx_serial", ++ .map_base = IMX_UART1_BASE, ++ .size = 16 * 1024, ++}; ++ ++static struct pad_desc cupid_pads[] = { ++ /* UART1 */ ++ MX35_PAD_CTS1__UART1_CTS, ++ MX35_PAD_RTS1__UART1_RTS, ++ MX35_PAD_TXD1__UART1_TXD_MUX, ++ MX35_PAD_RXD1__UART1_RXD_MUX, ++ /* UART2 */ ++ MX35_PAD_CTS2__UART2_CTS, ++ MX35_PAD_RTS2__UART2_RTS, ++ MX35_PAD_TXD2__UART2_TXD_MUX, ++ MX35_PAD_RXD2__UART2_RXD_MUX, ++ /* FEC */ ++ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, ++ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, ++ MX35_PAD_FEC_RX_DV__FEC_RX_DV, ++ MX35_PAD_FEC_COL__FEC_COL, ++ MX35_PAD_FEC_RDATA0__FEC_RDATA_0, ++ MX35_PAD_FEC_TDATA0__FEC_TDATA_0, ++ MX35_PAD_FEC_TX_EN__FEC_TX_EN, ++ MX35_PAD_FEC_MDC__FEC_MDC, ++ MX35_PAD_FEC_MDIO__FEC_MDIO, ++ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, ++ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, ++ MX35_PAD_FEC_CRS__FEC_CRS, ++ MX35_PAD_FEC_RDATA1__FEC_RDATA_1, ++ MX35_PAD_FEC_TDATA1__FEC_TDATA_1, ++ MX35_PAD_FEC_RDATA2__FEC_RDATA_2, ++ MX35_PAD_FEC_TDATA2__FEC_TDATA_2, ++ MX35_PAD_FEC_RDATA3__FEC_RDATA_3, ++ MX35_PAD_FEC_TDATA3__FEC_TDATA_3, ++ /* I2C1 */ ++ MX35_PAD_I2C1_CLK__I2C1_SCL, ++ MX35_PAD_I2C1_DAT__I2C1_SDA, ++ /* Display */ ++ MX35_PAD_LD0__IPU_DISPB_DAT_0, ++ MX35_PAD_LD1__IPU_DISPB_DAT_1, ++ MX35_PAD_LD2__IPU_DISPB_DAT_2, ++ MX35_PAD_LD3__IPU_DISPB_DAT_3, ++ MX35_PAD_LD4__IPU_DISPB_DAT_4, ++ MX35_PAD_LD5__IPU_DISPB_DAT_5, ++ MX35_PAD_LD6__IPU_DISPB_DAT_6, ++ MX35_PAD_LD7__IPU_DISPB_DAT_7, ++ MX35_PAD_LD8__IPU_DISPB_DAT_8, ++ MX35_PAD_LD9__IPU_DISPB_DAT_9, ++ MX35_PAD_LD10__IPU_DISPB_DAT_10, ++ MX35_PAD_LD11__IPU_DISPB_DAT_11, ++ MX35_PAD_LD12__IPU_DISPB_DAT_12, ++ MX35_PAD_LD13__IPU_DISPB_DAT_13, ++ MX35_PAD_LD14__IPU_DISPB_DAT_14, ++ MX35_PAD_LD15__IPU_DISPB_DAT_15, ++ MX35_PAD_LD16__IPU_DISPB_DAT_16, ++ MX35_PAD_LD17__IPU_DISPB_DAT_17, ++ MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, ++ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, ++ MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, ++ MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, ++ MX35_PAD_LD18__GPIO3_24, /* LCD enable */ ++ MX35_PAD_CSPI1_SS1__GPIO1_19, /* LCD backligtht PWM */ ++ /* USB Host*/ ++ MX35_PAD_MLB_CLK__GPIO3_3, /* USB Host PWR */ ++ MX35_PAD_MLB_DAT__GPIO3_4, /* USB Host Overcurrent */ ++ /* USB OTG */ ++ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR, ++ MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC, ++ /* SSI */ ++ MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, ++ MX35_PAD_STXD4__AUDMUX_AUD4_TXD, ++ MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, ++ MX35_PAD_SCK4__AUDMUX_AUD4_TXC, ++ /* UCB1400 IRQ */ ++ MX35_PAD_ATA_INTRQ__GPIO2_29, ++ /* Speaker On */ ++ MX35_PAD_LD20__GPIO3_26, ++ /* LEDs */ ++ MX35_PAD_TX1__GPIO1_14, ++ /* ESDHC1 */ ++ MX35_PAD_SD1_CMD__ESDHC1_CMD, ++ MX35_PAD_SD1_CLK__ESDHC1_CLK, ++ MX35_PAD_SD1_DATA0__ESDHC1_DAT0, ++ MX35_PAD_SD1_DATA1__ESDHC1_DAT1, ++ MX35_PAD_SD1_DATA2__ESDHC1_DAT2, ++ MX35_PAD_SD1_DATA3__ESDHC1_DAT3, ++ /* ESDHC1 CD */ ++ MX35_PAD_ATA_DATA5__GPIO2_18, ++ /* ESDHC1 WP */ ++ MX35_PAD_ATA_DATA6__GPIO2_19, ++}; ++ ++static int cupid_console_init(void) ++{ ++ mxc_iomux_v3_setup_multiple_pads(cupid_pads, ARRAY_SIZE(cupid_pads)); ++ ++ register_device(&cupid_serial_device); ++ return 0; ++} ++ ++console_initcall(cupid_console_init); ++ ++static int cupid_core_setup(void) ++{ ++ u32 tmp; ++ ++ /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ ++ /* ++ * Set all MPROTx to be non-bufferable, trusted for R/W, ++ * not forced to user-mode. ++ */ ++ writel(0x77777777, IMX_AIPS1_BASE); ++ writel(0x77777777, IMX_AIPS1_BASE + 0x4); ++ writel(0x77777777, IMX_AIPS2_BASE); ++ writel(0x77777777, IMX_AIPS2_BASE + 0x4); ++ ++ /* ++ * Clear the on and off peripheral modules Supervisor Protect bit ++ * for SDMA to access them. Did not change the AIPS control registers ++ * (offset 0x20) access type ++ */ ++ writel(0x0, IMX_AIPS1_BASE + 0x40); ++ writel(0x0, IMX_AIPS1_BASE + 0x44); ++ writel(0x0, IMX_AIPS1_BASE + 0x48); ++ writel(0x0, IMX_AIPS1_BASE + 0x4C); ++ tmp = readl(IMX_AIPS1_BASE + 0x50); ++ tmp &= 0x00FFFFFF; ++ writel(tmp, IMX_AIPS1_BASE + 0x50); ++ ++ writel(0x0, IMX_AIPS2_BASE + 0x40); ++ writel(0x0, IMX_AIPS2_BASE + 0x44); ++ writel(0x0, IMX_AIPS2_BASE + 0x48); ++ writel(0x0, IMX_AIPS2_BASE + 0x4C); ++ tmp = readl(IMX_AIPS2_BASE + 0x50); ++ tmp &= 0x00FFFFFF; ++ writel(tmp, IMX_AIPS2_BASE + 0x50); ++ ++ /* MAX (Multi-Layer AHB Crossbar Switch) setup */ ++ ++ /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ ++#define MAX_PARAM1 0x00302154 ++ writel(MAX_PARAM1, IMX_MAX_BASE + 0x0); /* for S0 */ ++ writel(MAX_PARAM1, IMX_MAX_BASE + 0x100); /* for S1 */ ++ writel(MAX_PARAM1, IMX_MAX_BASE + 0x200); /* for S2 */ ++ writel(MAX_PARAM1, IMX_MAX_BASE + 0x300); /* for S3 */ ++ writel(MAX_PARAM1, IMX_MAX_BASE + 0x400); /* for S4 */ ++ ++ /* SGPCR - always park on last master */ ++ writel(0x10, IMX_MAX_BASE + 0x10); /* for S0 */ ++ writel(0x10, IMX_MAX_BASE + 0x110); /* for S1 */ ++ writel(0x10, IMX_MAX_BASE + 0x210); /* for S2 */ ++ writel(0x10, IMX_MAX_BASE + 0x310); /* for S3 */ ++ writel(0x10, IMX_MAX_BASE + 0x410); /* for S4 */ ++ ++ /* MGPCR - restore default values */ ++ writel(0x0, IMX_MAX_BASE + 0x800); /* for M0 */ ++ writel(0x0, IMX_MAX_BASE + 0x900); /* for M1 */ ++ writel(0x0, IMX_MAX_BASE + 0xa00); /* for M2 */ ++ writel(0x0, IMX_MAX_BASE + 0xb00); /* for M3 */ ++ writel(0x0, IMX_MAX_BASE + 0xc00); /* for M4 */ ++ writel(0x0, IMX_MAX_BASE + 0xd00); /* for M5 */ ++ ++ writel(0x0000DCF6, CSCR_U(0)); /* CS0: NOR Flash */ ++ writel(0x444A4541, CSCR_L(0)); ++ writel(0x44443302, CSCR_A(0)); ++ ++ /* ++ * M3IF Control Register (M3IFCTL) ++ * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 ++ * MRRP[1] = MAX1 not on priority list (0 << 0) = 0x00000000 ++ * MRRP[2] = L2CC1 not on priority list (0 << 0) = 0x00000000 ++ * MRRP[3] = USB not on priority list (0 << 0) = 0x00000000 ++ * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 ++ * MRRP[5] = GPU not on priority list (0 << 0) = 0x00000000 ++ * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 ++ * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 ++ * ------------ ++ * 0x00000040 ++ */ ++ writel(0x40, IMX_M3IF_BASE); ++ ++ return 0; ++} ++ ++core_initcall(cupid_core_setup); ++ ++#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) ++#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) ++ ++static int do_cpufreq(struct command *cmdtp, int argc, char *argv[]) ++{ ++ unsigned long freq; ++ ++ if (argc != 2) ++ return COMMAND_ERROR_USAGE; ++ ++ freq = simple_strtoul(argv[1], NULL, 0); ++ ++ switch (freq) { ++ case 399: ++ writel(MPCTL_PARAM_399, IMX_CCM_BASE + CCM_MPCTL); ++ break; ++ case 532: ++ writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); ++ break; ++ default: ++ return COMMAND_ERROR_USAGE; ++ } ++ ++ printf("Switched CPU frequency to %dMHz\n", freq); ++ ++ return 0; ++} ++ ++static const __maybe_unused char cmd_cpufreq_help[] = ++"Usage: cpufreq 399|532\n" ++"\n" ++"Set CPU frequency to <freq> MHz\n"; ++ ++BAREBOX_CMD_START(cpufreq) ++ .cmd = do_cpufreq, ++ .usage = "adjust CPU frequency", ++ BAREBOX_CMD_HELP(cmd_cpufreq_help) ++BAREBOX_CMD_END ++ +diff --git a/arch/arm/boards/guf-cupid/config.h b/arch/arm/boards/guf-cupid/config.h +new file mode 100644 +index 0000000..0e3b175 +--- /dev/null ++++ b/arch/arm/boards/guf-cupid/config.h +@@ -0,0 +1,31 @@ ++/* ++ * (C) Copyright 2007 Juergen Beisert <jbe@pengutronix.de> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/* ++ * Definitions related to passing arguments to kernel. ++ */ ++ ++#define CONFIG_MX35_HCLK_FREQ 24000000 ++ ++#endif ++ ++/* nothing to do here yet */ +diff --git a/arch/arm/boards/guf-cupid/cupid.dox b/arch/arm/boards/guf-cupid/cupid.dox +new file mode 100644 +index 0000000..45f0e0c +--- /dev/null ++++ b/arch/arm/boards/guf-cupid/cupid.dox +@@ -0,0 +1,9 @@ ++/** @page board_cupid Garz+Fricke Cupid ++ ++This CPU card is based on a Freescale i.MX35 CPU. The card is shipped with: ++ ++- 256MiB Nand flash ++- 128MiB synchronous dynamic RAM ++ ++ ++*/ +diff --git a/arch/arm/boards/guf-cupid/env/config b/arch/arm/boards/guf-cupid/env/config +new file mode 100644 +index 0000000..4db05b6 +--- /dev/null ++++ b/arch/arm/boards/guf-cupid/env/config +@@ -0,0 +1,56 @@ ++#!/bin/sh ++ ++machine=cupid ++eth0.serverip= ++user= ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration ++ip=dhcp ++ ++# or set your networking parameters here ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'net', 'nor' or 'nand' ++kernel_loc=net ++# can be either 'net', 'nor', 'nand' or 'initrd' ++rootfs_loc=net ++ ++# can be either 'jffs2' or 'ubifs' ++rootfs_type=ubifs ++rootfsimage=root-$machine.$rootfs_type ++ ++# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo ++kernelimage_type=zimage ++kernelimage=zImage-$machine ++#kernelimage_type=uimage ++#kernelimage=uImage-$machine ++#kernelimage_type=raw ++#kernelimage=Image-$machine ++#kernelimage_type=raw_lzo ++#kernelimage=Image-$machine.lzo ++ ++if [ -n $user ]; then ++ kernelimage="$user"-"$kernelimage" ++ nfsroot="$eth0.serverip:/home/$user/nfsroot/$machine" ++ rootfsimage="$user"-"$rootfsimage" ++else ++ nfsroot="$eth0.serverip:/path/to/nfs/root" ++fi ++ ++autoboot_timeout=3 ++ ++bootargs="console=ttymxc0,115200" ++ ++bootargs="$bootargs video=mx3fb:CTP-CLAA070LC0ACW" ++ ++nand_parts="256k(barebox)ro,512k(bareboxenv),2M(kernel),-(root)" ++nand_device=mxc_nand ++rootfs_mtdblock_nand=3 ++ ++# set a fancy prompt (if support is compiled in) ++PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " ++ +diff --git a/arch/arm/boards/guf-cupid/lowlevel.c b/arch/arm/boards/guf-cupid/lowlevel.c +new file mode 100644 +index 0000000..8d403ee +--- /dev/null ++++ b/arch/arm/boards/guf-cupid/lowlevel.c +@@ -0,0 +1,349 @@ ++/* ++ * ++ * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++#include <common.h> ++#include <init.h> ++#include <mach/imx-regs.h> ++#include <mach/imx-pll.h> ++#include <mach/esdctl.h> ++#include <asm/cache-l2x0.h> ++#include <asm/io.h> ++#include <mach/imx-nand.h> ++#include <asm/barebox-arm.h> ++#include <asm-generic/memory_layout.h> ++#include <asm/system.h> ++ ++/* Assuming 24MHz input clock */ ++#define MPCTL_PARAM_399 (IMX_PLL_PD(0) | IMX_PLL_MFD(15) | IMX_PLL_MFI(8) | IMX_PLL_MFN(5)) ++#define MPCTL_PARAM_532 ((1 << 31) | IMX_PLL_PD(0) | IMX_PLL_MFD(11) | IMX_PLL_MFI(11) | IMX_PLL_MFN(1)) ++#define PPCTL_PARAM_300 (IMX_PLL_PD(0) | IMX_PLL_MFD(3) | IMX_PLL_MFI(6) | IMX_PLL_MFN(1)) ++ ++#define SDRAM_MODE_BL_8 0x0003 ++#define SDRAM_MODE_BSEQ 0x0000 ++#define SDRAM_MODE_CL_3 0x0030 ++#define MDDR_DS_HALF 0x20 ++#define SDRAM_COMPARE_CONST1 0x55555555 ++#define SDRAM_COMPARE_CONST2 0xaaaaaaaa ++ ++#ifdef CONFIG_NAND_IMX_BOOT ++static void __bare_init __naked insdram(void) ++{ ++ uint32_t r; ++ ++ /* Speed up NAND controller by adjusting the NFC divider */ ++ r = readl(IMX_CCM_BASE + CCM_PDR4); ++ r &= ~(0xf << 28); ++ r |= 0x1 << 28; ++ writel(r, IMX_CCM_BASE + CCM_PDR4); ++ ++ /* setup a stack to be able to call imx_nand_load_image() */ ++ r = STACK_BASE + STACK_SIZE - 12; ++ __asm__ __volatile__("mov sp, %0" : : "r"(r)); ++ ++ imx_nand_load_image((void *)TEXT_BASE, 256 * 1024); ++ ++ board_init_lowlevel_return(); ++} ++#endif ++ ++static void __bare_init noinline setup_sdram(u32 memsize, u32 mode, u32 sdram_addr) ++{ ++ volatile int loop; ++ void *r9 = (void *)IMX_SDRAM_CS0; ++ u32 r11 = 0xda; /* dummy constant */ ++ u32 r1, r0; ++ ++ /* disable second SDRAM region to save power */ ++ r1 = readl(ESDCTL1); ++ r1 &= ~ESDCTL0_SDE; ++ writel(r1, ESDCTL1); ++ ++ mode |= ESDMISC_RST | ESDMISC_MDDR_DL_RST; ++ writel(mode, ESDMISC); ++ ++ mode &= ~(ESDMISC_RST | ESDMISC_MDDR_DL_RST); ++ writel(mode, ESDMISC); ++ ++ /* wait for esdctl reset */ ++ for (loop = 0; loop < 0x20000; loop++); ++ ++ r1 = ESDCFGx_tXP_4 | ESDCFGx_tWTR_1 | ++ ESDCFGx_tRP_3 | ESDCFGx_tMRD_2 | ++ ESDCFGx_tWR_1_2 | ESDCFGx_tRAS_6 | ++ ESDCFGx_tRRD_2 | ESDCFGx_tCAS_3 | ++ ESDCFGx_tRCD_3 | ESDCFGx_tRC_20; ++ ++ writel(r1, ESDCFG0); ++ ++ /* enable SDRAM controller */ ++ writel(memsize | ESDCTL0_SMODE_NORMAL, ESDCTL0); ++ ++ /* Micron Datasheet Initialization Step 3: Wait 200us before first command */ ++ for (loop = 0; loop < 1000; loop++); ++ ++ /* Micron Datasheet Initialization Step 4: PRE CHARGE ALL */ ++ writel(memsize | ESDCTL0_SMODE_PRECHARGE, ESDCTL0); ++ writeb(r11, sdram_addr); ++ ++ /* Micron Datasheet Initialization Step 5: NOP for tRP (at least 22.5ns) ++ * The CPU is not fast enough to cause a problem here ++ */ ++ ++ /* Micron Datasheet Initialization Step 6: 2 AUTO REFRESH and tRFC NOP ++ * (at least 140ns) ++ */ ++ writel(memsize | ESDCTL0_SMODE_AUTO_REFRESH, ESDCTL0); ++ writeb(r11, r9); /* AUTO REFRESH #1 */ ++ ++ for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */ ++ ++ writeb(r11, r9); /* AUTO REFRESH #2 */ ++ ++ for (loop = 0; loop < 3; loop++); /* ~140ns delay at 532MHz */ ++ ++ /* Micron Datasheet Initialization Step 7: LOAD MODE REGISTER */ ++ writel(memsize | ESDCTL0_SMODE_LOAD_MODE, ESDCTL0); ++ writeb(r11, r9 + (SDRAM_MODE_BL_8 | SDRAM_MODE_BSEQ | SDRAM_MODE_CL_3)); ++ ++ /* Micron Datasheet Initialization Step 8: tMRD = 2 tCK NOP ++ * (The memory controller will take care of this delay) ++ */ ++ ++ /* Micron Datasheet Initialization Step 9: LOAD MODE REGISTER EXTENDED */ ++ writeb(r11, 0x84000000 | MDDR_DS_HALF); /*we assume 14 Rows / 10 Cols here */ ++ ++ /* Micron Datasheet Initialization Step 9: tMRD = 2 tCK NOP ++ * (The memory controller will take care of this delay) ++ */ ++ ++ /* Now configure SDRAM-Controller and check that it works */ ++ writel(memsize | ESDCTL0_BL | ESDCTL0_REF4, ESDCTL0); ++ ++ /* Freescale asks for first access to be a write to properly ++ * initialize DQS pin-state and keepers ++ */ ++ writel(0xdeadbeef, r9); ++ ++ /* test that the RAM is in fact working */ ++ writel(SDRAM_COMPARE_CONST1, r9); ++ writel(SDRAM_COMPARE_CONST2, r9 + 0x4); ++ ++ if (readl(r9) != SDRAM_COMPARE_CONST1) ++ while (1); ++ ++ /* Verify that the correct row and coloumn is selected */ ++ ++ /* So far we asssumed that we have 14 rows, verify this */ ++ writel(SDRAM_COMPARE_CONST1, r9); ++ writel(SDRAM_COMPARE_CONST2, r9 + (1 << 25)); ++ ++ /* if both value are identical, we don't have 14 rows. assume 13 instead */ ++ if (readl(r9) == readl(r9 + (1 << 25))) { ++ r0 = readl(ESDCTL0); ++ r0 &= ~ESDCTL0_ROW_MASK; ++ r0 |= ESDCTL0_ROW13; ++ writel(r0, ESDCTL0); ++ } ++ ++ /* So far we asssumed that we have 10 columns, verify this */ ++ writel(SDRAM_COMPARE_CONST1, r9); ++ writel(SDRAM_COMPARE_CONST2, r9 + (1 << 11)); ++ ++ /* if both value are identical, we don't have 10 cols. assume 9 instead */ ++ if (readl(r9) == readl(r9 + (1 << 11))) { ++ r0 = readl(ESDCTL0); ++ r0 &= ~ESDCTL0_COL_MASK; ++ r0 |= ESDCTL0_COL9; ++ writel(r0, ESDCTL0); ++ } ++} ++ ++#define BRANCH_PREDICTION_ENABLE ++#define UNALIGNED_ACCESS_ENABLE ++#define LOW_INT_LATENCY_ENABLE ++ ++void __bare_init __naked board_init_lowlevel(void) ++{ ++ u32 r0, r1; ++ void *iomuxc_base = (void *)IMX_IOMUXC_BASE; ++ int i; ++#ifdef CONFIG_NAND_IMX_BOOT ++ unsigned int *trg, *src; ++#endif ++ ++ r0 = 0x10000000 + 128 * 1024 - 16; ++ __asm__ __volatile__("mov sp, %0" : : "r"(r0)); ++ ++ /* ++ * ARM1136 init ++ * - invalidate I/D cache/TLB and drain write buffer; ++ * - invalidate L2 cache ++ * - unaligned access ++ * - branch predictions ++ */ ++#ifdef TURN_OFF_IMPRECISE_ABORT ++ __asm__ __volatile__("mrs %0, cpsr":"=r"(r0)); ++ r0 &= ~0x100; ++ __asm__ __volatile__("msr cpsr, %0" : : "r"(r0)); ++#endif ++ /* ensure L1 caches and MMU are turned-off for now */ ++ r1 = get_cr(); ++ r1 &= ~(CR_I | CR_M | CR_C); ++ ++ /* setup core features */ ++ __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1":"=r"(r0)); ++#ifdef BRANCH_PREDICTION_ENABLE ++ r0 |= 7; ++ r1 |= CR_Z; ++#else ++ r0 &= ~7; ++ r1 &= ~CR_Z; ++#endif ++ __asm__ __volatile__("mcr p15, 0, r0, c1, c0, 1" : : "r"(r0)); ++ ++#ifdef UNALIGNED_ACCESS_ENABLE ++ r1 |= CR_U; ++#else ++ r1 &= ~CR_U; ++#endif ++ ++#ifdef LOW_INT_LATENCY_ENABLE ++ r1 |= CR_FI; ++#else ++ r1 &= ~CR_FI; ++#endif ++ set_cr(r1); ++ ++ r0 = 0; ++ __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 6" : : "r"(r0)); ++ ++ /* invalidate I cache and D cache */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c7, 0" : : "r"(r0)); ++ /* invalidate TLBs */ ++ __asm__ __volatile__("mcr p15, 0, r0, c8, c7, 0" : : "r"(r0)); ++ /* Drain the write buffer */ ++ __asm__ __volatile__("mcr p15, 0, r0, c7, c10, 4" : : "r"(r0)); ++ ++ /* Also setup the Peripheral Port Remap register inside the core */ ++ r0 = 0x40000015; /* start from AIPS 2GB region */ ++ __asm__ __volatile__("mcr p15, 0, r0, c15, c2, 4" : : "r"(r0)); ++ ++#define WDOG_WMCR 0x8 ++ /* silence reset WDOG */ ++ writew(0, IMX_WDOG_BASE + WDOG_WMCR); ++ ++ /* Skip SDRAM initialization if we run from RAM */ ++ r0 = get_pc(); ++ if (r0 > 0x80000000 && r0 < 0x90000000) ++ board_init_lowlevel_return(); ++ ++ /* Configure drive strength */ ++ ++ /* Configure DDR-pins to correct mode */ ++ r0 = 0x00001800; ++ writel(r0, iomuxc_base + 0x794); ++ writel(r0, iomuxc_base + 0x798); ++ writel(r0, iomuxc_base + 0x79c); ++ writel(r0, iomuxc_base + 0x7a0); ++ writel(r0, iomuxc_base + 0x7a4); ++ ++ /* Set drive strength for DDR-pins */ ++ for (i = 0x368; i <= 0x4c8; i += 4) { ++ r0 = readl(iomuxc_base + i); ++ r0 &= ~0x6; ++ r0 |= 0x2; ++ writel(r0, iomuxc_base + i); ++ if (i == 0x468) ++ i = 0x4a4; ++ } ++ ++ r0 = readl(iomuxc_base + 0x480); ++ r0 &= ~0x6; ++ r0 |= 0x2; ++ writel(r0, iomuxc_base + 0x480); ++ ++ r0 = readl(iomuxc_base + 0x4b8); ++ r0 &= ~0x6; ++ r0 |= 0x2; ++ writel(r0, iomuxc_base + 0x4b8); ++ ++ /* Configure static chip-selects */ ++ r0 = readl(iomuxc_base + 0x000); ++ r0 &= ~1; /* configure CS2/CSD0 for SDRAM */ ++ writel(r0, iomuxc_base + 0x000); ++ ++ /* start-up code doesn't need any static chip-select. ++ * Leave their initialization to high-level code that ++ * can initialize them depending on the baseboard. ++ */ ++ ++ /* Configure clocks */ ++ ++ /* setup cpu/bus clocks */ ++ writel(0x003f4208, IMX_CCM_BASE + CCM_CCMR); ++ ++ /* configure MPLL */ ++ writel(MPCTL_PARAM_532, IMX_CCM_BASE + CCM_MPCTL); ++ ++ /* configure PPLL */ ++ writel(PPCTL_PARAM_300, IMX_CCM_BASE + CCM_PPCTL); ++ ++ /* configure core dividers */ ++ r0 = PDR0_CCM_PER_AHB(1) | PDR0_HSP_PODF(2); ++ ++ writel(r0, IMX_CCM_BASE + CCM_PDR0); ++ ++ /* configure clock-gates */ ++ r0 = readl(IMX_CCM_BASE + CCM_CGR0); ++ r0 |= 0x00300000; ++ writel(r0, IMX_CCM_BASE + CCM_CGR0); ++ ++ r0 = readl(IMX_CCM_BASE + CCM_CGR1); ++ r0 |= 0x00000c03; ++ writel(r0, IMX_CCM_BASE + CCM_CGR1); ++ ++ /* Configure SDRAM */ ++ /* Try 32-Bit 256 MB DDR memory */ ++ r0 = ESDCTL0_SDE | ESDCTL0_ROW14 | ESDCTL0_COL10 | ESDCTL0_DSIZ_31_0; /* 1024 MBit DDR-SDRAM */ ++ setup_sdram(r0, ESDMISC_MDDR_EN, 0x80000f00); ++ ++#ifdef CONFIG_NAND_IMX_BOOT ++ /* skip NAND boot if not running from NFC space */ ++ r0 = get_pc(); ++ if (r0 < IMX_NFC_BASE || r0 > IMX_NFC_BASE + 0x800) ++ board_init_lowlevel_return(); ++ ++ src = (unsigned int *)IMX_NFC_BASE; ++ trg = (unsigned int *)TEXT_BASE; ++ ++ /* Move ourselves out of NFC SRAM */ ++ for (i = 0; i < 0x800 / sizeof(int); i++) ++ *trg++ = *src++; ++ ++ /* Jump to SDRAM */ ++ r0 = (unsigned int)&insdram; ++ __asm__ __volatile__("mov pc, %0" : : "r"(r0)); ++#else ++ board_init_lowlevel_return(); ++#endif ++} ++ +diff --git a/arch/arm/boards/guf-neso/board.c b/arch/arm/boards/guf-neso/board.c +index 9c85c08..d371dd6 100644 +--- a/arch/arm/boards/guf-neso/board.c ++++ b/arch/arm/boards/guf-neso/board.c +@@ -44,6 +44,7 @@ + #include <mach/imx-nand.h> + #include <mach/imx-pll.h> + #include <mach/imxfb.h> ++#include <mach/devices-imx27.h> + + /* two pins are controlling the CS signals to the USB phys */ + #define USBH2_PHY_CS_GPIO (GPIO_PORTF + 20) +@@ -71,26 +72,12 @@ static struct fec_platform_data fec_info = { + .phy_addr = 31, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = 0x1002b000, +- .platform_data = &fec_info, +-}; +- + static struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, + .flash_bbt = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = 0xd8000000, +- .platform_data = &nand_info, +-}; +- + static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "CPT CLAA070LC0JCT", +@@ -139,14 +126,6 @@ static struct imx_fb_platform_data neso_fb_data = { + .framebuffer_ovl = (void *)0xa7f00000, + }; + +-static struct device_d imxfb_dev = { +- .id = -1, +- .name = "imxfb", +- .map_base = 0x10021000, +- .size = 0x1000, +- .platform_data = &neso_fb_data, +-}; +- + #ifdef CONFIG_USB + + static struct device_d usbh2_dev = { +@@ -334,16 +313,16 @@ static int neso_devices_init(void) + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +- register_device(&nand_dev); ++ imx27_add_nand(&nand_info); + register_device(&sdram_dev); +- register_device(&imxfb_dev); ++ imx27_add_fb(&neso_fb_data); + + #ifdef CONFIG_USB + neso_usbh_init(); + register_device(&usbh2_dev); + #endif + +- register_device(&fec_dev); ++ imx27_add_fec(&fec_info); + + devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); + dev_add_bb_dev("self_raw", "self0"); +@@ -360,16 +339,9 @@ static int neso_devices_init(void) + + device_initcall(neso_devices_init); + +-static struct device_d neso_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 4096, +-}; +- + static int neso_console_init(void) + { +- register_device(&neso_serial_device); ++ imx27_add_uart0(); + + return 0; + } +diff --git a/arch/arm/boards/imx21ads/imx21ads.c b/arch/arm/boards/imx21ads/imx21ads.c +index 44d37aa..3942581 100644 +--- a/arch/arm/boards/imx21ads/imx21ads.c ++++ b/arch/arm/boards/imx21ads/imx21ads.c +@@ -36,6 +36,7 @@ + #include <mach/imx-nand.h> + #include <mach/imxfb.h> + #include <mach/iomux-mx21.h> ++#include <mach/devices-imx21.h> + + #define MX21ADS_IO_REG 0xCC800000 + #define MX21ADS_IO_LCDON (1 << 9) +@@ -65,13 +66,6 @@ struct imx_nand_platform_data nand_info = { + .hw_ecc = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = 0xDF003000, +- .platform_data = &nand_info, +-}; +- + static struct device_d cs8900_dev = { + .id = -1, + .name = "cs8900", +@@ -111,14 +105,6 @@ static struct imx_fb_platform_data imx_fb_data = { + .dmacr = 0x00020008, + }; + +-static struct device_d imxfb_dev = { +- .id = -1, +- .name = "imxfb", +- .map_base = 0x10021000, +- .size = 0x1000, +- .platform_data = &imx_fb_data, +-}; +- + static int imx21ads_timing_init(void) + { + u32 temp; +@@ -199,9 +185,9 @@ static int mx21ads_devices_init(void) + + register_device(&cfi_dev); + register_device(&sdram_dev); +- register_device(&nand_dev); ++ imx21_add_nand(&nand_info); + register_device(&cs8900_dev); +- register_device(&imxfb_dev); ++ imx21_add_fb(&imx_fb_data); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void *)0xc0000100); +@@ -224,16 +210,9 @@ static int mx21ads_enable_display(void) + + late_initcall(mx21ads_enable_display); + +-static struct device_d mx21ads_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 4096, +-}; +- + static int mx21ads_console_init(void) + { +- register_device(&mx21ads_serial_device); ++ imx21_add_uart0(); + return 0; + } + +diff --git a/arch/arm/boards/imx27ads/imx27ads.c b/arch/arm/boards/imx27ads/imx27ads.c +index ae5da7f..0d433c1 100644 +--- a/arch/arm/boards/imx27ads/imx27ads.c ++++ b/arch/arm/boards/imx27ads/imx27ads.c +@@ -32,6 +32,7 @@ + #include <fcntl.h> + #include <generated/mach-types.h> + #include <mach/iomux-mx27.h> ++#include <mach/devices-imx27.h> + + static struct device_d cfi_dev = { + .id = -1, +@@ -58,13 +59,6 @@ static struct fec_platform_data fec_info = { + .phy_addr = 1, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = 0x1002b000, +- .platform_data = &fec_info, +-}; +- + static int imx27ads_timing_init(void) + { + /* configure cpld on cs4 */ +@@ -134,7 +128,7 @@ static int mx27ads_devices_init(void) + + register_device(&cfi_dev); + register_device(&sdram_dev); +- register_device(&fec_dev); ++ imx27_add_fec(&fec_info); + + devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0"); + devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0"); +@@ -149,16 +143,9 @@ static int mx27ads_devices_init(void) + + device_initcall(mx27ads_devices_init); + +-static struct device_d mx27ads_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 4096, +-}; +- + static int mx27ads_console_init(void) + { +- register_device(&mx27ads_serial_device); ++ imx27_add_uart0(); + return 0; + } + +diff --git a/arch/arm/boards/mini2440/Makefile b/arch/arm/boards/mini2440/Makefile +new file mode 100644 +index 0000000..09f7e7d +--- /dev/null ++++ b/arch/arm/boards/mini2440/Makefile +@@ -0,0 +1,2 @@ ++ ++obj-y += mini2440.o +diff --git a/arch/arm/boards/mini2440/config.h b/arch/arm/boards/mini2440/config.h +new file mode 100644 +index 0000000..a664017 +--- /dev/null ++++ b/arch/arm/boards/mini2440/config.h +@@ -0,0 +1,50 @@ ++/** ++ * @file ++ * @brief Global defintions for the ARM S3C2440 based mini2440 CPU card ++ */ ++/* This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++/** ++ * The external clock reference is a 12.00 MHz crystal ++ */ ++#define S3C24XX_CLOCK_REFERENCE 12000000 ++ ++/* ++ * Flash access timings ++ * Tacls = 0ns (but 20ns data setup time) ++ * Twrph0 = 25ns (write) 35ns (read) ++ * Twrph1 = 10ns (10ns data hold time) ++ * Read cycle time = 50ns ++ * ++ * Assumed HCLK is 100MHz ++ * Tacls = 1 (-> 20ns) ++ * Twrph0 = 3 (-> 40ns) ++ * Twrph1 = 1 (-> 20ns) ++ * Cycle time = 80ns ++ */ ++#define A9M2440_TACLS 1 ++#define A9M2440_TWRPH0 3 ++#define A9M2440_TWRPH1 1 ++ ++/* needed in the generic NAND boot code only */ ++#ifdef CONFIG_S3C24XX_NAND_BOOT ++# define BOARD_DEFAULT_NAND_TIMING CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1) ++#endif ++#endif /* __CONFIG_H */ +diff --git a/arch/arm/boards/mini2440/env/bin/_update b/arch/arm/boards/mini2440/env/bin/_update +new file mode 100644 +index 0000000..b10682e +--- /dev/null ++++ b/arch/arm/boards/mini2440/env/bin/_update +@@ -0,0 +1,34 @@ ++#!/bin/sh ++ ++if [ -z "$part" -o -z "$image" ]; then ++ echo "define \$part and \$image" ++ exit 1 ++fi ++ ++if [ ! -e "$part" ]; then ++ echo "Partition $part does not exist" ++ exit 1 ++fi ++ ++if [ $# = 1 ]; then ++ image=$1 ++fi ++ ++if [ x$ip = xdhcp ]; then ++ dhcp ++fi ++ ++ping $eth0.serverip ++if [ $? -ne 0 ] ; then ++ echo "update aborted" ++ exit 1 ++fi ++ ++echo ++echo "erasing partition $part" ++erase $part ++ ++echo ++echo "flashing $image to $part" ++echo ++tftp $image $part +diff --git a/arch/arm/boards/mini2440/env/bin/boot b/arch/arm/boards/mini2440/env/bin/boot +new file mode 100644 +index 0000000..86e22cf +--- /dev/null ++++ b/arch/arm/boards/mini2440/env/bin/boot +@@ -0,0 +1,40 @@ ++#!/bin/sh ++ ++. /env/config ++ ++if [ x$1 = xnand ]; then ++ root=nand ++ kernel=nand ++fi ++ ++if [ x$1 = xnet ]; then ++ root=net ++ kernel=net ++fi ++ ++if [ x$root = xnand ]; then ++ bootargs="$bootargs root=$rootpart_nand rootfstype=jffs2" ++fi ++if [ x$root = xnet ]; then ++ bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot,v3,tcp" ++ if [ x$ip = xdhcp ]; then ++ bootargs="$bootargs ip=dhcp" ++ else ++ bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" ++ fi ++fi ++ ++bootargs="$bootargs mtdparts=\"NAND 32MiB 3,3V 8-bit:$nand_parts\"" ++ ++bootargs="$bootargs cs89x0_media=rj45 cs89x0_mac=$eth0.ethaddr" ++ ++if [ x$kernel = xnet ]; then ++ if [ x$ip = xdhcp ]; then ++ dhcp ++ fi ++ tftp $uimage uImage || exit 1 ++ bootm uImage ++else ++ bootm /dev/nand0.kernel.bb ++fi ++ +diff --git a/arch/arm/boards/mini2440/env/bin/hush_hack b/arch/arm/boards/mini2440/env/bin/hush_hack +new file mode 100644 +index 0000000..5fffa92 +--- /dev/null ++++ b/arch/arm/boards/mini2440/env/bin/hush_hack +@@ -0,0 +1 @@ ++nand -a /dev/nand0.* +diff --git a/arch/arm/boards/mini2440/env/bin/init b/arch/arm/boards/mini2440/env/bin/init +new file mode 100644 +index 0000000..e98ab84 +--- /dev/null ++++ b/arch/arm/boards/mini2440/env/bin/init +@@ -0,0 +1,34 @@ ++#!/bin/sh ++ ++PATH=/env/bin ++export PATH ++ ++. /env/config ++ ++if [ -e /dev/nand0 ]; then ++#addpart /dev/nand0 $nand_parts ++ ++ # Uh, oh, hush first expands wildcards and then starts executing ++ # commands. What a bug! ++ source /env/bin/hush_hack ++fi ++ ++if [ -z $eth0.ethaddr ]; then ++ while [ -z $eth0.ethaddr ]; do ++ readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr ++ done ++ echo -a /env/config "eth0.ethaddr=$eth0.ethaddr" ++fi ++ ++echo ++echo -n "Hit any key to stop autoboot: " ++timeout -a $autoboot_timeout ++if [ $? != 0 ]; then ++ echo ++ echo "type update_kernel [<imagename>] to update kernel into flash" ++ echo "type update_root [<imagename>] to update rootfs into flash" ++ echo ++ exit ++fi ++ ++boot +diff --git a/arch/arm/boards/mini2440/env/bin/update_kernel b/arch/arm/boards/mini2440/env/bin/update_kernel +new file mode 100644 +index 0000000..c43a557 +--- /dev/null ++++ b/arch/arm/boards/mini2440/env/bin/update_kernel +@@ -0,0 +1,13 @@ ++#!/bin/sh ++ ++. /env/config ++ ++part=/dev/nand0.kernel.bb ++ ++if [ x$1 = x ]; then ++ image=$uimage ++else ++ image=$1 ++fi ++ ++. /env/bin/_update $image +diff --git a/arch/arm/boards/mini2440/env/bin/update_root b/arch/arm/boards/mini2440/env/bin/update_root +new file mode 100644 +index 0000000..46cbca5 +--- /dev/null ++++ b/arch/arm/boards/mini2440/env/bin/update_root +@@ -0,0 +1,13 @@ ++#!/bin/sh ++ ++. /env/config ++ ++part=/dev/nand0.root.bb ++ ++if [ x$1 = x ]; then ++ image=$jffs2 ++else ++ image=$1 ++fi ++ ++. /env/bin/_update $image +diff --git a/arch/arm/boards/mini2440/env/config b/arch/arm/boards/mini2440/env/config +new file mode 100644 +index 0000000..05a2d01 +--- /dev/null ++++ b/arch/arm/boards/mini2440/env/config +@@ -0,0 +1,27 @@ ++#!/bin/sh ++ ++# can be either 'net' or 'nand'' ++kernel=net ++root=net ++ ++#uimage=uImage-a9m2440 ++uimage=uImage ++jffs2=root-a9m2440.jffs2 ++ ++autoboot_timeout=3 ++ ++nfsroot="/home/open-nandra/rootfs" ++bootargs="console=ttySAC0,115200" ++ ++nand_parts="256k(barebox),128k(bareboxenv),1536k(kernel),-(root)" ++rootpart_nand="/dev/mtdblock3" ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++#ip=dhcp ++ ++# or set your networking parameters here ++eth0.ipaddr=192.168.42.32 ++eth0.netmask=255.255.0.0 ++eth0.gateway=192.168.23.1 ++eth0.serverip=192.168.23.2 ++eth0.ethaddr=00:04:f3:00:06:35 +diff --git a/arch/arm/boards/mini2440/mini2440.c b/arch/arm/boards/mini2440/mini2440.c +new file mode 100644 +index 0000000..a673a5d +--- /dev/null ++++ b/arch/arm/boards/mini2440/mini2440.c +@@ -0,0 +1,139 @@ ++/* ++ * Copyright (C) 2010 Marek Belisko <marek.belisko@open-nandra.com> ++ * ++ * Based on a9m2440.c board init by Juergen Beisert, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++/** ++ * @file ++ * @brief mini2440 Specific Board Initialization routines ++ * ++ */ ++ ++#include <common.h> ++#include <driver.h> ++#include <init.h> ++#include <asm/armlinux.h> ++#include <generated/mach-types.h> ++#include <partition.h> ++#include <nand.h> ++#include <asm/io.h> ++#include <mach/s3c24x0-iomap.h> ++#include <mach/s3c24x0-nand.h> ++#include <mach/s3c24xx-generic.h> ++#include <dm9000.h> ++ ++static struct memory_platform_data ram_pdata = { ++ .name = "ram0", ++ .flags = DEVFS_RDWR, ++}; ++ ++static struct device_d sdram_dev = { ++ .name = "mem", ++ .map_base = CS6_BASE, ++ .platform_data = &ram_pdata, ++}; ++ ++static struct s3c24x0_nand_platform_data nand_info = { ++ .nand_timing = CALC_NFCONF_TIMING(A9M2440_TACLS, A9M2440_TWRPH0, A9M2440_TWRPH1) ++}; ++ ++static struct device_d nand_dev = { ++ .name = "s3c24x0_nand", ++ .map_base = S3C24X0_NAND_BASE, ++ .platform_data = &nand_info, ++}; ++ ++/* ++ * dm9000 network controller onboard ++ */ ++static struct dm9000_platform_data dm9000_data = { ++ .iobase = CS4_BASE + 0x300, ++ .iodata = CS4_BASE + 0x304, ++ .buswidth = DM9000_WIDTH_16, ++ .srom = 1, ++}; ++ ++static struct device_d dm9000_dev = { ++ .name = "dm9000", ++ .map_base = CS4_BASE + 0x300, ++ .size = 8, ++ .platform_data = &dm9000_data, ++}; ++ ++static int mini2440_devices_init(void) ++{ ++ uint32_t reg; ++ ++ reg = readl(BWSCON); ++ ++ /* CS#4 to access the network controller */ ++ reg &= ~0x000f0000; ++ reg |= 0x000d0000; /* 16 bit */ ++ writel(0x1f4c, BANKCON4); ++ ++ writel(reg, BWSCON); ++ ++ /* release the reset signal to external devices */ ++ reg = readl(MISCCR); ++ reg |= 0x10000; ++ writel(reg, MISCCR); ++ ++ register_device(&nand_dev); ++ register_device(&sdram_dev); ++ register_device(&dm9000_dev); ++#ifdef CONFIG_NAND ++ /* ----------- add some vital partitions -------- */ ++ devfs_del_partition("self_raw"); ++ devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw"); ++ dev_add_bb_dev("self_raw", NULL); ++ ++ devfs_del_partition("env_raw"); ++ devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw"); ++ dev_add_bb_dev("env_raw", NULL); ++#endif ++ armlinux_add_dram(&sdram_dev); ++ armlinux_set_bootparams((void *)sdram_dev.map_base + 0x100); ++ armlinux_set_architecture(MACH_TYPE_MINI2440); ++ ++ return 0; ++} ++ ++device_initcall(mini2440_devices_init); ++ ++#ifdef CONFIG_S3C24XX_NAND_BOOT ++void __bare_init nand_boot(void) ++{ ++ s3c24x0_nand_load_image((void *)TEXT_BASE, 256 * 1024, 0, 512); ++} ++#endif ++ ++static struct device_d mini2440_serial_device = { ++ .name = "s3c24x0_serial", ++ .map_base = UART1_BASE, ++ .size = UART1_SIZE, ++}; ++ ++static int mini2440_console_init(void) ++{ ++ register_device(&mini2440_serial_device); ++ return 0; ++} ++ ++console_initcall(mini2440_console_init); +diff --git a/arch/arm/boards/nhk8815/env/bin/_update b/arch/arm/boards/nhk8815/env/bin/_update +deleted file mode 100644 +index fb7cbe8..0000000 +--- a/arch/arm/boards/nhk8815/env/bin/_update ++++ /dev/null +@@ -1,36 +0,0 @@ +-#!/bin/sh +- +-if [ -z "$part" -o -z "$image" ]; then +- echo "define \$part and \$image" +- exit 1 +-fi +- +-if [ \! -e "$part" ]; then +- echo "Partition $part does not exist" +- exit 1 +-fi +- +-if [ $# = 1 ]; then +- image=$1 +-fi +- +-if [ x$ip = xdhcp ]; then +- dhcp +-fi +- +-ping $eth0.serverip +-if [ $? -ne 0 ] ; then +- echo "update aborted" +- exit 1 +-fi +- +-unprotect $part +- +-echo +-echo "erasing partition $part" +-erase $part +- +-echo +-echo "flashing $image to $part" +-echo +-tftp $image $part +diff --git a/arch/arm/boards/nhk8815/env/bin/boot b/arch/arm/boards/nhk8815/env/bin/boot +deleted file mode 100644 +index fd8d957..0000000 +--- a/arch/arm/boards/nhk8815/env/bin/boot ++++ /dev/null +@@ -1,38 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-if [ x$1 = xflash ]; then +- root=flash +- kernel=flash +-fi +- +-if [ x$1 = xnet ]; then +- root=net +- kernel=net +-fi +- +-if [ x$ip = xdhcp ]; then +- bootargs="$bootargs ip=dhcp" +-else +- bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +-fi +- +-if [ x$root = xflash ]; then +- bootargs="$bootargs root=$rootpart rootfstype=jffs2" +-else +- bootargs="$bootargs root=/dev/nfs nfsroot=192.168.23.111:$nfsroot" +-fi +- +-bootargs="$bootargs" +- +-if [ $kernel = net ]; then +- if [ x$ip = xdhcp ]; then +- dhcp +- fi +- tftp $uimage uImage +- bootm uImage +-else +- bootm /dev/nor0.kernel +-fi +- +diff --git a/arch/arm/boards/nhk8815/env/bin/init b/arch/arm/boards/nhk8815/env/bin/init +deleted file mode 100644 +index 5b45a70..0000000 +--- a/arch/arm/boards/nhk8815/env/bin/init ++++ /dev/null +@@ -1,28 +0,0 @@ +-#!/bin/sh +- +-PATH=/env/bin +-export PATH +- +-. /env/config +- +-if [ -e /dev/nand0 ]; then +- addpart /dev/nand0 $nand_parts +- +- # Uh, oh, hush first expands wildcards and then starts executing +- # commands. What a bug! +- source /env/bin/hush_hack +-fi +- +-echo +-echo -n "Hit any key to stop autoboot: " +-timeout -a $autoboot_timeout +-if [ $? != 0 ]; then +- echo +- echo "type update_kernel [<imagename>] to update kernel into flash" +- echo "type udate_root [<imagename>] to update rootfs into flash" +- echo "type update_barebox_xmodem nor to update barebox into flash" +- echo +- exit +-fi +- +-boot +diff --git a/arch/arm/boards/nhk8815/env/bin/update_barebox_xmodem b/arch/arm/boards/nhk8815/env/bin/update_barebox_xmodem +deleted file mode 100644 +index 40f4ad3..0000000 +--- a/arch/arm/boards/nhk8815/env/bin/update_barebox_xmodem ++++ /dev/null +@@ -1,19 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-part=/dev/nand0.barebox +- +-loadb -f barebox.bin -c +- +-unprotect $part +-echo +-echo "erasing partition $part" +-erase $part +- +-echo +-echo "flashing barebox.bin to $part" +-echo +-cp barebox.bin $part +-crc32 -f barebox.bin +-crc32 -f $part +diff --git a/arch/arm/boards/nhk8815/env/bin/update_kernel b/arch/arm/boards/nhk8815/env/bin/update_kernel +deleted file mode 100644 +index db0f4c2..0000000 +--- a/arch/arm/boards/nhk8815/env/bin/update_kernel ++++ /dev/null +@@ -1,8 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-image=$uimage +-part=/dev/nand0.kernel +- +-. /env/bin/_update $1 +diff --git a/arch/arm/boards/nhk8815/env/bin/update_root b/arch/arm/boards/nhk8815/env/bin/update_root +deleted file mode 100644 +index 9530e84..0000000 +--- a/arch/arm/boards/nhk8815/env/bin/update_root ++++ /dev/null +@@ -1,8 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-image=$jffs2 +-part=/dev/nand0.rootfs +- +-. /env/bin/_update $1 +diff --git a/arch/arm/boards/nhk8815/env/config b/arch/arm/boards/nhk8815/env/config +index 7e7fc45..e657a76 100644 +--- a/arch/arm/boards/nhk8815/env/config ++++ b/arch/arm/boards/nhk8815/env/config +@@ -1,16 +1,33 @@ + #!/bin/sh + +-# can be either 'net' or 'flash' +-kernel=net +-root=net +- +-# use 'dhcp' todo dhcp in uboot and in kernel ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration + ip=dhcp + +-# +-# setup default ethernet address +-# +-#eth0.serverip=192.168.23.108 ++# or set your networking parameters here ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'net' or 'nand' ++kernel_loc=net ++# can be either 'net', 'nand' or 'initrd' ++rootfs_loc=net ++ ++# can be either 'jffs2' or 'ubifs' ++rootfs_type=ubifs ++rootfsimage=root.$rootfs_type ++ ++# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo ++#kernelimage_type=zimage ++#kernelimage=zImage ++kernelimage_type=uimage ++kernelimage=uImage ++#kernelimage_type=raw ++#kernelimage=Image ++#kernelimage_type=raw_lzo ++#kernelimage=Image.lzo + + # Partition Size Start + # XloaderTOC + X-Loader 256KB 0x00000000 +@@ -22,11 +39,10 @@ ip=dhcp + + nand_parts="256k(xloader)ro,256k(meminit),2M(barebox),3M(kernel),22M(rootfs),100M(userfs),384k(free),128k(bareboxenv)" + +-uimage=uImage-nhk15 +- +-# use 'dhcp' to do dhcp in uboot and in kernel +-ip=dhcp +- + autoboot_timeout=3 + + bootargs="root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc" ++ ++# set a fancy prompt (if support is compiled in) ++PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " ++ +diff --git a/arch/arm/boards/pcm037/env/config b/arch/arm/boards/pcm037/env/config +index bf15620..df2f694 100644 +--- a/arch/arm/boards/pcm037/env/config ++++ b/arch/arm/boards/pcm037/env/config +@@ -50,6 +50,7 @@ rootfs_mtdblock_nor=3 + + nand_parts="256k(barebox)ro,128k(bareboxenv),2M(kernel),-(root)" + rootfs_mtdblock_nand=7 ++nand_device="mxc_nand" + + # set a fancy prompt (if support is compiled in) + PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " +diff --git a/arch/arm/boards/pcm037/pcm037.c b/arch/arm/boards/pcm037/pcm037.c +index 89e2481..ffecec2 100644 +--- a/arch/arm/boards/pcm037/pcm037.c ++++ b/arch/arm/boards/pcm037/pcm037.c +@@ -37,7 +37,7 @@ + #include <partition.h> + #include <generated/mach-types.h> + #include <mach/imx-nand.h> +- ++#include <mach/devices-imx31.h> + + /* + * Up to 32MiB NOR type flash, connected to +@@ -126,13 +126,6 @@ struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = 0xB8000000, +- .platform_data = &nand_info, +-}; +- + #ifdef CONFIG_USB + static struct device_d usbotg_dev = { + .id = -1, +@@ -295,7 +288,7 @@ static int imx31_devices_init(void) + protect_file("/dev/env0", 1); + + register_device(&sram_dev); +- register_device(&nand_dev); ++ imx31_add_nand(&nand_info); + register_device(&network_dev); + + register_device(&sdram0_dev); +@@ -320,13 +313,6 @@ static int imx31_devices_init(void) + + device_initcall(imx31_devices_init); + +-static struct device_d imx31_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 16 * 1024, +-}; +- + static int imx31_console_init(void) + { + /* init gpios for serial port */ +@@ -335,7 +321,7 @@ static int imx31_console_init(void) + imx_iomux_mode(MX31_PIN_CTS1__CTS1); + imx_iomux_mode(MX31_PIN_RTS1__RTS1); + +- register_device(&imx31_serial_device); ++ imx31_add_uart0(); + return 0; + } + +diff --git a/arch/arm/boards/pcm038/Makefile b/arch/arm/boards/pcm038/Makefile +index a681dda..970804e 100644 +--- a/arch/arm/boards/pcm038/Makefile ++++ b/arch/arm/boards/pcm038/Makefile +@@ -1,3 +1,3 @@ + +-obj-y += lowlevel.o pll_init.o ++obj-y += lowlevel.o + obj-y += pcm038.o +diff --git a/arch/arm/boards/pcm038/lowlevel.c b/arch/arm/boards/pcm038/lowlevel.c +index eb85e8f..b50e1c8 100644 +--- a/arch/arm/boards/pcm038/lowlevel.c ++++ b/arch/arm/boards/pcm038/lowlevel.c +@@ -31,6 +31,8 @@ + #include <asm/system.h> + #include <asm-generic/memory_layout.h> + ++#include "pll.h" ++ + #ifdef CONFIG_NAND_IMX_BOOT + static void __bare_init __naked insdram(void) + { +@@ -68,6 +70,11 @@ void __bare_init __naked board_init_lowlevel(void) + if (r > 0xa0000000 && r < 0xb0000000) + board_init_lowlevel_return(); + ++ /* re-program the PLL prior(!) starting the SDRAM controller */ ++ MPCTL0 = MPCTL0_VAL; ++ SPCTL0 = SPCTL0_VAL; ++ CSCR = CSCR_VAL | CSCR_UPDATE_DIS | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART; ++ + /* + * DDR on CSD0 + */ +diff --git a/arch/arm/boards/pcm038/pcm038.c b/arch/arm/boards/pcm038/pcm038.c +index fda3262..1dbc6b6 100644 +--- a/arch/arm/boards/pcm038/pcm038.c ++++ b/arch/arm/boards/pcm038/pcm038.c +@@ -43,6 +43,9 @@ + #include <usb/isp1504.h> + #include <mach/spi.h> + #include <mach/iomux-mx27.h> ++#include <mach/devices-imx27.h> ++ ++#include "pll.h" + + static struct device_d cfi_dev = { + .id = -1, +@@ -82,13 +85,6 @@ static struct fec_platform_data fec_info = { + .phy_addr = 1, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = 0x1002b000, +- .platform_data = &fec_info, +-}; +- + static int pcm038_spi_cs[] = {GPIO_PORTD + 28}; + + static struct spi_imx_master pcm038_spi_0_data = { +@@ -96,13 +92,6 @@ static struct spi_imx_master pcm038_spi_0_data = { + .num_chipselect = ARRAY_SIZE(pcm038_spi_cs), + }; + +-static struct device_d spi_dev = { +- .id = -1, +- .name = "imx_spi", +- .map_base = 0x1000e000, +- .platform_data = &pcm038_spi_0_data, +-}; +- + static struct spi_board_info pcm038_spi_board_info[] = { + { + .name = "mc13783", +@@ -118,13 +107,6 @@ static struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = 0xd8000000, +- .platform_data = &nand_info, +-}; +- + static struct imx_fb_videomode imxfb_mode = { + .mode = { + .name = "Sharp-LQ035Q7", +@@ -159,14 +141,6 @@ static struct imx_fb_platform_data pcm038_fb_data = { + .dmacr = 0x00020010, + }; + +-static struct device_d imxfb_dev = { +- .id = -1, +- .name = "imxfb", +- .map_base = 0x10021000, +- .size = 0x1000, +- .platform_data = &pcm038_fb_data, +-}; +- + #ifdef CONFIG_USB + static struct device_d usbh2_dev = { + .id = -1, +@@ -321,13 +295,13 @@ static int pcm038_devices_init(void) + gpio_direction_output(GPIO_PORTD | 28, 0); + gpio_set_value(GPIO_PORTD | 28, 0); + spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info)); +- register_device(&spi_dev); ++ imx27_add_spi0(&pcm038_spi_0_data); + + register_device(&cfi_dev); +- register_device(&nand_dev); ++ imx27_add_nand(&nand_info); + register_device(&sdram_dev); + register_device(&sram_dev); +- register_device(&imxfb_dev); ++ imx27_add_fb(&pcm038_fb_data); + + #ifdef CONFIG_USB + pcm038_usbh_init(); +@@ -337,7 +311,7 @@ static int pcm038_devices_init(void) + /* Register the fec device after the PLL re-initialisation + * as the fec depends on the (now higher) ipg clock + */ +- register_device(&fec_dev); ++ imx27_add_fec(&fec_info); + + switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) { + case GPCR_BOOT_8BIT_NAND_2k: +@@ -370,61 +344,59 @@ static int pcm038_devices_init(void) + + device_initcall(pcm038_devices_init); + +-static struct device_d pcm038_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 4096, +-}; +- + static int pcm038_console_init(void) + { +- /* bring PLLs to reset default */ +- MPCTL0 = 0x00211803; +- SPCTL0 = 0x1002700c; +- CSCR = 0x33fc1307; +- +- register_device(&pcm038_serial_device); ++ imx27_add_uart0(); + + return 0; + } + + console_initcall(pcm038_console_init); + +-extern void *pcm038_pll_init, *pcm038_pll_init_end; +- +-static int pcm038_power_init(void) ++/** ++ * The spctl0 register is a beast: Seems you can read it ++ * only one times without writing it again. ++ */ ++static inline uint32_t get_pll_spctl10(void) + { +- int ret; +- void *vram = (void*)0xffff4c00; +- void (*pllfunc)(void) = vram; ++ uint32_t reg; + +- printf("initialising PLLs: 0x%p 0x%p\n", &pcm038_pll_init); ++ reg = SPCTL0; ++ SPCTL0 = reg; + +- memcpy(vram, &pcm038_pll_init, 0x100); ++ return reg; ++} + +- console_flush(); ++/** ++ * If the PLL settings are in place switch the CPU core frequency to the max. value ++ */ ++static int pcm038_power_init(void) ++{ ++ uint32_t spctl0; ++ int ret; + +- ret = pmic_power(); +- if (ret) { +- printf("Failed to initialize PMIC. Will continue with low CPU speed\n"); +- return 0; ++ spctl0 = get_pll_spctl10(); ++ ++ /* PLL registers already set to their final values? */ ++ if (spctl0 == SPCTL0_VAL && MPCTL0 == MPCTL0_VAL) { ++ console_flush(); ++ ret = pmic_power(); ++ if (ret == 0) { ++ /* wait for required power level to run the CPU at 400 MHz */ ++ udelay(100000); ++ CSCR = CSCR_VAL_FINAL; ++ PCDR0 = 0x130410c3; ++ PCDR1 = 0x09030911; ++ /* Clocks have changed. Notify clients */ ++ clock_notifier_call_chain(); ++ } else { ++ printf("Failed to initialize PMIC. Will continue with low CPU speed\n"); ++ } + } + +- /* wait for good power level */ +- udelay(100000); +- +- pllfunc(); +- + /* clock gating enable */ + GPCR = 0x00050f08; + +- PCDR0 = 0x130410c3; +- PCDR1 = 0x09030911; +- +- /* Clocks have changed. Notify clients */ +- clock_notifier_call_chain(); +- + return 0; + } + +diff --git a/arch/arm/boards/pcm038/pll.h b/arch/arm/boards/pcm038/pll.h +new file mode 100644 +index 0000000..13a7989 +--- /dev/null ++++ b/arch/arm/boards/pcm038/pll.h +@@ -0,0 +1,70 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/** ++ * @file ++ * @brief phyCORE-i.MX27 specific PLL setup ++ */ ++ ++#ifndef __PCM038_PLL_H ++#define __PCM038_PLL_H ++ ++/* define the PLL setting we want to run the system */ ++ ++/* main clock divider settings immediately after reset (at 1.25 V core supply) */ ++#define CSCR_VAL (CSCR_USB_DIV(3) | \ ++ CSCR_SD_CNT(3) | \ ++ CSCR_MSHC_SEL | \ ++ CSCR_H264_SEL | \ ++ CSCR_SSI1_SEL | \ ++ CSCR_SSI2_SEL | \ ++ CSCR_SP_SEL | /* 26 MHz reference */ \ ++ CSCR_MCU_SEL | /* 26 MHz reference */ \ ++ CSCR_ARM_DIV(0) | /* CPU runs at MPLL/3 clock */ \ ++ CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ ++ CSCR_SPEN | \ ++ CSCR_MPEN) ++ ++/* main clock divider settings after core voltage increases to 1.45 V */ ++#define CSCR_VAL_FINAL (CSCR_USB_DIV(3) | \ ++ CSCR_SD_CNT(3) | \ ++ CSCR_MSHC_SEL | \ ++ CSCR_H264_SEL | \ ++ CSCR_SSI1_SEL | \ ++ CSCR_SSI2_SEL | \ ++ CSCR_SP_SEL | /* 26 MHz reference */ \ ++ CSCR_MCU_SEL | /* 26 MHz reference */ \ ++ CSCR_ARM_SRC_MPLL | /* use main MPLL clock */ \ ++ CSCR_ARM_DIV(0) | /* CPU run at full MPLL clock */ \ ++ CSCR_AHB_DIV(1) | /* AHB runs at MPLL/6 clock */ \ ++ CSCR_SPEN | \ ++ CSCR_MPEN) ++ ++/* MPLL should provide a 399 MHz clock from the 26 MHz reference */ ++#define MPCTL0_VAL (IMX_PLL_PD(0) | \ ++ IMX_PLL_MFD(51) | \ ++ IMX_PLL_MFI(7) | \ ++ IMX_PLL_MFN(35)) ++ ++/* SPLL should provide a 240 MHz clock from the 26 MHz reference */ ++#define SPCTL0_VAL (IMX_PLL_PD(1) | \ ++ IMX_PLL_MFD(12) | \ ++ IMX_PLL_MFI(9) | \ ++ IMX_PLL_MFN(3)) ++ ++ ++#endif /* __PCM038_PLL_H */ +diff --git a/arch/arm/boards/pcm038/pll_init.S b/arch/arm/boards/pcm038/pll_init.S +deleted file mode 100644 +index 0c1ff13..0000000 +--- a/arch/arm/boards/pcm038/pll_init.S ++++ /dev/null +@@ -1,48 +0,0 @@ +-#include <config.h> +-#include <mach/imx-regs.h> +-#include <mach/imx-pll.h> +-#include <linux/linkage.h> +- +-#define writel(val, reg) \ +- ldr r0, =reg; \ +- ldr r1, =val; \ +- str r1, [r0]; +- +-#define CSCR_VAL CSCR_USB_DIV(3) | \ +- CSCR_SD_CNT(3) | \ +- CSCR_MSHC_SEL | \ +- CSCR_H264_SEL | \ +- CSCR_SSI1_SEL | \ +- CSCR_SSI2_SEL | \ +- CSCR_MCU_SEL | \ +- CSCR_ARM_SRC_MPLL | \ +- CSCR_SP_SEL | \ +- CSCR_ARM_DIV(0) | \ +- CSCR_FPM_EN | \ +- CSCR_SPEN | \ +- CSCR_MPEN | \ +- CSCR_AHB_DIV(1) +- +-ENTRY(pcm038_pll_init) +- +- writel(IMX_PLL_PD(0) | +- IMX_PLL_MFD(51) | +- IMX_PLL_MFI(7) | +- IMX_PLL_MFN(35), MPCTL0) /* 399 MHz */ +- +- writel(IMX_PLL_PD(1) | +- IMX_PLL_MFD(12) | +- IMX_PLL_MFI(9) | +- IMX_PLL_MFN(3), SPCTL0) /* SPLL = 2 * 26 * 4.61538 MHz = 240 MHz */ +- +- writel(CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART, CSCR) +- +- ldr r2, =16000 +-1: +- subs r2, r2, #1 +- nop +- bcs 1b +- +- mov pc, lr +-ENDPROC(pcm038_pll_init) +- +diff --git a/arch/arm/boards/pcm043/pcm043.c b/arch/arm/boards/pcm043/pcm043.c +index 9f98795..2191bc8 100644 +--- a/arch/arm/boards/pcm043/pcm043.c ++++ b/arch/arm/boards/pcm043/pcm043.c +@@ -43,6 +43,7 @@ + #include <mach/imx-ipu-fb.h> + #include <mach/imx-pll.h> + #include <mach/iomux-mx35.h> ++#include <mach/devices-imx35.h> + + /* + * Up to 32MiB NOR type flash, connected to +@@ -59,13 +60,6 @@ static struct fec_platform_data fec_info = { + .xcv_type = MII100, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = IMX_FEC_BASE, +- .platform_data = &fec_info, +-}; +- + static struct memory_platform_data ram_pdata = { + .name = "ram0", + .flags = DEVFS_RDWR, +@@ -85,15 +79,8 @@ struct imx_nand_platform_data nand_info = { + .flash_bbt = 1, + }; + +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = IMX_NFC_BASE, +- .platform_data = &nand_info, +-}; +- + #ifdef CONFIG_PCM043_DISPLAY_SHARP +-static const struct fb_videomode pcm043_fb_mode = { ++static struct fb_videomode pcm043_fb_mode = { + /* 240x320 @ 60 Hz */ + .name = "Sharp-LQ035Q7", + .refresh = 60, +@@ -111,7 +98,7 @@ static const struct fb_videomode pcm043_fb_mode = { + .flag = 0, + }; + #else +-static const struct fb_videomode pcm043_fb_mode = { ++static struct fb_videomode pcm043_fb_mode = { + /* 240x320 @ 60 Hz */ + .name = "TX090", + .refresh = 60, +@@ -135,14 +122,6 @@ static struct imx_ipu_fb_platform_data ipu_fb_data = { + .bpp = 16, + }; + +-static struct device_d imx_ipu_fb_dev = { +- .id = -1, +- .name = "imx-ipu-fb", +- .map_base = 0x53fc0000, +- .size = 0x1000, +- .platform_data = &ipu_fb_data, +-}; +- + #ifdef CONFIG_MMU + static int pcm043_mmu_init(void) + { +@@ -185,11 +164,11 @@ static int imx35_devices_init(void) + else + nand_info.width = 1; /* 8 bit */ + +- register_device(&fec_dev); ++ imx35_add_fec(&fec_info); + /* + * This platform supports NOR and NAND + */ +- register_device(&nand_dev); ++ imx35_add_nand(&nand_info); + register_device(&cfi_dev); + + if ((reg & 0xc00) == 0x800) { /* reset mode: external boot */ +@@ -210,7 +189,7 @@ static int imx35_devices_init(void) + } + + register_device(&sdram0_dev); +- register_device(&imx_ipu_fb_dev); ++ imx35_add_fb(&ipu_fb_data); + + armlinux_add_dram(&sdram0_dev); + armlinux_set_bootparams((void *)0x80000100); +@@ -221,13 +200,6 @@ static int imx35_devices_init(void) + + device_initcall(imx35_devices_init); + +-static struct device_d imx35_serial_device = { +- .id = -1, +- .name = "imx_serial", +- .map_base = IMX_UART1_BASE, +- .size = 16 * 1024, +-}; +- + static struct pad_desc pcm043_pads[] = { + MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, + MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, +@@ -261,7 +233,7 @@ static int imx35_console_init(void) + { + mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); + +- register_device(&imx35_serial_device); ++ imx35_add_uart0(); + return 0; + } + +diff --git a/arch/arm/boards/phycard-i.MX27/pca100.c b/arch/arm/boards/phycard-i.MX27/pca100.c +index 7328a6c..32f7e74 100644 +--- a/arch/arm/boards/phycard-i.MX27/pca100.c ++++ b/arch/arm/boards/phycard-i.MX27/pca100.c +@@ -1,4 +1,4 @@ +- /* ++/* + * Copyright (C) 2007 Sascha Hauer, Pengutronix + * + * This program is free software; you can redistribute it and/or +@@ -39,6 +39,7 @@ + #include <asm/mmu.h> + #include <usb/isp1504.h> + #include <mach/iomux-mx27.h> ++#include <mach/devices-imx27.h> + + static struct memory_platform_data ram_pdata = { + .name = "ram0", +@@ -58,23 +59,10 @@ static struct fec_platform_data fec_info = { + .phy_addr = 1, + }; + +-static struct device_d fec_dev = { +- .id = -1, +- .name = "fec_imx", +- .map_base = 0x1002b000, +- .platform_data = &fec_info, +-}; +- + struct imx_nand_platform_data nand_info = { + .width = 1, + .hw_ecc = 1, +-}; +- +-static struct device_d nand_dev = { +- .id = -1, +- .name = "imx_nand", +- .map_base = 0xd8000000, +- .platform_data = &nand_info, ++ .flash_bbt = 1, + }; + + #ifdef CONFIG_USB +@@ -180,8 +168,17 @@ static int pca100_devices_init(void) + PD23_AF_USBH2_DATA2, + PD24_AF_USBH2_DATA1, + PD26_AF_USBH2_DATA5, ++ /* SDHC */ ++ PB4_PF_SD2_D0, ++ PB5_PF_SD2_D1, ++ PB6_PF_SD2_D2, ++ PB7_PF_SD2_D3, ++ PB8_PF_SD2_CMD, ++ PB9_PF_SD2_CLK, + }; + ++ PCCR0 |= PCCR0_SDHC2_EN; ++ + /* disable the usb phys */ + imx_gpio_mode((GPIO_PORTB | 23) | GPIO_GPIO | GPIO_IN); + gpio_direction_output(GPIO_PORTB + 23, 1); +@@ -192,9 +189,10 @@ static int pca100_devices_init(void) + for (i = 0; i < ARRAY_SIZE(mode); i++) + imx_gpio_mode(mode[i]); + +- register_device(&nand_dev); ++ imx27_add_nand(&nand_info); + register_device(&sdram_dev); +- register_device(&fec_dev); ++ imx27_add_fec(&fec_info); ++ imx27_add_mmc0(NULL); + + PCCR1 |= PCCR1_PERCLK2_EN; + +diff --git a/arch/arm/boards/pm9261/Makefile b/arch/arm/boards/pm9261/Makefile +new file mode 100644 +index 0000000..eb072c0 +--- /dev/null ++++ b/arch/arm/boards/pm9261/Makefile +@@ -0,0 +1 @@ ++obj-y += init.o +diff --git a/arch/arm/boards/pm9261/config.h b/arch/arm/boards/pm9261/config.h +new file mode 100644 +index 0000000..97f8efc +--- /dev/null ++++ b/arch/arm/boards/pm9261/config.h +@@ -0,0 +1,110 @@ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ ++ ++#define MASTER_PLL_DIV 15 ++#define MASTER_PLL_MUL 162 ++#define MAIN_PLL_DIV 2 ++ ++/* clocks */ ++#define CONFIG_SYS_MOR_VAL \ ++ (AT91_PMC_MOSCEN | \ ++ (255 << 8)) /* Main Oscillator Start-up Time */ ++#define CONFIG_SYS_PLLAR_VAL \ ++ (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ ++ AT91_PMC_OUT | \ ++ ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) ++ ++/* PCK/2 = MCK Master Clock from PLLA */ ++#define CONFIG_SYS_MCKR1_VAL \ ++ (AT91_PMC_CSS_SLOW | \ ++ AT91_PMC_PRES_1 | \ ++ AT91SAM9_PMC_MDIV_2 | \ ++ AT91_PMC_PDIV_1) ++ ++/* PCK/2 = MCK Master Clock from PLLA */ ++#define CONFIG_SYS_MCKR2_VAL \ ++ (AT91_PMC_CSS_PLLA | \ ++ AT91_PMC_PRES_1 | \ ++ AT91SAM9_PMC_MDIV_2 | \ ++ AT91_PMC_PDIV_1) ++ ++/* define PDC[31:16] as DATA[31:16] */ ++#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 ++/* no pull-up for D[31:16] */ ++#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 ++ ++/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ ++#define CONFIG_SYS_MATRIX_EBICSA_VAL \ ++ (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) ++ ++/* SDRAM */ ++/* SDRAMC_MR Mode register */ ++#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL ++/* SDRAMC_TR - Refresh Timer register */ ++#define CONFIG_SYS_SDRC_TR_VAL1 0x13C ++/* SDRAMC_CR - Configuration register*/ ++#define CONFIG_SYS_SDRC_CR_VAL \ ++ (AT91_SDRAMC_NC_9 | \ ++ AT91_SDRAMC_NR_13 | \ ++ AT91_SDRAMC_NB_4 | \ ++ AT91_SDRAMC_CAS_3 | \ ++ AT91_SDRAMC_DBW_32 | \ ++ (1 << 8) | /* Write Recovery Delay */ \ ++ (7 << 12) | /* Row Cycle Delay */ \ ++ (3 << 16) | /* Row Precharge Delay */ \ ++ (2 << 20) | /* Row to Column Delay */ \ ++ (5 << 24) | /* Active to Precharge Delay */ \ ++ (1 << 28)) /* Exit Self Refresh to Active Delay */ ++ ++/* Memory Device Register -> SDRAM */ ++#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM ++#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE ++#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH ++#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR ++#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL ++#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ ++#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ ++#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ ++ ++/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ ++#define CONFIG_SYS_SMC0_SETUP0_VAL \ ++ (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ ++ AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) ++#define CONFIG_SYS_SMC0_PULSE0_VAL \ ++ (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ ++ AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) ++#define CONFIG_SYS_SMC0_CYCLE0_VAL \ ++ (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) ++#define CONFIG_SYS_SMC0_MODE0_VAL \ ++ (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ ++ AT91_SMC_DBW_16 | \ ++ AT91_SMC_TDFMODE | \ ++ AT91_SMC_TDF_(6)) ++ ++/* user reset enable */ ++#define CONFIG_SYS_RSTC_RMR_VAL \ ++ (AT91_RSTC_KEY | \ ++ AT91_RSTC_PROCRST | \ ++ AT91_RSTC_RSTTYP_WAKEUP | \ ++ AT91_RSTC_RSTTYP_WATCHDOG) ++ ++/* Disable Watchdog */ ++#define CONFIG_SYS_WDTC_WDMR_VAL \ ++ (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ ++ AT91_WDT_WDV | \ ++ AT91_WDT_WDDIS | \ ++ AT91_WDT_WDD) ++ ++#endif /* __CONFIG_H */ +diff --git a/arch/arm/boards/pm9261/env/config b/arch/arm/boards/pm9261/env/config +new file mode 100644 +index 0000000..f7e133e +--- /dev/null ++++ b/arch/arm/boards/pm9261/env/config +@@ -0,0 +1,41 @@ ++#!/bin/sh ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration ++ip=dhcp ++ ++# or set your networking parameters here ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'net' or 'nand' ++kernel_loc=net ++# can be either 'net', 'nand' or 'initrd' ++rootfs_loc=net ++ ++# can be either 'jffs2' or 'ubifs' ++rootfs_type=ubifs ++rootfsimage=root.$rootfs_type ++ ++# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo ++#kernelimage_type=zimage ++#kernelimage=zImage ++kernelimage_type=uimage ++kernelimage=uImage ++#kernelimage_type=raw ++#kernelimage=Image ++#kernelimage_type=raw_lzo ++#kernelimage=Image.lzo ++ ++nor_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" ++rootfs_mtdblock_nor=3 ++ ++autoboot_timeout=3 ++ ++bootargs="console=ttyS0,115200" ++ ++# set a fancy prompt (if support is compiled in) ++PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " ++ +diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c +new file mode 100644 +index 0000000..6fb14f7 +--- /dev/null ++++ b/arch/arm/boards/pm9261/init.c +@@ -0,0 +1,168 @@ ++/* ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <net.h> ++#include <init.h> ++#include <environment.h> ++#include <asm/armlinux.h> ++#include <generated/mach-types.h> ++#include <partition.h> ++#include <fs.h> ++#include <fcntl.h> ++#include <asm/io.h> ++#include <asm/hardware.h> ++#include <nand.h> ++#include <linux/mtd/nand.h> ++#include <mach/at91_pmc.h> ++#include <mach/board.h> ++#include <mach/gpio.h> ++#include <mach/io.h> ++#include <mach/at91sam9_smc.h> ++#include <mach/sam9_smc.h> ++#include <dm9000.h> ++ ++static struct atmel_nand_data nand_pdata = { ++ .ale = 22, ++ .cle = 21, ++/* .det_pin = ... not connected */ ++ .rdy_pin = AT91_PIN_PA16, ++ .enable_pin = AT91_PIN_PC14, ++#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16) ++ .bus_width_16 = 1, ++#else ++ .bus_width_16 = 0, ++#endif ++}; ++ ++static struct sam9_smc_config pm_nand_smc_config = { ++ .ncs_read_setup = 0, ++ .nrd_setup = 1, ++ .ncs_write_setup = 0, ++ .nwe_setup = 1, ++ ++ .ncs_read_pulse = 3, ++ .nrd_pulse = 3, ++ .ncs_write_pulse = 3, ++ .nwe_pulse = 3, ++ ++ .read_cycle = 5, ++ .write_cycle = 5, ++ ++ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, ++ .tdf_cycles = 2, ++}; ++ ++static void pm_add_device_nand(void) ++{ ++ /* setup bus-width (8 or 16) */ ++ if (nand_pdata.bus_width_16) ++ pm_nand_smc_config.mode |= AT91_SMC_DBW_16; ++ else ++ pm_nand_smc_config.mode |= AT91_SMC_DBW_8; ++ ++ /* configure chip-select 3 (NAND) */ ++ sam9_smc_configure(3, &pm_nand_smc_config); ++ ++ at91_add_device_nand(&nand_pdata); ++} ++ ++/* ++ * DM9000 ethernet device ++ */ ++#if defined(CONFIG_DRIVER_NET_DM9000) ++static struct dm9000_platform_data dm9000_data = { ++ .iobase = AT91_CHIPSELECT_2, ++ .iodata = AT91_CHIPSELECT_2 + 4, ++ .buswidth = DM9000_WIDTH_16, ++ .srom = 1, ++}; ++ ++static struct device_d dm9000_dev = { ++ .id = 0, ++ .name = "dm9000", ++ .map_base = AT91_CHIPSELECT_2, ++ .size = 8, ++ .platform_data = &dm9000_data, ++}; ++ ++/* ++ * SMC timings for the DM9000. ++ * Note: These timings were calculated for MASTER_CLOCK = 100000000 according to the DM9000 timings. ++ */ ++static struct sam9_smc_config __initdata dm9000_smc_config = { ++ .ncs_read_setup = 0, ++ .nrd_setup = 2, ++ .ncs_write_setup = 0, ++ .nwe_setup = 2, ++ ++ .ncs_read_pulse = 8, ++ .nrd_pulse = 4, ++ .ncs_write_pulse = 8, ++ .nwe_pulse = 4, ++ ++ .read_cycle = 16, ++ .write_cycle = 16, ++ ++ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16, ++ .tdf_cycles = 1, ++}; ++ ++static void __init pm_add_device_dm9000(void) ++{ ++ /* Configure chip-select 2 (DM9000) */ ++ sam9_smc_configure(2, &dm9000_smc_config); ++ ++ register_device(&dm9000_dev); ++} ++#else ++static void __init ek_add_device_dm9000(void) {} ++#endif /* CONFIG_DRIVER_NET_DM9000 */ ++ ++static struct device_d cfi_dev = { ++ .id = 0, ++ .name = "cfi_flash", ++ .map_base = AT91_CHIPSELECT_0, ++ .size = 4 * 1024 * 1024, ++}; ++ ++static int pm9261_devices_init(void) ++{ ++ at91_add_device_sdram(64 * 1024 * 1024); ++ pm_add_device_nand(); ++ register_device(&cfi_dev); ++ pm_add_device_dm9000(); ++ ++ devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self"); ++ devfs_add_partition("nor0", 0x40000, 0x10000, PARTITION_FIXED, "env0"); ++ ++ armlinux_set_bootparams((void *)(AT91_CHIPSELECT_1 + 0x100)); ++ armlinux_set_architecture(MACH_TYPE_PM9261); ++ ++ return 0; ++} ++device_initcall(pm9261_devices_init); ++ ++static int pm9261_console_init(void) ++{ ++ at91_register_uart(0, 0); ++ return 0; ++} ++console_initcall(pm9261_console_init); +diff --git a/arch/arm/boards/pm9g45/Makefile b/arch/arm/boards/pm9g45/Makefile +new file mode 100644 +index 0000000..eb072c0 +--- /dev/null ++++ b/arch/arm/boards/pm9g45/Makefile +@@ -0,0 +1 @@ ++obj-y += init.o +diff --git a/arch/arm/boards/pm9g45/config.h b/arch/arm/boards/pm9g45/config.h +new file mode 100644 +index 0000000..ac3114d +--- /dev/null ++++ b/arch/arm/boards/pm9g45/config.h +@@ -0,0 +1,6 @@ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ ++ ++#endif /* __CONFIG_H */ +diff --git a/arch/arm/boards/pm9g45/env/config b/arch/arm/boards/pm9g45/env/config +new file mode 100644 +index 0000000..3b92233 +--- /dev/null ++++ b/arch/arm/boards/pm9g45/env/config +@@ -0,0 +1,41 @@ ++#!/bin/sh ++ ++# use 'dhcp' to do dhcp in barebox and in kernel ++# use 'none' if you want to skip kernel ip autoconfiguration ++ip=dhcp ++ ++# or set your networking parameters here ++#eth0.ipaddr=a.b.c.d ++#eth0.netmask=a.b.c.d ++#eth0.gateway=a.b.c.d ++#eth0.serverip=a.b.c.d ++ ++# can be either 'net' or 'nand' ++kernel_loc=net ++# can be either 'net', 'nand' or 'initrd' ++rootfs_loc=net ++ ++# can be either 'jffs2' or 'ubifs' ++rootfs_type=ubifs ++rootfsimage=root.$rootfs_type ++ ++# The image type of the kernel. Can be uimage, zimage, raw, or raw_lzo ++#kernelimage_type=zimage ++#kernelimage=zImage ++kernelimage_type=uimage ++kernelimage=uImage ++#kernelimage_type=raw ++#kernelimage=Image ++#kernelimage_type=raw_lzo ++#kernelimage=Image.lzo ++ ++nand_parts="256k(barebox)ro,64k(bareboxenv),1536k(kernel),-(root)" ++rootfs_mtdblock_nand=3 ++ ++autoboot_timeout=3 ++ ++bootargs="console=ttyS0,115200" ++ ++# set a fancy prompt (if support is compiled in) ++PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m " ++ +diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c +new file mode 100644 +index 0000000..8031ce5 +--- /dev/null ++++ b/arch/arm/boards/pm9g45/init.c +@@ -0,0 +1,108 @@ ++/* ++ * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnio@jcrosoft.com> ++ * ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <net.h> ++#include <init.h> ++#include <environment.h> ++#include <asm/armlinux.h> ++#include <generated/mach-types.h> ++#include <partition.h> ++#include <fs.h> ++#include <fcntl.h> ++#include <asm/io.h> ++#include <asm/hardware.h> ++#include <nand.h> ++#include <linux/mtd/nand.h> ++#include <mach/at91_pmc.h> ++#include <mach/board.h> ++#include <mach/gpio.h> ++#include <mach/io.h> ++#include <mach/at91sam9_smc.h> ++#include <mach/sam9_smc.h> ++ ++static struct atmel_nand_data nand_pdata = { ++ .ale = 21, ++ .cle = 22, ++/* .det_pin = ... not connected */ ++ .rdy_pin = AT91_PIN_PD3, ++ .enable_pin = AT91_PIN_PC14, ++ .bus_width_16 = 0, ++}; ++ ++static struct sam9_smc_config pm_nand_smc_config = { ++ .ncs_read_setup = 0, ++ .nrd_setup = 1, ++ .ncs_write_setup = 0, ++ .nwe_setup = 1, ++ ++ .ncs_read_pulse = 2, ++ .nrd_pulse = 3, ++ .ncs_write_pulse = 3, ++ .nwe_pulse = 4, ++ ++ .read_cycle = 4, ++ .write_cycle = 7, ++ ++ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, ++ .tdf_cycles = 3, ++}; ++ ++static void pm_add_device_nand(void) ++{ ++ pm_nand_smc_config.mode |= AT91_SMC_DBW_8; ++ ++ /* configure chip-select 3 (NAND) */ ++ sam9_smc_configure(3, &pm_nand_smc_config); ++ ++ at91_add_device_nand(&nand_pdata); ++} ++ ++static struct at91_ether_platform_data macb_pdata = { ++ .flags = AT91SAM_ETHER_RMII, ++ .phy_addr = 0, ++}; ++ ++static int pm9g45_devices_init(void) ++{ ++ at91_add_device_sdram(128 * 1024 * 1024); ++ pm_add_device_nand(); ++ at91_add_device_eth(&macb_pdata); ++ ++ devfs_add_partition("nand0", 0x00000, 0x80000, PARTITION_FIXED, "self_raw"); ++ dev_add_bb_dev("self_raw", "self0"); ++ devfs_add_partition("nand0", 0x40000, 0x40000, PARTITION_FIXED, "env_raw"); ++ dev_add_bb_dev("env_raw", "env0"); ++ ++ armlinux_set_bootparams((void *)(AT91_CHIPSELECT_6 + 0x100)); ++ armlinux_set_architecture(MACH_TYPE_PM9G45); ++ ++ return 0; ++} ++device_initcall(pm9g45_devices_init); ++ ++static int pm9g45_console_init(void) ++{ ++ at91_register_uart(0, 0); ++ return 0; ++} ++console_initcall(pm9g45_console_init); +diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig +new file mode 100644 +index 0000000..c753eb3 +--- /dev/null ++++ b/arch/arm/configs/at91sam9261ek_defconfig +@@ -0,0 +1,49 @@ ++CONFIG_ARCH_AT91SAM9261=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_PROMPT="9261-EK:" ++CONFIG_LONGHELP=y ++CONFIG_GLOB=y ++CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_MENU=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9261ek/env" ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_MENU=y ++CONFIG_CMD_MENU_MANAGEMENT=y ++CONFIG_CMD_PASSWD=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_LOADB=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MTEST=y ++CONFIG_CMD_FLASH=y ++CONFIG_CMD_BOOTM_ZLIB=y ++CONFIG_CMD_BOOTM_BZLIB=y ++CONFIG_CMD_BOOTM_SHOW_TYPE=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_UNLZO=y ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++CONFIG_NET_NFS=y ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++CONFIG_NET_TFTP_PUSH=y ++CONFIG_NET_RESOLV=y ++CONFIG_DRIVER_NET_DM9000=y ++# CONFIG_SPI is not set ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_NAND_ATMEL=y ++CONFIG_UBI=y +diff --git a/arch/arm/configs/at91sam9g10ek_defconfig b/arch/arm/configs/at91sam9g10ek_defconfig +new file mode 100644 +index 0000000..d39639a +--- /dev/null ++++ b/arch/arm/configs/at91sam9g10ek_defconfig +@@ -0,0 +1,41 @@ ++CONFIG_ARCH_AT91SAM9G10=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_PROMPT="9G10-EK:" ++CONFIG_LONGHELP=y ++CONFIG_GLOB=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9261ek/env" ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_CRC=y ++CONFIG_CMD_MTEST=y ++CONFIG_CMD_FLASH=y ++CONFIG_CMD_BOOTM_ZLIB=y ++CONFIG_CMD_BOOTM_BZLIB=y ++CONFIG_CMD_BOOTM_SHOW_TYPE=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_UNLZO=y ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++CONFIG_NET_NFS=y ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++CONFIG_DRIVER_NET_DM9000=y ++# CONFIG_SPI is not set ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_NAND_ATMEL=y ++CONFIG_UBI=y +diff --git a/arch/arm/configs/at91sam9m10g45ek_defconfig b/arch/arm/configs/at91sam9m10g45ek_defconfig +new file mode 100644 +index 0000000..e1c6cef +--- /dev/null ++++ b/arch/arm/configs/at91sam9m10g45ek_defconfig +@@ -0,0 +1,55 @@ ++CONFIG_ARCH_AT91SAM9G45=y ++CONFIG_MACH_AT91SAM9M10G45EK=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_PROMPT="9M10G45-EK:" ++CONFIG_LONGHELP=y ++CONFIG_GLOB=y ++CONFIG_PROMPT_HUSH_PS2="y" ++CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_MENU=y ++CONFIG_PASSWD_SUM_SHA1=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/at91sam9m10g45ek/env" ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_MENU=y ++CONFIG_CMD_MENU_MANAGEMENT=y ++CONFIG_CMD_PASSWD=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_LOADB=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MTEST=y ++CONFIG_CMD_MTEST_ALTERNATIVE=y ++CONFIG_CMD_FLASH=y ++CONFIG_CMD_BOOTM_ZLIB=y ++CONFIG_CMD_BOOTM_BZLIB=y ++CONFIG_CMD_BOOTM_SHOW_TYPE=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_UNLZO=y ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++CONFIG_NET_NFS=y ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++CONFIG_NET_TFTP_PUSH=y ++CONFIG_NET_NETCONSOLE=y ++CONFIG_NET_RESOLV=y ++CONFIG_DRIVER_NET_MACB=y ++# CONFIG_SPI is not set ++CONFIG_DRIVER_CFI=y ++CONFIG_CFI_BUFFER_WRITE=y ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_UBI=y +diff --git a/arch/arm/configs/chumbyone_defconfig b/arch/arm/configs/chumbyone_defconfig +new file mode 100644 +index 0000000..595b6a9 +--- /dev/null ++++ b/arch/arm/configs/chumbyone_defconfig +@@ -0,0 +1,29 @@ ++CONFIG_ARCH_STM=y ++CONFIG_MACH_CHUMBY=y ++CONFIG_AEABI=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_BROKEN=y ++CONFIG_PROMPT="chumby:" ++CONFIG_LONGHELP=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/chumby_falconwing/env" ++CONFIG_DEBUG_INFO=y ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_MTEST=y ++CONFIG_CMD_MTEST_ALTERNATIVE=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++# CONFIG_SPI is not set ++CONFIG_MCI=y ++CONFIG_MCI_STARTUP=y ++CONFIG_MCI_STM378X=y +diff --git a/arch/arm/configs/cupid_defconfig b/arch/arm/configs/cupid_defconfig +new file mode 100644 +index 0000000..e24afe1 +--- /dev/null ++++ b/arch/arm/configs/cupid_defconfig +@@ -0,0 +1,56 @@ ++CONFIG_ARCH_IMX=y ++CONFIG_CACHE_L2X0=y ++CONFIG_ARCH_IMX35=y ++CONFIG_MACH_GUF_CUPID=y ++CONFIG_IMX_CLKO=y ++CONFIG_AEABI=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_MMU=y ++CONFIG_TEXT_BASE=0x87F00000 ++CONFIG_MALLOC_SIZE=0x1000000 ++CONFIG_LONGHELP=y ++CONFIG_GLOB=y ++CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_MENU=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/guf-cupid/env" ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_FLASH=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_BMP=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_UNLZO=y ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++CONFIG_NET_NFS=y ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++CONFIG_NET_TFTP_PUSH=y ++CONFIG_NET_NETCONSOLE=y ++CONFIG_NET_RESOLV=y ++CONFIG_DRIVER_NET_FEC_IMX=y ++# CONFIG_SPI is not set ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_NAND_IMX=y ++CONFIG_NAND_IMX_BOOT=y ++CONFIG_NAND_IMX_BOOT_2K=y ++CONFIG_UBI=y ++CONFIG_VIDEO=y ++CONFIG_DRIVER_VIDEO_IMX_IPU=y ++CONFIG_MCI=y ++CONFIG_MCI_IMX_ESDHC=y +diff --git a/arch/arm/configs/eukrea_cpuimx25_defconfig b/arch/arm/configs/eukrea_cpuimx25_defconfig +index feb758e..bc68804 100644 +--- a/arch/arm/configs/eukrea_cpuimx25_defconfig ++++ b/arch/arm/configs/eukrea_cpuimx25_defconfig +@@ -9,6 +9,7 @@ CONFIG_LONGHELP=y + CONFIG_GLOB=y + CONFIG_PROMPT_HUSH_PS2="cpuimx25>" + CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_HUSH_GETOPT=y + CONFIG_CMDLINE_EDITING=y + CONFIG_AUTO_COMPLETE=y + CONFIG_PARTITION=y +@@ -23,6 +24,7 @@ CONFIG_CMD_READLINE=y + CONFIG_CMD_ECHO_E=y + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_CRC=y ++CONFIG_CMD_CRC_CMP=y + CONFIG_CMD_MTEST=y + CONFIG_CMD_FLASH=y + CONFIG_CMD_BOOTM_ZLIB=y +@@ -35,15 +37,23 @@ CONFIG_CMD_PARTITION=y + CONFIG_CMD_BMP=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_UNLZO=y ++CONFIG_CMD_I2C=y + CONFIG_NET=y + CONFIG_NET_DHCP=y + CONFIG_NET_PING=y + CONFIG_NET_TFTP=y + CONFIG_DRIVER_NET_FEC_IMX=y + # CONFIG_SPI is not set ++CONFIG_I2C=y ++CONFIG_I2C_IMX=y + CONFIG_MTD=y + CONFIG_NAND=y + CONFIG_NAND_IMX=y +-CONFIG_NAND_IMX_BOOT=y ++CONFIG_USB=y ++CONFIG_USB_EHCI=y ++CONFIG_USB_GADGET=y + CONFIG_VIDEO=y + CONFIG_DRIVER_VIDEO_IMX=y ++CONFIG_MCI=y ++CONFIG_MCI_IMX_ESDHC=y ++CONFIG_MCI_IMX_ESDHC_PIO=y +diff --git a/arch/arm/configs/eukrea_cpuimx35_defconfig b/arch/arm/configs/eukrea_cpuimx35_defconfig +index 975d095..af82827 100644 +--- a/arch/arm/configs/eukrea_cpuimx35_defconfig ++++ b/arch/arm/configs/eukrea_cpuimx35_defconfig +@@ -8,8 +8,11 @@ CONFIG_MALLOC_SIZE=0x800000 + CONFIG_LONGHELP=y + CONFIG_GLOB=y + CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_HUSH_GETOPT=y + CONFIG_CMDLINE_EDITING=y + CONFIG_AUTO_COMPLETE=y ++# CONFIG_CONSOLE_ACTIVATE_FIRST is not set ++CONFIG_CONSOLE_ACTIVATE_ALL=y + CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/eukrea_cpuimx35/env" + CONFIG_CMD_EDIT=y + CONFIG_CMD_SLEEP=y +@@ -22,6 +25,7 @@ CONFIG_CMD_ECHO_E=y + CONFIG_CMD_LOADB=y + CONFIG_CMD_MEMINFO=y + CONFIG_CMD_CRC=y ++CONFIG_CMD_CRC_CMP=y + CONFIG_CMD_MTEST=y + CONFIG_CMD_FLASH=y + CONFIG_CMD_RESET=y +@@ -31,15 +35,23 @@ CONFIG_CMD_PARTITION=y + CONFIG_CMD_BMP=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_UNLZO=y ++CONFIG_CMD_I2C=y + CONFIG_NET=y + CONFIG_NET_DHCP=y + CONFIG_NET_PING=y + CONFIG_NET_TFTP=y + CONFIG_DRIVER_NET_FEC_IMX=y + # CONFIG_SPI is not set ++CONFIG_I2C=y ++CONFIG_I2C_IMX=y + CONFIG_MTD=y + CONFIG_NAND=y + CONFIG_NAND_IMX=y +-CONFIG_NAND_IMX_BOOT=y ++CONFIG_USB=y ++CONFIG_USB_EHCI=y ++CONFIG_USB_GADGET=y + CONFIG_VIDEO=y + CONFIG_DRIVER_VIDEO_IMX_IPU=y ++CONFIG_MCI=y ++CONFIG_MCI_IMX_ESDHC=y ++CONFIG_MCI_IMX_ESDHC_PIO=y +diff --git a/arch/arm/configs/freescale_mx51_babbage_defconfig b/arch/arm/configs/freescale_mx51_babbage_defconfig +new file mode 100644 +index 0000000..d99d91a +--- /dev/null ++++ b/arch/arm/configs/freescale_mx51_babbage_defconfig +@@ -0,0 +1,43 @@ ++CONFIG_ARCH_IMX=y ++CONFIG_ARCH_IMX_INTERNAL_BOOT=y ++CONFIG_ARCH_IMX51=y ++CONFIG_AEABI=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_MMU=y ++CONFIG_TEXT_BASE=0x97f00000 ++CONFIG_MALLOC_SIZE=0x2000000 ++CONFIG_LONGHELP=y ++CONFIG_GLOB=y ++CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/freescale-mx51-pdk/env/" ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_CRC=y ++CONFIG_CMD_FLASH=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_GPIO=y ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++CONFIG_DRIVER_NET_FEC_IMX=y ++CONFIG_DRIVER_SPI_IMX=y ++CONFIG_DRIVER_CFI=y ++CONFIG_CFI_BUFFER_WRITE=y ++CONFIG_MCI=y ++CONFIG_MCI_STARTUP=y ++CONFIG_MCI_IMX_ESDHC=y ++CONFIG_I2C_MC13892=y +diff --git a/arch/arm/configs/imx23evk_defconfig b/arch/arm/configs/imx23evk_defconfig +new file mode 100644 +index 0000000..047a7e1 +--- /dev/null ++++ b/arch/arm/configs/imx23evk_defconfig +@@ -0,0 +1,24 @@ ++CONFIG_ARCH_STM=y ++CONFIG_AEABI=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_BROKEN=y ++CONFIG_LONGHELP=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_PARTITION=y ++# CONFIG_DEFAULT_ENVIRONMENT is not set ++CONFIG_DEBUG_INFO=y ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_MTEST=y ++CONFIG_CMD_MTEST_ALTERNATIVE=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++# CONFIG_SPI is not set +diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig +new file mode 100644 +index 0000000..f289f0d +--- /dev/null ++++ b/arch/arm/configs/mini2440_defconfig +@@ -0,0 +1,251 @@ ++# ++# Automatically generated make config: don't edit ++# Linux barebox version: 2010.10.0 ++# Tue Oct 19 09:01:55 2010 ++# ++# CONFIG_BOARD_LINKER_SCRIPT is not set ++CONFIG_GENERIC_LINKER_SCRIPT=y ++CONFIG_ARM=y ++ ++# ++# System Type ++# ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_IMX is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_NOMADIK is not set ++# CONFIG_ARCH_OMAP is not set ++CONFIG_ARCH_S3C24xx=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_32=y ++CONFIG_CPU_ARM920T=y ++CONFIG_CPU_32v4T=y ++ ++# ++# processor features ++# ++CONFIG_ARCH_TEXT_BASE=0x31fc0000 ++CONFIG_BOARDINFO="Mini 2440" ++CONFIG_CPU_S3C2440=y ++# CONFIG_MACH_A9M2410 is not set ++# CONFIG_MACH_A9M2440 is not set ++CONFIG_MACH_MINI2440=y ++ ++# ++# Board specific settings ++# ++ ++# ++# S3C24X0 Features ++# ++# CONFIG_S3C24XX_PLL_INIT is not set ++# CONFIG_S3C24XX_SDRAM_INIT is not set ++CONFIG_S3C24XX_NAND_BOOT=y ++# CONFIG_AEABI is not set ++ ++# ++# Arm specific settings ++# ++CONFIG_CMD_ARM_CPUINFO=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_DEFCONFIG_LIST="$ARCH_DEFCONFIG" ++CONFIG_GREGORIAN_CALENDER=y ++CONFIG_HAS_KALLSYMS=y ++CONFIG_HAS_MODULES=y ++CONFIG_CMD_MEMORY=y ++CONFIG_ENV_HANDLING=y ++ ++# ++# General Settings ++# ++CONFIG_LOCALVERSION_AUTO=y ++ ++# ++# memory layout ++# ++CONFIG_HAVE_CONFIGURABLE_TEXT_BASE=y ++CONFIG_TEXT_BASE=0x31fc0000 ++CONFIG_HAVE_CONFIGURABLE_MEMORY_LAYOUT=y ++CONFIG_MEMORY_LAYOUT_DEFAULT=y ++# CONFIG_MEMORY_LAYOUT_FIXED is not set ++CONFIG_STACK_SIZE=0x8000 ++CONFIG_MALLOC_SIZE=0x400000 ++CONFIG_BROKEN=y ++CONFIG_EXPERIMENTAL=y ++# CONFIG_MODULES is not set ++# CONFIG_KALLSYMS is not set ++CONFIG_PROMPT="barebox:" ++CONFIG_BAUDRATE=38400 ++CONFIG_LONGHELP=y ++CONFIG_CBSIZE=1024 ++CONFIG_MAXARGS=16 ++CONFIG_SHELL_HUSH=y ++# CONFIG_SHELL_SIMPLE is not set ++CONFIG_GLOB=y ++CONFIG_PROMPT_HUSH_PS2="> " ++# CONFIG_HUSH_FANCY_PROMPT is not set ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++# CONFIG_MENU is not set ++# CONFIG_PASSWORD is not set ++CONFIG_DYNAMIC_CRC_TABLE=y ++CONFIG_ERRNO_MESSAGES=y ++CONFIG_TIMESTAMP=y ++CONFIG_CONSOLE_FULL=y ++CONFIG_CONSOLE_ACTIVATE_FIRST=y ++# CONFIG_OF_FLAT_TREE is not set ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/mini2440/env" ++ ++# ++# Debugging ++# ++CONFIG_DEBUG_INFO=y ++# CONFIG_ENABLE_FLASH_NOISE is not set ++# CONFIG_ENABLE_PARTITION_NOISE is not set ++CONFIG_ENABLE_DEVICE_NOISE=y ++ ++# ++# Commands ++# ++ ++# ++# scripting ++# ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_TRUE=y ++CONFIG_CMD_FALSE=y ++# CONFIG_CMD_LOGIN is not set ++# CONFIG_CMD_PASSWD is not set ++ ++# ++# file commands ++# ++CONFIG_CMD_LS=y ++CONFIG_CMD_RM=y ++CONFIG_CMD_CAT=y ++CONFIG_CMD_MKDIR=y ++CONFIG_CMD_RMDIR=y ++CONFIG_CMD_CP=y ++CONFIG_CMD_PWD=y ++CONFIG_CMD_CD=y ++CONFIG_CMD_MOUNT=y ++CONFIG_CMD_UMOUNT=y ++ ++# ++# console ++# ++CONFIG_CMD_CLEAR=y ++CONFIG_CMD_ECHO=y ++# CONFIG_CMD_ECHO_E is not set ++ ++# ++# memory ++# ++# CONFIG_CMD_LOADB is not set ++# CONFIG_CMD_LOADY is not set ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_CRC=y ++CONFIG_CMD_MTEST=y ++# CONFIG_CMD_MTEST_ALTERNATIVE is not set ++ ++# ++# flash ++# ++CONFIG_CMD_FLASH=y ++# CONFIG_CMD_UBI is not set ++ ++# ++# booting ++# ++CONFIG_CMD_BOOTM=y ++# CONFIG_CMD_BOOTM_ZLIB is not set ++# CONFIG_CMD_BOOTM_BZLIB is not set ++# CONFIG_CMD_BOOTM_LZO is not set ++# CONFIG_CMD_BOOTM_SHOW_TYPE is not set ++CONFIG_CMD_BOOTZ=y ++CONFIG_CMD_BOOTU=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_TEST=y ++CONFIG_CMD_VERSION=y ++CONFIG_CMD_HELP=y ++CONFIG_CMD_DEVINFO=y ++# CONFIG_CMD_UNLZO is not set ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++# CONFIG_NET_NFS is not set ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++# CONFIG_NET_TFTP_PUSH is not set ++# CONFIG_NET_NETCONSOLE is not set ++# CONFIG_NET_RESOLV is not set ++ ++# ++# Drivers ++# ++ ++# ++# serial drivers ++# ++# CONFIG_DRIVER_SERIAL_ARM_DCC is not set ++# CONFIG_DRIVER_SERIAL_NS16550 is not set ++CONFIG_DRIVER_SERIAL_S3C24X0=y ++# CONFIG_DRIVER_SERIAL_S3C24X0_AUTOSYNC is not set ++CONFIG_HAS_DM9000=y ++CONFIG_MIIDEV=y ++ ++# ++# Network drivers ++# ++# CONFIG_DRIVER_NET_SMC911X is not set ++# CONFIG_DRIVER_NET_SMC91111 is not set ++CONFIG_DRIVER_NET_DM9000=y ++ ++# ++# SPI drivers ++# ++# CONFIG_SPI is not set ++# CONFIG_I2C is not set ++ ++# ++# flash drivers ++# ++# CONFIG_DRIVER_CFI is not set ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_NAND_S3C24X0=y ++# CONFIG_MTD_NAND_VERIFY_WRITE is not set ++# CONFIG_MTD_NAND_ECC_SMC is not set ++CONFIG_MTD_NAND_IDS=y ++# CONFIG_MTD_NAND_DISKONCHIP is not set ++# CONFIG_UBI is not set ++# CONFIG_ATA is not set ++# CONFIG_USB is not set ++# CONFIG_USB_GADGET is not set ++# CONFIG_VIDEO is not set ++ ++# ++# Filesystem support ++# ++# CONFIG_FS_CRAMFS is not set ++CONFIG_FS_RAMFS=y ++CONFIG_FS_DEVFS=y ++CONFIG_CRC32=y ++# CONFIG_DIGEST is not set ++# CONFIG_GENERIC_FIND_NEXT_BIT is not set ++# CONFIG_PROCESS_ESCAPE_SEQUENCE is not set +diff --git a/arch/arm/configs/neso_defconfig b/arch/arm/configs/neso_defconfig +index 9f6e3f4..24125f9 100644 +--- a/arch/arm/configs/neso_defconfig ++++ b/arch/arm/configs/neso_defconfig +@@ -12,7 +12,8 @@ CONFIG_HUSH_FANCY_PROMPT=y + CONFIG_CMDLINE_EDITING=y + CONFIG_AUTO_COMPLETE=y + CONFIG_PARTITION=y +-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/guf-neso/env" ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/guf-neso/env" + CONFIG_CMD_EDIT=y + CONFIG_CMD_SLEEP=y + CONFIG_CMD_SAVEENV=y +diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig +index e3f4102..b81afe2 100644 +--- a/arch/arm/configs/nhk8815_defconfig ++++ b/arch/arm/configs/nhk8815_defconfig +@@ -10,7 +10,8 @@ CONFIG_AUTO_COMPLETE=y + CONFIG_MENU=y + CONFIG_PASSWD_SUM_SHA1=y + CONFIG_PARTITION=y +-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/nhk8815/env" ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/nhk8815/env" + CONFIG_CMD_EDIT=y + CONFIG_CMD_SLEEP=y + CONFIG_CMD_SAVEENV=y +@@ -22,8 +23,8 @@ CONFIG_CMD_MENU=y + CONFIG_CMD_MENU_MANAGEMENT=y + CONFIG_CMD_PASSWD=y + CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_LOADB=y + CONFIG_CMD_MEMINFO=y +-CONFIG_CMD_CRC=y + CONFIG_CMD_MTEST=y + CONFIG_CMD_FLASH=y + CONFIG_CMD_BOOTM_ZLIB=y +diff --git a/arch/arm/configs/pca100_defconfig b/arch/arm/configs/pca100_defconfig +index d1708a6..8c72bdf 100644 +--- a/arch/arm/configs/pca100_defconfig ++++ b/arch/arm/configs/pca100_defconfig +@@ -12,7 +12,8 @@ CONFIG_HUSH_FANCY_PROMPT=y + CONFIG_CMDLINE_EDITING=y + CONFIG_AUTO_COMPLETE=y + CONFIG_PARTITION=y +-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/phycard-i.MX27/env" ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/phycard-i.MX27/env" + CONFIG_CMD_EDIT=y + CONFIG_CMD_SLEEP=y + CONFIG_CMD_SAVEENV=y +diff --git a/arch/arm/configs/pcm037_defconfig b/arch/arm/configs/pcm037_defconfig +index 8e60b0a..b8ba53c 100644 +--- a/arch/arm/configs/pcm037_defconfig ++++ b/arch/arm/configs/pcm037_defconfig +@@ -10,7 +10,8 @@ CONFIG_HUSH_FANCY_PROMPT=y + CONFIG_CMDLINE_EDITING=y + CONFIG_AUTO_COMPLETE=y + CONFIG_PARTITION=y +-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm037/env" ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm037/env" + CONFIG_CMD_EDIT=y + CONFIG_CMD_SLEEP=y + CONFIG_CMD_SAVEENV=y +@@ -20,13 +21,13 @@ CONFIG_CMD_PRINTENV=y + CONFIG_CMD_READLINE=y + CONFIG_CMD_ECHO_E=y + CONFIG_CMD_MEMINFO=y +-CONFIG_CMD_CRC=y + CONFIG_CMD_FLASH=y + CONFIG_CMD_RESET=y + CONFIG_CMD_GO=y + CONFIG_CMD_TIMEOUT=y + CONFIG_CMD_PARTITION=y + CONFIG_CMD_GPIO=y ++CONFIG_CMD_UNLZO=y + CONFIG_NET=y + CONFIG_NET_DHCP=y + CONFIG_NET_PING=y +@@ -38,5 +39,9 @@ CONFIG_NET_USB=y + CONFIG_NET_USB_ASIX=y + CONFIG_DRIVER_CFI=y + CONFIG_CFI_BUFFER_WRITE=y ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_NAND_IMX=y ++CONFIG_UBI=y + CONFIG_USB=y + CONFIG_USB_EHCI=y +diff --git a/arch/arm/configs/pcm038_defconfig b/arch/arm/configs/pcm038_defconfig +index eacbbc6..2038f14 100644 +--- a/arch/arm/configs/pcm038_defconfig ++++ b/arch/arm/configs/pcm038_defconfig +@@ -13,7 +13,8 @@ CONFIG_HUSH_FANCY_PROMPT=y + CONFIG_CMDLINE_EDITING=y + CONFIG_AUTO_COMPLETE=y + CONFIG_PARTITION=y +-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm038/env" ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm038/env" + CONFIG_CMD_EDIT=y + CONFIG_CMD_SLEEP=y + CONFIG_CMD_SAVEENV=y +diff --git a/arch/arm/configs/pcm043_defconfig b/arch/arm/configs/pcm043_defconfig +index 51ca833..2dd711b 100644 +--- a/arch/arm/configs/pcm043_defconfig ++++ b/arch/arm/configs/pcm043_defconfig +@@ -13,7 +13,8 @@ CONFIG_HUSH_FANCY_PROMPT=y + CONFIG_CMDLINE_EDITING=y + CONFIG_AUTO_COMPLETE=y + CONFIG_PARTITION=y +-CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/pcm043/env" ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pcm043/env" + CONFIG_CMD_EDIT=y + CONFIG_CMD_SLEEP=y + CONFIG_CMD_SAVEENV=y +diff --git a/arch/arm/configs/pm9261_defconfig b/arch/arm/configs/pm9261_defconfig +new file mode 100644 +index 0000000..0bd9483 +--- /dev/null ++++ b/arch/arm/configs/pm9261_defconfig +@@ -0,0 +1,52 @@ ++CONFIG_ARCH_AT91SAM9261=y ++CONFIG_MACH_PM9261=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_PROMPT="PM9261:" ++CONFIG_LONGHELP=y ++CONFIG_GLOB=y ++CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_MENU=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pm9261/env/" ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_MENU=y ++CONFIG_CMD_MENU_MANAGEMENT=y ++CONFIG_CMD_PASSWD=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_LOADB=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MTEST=y ++CONFIG_CMD_FLASH=y ++CONFIG_CMD_BOOTM_ZLIB=y ++CONFIG_CMD_BOOTM_BZLIB=y ++CONFIG_CMD_BOOTM_SHOW_TYPE=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_UNLZO=y ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++CONFIG_NET_NFS=y ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++CONFIG_NET_TFTP_PUSH=y ++CONFIG_NET_RESOLV=y ++CONFIG_DRIVER_NET_DM9000=y ++# CONFIG_SPI is not set ++CONFIG_DRIVER_CFI=y ++CONFIG_CFI_BUFFER_WRITE=y ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_NAND_ATMEL=y ++CONFIG_UBI=y +diff --git a/arch/arm/configs/pm9g45_defconfig b/arch/arm/configs/pm9g45_defconfig +new file mode 100644 +index 0000000..20bfd71 +--- /dev/null ++++ b/arch/arm/configs/pm9g45_defconfig +@@ -0,0 +1,55 @@ ++CONFIG_ARCH_AT91SAM9G45=y ++CONFIG_MACH_PM9G45=y ++CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y ++CONFIG_PROMPT="pm9g45:" ++CONFIG_LONGHELP=y ++CONFIG_GLOB=y ++CONFIG_PROMPT_HUSH_PS2="y" ++CONFIG_HUSH_FANCY_PROMPT=y ++CONFIG_CMDLINE_EDITING=y ++CONFIG_AUTO_COMPLETE=y ++CONFIG_MENU=y ++CONFIG_PASSWD_SUM_SHA1=y ++CONFIG_PARTITION=y ++CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y ++CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/arm/boards/pm9g45/env" ++CONFIG_CMD_EDIT=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SAVEENV=y ++CONFIG_CMD_LOADENV=y ++CONFIG_CMD_EXPORT=y ++CONFIG_CMD_PRINTENV=y ++CONFIG_CMD_READLINE=y ++CONFIG_CMD_MENU=y ++CONFIG_CMD_MENU_MANAGEMENT=y ++CONFIG_CMD_PASSWD=y ++CONFIG_CMD_ECHO_E=y ++CONFIG_CMD_LOADB=y ++CONFIG_CMD_MEMINFO=y ++CONFIG_CMD_MTEST=y ++CONFIG_CMD_MTEST_ALTERNATIVE=y ++CONFIG_CMD_FLASH=y ++CONFIG_CMD_BOOTM_ZLIB=y ++CONFIG_CMD_BOOTM_BZLIB=y ++CONFIG_CMD_BOOTM_SHOW_TYPE=y ++CONFIG_CMD_RESET=y ++CONFIG_CMD_GO=y ++CONFIG_CMD_TIMEOUT=y ++CONFIG_CMD_PARTITION=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_UNLZO=y ++CONFIG_NET=y ++CONFIG_NET_DHCP=y ++CONFIG_NET_NFS=y ++CONFIG_NET_PING=y ++CONFIG_NET_TFTP=y ++CONFIG_NET_TFTP_PUSH=y ++CONFIG_NET_NETCONSOLE=y ++CONFIG_NET_RESOLV=y ++CONFIG_DRIVER_NET_MACB=y ++# CONFIG_SPI is not set ++CONFIG_DRIVER_CFI=y ++CONFIG_CFI_BUFFER_WRITE=y ++CONFIG_MTD=y ++CONFIG_NAND=y ++CONFIG_UBI=y +diff --git a/arch/arm/cpu/cache-l2x0.c b/arch/arm/cpu/cache-l2x0.c +index 61569d2..1ea7bab 100644 +--- a/arch/arm/cpu/cache-l2x0.c ++++ b/arch/arm/cpu/cache-l2x0.c +@@ -127,7 +127,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end) + cache_sync(); + } + +-void l2x0_flush_range(unsigned long start, unsigned long end) ++static void l2x0_flush_range(unsigned long start, unsigned long end) + { + start &= ~(CACHE_LINE_SIZE - 1); + while (start < end) { +diff --git a/arch/arm/cpu/cpu.c b/arch/arm/cpu/cpu.c +index 133d144..346f8dc 100644 +--- a/arch/arm/cpu/cpu.c ++++ b/arch/arm/cpu/cpu.c +@@ -27,6 +27,7 @@ + + #include <common.h> + #include <command.h> ++#include <cache.h> + #include <asm/mmu.h> + #include <asm/system.h> + +diff --git a/arch/arm/cpu/interrupts.c b/arch/arm/cpu/interrupts.c +index 0557172..4a0b3f8 100644 +--- a/arch/arm/cpu/interrupts.c ++++ b/arch/arm/cpu/interrupts.c +@@ -28,6 +28,14 @@ + #include <common.h> + #include <asm/ptrace.h> + ++void do_undefined_instruction (struct pt_regs *pt_regs); ++void do_software_interrupt (struct pt_regs *pt_regs); ++void do_prefetch_abort (struct pt_regs *pt_regs); ++void do_data_abort (struct pt_regs *pt_regs); ++void do_not_used (struct pt_regs *pt_regs); ++void do_fiq (struct pt_regs *pt_regs); ++void do_irq (struct pt_regs *pt_regs); ++ + #ifdef CONFIG_USE_IRQ + /* enable IRQ interrupts */ + void enable_interrupts (void) +@@ -62,7 +70,7 @@ int disable_interrupts (void) + /** + * FIXME + */ +-void bad_mode (void) ++static void bad_mode (void) + { + panic ("Resetting CPU ...\n"); + reset_cpu (0); +diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c +index 5bf31c0..08a57ce 100644 +--- a/arch/arm/cpu/mmu.c ++++ b/arch/arm/cpu/mmu.c +@@ -16,12 +16,10 @@ void arm_create_section(unsigned long virt, unsigned long phys, int size_m, + ttb[virt] = (phys << 20) | flags; + + asm volatile ( +- "mov r0, #0;" +- "mcr p15, 0, r0, c7, c6, 0;" /* flush d-cache */ +- "mcr p15, 0, r0, c8, c7, 0;" /* flush i+d-TLBs */ ++ "bl __mmu_cache_flush;" + : + : +- : "r0","memory" /* clobber list */ ++ : "r0", "r1", "r2", "r3", "r6", "r10", "r12", "cc", "memory" + ); + } + +diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile +index c1ac1aa..1d7f15a 100644 +--- a/arch/arm/lib/Makefile ++++ b/arch/arm/lib/Makefile +@@ -1,7 +1,6 @@ + obj-y += armlinux.o + obj-y += _ashldi3.o + obj-y += _ashrdi3.o +-obj-y += cache.o + obj-y += div0.o + obj-y += _divsi3.o + obj-y += _modsi3.o +diff --git a/arch/arm/lib/armlinux.c b/arch/arm/lib/armlinux.c +index 7c2cbf9..f826da6 100644 +--- a/arch/arm/lib/armlinux.c ++++ b/arch/arm/lib/armlinux.c +@@ -40,6 +40,7 @@ + #include <asm/global_data.h> + #include <asm/setup.h> + #include <asm/barebox-arm.h> ++#include <asm/armlinux.h> + + static struct tag *params; + static int armlinux_architecture = 0; +@@ -135,8 +136,7 @@ static void setup_serial_tag(void) + } + } + +-#if 0 +-static void setup_initrd_tag(ulong initrd_start, ulong initrd_end) ++static void setup_initrd_tag(image_header_t *header) + { + /* an ATAG_INITRD node tells the kernel where the compressed + * ramdisk can be found. ATAG_RDIMG is a better name, actually. +@@ -144,12 +144,11 @@ static void setup_initrd_tag(ulong initrd_start, ulong initrd_end) + params->hdr.tag = ATAG_INITRD2; + params->hdr.size = tag_size(tag_initrd); + +- params->u.initrd.start = initrd_start; +- params->u.initrd.size = initrd_end - initrd_start; ++ params->u.initrd.start = image_get_load(header); ++ params->u.initrd.size = image_get_data_size(header); + + params = tag_next(params); + } +-#endif + + static void setup_end_tag (void) + { +@@ -157,17 +156,17 @@ static void setup_end_tag (void) + params->hdr.size = 0; + } + +-static void setup_tags(void) ++static void setup_tags(struct image_data *data) + { + const char *commandline = getenv("bootargs"); + + setup_start_tag(); + setup_memory_tags(); + setup_commandline_tag(commandline); +-#if 0 +- if (initrd_start && initrd_end) +- setup_initrd_tag (initrd_start, initrd_end); +-#endif ++ ++ if (data && data->initrd) ++ setup_initrd_tag (&data->initrd->header); ++ + setup_revision_tag(); + setup_serial_tag(); + setup_end_tag(); +@@ -207,12 +206,12 @@ void armlinux_set_serial(u64 serial) + } + + #ifdef CONFIG_CMD_BOOTM +-int do_bootm_linux(struct image_data *data) ++static int do_bootm_linux(struct image_data *data) + { + void (*theKernel)(int zero, int arch, void *params); + image_header_t *os_header = &data->os->header; + +- if (image_check_type(os_header, IH_TYPE_MULTI)) { ++ if (image_get_type(os_header) == IH_TYPE_MULTI) { + printf("Multifile images not handled at the moment\n"); + return -1; + } +@@ -232,13 +231,17 @@ int do_bootm_linux(struct image_data *data) + debug("## Transferring control to Linux (at address 0x%p) ...\n", + theKernel); + +- setup_tags(); ++ setup_tags(data); + + if (relocate_image(data->os, (void *)image_get_load(os_header))) + return -1; + ++ if (data->initrd) ++ if (relocate_image(data->initrd, (void *)image_get_load(&data->initrd->header))) ++ return -1; ++ + /* we assume that the kernel is in place */ +- printf("\nStarting kernel ...\n\n"); ++ printf("\nStarting kernel %s...\n\n", data->initrd ? "with initrd " : ""); + + shutdown_barebox(); + theKernel (0, armlinux_architecture, armlinux_bootparams); +@@ -335,7 +338,7 @@ static int do_bootz(struct command *cmdtp, int argc, char *argv[]) + + printf("loaded zImage from %s with size %d\n", argv[1], header.end); + +- setup_tags(); ++ setup_tags(NULL); + + shutdown_barebox(); + theKernel(0, armlinux_architecture, armlinux_bootparams); +@@ -379,7 +382,7 @@ static int do_bootu(struct command *cmdtp, int argc, char *argv[]) + if (!theKernel) + theKernel = (void *)simple_strtoul(argv[1], NULL, 0); + +- setup_tags(); ++ setup_tags(NULL); + + shutdown_barebox(); + theKernel(0, armlinux_architecture, armlinux_bootparams); +diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c +deleted file mode 100644 +index 61ee9d3..0000000 +--- a/arch/arm/lib/cache.c ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* +- * (C) Copyright 2002 +- * Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +- +-/* for now: just dummy functions to satisfy the linker */ +- +-#include <common.h> +- +-void flush_cache (unsigned long dummy1, unsigned long dummy2) +-{ +-#ifdef CONFIG_OMAP2420 +- void arm1136_cache_flush(void); +- +- arm1136_cache_flush(); +-#endif +- return; +-} +diff --git a/arch/arm/lib/div0.c b/arch/arm/lib/div0.c +index 6267bf1..99d6b85 100644 +--- a/arch/arm/lib/div0.c ++++ b/arch/arm/lib/div0.c +@@ -20,11 +20,12 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ ++#include <common.h> ++ ++extern void __div0(void); + + /* Replacement (=dummy) for GNU/Linux division-by zero handler */ + void __div0 (void) + { +- extern void hang (void); +- + hang(); + } +diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig +index 1491161..e5bd45e 100644 +--- a/arch/arm/mach-at91/Kconfig ++++ b/arch/arm/mach-at91/Kconfig +@@ -6,10 +6,15 @@ config ARCH_TEXT_BASE + + config BOARDINFO + default "Atmel 91SAM9260-EK" if MACH_AT91SAM9260EK ++ default "Atmel at91sam9261-ek" if MACH_AT91SAM9261EK + default "Atmel at91sam9263-ek" if MACH_AT91SAM9263EK ++ default "Atmel at91sam9g10-ek" if MACH_AT91SAM9G10EK + default "Atmel at91sam9g20-ek" if MACH_AT91SAM9G20EK ++ default "Atmel at91sam9m10g45-ek" if MACH_AT91SAM9M10G45EK + default "Bucyrus MMC-CPU" if MACH_MMCCPU ++ default "Ronetix PM9261" if MACH_PM9261 + default "Ronetix PM9263" if MACH_PM9263 ++ default "Ronetix PM9G45" if MACH_PM9G45 + + config HAVE_NAND_ATMEL_BUSWIDTH_16 + bool +@@ -24,16 +29,29 @@ config ARCH_AT91SAM9260 + select CPU_ARM926T + select HAS_MACB + ++config ARCH_AT91SAM9261 ++ bool "AT91SAM9261" ++ select CPU_ARM926T ++ + config ARCH_AT91SAM9263 + bool "AT91SAM9263" + select CPU_ARM926T + select HAS_MACB + ++config ARCH_AT91SAM9G10 ++ bool "AT91SAM9G10" ++ select CPU_ARM926T ++ + config ARCH_AT91SAM9G20 + bool "AT91SAM9G20" + select CPU_ARM926T + select HAS_MACB + ++config ARCH_AT91SAM9G45 ++ bool "AT91SAM9G45 or AT91SAM9M10" ++ select CPU_ARM926T ++ select HAS_MACB ++ + endchoice + + # ---------------------------------------------------------- +@@ -56,6 +74,51 @@ endif + + # ---------------------------------------------------------- + ++if ARCH_AT91SAM9261 ++ ++choice ++ prompt "AT91SAM9261 Board Type" ++ ++config MACH_AT91SAM9261EK ++ bool "Atmel AT91SAM9261-EK Evaluation Kit" ++ select HAS_DM9000 ++ select HAVE_NAND_ATMEL_BUSWIDTH_16 ++ help ++ Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit. ++ <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820> ++ ++config MACH_PM9261 ++ bool "Ronetix PM9261" ++ select HAS_DM9000 ++ select MACH_HAS_LOWLEVEL_INIT ++ help ++ Say y here if you are using the Ronetix PM9261 Board ++ ++endchoice ++ ++endif ++ ++# ---------------------------------------------------------- ++ ++if ARCH_AT91SAM9G10 ++ ++choice ++ prompt "AT91SAM9G10 Board Type" ++ ++config MACH_AT91SAM9G10EK ++ bool "Atmel AT91SAM9G10-EK Evaluation Kit" ++ select HAVE_NAND_ATMEL_BUSWIDTH_16 ++ select HAS_DM9000 ++ help ++ Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. ++ <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> ++ ++endchoice ++ ++endif ++ ++# ---------------------------------------------------------- ++ + if ARCH_AT91SAM9G20 + + choice +@@ -102,6 +165,27 @@ endchoice + + endif + ++if ARCH_AT91SAM9G45 ++ ++choice ++ prompt "AT91SAM9G45 or AT91SAM9M10 Board Type" ++ ++config MACH_AT91SAM9M10G45EK ++ bool "Atmel AT91SAM9M10G45-EK Evaluation Kit" ++ select HAVE_NAND_ATMEL_BUSWIDTH_16 ++ help ++ Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit. ++ <http://atmel.com/dyn/products/tools_card_v2.asp?tool_id=4735> ++ ++config MACH_PM9G45 ++ bool "Ronetix PM9G45" ++ help ++ Say y here if you are using the Ronetix PM9G45 Board ++ ++endchoice ++ ++endif ++ + # ---------------------------------------------------------- + + comment "AT91 Board Options" +diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile +index 1bedadb..d57c8f5 100644 +--- a/arch/arm/mach-at91/Makefile ++++ b/arch/arm/mach-at91/Makefile +@@ -4,5 +4,8 @@ obj-$(CONFIG_MACH_DO_LOWLEVEL_INIT) += lowlevel_init.o + + # CPU-specific support + obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o ++obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o + obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o ++obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o + obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o ++obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o +diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c +index c6ddb13..fc8f828 100644 +--- a/arch/arm/mach-at91/at91sam9260_devices.c ++++ b/arch/arm/mach-at91/at91sam9260_devices.c +@@ -120,7 +120,7 @@ void at91_add_device_nand(struct atmel_nand_data *data) {} + #endif + + static struct device_d dbgu_serial_device = { +- .id = -1, ++ .id = 0, + .name = "atmel_serial", + .map_base = AT91_BASE_SYS + AT91_DBGU, + .size = 4096, +@@ -133,7 +133,7 @@ static inline void configure_dbgu_pins(void) + } + + static struct device_d uart0_serial_device = { +- .id = -1, ++ .id = 1, + .name = "atmel_serial", + .map_base = AT91SAM9260_BASE_US0, + .size = 4096, +@@ -159,7 +159,7 @@ static inline void configure_usart0_pins(unsigned pins) + } + + static struct device_d uart1_serial_device = { +- .id = -1, ++ .id = 2, + .name = "atmel_serial", + .map_base = AT91SAM9260_BASE_US1, + .size = 4096, +@@ -177,7 +177,7 @@ static inline void configure_usart1_pins(unsigned pins) + } + + static struct device_d uart2_serial_device = { +- .id = -1, ++ .id = 3, + .name = "atmel_serial", + .map_base = AT91SAM9260_BASE_US2, + .size = 4096, +@@ -195,7 +195,7 @@ static inline void configure_usart2_pins(unsigned pins) + } + + static struct device_d uart3_serial_device = { +- .id = -1, ++ .id = 4, + .name = "atmel_serial", + .map_base = AT91SAM9260_BASE_US3, + .size = 4096, +@@ -213,7 +213,7 @@ static inline void configure_usart3_pins(unsigned pins) + } + + static struct device_d uart4_serial_device = { +- .id = -1, ++ .id = 5, + .name = "atmel_serial", + .map_base = AT91SAM9260_BASE_US4, + .size = 4096, +@@ -226,7 +226,7 @@ static inline void configure_usart4_pins(void) + } + + static struct device_d uart5_serial_device = { +- .id = -1, ++ .id = 6, + .name = "atmel_serial", + .map_base = AT91SAM9260_BASE_US5, + .size = 4096, +diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c +new file mode 100644 +index 0000000..3d503aa +--- /dev/null ++++ b/arch/arm/mach-at91/at91sam9261.c +@@ -0,0 +1,230 @@ ++#include <common.h> ++#include <gpio.h> ++#include <init.h> ++#include <asm/hardware.h> ++#include <mach/at91_pmc.h> ++ ++#include "generic.h" ++#include "clock.h" ++ ++/* -------------------------------------------------------------------- ++ * Clocks ++ * -------------------------------------------------------------------- */ ++ ++/* ++ * The peripheral clocks. ++ */ ++static struct clk pioA_clk = { ++ .name = "pioA_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_PIOA, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pioB_clk = { ++ .name = "pioB_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_PIOB, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pioC_clk = { ++ .name = "pioC_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_PIOC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart0_clk = { ++ .name = "usart0_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_US0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart1_clk = { ++ .name = "usart1_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_US1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart2_clk = { ++ .name = "usart2_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_US2, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk mmc_clk = { ++ .name = "mci_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_MCI, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk udc_clk = { ++ .name = "udc_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_UDP, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk twi_clk = { ++ .name = "twi_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_TWI, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk spi0_clk = { ++ .name = "spi0_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_SPI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk spi1_clk = { ++ .name = "spi1_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_SPI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ssc0_clk = { ++ .name = "ssc0_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_SSC0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ssc1_clk = { ++ .name = "ssc1_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_SSC1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ssc2_clk = { ++ .name = "ssc2_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_SSC2, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk tc0_clk = { ++ .name = "tc0_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_TC0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk tc1_clk = { ++ .name = "tc1_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_TC1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk tc2_clk = { ++ .name = "tc2_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_TC2, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ohci_clk = { ++ .name = "ohci_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_UHP, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk lcdc_clk = { ++ .name = "lcdc_clk", ++ .pmc_mask = 1 << AT91SAM9261_ID_LCDC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++ ++static struct clk *periph_clocks[] = { ++ &pioA_clk, ++ &pioB_clk, ++ &pioC_clk, ++ &usart0_clk, ++ &usart1_clk, ++ &usart2_clk, ++ &mmc_clk, ++ &udc_clk, ++ &twi_clk, ++ &spi0_clk, ++ &spi1_clk, ++ &ssc0_clk, ++ &ssc1_clk, ++ &ssc2_clk, ++ &tc0_clk, ++ &tc1_clk, ++ &tc2_clk, ++ &ohci_clk, ++ &lcdc_clk, ++ // irq0 .. irq2 ++}; ++ ++/* ++ * The four programmable clocks. ++ * You must configure pin multiplexing to bring these signals out. ++ */ ++static struct clk pck0 = { ++ .name = "pck0", ++ .pmc_mask = AT91_PMC_PCK0, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 0, ++}; ++static struct clk pck1 = { ++ .name = "pck1", ++ .pmc_mask = AT91_PMC_PCK1, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 1, ++}; ++static struct clk pck2 = { ++ .name = "pck2", ++ .pmc_mask = AT91_PMC_PCK2, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 2, ++}; ++static struct clk pck3 = { ++ .name = "pck3", ++ .pmc_mask = AT91_PMC_PCK3, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 3, ++}; ++ ++/* HClocks */ ++static struct clk hck0 = { ++ .name = "hck0", ++ .pmc_mask = AT91_PMC_HCK0, ++ .type = CLK_TYPE_SYSTEM, ++ .id = 0, ++}; ++static struct clk hck1 = { ++ .name = "hck1", ++ .pmc_mask = AT91_PMC_HCK1, ++ .type = CLK_TYPE_SYSTEM, ++ .id = 1, ++}; ++ ++static void at91sam9261_register_clocks(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) ++ clk_register(periph_clocks[i]); ++ ++ clk_register(&pck0); ++ clk_register(&pck1); ++ clk_register(&pck2); ++ clk_register(&pck3); ++ ++ clk_register(&hck0); ++ clk_register(&hck1); ++} ++ ++ ++/* -------------------------------------------------------------------- ++ * GPIO ++ * -------------------------------------------------------------------- */ ++ ++static struct at91_gpio_bank at91sam9261_gpio[] = { ++ { ++ .id = AT91SAM9261_ID_PIOA, ++ .offset = AT91_PIOA, ++ .clock = &pioA_clk, ++ }, { ++ .id = AT91SAM9261_ID_PIOB, ++ .offset = AT91_PIOB, ++ .clock = &pioB_clk, ++ }, { ++ .id = AT91SAM9261_ID_PIOC, ++ .offset = AT91_PIOC, ++ .clock = &pioC_clk, ++ } ++}; ++ ++ ++static int at91sam9261_initialize(void) ++{ ++ /* Init clock subsystem */ ++ at91_clock_init(AT91_MAIN_CLOCK); ++ ++ /* Register the processor-specific clocks */ ++ at91sam9261_register_clocks(); ++ ++ /* Register GPIO subsystem */ ++ at91_gpio_init(at91sam9261_gpio, 3); ++ return 0; ++} ++ ++core_initcall(at91sam9261_initialize); +diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c +new file mode 100644 +index 0000000..45bfb23 +--- /dev/null ++++ b/arch/arm/mach-at91/at91sam9261_devices.c +@@ -0,0 +1,175 @@ ++/* ++ * arch/arm/mach-at91/at91sam9261_devices.c ++ * ++ * Copyright (C) 2006 Atmel ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#include <common.h> ++#include <asm/armlinux.h> ++#include <asm/hardware.h> ++#include <mach/at91_pmc.h> ++#include <mach/at91sam9261_matrix.h> ++#include <mach/board.h> ++#include <mach/gpio.h> ++#include <mach/io.h> ++ ++#include "generic.h" ++ ++static struct memory_platform_data ram_pdata = { ++ .name = "ram0", ++ .flags = DEVFS_RDWR, ++}; ++ ++static struct device_d sdram_dev = { ++ .id = 0, ++ .name = "mem", ++ .map_base = AT91_CHIPSELECT_1, ++ .platform_data = &ram_pdata, ++}; ++ ++void at91_add_device_sdram(u32 size) ++{ ++ sdram_dev.size = size; ++ register_device(&sdram_dev); ++ armlinux_add_dram(&sdram_dev); ++} ++ ++#if defined(CONFIG_NAND_ATMEL) ++static struct device_d nand_dev = { ++ .id = 0, ++ .name = "atmel_nand", ++ .map_base = AT91_CHIPSELECT_3, ++ .size = 0x10, ++}; ++ ++void at91_add_device_nand(struct atmel_nand_data *data) ++{ ++ unsigned long csa; ++ ++ if (!data) ++ return; ++ ++ csa = at91_sys_read(AT91_MATRIX_EBICSA); ++ at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); ++ ++ /* enable pin */ ++ if (data->enable_pin) ++ at91_set_gpio_output(data->enable_pin, 1); ++ ++ /* ready/busy pin */ ++ if (data->rdy_pin) ++ at91_set_gpio_input(data->rdy_pin, 1); ++ ++ /* card detect pin */ ++ if (data->det_pin) ++ at91_set_gpio_input(data->det_pin, 1); ++ ++ at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ ++ at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ ++ ++ nand_dev.platform_data = data; ++ register_device(&nand_dev); ++} ++#else ++void at91_add_device_nand(struct atmel_nand_data *data) {} ++#endif ++ ++static struct device_d dbgu_serial_device = { ++ .id = 0, ++ .name = "atmel_serial", ++ .map_base = (AT91_BASE_SYS + AT91_DBGU), ++ .size = 4096, ++}; ++ ++static inline void configure_dbgu_pins(void) ++{ ++ at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ ++ at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ ++} ++ ++static struct device_d uart0_serial_device = { ++ .id = 1, ++ .name = "atmel_serial", ++ .map_base = AT91SAM9261_BASE_US0, ++ .size = 4096, ++}; ++ ++static inline void configure_usart0_pins(unsigned pins) ++{ ++ at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ ++ at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ ++ ++ if (pins & ATMEL_UART_RTS) ++ at91_set_A_periph(AT91_PIN_PC10, 0); /* RTS0 */ ++ if (pins & ATMEL_UART_CTS) ++ at91_set_A_periph(AT91_PIN_PC11, 0); /* CTS0 */ ++} ++ ++static struct device_d uart1_serial_device = { ++ .id = 2, ++ .name = "atmel_serial", ++ .map_base = AT91SAM9261_BASE_US1, ++ .size = 4096, ++}; ++ ++static inline void configure_usart1_pins(unsigned pins) ++{ ++ at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ ++ at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ ++ ++ if (pins & ATMEL_UART_RTS) ++ at91_set_B_periph(AT91_PIN_PA12, 0); /* RTS1 */ ++ if (pins & ATMEL_UART_CTS) ++ at91_set_B_periph(AT91_PIN_PA13, 0); /* CTS1 */ ++} ++ ++static struct device_d uart2_serial_device = { ++ .id = 3, ++ .name = "atmel_serial", ++ .map_base = AT91SAM9261_BASE_US2, ++ .size = 4096, ++}; ++ ++static inline void configure_usart2_pins(unsigned pins) ++{ ++ at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ ++ at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ ++ ++ if (pins & ATMEL_UART_RTS) ++ at91_set_B_periph(AT91_PIN_PA15, 0); /* RTS2*/ ++ if (pins & ATMEL_UART_CTS) ++ at91_set_B_periph(AT91_PIN_PA16, 0); /* CTS2 */ ++} ++ ++void at91_register_uart(unsigned id, unsigned pins) ++{ ++ switch (id) { ++ case 0: /* DBGU */ ++ configure_dbgu_pins(); ++ at91_clock_associate("mck", &dbgu_serial_device, "usart"); ++ register_device(&dbgu_serial_device); ++ break; ++ case AT91SAM9261_ID_US0: ++ configure_usart0_pins(pins); ++ at91_clock_associate("usart0_clk", &uart0_serial_device, "usart"); ++ register_device(&uart0_serial_device); ++ break; ++ case AT91SAM9261_ID_US1: ++ configure_usart1_pins(pins); ++ at91_clock_associate("usart1_clk", &uart1_serial_device, "usart"); ++ register_device(&uart1_serial_device); ++ break; ++ case AT91SAM9261_ID_US2: ++ configure_usart2_pins(pins); ++ at91_clock_associate("usart2_clk", &uart2_serial_device, "usart"); ++ register_device(&uart2_serial_device); ++ break; ++ default: ++ return; ++ } ++} +diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c +index 807a6a7..346426c 100644 +--- a/arch/arm/mach-at91/at91sam9263_devices.c ++++ b/arch/arm/mach-at91/at91sam9263_devices.c +@@ -119,7 +119,7 @@ void at91_add_device_nand(struct atmel_nand_data *data) {} + #endif + + static struct device_d dbgu_serial_device = { +- .id = -1, ++ .id = 0, + .name = "atmel_serial", + .map_base = (AT91_BASE_SYS + AT91_DBGU), + .size = 4096, +@@ -132,7 +132,7 @@ static inline void configure_dbgu_pins(void) + } + + static struct device_d uart0_serial_device = { +- .id = -1, ++ .id = 1, + .name = "atmel_serial", + .map_base = AT91SAM9263_BASE_US0, + .size = 4096, +@@ -150,7 +150,7 @@ static inline void configure_usart0_pins(unsigned pins) + } + + static struct device_d uart1_serial_device = { +- .id = -1, ++ .id = 2, + .name = "atmel_serial", + .map_base = AT91SAM9263_BASE_US1, + .size = 4096, +@@ -168,7 +168,7 @@ static inline void configure_usart1_pins(unsigned pins) + } + + static struct device_d uart2_serial_device = { +- .id = -1, ++ .id = 3, + .name = "atmel_serial", + .map_base = AT91SAM9263_BASE_US2, + .size = 4096, +diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c +index 84df1a1..c1b42f9 100644 +--- a/arch/arm/mach-at91/at91sam926x_time.c ++++ b/arch/arm/mach-at91/at91sam926x_time.c +@@ -73,7 +73,7 @@ core_initcall(clocksource_init); + /* + * Reset the cpu through the reset controller + */ +-void __noreturn reset_cpu (unsigned long ignored) ++void __noreturn reset_cpu (unsigned long addr) + { + at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | + AT91_RSTC_PROCRST | +diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c +new file mode 100644 +index 0000000..2eaae58 +--- /dev/null ++++ b/arch/arm/mach-at91/at91sam9g45.c +@@ -0,0 +1,277 @@ ++#include <common.h> ++#include <gpio.h> ++#include <init.h> ++#include <mach/io.h> ++#include <mach/hardware.h> ++#include <mach/at91_pmc.h> ++#include <mach/cpu.h> ++ ++#include "generic.h" ++#include "clock.h" ++ ++/* -------------------------------------------------------------------- ++ * Clocks ++ * -------------------------------------------------------------------- */ ++ ++/* ++ * The peripheral clocks. ++ */ ++static struct clk pioA_clk = { ++ .name = "pioA_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_PIOA, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pioB_clk = { ++ .name = "pioB_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_PIOB, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pioC_clk = { ++ .name = "pioC_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_PIOC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pioDE_clk = { ++ .name = "pioDE_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_PIODE, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart0_clk = { ++ .name = "usart0_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_US0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart1_clk = { ++ .name = "usart1_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_US1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart2_clk = { ++ .name = "usart2_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_US2, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk usart3_clk = { ++ .name = "usart3_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_US3, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk mmc0_clk = { ++ .name = "mci0_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_MCI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk twi0_clk = { ++ .name = "twi0_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_TWI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk twi1_clk = { ++ .name = "twi1_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_TWI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk spi0_clk = { ++ .name = "spi0_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_SPI0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk spi1_clk = { ++ .name = "spi1_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_SPI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ssc0_clk = { ++ .name = "ssc0_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_SSC0, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ssc1_clk = { ++ .name = "ssc1_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_SSC1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk tcb0_clk = { ++ .name = "tcb0_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_TCB, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk pwm_clk = { ++ .name = "pwm_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_PWMC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk tsc_clk = { ++ .name = "tsc_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_TSC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk dma_clk = { ++ .name = "dma_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_DMA, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk uhphs_clk = { ++ .name = "uhphs_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk lcdc_clk = { ++ .name = "lcdc_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_LCDC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk ac97_clk = { ++ .name = "ac97_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_AC97C, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk macb_clk = { ++ .name = "macb_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_EMAC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk isi_clk = { ++ .name = "isi_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_ISI, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk udphs_clk = { ++ .name = "udphs_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++static struct clk mmc1_clk = { ++ .name = "mci1_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_MCI1, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++ ++/* Video decoder clock - Only for sam9m10/sam9m11 */ ++static struct clk vdec_clk = { ++ .name = "vdec_clk", ++ .pmc_mask = 1 << AT91SAM9G45_ID_VDEC, ++ .type = CLK_TYPE_PERIPHERAL, ++}; ++ ++/* One additional fake clock for ohci */ ++static struct clk ohci_clk = { ++ .name = "ohci_clk", ++ .pmc_mask = 0, ++ .type = CLK_TYPE_PERIPHERAL, ++ .parent = &uhphs_clk, ++}; ++ ++/* One additional fake clock for second TC block */ ++static struct clk tcb1_clk = { ++ .name = "tcb1_clk", ++ .pmc_mask = 0, ++ .type = CLK_TYPE_PERIPHERAL, ++ .parent = &tcb0_clk, ++}; ++ ++static struct clk *periph_clocks[] __initdata = { ++ &pioA_clk, ++ &pioB_clk, ++ &pioC_clk, ++ &pioDE_clk, ++ &usart0_clk, ++ &usart1_clk, ++ &usart2_clk, ++ &usart3_clk, ++ &mmc0_clk, ++ &twi0_clk, ++ &twi1_clk, ++ &spi0_clk, ++ &spi1_clk, ++ &ssc0_clk, ++ &ssc1_clk, ++ &tcb0_clk, ++ &pwm_clk, ++ &tsc_clk, ++ &dma_clk, ++ &uhphs_clk, ++ &lcdc_clk, ++ &ac97_clk, ++ &macb_clk, ++ &isi_clk, ++ &udphs_clk, ++ &mmc1_clk, ++ // irq0 ++ &ohci_clk, ++ &tcb1_clk, ++}; ++ ++/* ++ * The two programmable clocks. ++ * You must configure pin multiplexing to bring these signals out. ++ */ ++static struct clk pck0 = { ++ .name = "pck0", ++ .pmc_mask = AT91_PMC_PCK0, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 0, ++}; ++static struct clk pck1 = { ++ .name = "pck1", ++ .pmc_mask = AT91_PMC_PCK1, ++ .type = CLK_TYPE_PROGRAMMABLE, ++ .id = 1, ++}; ++ ++static void __init at91sam9g45_register_clocks(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) ++ clk_register(periph_clocks[i]); ++ ++ if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11()) ++ clk_register(&vdec_clk); ++ ++ clk_register(&pck0); ++ clk_register(&pck1); ++} ++ ++/* -------------------------------------------------------------------- ++ * GPIO ++ * -------------------------------------------------------------------- */ ++ ++static struct at91_gpio_bank at91sam9g45_gpio[] = { ++ { ++ .id = AT91SAM9G45_ID_PIOA, ++ .offset = AT91_PIOA, ++ .clock = &pioA_clk, ++ }, { ++ .id = AT91SAM9G45_ID_PIOB, ++ .offset = AT91_PIOB, ++ .clock = &pioB_clk, ++ }, { ++ .id = AT91SAM9G45_ID_PIOC, ++ .offset = AT91_PIOC, ++ .clock = &pioC_clk, ++ }, { ++ .id = AT91SAM9G45_ID_PIODE, ++ .offset = AT91_PIOD, ++ .clock = &pioDE_clk, ++ }, { ++ .id = AT91SAM9G45_ID_PIODE, ++ .offset = AT91_PIOE, ++ .clock = &pioDE_clk, ++ } ++}; ++ ++static int at91sam9g45_initialize(void) ++{ ++ /* Init clock subsystem */ ++ at91_clock_init(AT91_MAIN_CLOCK); ++ ++ /* Register the processor-specific clocks */ ++ at91sam9g45_register_clocks(); ++ ++ /* Register GPIO subsystem */ ++ at91_gpio_init(at91sam9g45_gpio, 5); ++ return 0; ++} ++ ++core_initcall(at91sam9g45_initialize); +diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c +new file mode 100644 +index 0000000..ddb005a +--- /dev/null ++++ b/arch/arm/mach-at91/at91sam9g45_devices.c +@@ -0,0 +1,242 @@ ++/* ++ * arch/arm/mach-at91/at91sam9263_devices.c ++ * ++ * Copyright (C) 2006 Atmel ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ */ ++#include <common.h> ++#include <asm/armlinux.h> ++#include <asm/hardware.h> ++#include <mach/at91_pmc.h> ++#include <mach/at91sam9g45_matrix.h> ++#include <mach/board.h> ++#include <mach/gpio.h> ++#include <mach/io.h> ++ ++#include "generic.h" ++ ++static struct memory_platform_data ram_pdata = { ++ .name = "ram0", ++ .flags = DEVFS_RDWR, ++}; ++ ++static struct device_d sdram_dev = { ++ .id = -1, ++ .name = "mem", ++ .map_base = AT91_CHIPSELECT_6, ++ .platform_data = &ram_pdata, ++}; ++ ++void at91_add_device_sdram(u32 size) ++{ ++ sdram_dev.size = size; ++ register_device(&sdram_dev); ++ armlinux_add_dram(&sdram_dev); ++} ++ ++#if defined(CONFIG_DRIVER_NET_MACB) ++static struct device_d macb_dev = { ++ .id = 0, ++ .name = "macb", ++ .map_base = AT91SAM9G45_BASE_EMAC, ++ .size = 0x1000, ++}; ++ ++void at91_add_device_eth(struct at91_ether_platform_data *data) ++{ ++ if (!data) ++ return; ++ ++ /* Pins used for MII and RMII */ ++ at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ ++ at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ ++ at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ ++ at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ ++ at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ ++ at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ ++ at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ ++ at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ ++ at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ ++ at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ ++ ++ if (!(data->flags & AT91SAM_ETHER_RMII)) { ++ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ ++ at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ ++ at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ ++ at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ ++ at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ ++ at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ ++ at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ ++ at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ ++ } ++ ++ macb_dev.platform_data = data; ++ register_device(&macb_dev); ++} ++#else ++void at91_add_device_eth(struct at91_ether_platform_data *data) {} ++#endif ++ ++#if defined(CONFIG_NAND_ATMEL) ++static struct device_d nand_dev = { ++ .id = -1, ++ .name = "atmel_nand", ++ .map_base = AT91_CHIPSELECT_3, ++ .size = 0x10, ++}; ++ ++void at91_add_device_nand(struct atmel_nand_data *data) ++{ ++ unsigned long csa; ++ ++ if (!data) ++ return; ++ ++ data->ecc_base = (void __iomem *)(AT91_BASE_SYS + AT91_ECC); ++ data->ecc_mode = NAND_ECC_HW; ++ ++ csa = at91_sys_read(AT91_MATRIX_EBICSA); ++ at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); ++ ++ /* enable pin */ ++ if (data->enable_pin) ++ at91_set_gpio_output(data->enable_pin, 1); ++ ++ /* ready/busy pin */ ++ if (data->rdy_pin) ++ at91_set_gpio_input(data->rdy_pin, 1); ++ ++ /* card detect pin */ ++ if (data->det_pin) ++ at91_set_gpio_input(data->det_pin, 1); ++ ++ nand_dev.platform_data = data; ++ register_device(&nand_dev); ++} ++#else ++void at91_add_device_nand(struct atmel_nand_data *data) {} ++#endif ++ ++static struct device_d dbgu_serial_device = { ++ .id = -1, ++ .name = "atmel_serial", ++ .map_base = (AT91_BASE_SYS + AT91_DBGU), ++ .size = 4096, ++}; ++ ++static inline void configure_dbgu_pins(void) ++{ ++ at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ ++ at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ ++} ++ ++static struct device_d uart0_serial_device = { ++ .id = -1, ++ .name = "atmel_serial", ++ .map_base = AT91SAM9G45_BASE_US0, ++ .size = 4096, ++}; ++ ++static inline void configure_usart0_pins(unsigned pins) ++{ ++ at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ ++ at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ ++ ++ if (pins & ATMEL_UART_RTS) ++ at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */ ++ if (pins & ATMEL_UART_CTS) ++ at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */ ++} ++ ++static struct device_d uart1_serial_device = { ++ .id = -1, ++ .name = "atmel_serial", ++ .map_base = AT91SAM9G45_BASE_US1, ++ .size = 4096, ++}; ++ ++static inline void configure_usart1_pins(unsigned pins) ++{ ++ at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ ++ at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ ++ ++ if (pins & ATMEL_UART_RTS) ++ at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */ ++ if (pins & ATMEL_UART_CTS) ++ at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */ ++} ++ ++static struct device_d uart2_serial_device = { ++ .id = -1, ++ .name = "atmel_serial", ++ .map_base = AT91SAM9G45_BASE_US2, ++ .size = 4096, ++}; ++ ++static inline void configure_usart2_pins(unsigned pins) ++{ ++ at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */ ++ at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */ ++ ++ if (pins & ATMEL_UART_RTS) ++ at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */ ++ if (pins & ATMEL_UART_CTS) ++ at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */ ++} ++ ++static struct device_d uart3_serial_device = { ++ .id = -1, ++ .name = "atmel_serial", ++ .map_base = AT91SAM9G45_ID_US3, ++ .size = 4096, ++}; ++ ++static inline void configure_usart3_pins(unsigned pins) ++{ ++ at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */ ++ at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */ ++ ++ if (pins & ATMEL_UART_RTS) ++ at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */ ++ if (pins & ATMEL_UART_CTS) ++ at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */ ++} ++ ++void at91_register_uart(unsigned id, unsigned pins) ++{ ++ switch (id) { ++ case 0: /* DBGU */ ++ configure_dbgu_pins(); ++ at91_clock_associate("mck", &dbgu_serial_device, "usart"); ++ register_device(&dbgu_serial_device); ++ break; ++ case AT91SAM9G45_ID_US0: ++ configure_usart0_pins(pins); ++ at91_clock_associate("usart0_clk", &uart0_serial_device, "usart"); ++ register_device(&uart0_serial_device); ++ break; ++ case AT91SAM9G45_ID_US1: ++ configure_usart1_pins(pins); ++ at91_clock_associate("usart1_clk", &uart1_serial_device, "usart"); ++ register_device(&uart1_serial_device); ++ break; ++ case AT91SAM9G45_ID_US2: ++ configure_usart2_pins(pins); ++ at91_clock_associate("usart2_clk", &uart2_serial_device, "usart"); ++ register_device(&uart2_serial_device); ++ break; ++ case AT91SAM9G45_ID_US3: ++ configure_usart3_pins(pins); ++ at91_clock_associate("usart3_clk", &uart2_serial_device, "usart"); ++ register_device(&uart3_serial_device); ++ break; ++ default: ++ return; ++ } ++ ++} +diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h +new file mode 100644 +index 0000000..b303e07 +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9261.h +@@ -0,0 +1,109 @@ ++/* ++ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261.h] ++ * ++ * Copyright (C) SAN People ++ * ++ * Common definitions. ++ * Based on AT91SAM9261 datasheet revision E. (Preliminary) ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef AT91SAM9261_H ++#define AT91SAM9261_H ++ ++/* ++ * Peripheral identifiers/interrupts. ++ */ ++#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ ++#define AT91_ID_SYS 1 /* System Peripherals */ ++#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */ ++#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */ ++#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */ ++#define AT91SAM9261_ID_US0 6 /* USART 0 */ ++#define AT91SAM9261_ID_US1 7 /* USART 1 */ ++#define AT91SAM9261_ID_US2 8 /* USART 2 */ ++#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */ ++#define AT91SAM9261_ID_UDP 10 /* USB Device Port */ ++#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */ ++#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */ ++#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */ ++#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */ ++#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */ ++#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */ ++#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */ ++#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */ ++#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */ ++#define AT91SAM9261_ID_UHP 20 /* USB Host port */ ++#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */ ++#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */ ++#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */ ++#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */ ++ ++ ++/* ++ * User Peripheral physical base addresses. ++ */ ++#define AT91SAM9261_BASE_TCB0 0xfffa0000 ++#define AT91SAM9261_BASE_TC0 0xfffa0000 ++#define AT91SAM9261_BASE_TC1 0xfffa0040 ++#define AT91SAM9261_BASE_TC2 0xfffa0080 ++#define AT91SAM9261_BASE_UDP 0xfffa4000 ++#define AT91SAM9261_BASE_MCI 0xfffa8000 ++#define AT91SAM9261_BASE_TWI 0xfffac000 ++#define AT91SAM9261_BASE_US0 0xfffb0000 ++#define AT91SAM9261_BASE_US1 0xfffb4000 ++#define AT91SAM9261_BASE_US2 0xfffb8000 ++#define AT91SAM9261_BASE_SSC0 0xfffbc000 ++#define AT91SAM9261_BASE_SSC1 0xfffc0000 ++#define AT91SAM9261_BASE_SSC2 0xfffc4000 ++#define AT91SAM9261_BASE_SPI0 0xfffc8000 ++#define AT91SAM9261_BASE_SPI1 0xfffcc000 ++#define AT91_BASE_SYS 0xffffea00 ++ ++ ++/* ++ * System Peripherals (offset from AT91_BASE_SYS) ++ */ ++#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) ++#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) ++#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) ++#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) ++#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) ++#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) ++#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) ++#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) ++#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) ++#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) ++#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) ++#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) ++#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) ++#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) ++#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) ++ ++#define AT91_USART0 AT91SAM9261_BASE_US0 ++#define AT91_USART1 AT91SAM9261_BASE_US1 ++#define AT91_USART2 AT91SAM9261_BASE_US2 ++ ++ ++/* ++ * Internal Memory. ++ */ ++#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ ++#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ ++ ++#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ ++#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ ++ ++#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */ ++#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ ++ ++/* ++ * Cpu Name ++ */ ++#define AT91_CPU_NAME "AT91SAM9261" ++ ++#endif +diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h +new file mode 100644 +index 0000000..7de0157 +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h +@@ -0,0 +1,64 @@ ++/* ++ * [origin: Linux kernel include/asm-arm/arch-at91/at91sam9261_matrix.h] ++ * ++ * Copyright (C) 2007 Atmel Corporation. ++ * ++ * Memory Controllers (MATRIX, EBI) - System peripherals registers. ++ * Based on AT91SAM9261 datasheet revision D. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef AT91SAM9261_MATRIX_H ++#define AT91SAM9261_MATRIX_H ++ ++#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ ++#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ ++#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ ++ ++#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ ++#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ ++#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ ++#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ ++#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ ++#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ ++#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ ++#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) ++#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) ++#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) ++#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ ++ ++#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ ++#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ ++#define AT91_MATRIX_ITCM_0 (0 << 0) ++#define AT91_MATRIX_ITCM_16 (5 << 0) ++#define AT91_MATRIX_ITCM_32 (6 << 0) ++#define AT91_MATRIX_ITCM_64 (7 << 0) ++#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ ++#define AT91_MATRIX_DTCM_0 (0 << 4) ++#define AT91_MATRIX_DTCM_16 (5 << 4) ++#define AT91_MATRIX_DTCM_32 (6 << 4) ++#define AT91_MATRIX_DTCM_64 (7 << 4) ++ ++#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ ++#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ ++#define AT91_MATRIX_CS1A_SMC (0 << 1) ++#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) ++#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ ++#define AT91_MATRIX_CS3A_SMC (0 << 3) ++#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) ++#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ ++#define AT91_MATRIX_CS4A_SMC (0 << 4) ++#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) ++#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ ++#define AT91_MATRIX_CS5A_SMC (0 << 5) ++#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) ++#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ ++ ++#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ ++#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ ++ ++#endif +diff --git a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h +index 58cafd8..1d1d905 100644 +--- a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h ++++ b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h +@@ -13,7 +13,7 @@ + + #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) + #include <mach/at91sam9260_matrix.h> +-#elif defined(CONFIG_ARCH_AT91SAM9261) ++#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) + #include <mach/at91sam9261_matrix.h> + #elif defined(CONFIG_ARCH_AT91SAM9263) + #include <mach/at91sam9263_matrix.h> +diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h +new file mode 100644 +index 0000000..c5c7f49 +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h +@@ -0,0 +1,160 @@ ++/* ++ * Chip-specific header file for the AT91SAM9G45 family ++ * ++ * Copyright (C) 2008-2009 Atmel Corporation. ++ * ++ * Common definitions. ++ * Based on AT91SAM9G45 preliminary datasheet. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef AT91SAM9G45_H ++#define AT91SAM9G45_H ++ ++/* ++ * Peripheral identifiers/interrupts. ++ */ ++#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ ++#define AT91_ID_SYS 1 /* System Controller Interrupt */ ++#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ ++#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ ++#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ ++#define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ ++#define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ ++#define AT91SAM9G45_ID_US0 7 /* USART 0 */ ++#define AT91SAM9G45_ID_US1 8 /* USART 1 */ ++#define AT91SAM9G45_ID_US2 9 /* USART 2 */ ++#define AT91SAM9G45_ID_US3 10 /* USART 3 */ ++#define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ ++#define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ ++#define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ ++#define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ ++#define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ ++#define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ ++#define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ ++#define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ ++#define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ ++#define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ ++#define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ ++#define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ ++#define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ ++#define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ ++#define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ ++#define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ ++#define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ ++#define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ ++#define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ ++#define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ ++#define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ ++ ++/* ++ * User Peripheral physical base addresses. ++ */ ++#define AT91SAM9G45_BASE_UDPHS 0xfff78000 ++#define AT91SAM9G45_BASE_TCB0 0xfff7c000 ++#define AT91SAM9G45_BASE_TC0 0xfff7c000 ++#define AT91SAM9G45_BASE_TC1 0xfff7c040 ++#define AT91SAM9G45_BASE_TC2 0xfff7c080 ++#define AT91SAM9G45_BASE_MCI0 0xfff80000 ++#define AT91SAM9G45_BASE_TWI0 0xfff84000 ++#define AT91SAM9G45_BASE_TWI1 0xfff88000 ++#define AT91SAM9G45_BASE_US0 0xfff8c000 ++#define AT91SAM9G45_BASE_US1 0xfff90000 ++#define AT91SAM9G45_BASE_US2 0xfff94000 ++#define AT91SAM9G45_BASE_US3 0xfff98000 ++#define AT91SAM9G45_BASE_SSC0 0xfff9c000 ++#define AT91SAM9G45_BASE_SSC1 0xfffa0000 ++#define AT91SAM9G45_BASE_SPI0 0xfffa4000 ++#define AT91SAM9G45_BASE_SPI1 0xfffa8000 ++#define AT91SAM9G45_BASE_AC97C 0xfffac000 ++#define AT91SAM9G45_BASE_TSC 0xfffb0000 ++#define AT91SAM9G45_BASE_ISI 0xfffb4000 ++#define AT91SAM9G45_BASE_PWMC 0xfffb8000 ++#define AT91SAM9G45_BASE_EMAC 0xfffbc000 ++#define AT91SAM9G45_BASE_AES 0xfffc0000 ++#define AT91SAM9G45_BASE_TDES 0xfffc4000 ++#define AT91SAM9G45_BASE_SHA 0xfffc8000 ++#define AT91SAM9G45_BASE_TRNG 0xfffcc000 ++#define AT91SAM9G45_BASE_MCI1 0xfffd0000 ++#define AT91SAM9G45_BASE_TCB1 0xfffd4000 ++#define AT91SAM9G45_BASE_TC3 0xfffd4000 ++#define AT91SAM9G45_BASE_TC4 0xfffd4040 ++#define AT91SAM9G45_BASE_TC5 0xfffd4080 ++#define AT91_BASE_SYS 0xffffe200 ++ ++/* ++ * System Peripherals (offset from AT91_BASE_SYS) ++ */ ++#define AT91_ECC (0xffffe200 - AT91_BASE_SYS) ++#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) ++#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) ++#define AT91_SMC (0xffffe800 - AT91_BASE_SYS) ++#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) ++#define AT91_DMA (0xffffec00 - AT91_BASE_SYS) ++#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) ++#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) ++#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) ++#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) ++#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) ++#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) ++#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) ++#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) ++#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) ++#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) ++#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) ++#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) ++#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) ++#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) ++#define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) ++ ++#define AT91_USART0 AT91SAM9G45_BASE_US0 ++#define AT91_USART1 AT91SAM9G45_BASE_US1 ++#define AT91_USART2 AT91SAM9G45_BASE_US2 ++#define AT91_USART3 AT91SAM9G45_BASE_US3 ++ ++/* ++ * Internal Memory. ++ */ ++#define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ ++#define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ ++ ++#define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ ++#define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ ++ ++#define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ ++#define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ ++#define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ ++#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ ++#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ ++ ++#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 ++ ++#define CONSISTENT_DMA_SIZE SZ_4M ++ ++/* ++ * DMA peripheral identifiers ++ * for hardware handshaking interface ++ */ ++#define AT_DMA_ID_MCI0 0 ++#define AT_DMA_ID_SPI0_TX 1 ++#define AT_DMA_ID_SPI0_RX 2 ++#define AT_DMA_ID_SPI1_TX 3 ++#define AT_DMA_ID_SPI1_RX 4 ++#define AT_DMA_ID_SSC0_TX 5 ++#define AT_DMA_ID_SSC0_RX 6 ++#define AT_DMA_ID_SSC1_TX 7 ++#define AT_DMA_ID_SSC1_RX 8 ++#define AT_DMA_ID_AC97_TX 9 ++#define AT_DMA_ID_AC97_RX 10 ++#define AT_DMA_ID_MCI1 13 ++ ++/* ++ * Cpu Name ++ */ ++#define AT91_CPU_NAME "AT91SAM9G45" ++ ++#endif +diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h +new file mode 100644 +index 0000000..c972d60 +--- /dev/null ++++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h +@@ -0,0 +1,153 @@ ++/* ++ * Matrix-centric header file for the AT91SAM9G45 family ++ * ++ * Copyright (C) 2008-2009 Atmel Corporation. ++ * ++ * Memory Controllers (MATRIX, EBI) - System peripherals registers. ++ * Based on AT91SAM9G45 preliminary datasheet. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ */ ++ ++#ifndef AT91SAM9G45_MATRIX_H ++#define AT91SAM9G45_MATRIX_H ++ ++#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ ++#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ ++#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ ++#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ ++#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ ++#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ ++#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ ++#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ ++#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ ++#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ ++#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ ++#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ ++#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ ++#define AT91_MATRIX_ULBT_INFINITE (0 << 0) ++#define AT91_MATRIX_ULBT_SINGLE (1 << 0) ++#define AT91_MATRIX_ULBT_FOUR (2 << 0) ++#define AT91_MATRIX_ULBT_EIGHT (3 << 0) ++#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) ++#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) ++#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) ++#define AT91_MATRIX_ULBT_128 (7 << 0) ++ ++#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ ++#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ ++#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ ++#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ ++#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ ++#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ ++#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ ++#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ ++#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ ++#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ ++#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) ++#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) ++#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) ++#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ ++ ++#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ ++#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ ++#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ ++#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ ++#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ ++#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ ++#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ ++#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ ++#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ ++#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ ++#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ ++#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ ++#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ ++#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ ++#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ ++#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ ++#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ ++#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ ++#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ ++#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ ++#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ ++#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ ++#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ ++#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ ++#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ ++#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ ++#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ ++#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ ++ ++#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ ++#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ ++#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ ++#define AT91_MATRIX_RCB2 (1 << 2) ++#define AT91_MATRIX_RCB3 (1 << 3) ++#define AT91_MATRIX_RCB4 (1 << 4) ++#define AT91_MATRIX_RCB5 (1 << 5) ++#define AT91_MATRIX_RCB6 (1 << 6) ++#define AT91_MATRIX_RCB7 (1 << 7) ++#define AT91_MATRIX_RCB8 (1 << 8) ++#define AT91_MATRIX_RCB9 (1 << 9) ++#define AT91_MATRIX_RCB10 (1 << 10) ++#define AT91_MATRIX_RCB11 (1 << 11) ++ ++#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ ++#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ ++#define AT91_MATRIX_ITCM_0 (0 << 0) ++#define AT91_MATRIX_ITCM_32 (6 << 0) ++#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ ++#define AT91_MATRIX_DTCM_0 (0 << 4) ++#define AT91_MATRIX_DTCM_32 (6 << 4) ++#define AT91_MATRIX_DTCM_64 (7 << 4) ++#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ ++#define AT91_MATRIX_TCM_NO_WS (0x0 << 11) ++#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) ++ ++#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ ++#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ ++#define AT91C_VDEC_SEL_OFF (0 << 0) ++#define AT91C_VDEC_SEL_ON (1 << 0) ++ ++#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ ++#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ ++#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) ++#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) ++#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ ++#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) ++#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) ++#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ ++#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) ++#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) ++#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ ++#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) ++#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) ++#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ ++#define AT91_MATRIX_EBI_DBPU_ON (0 << 8) ++#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) ++#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ ++#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) ++#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) ++#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ ++#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) ++#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) ++#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ ++#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) ++#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) ++ ++#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ ++#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ ++#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) ++#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) ++#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ ++ ++#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ ++#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ ++#define AT91_MATRIX_WPSR_NO_WPV (0 << 0) ++#define AT91_MATRIX_WPSR_WPV (1 << 0) ++#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ ++ ++#endif +diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h +index 833659d..3bef931 100644 +--- a/arch/arm/mach-at91/include/mach/cpu.h ++++ b/arch/arm/mach-at91/include/mach/cpu.h +@@ -52,6 +52,7 @@ static inline unsigned long at91_cpu_fully_identify(void) + + #define ARCH_EXID_AT91SAM9M11 0x00000001 + #define ARCH_EXID_AT91SAM9M10 0x00000002 ++#define ARCH_EXID_AT91SAM9G46 0x00000003 + #define ARCH_EXID_AT91SAM9G45 0x00000004 + + static inline unsigned long at91_exid_identify(void) +@@ -128,9 +129,18 @@ static inline unsigned long at91cap9_rev_identify(void) + #ifdef CONFIG_ARCH_AT91SAM9G45 + #define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) + #define cpu_is_at91sam9g45es() (at91_cpu_fully_identify() == ARCH_ID_AT91SAM9G45ES) ++#define cpu_is_at91sam9m10() (cpu_is_at91sam9g45() && \ ++ (at91_exid_identify() == ARCH_EXID_AT91SAM9M10)) ++#define cpu_is_at91sam9m46() (cpu_is_at91sam9g45() && \ ++ (at91_exid_identify() == ARCH_EXID_AT91SAM9G46)) ++#define cpu_is_at91sam9m11() (cpu_is_at91sam9g45() && \ ++ (at91_exid_identify() == ARCH_EXID_AT91SAM9M11)) + #else + #define cpu_is_at91sam9g45() (0) + #define cpu_is_at91sam9g45es() (0) ++#define cpu_is_at91sam9m10() (0) ++#define cpu_is_at91sam9g46() (0) ++#define cpu_is_at91sam9m11() (0) + #endif + + #ifdef CONFIG_ARCH_AT91CAP9 +diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h +index 82b574e..fcb1bd4 100644 +--- a/arch/arm/mach-at91/include/mach/hardware.h ++++ b/arch/arm/mach-at91/include/mach/hardware.h +@@ -24,7 +24,7 @@ + #include <mach/at91sam9263.h> + #elif defined(CONFIG_ARCH_AT91SAM9RL) + #include <mach/at91sam9rl.h> +-#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9M10G45) ++#elif defined(CONFIG_ARCH_AT91SAM9G45) + #include <mach/at91sam9g45.h> + #elif defined(CONFIG_ARCH_AT91CAP9) + #include <mach/at91cap9.h> +diff --git a/arch/arm/mach-at91/lowlevel_init.S b/arch/arm/mach-at91/lowlevel_init.S +index 8a0ae02..805b201 100644 +--- a/arch/arm/mach-at91/lowlevel_init.S ++++ b/arch/arm/mach-at91/lowlevel_init.S +@@ -194,7 +194,7 @@ SMRDATA: + .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) + .word CONFIG_SYS_PIOD_PPUDR_VAL + #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) \ +- || defined(CONFIG_ARCH_AT91SAM9G20) ++ || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91SAM9G10) + .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) + .word CONFIG_SYS_PIOC_PDR_VAL1 + .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) +diff --git a/arch/arm/mach-ep93xx/clocksource.c b/arch/arm/mach-ep93xx/clocksource.c +index 3aa8e14..a1e315d 100644 +--- a/arch/arm/mach-ep93xx/clocksource.c ++++ b/arch/arm/mach-ep93xx/clocksource.c +@@ -72,7 +72,7 @@ core_initcall(clocksource_init); + /* + * Reset the cpu + */ +-void __noreturn reset_cpu(unsigned long ignored) ++void __noreturn reset_cpu(unsigned long addr) + { + struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; + uint32_t value; +diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig +index 4f95393..f3506af 100644 +--- a/arch/arm/mach-imx/Kconfig ++++ b/arch/arm/mach-imx/Kconfig +@@ -17,6 +17,8 @@ config ARCH_TEXT_BASE + default 0x87f00000 if MACH_PCM043 + default 0x08f80000 if MACH_SCB9328 + default 0xa7e00000 if MACH_NESO ++ default 0x97f00000 if MACH_MX51_PDK ++ default 0x87f00000 if MACH_GUF_CUPID + + config BOARDINFO + default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25 +@@ -32,13 +34,15 @@ config BOARDINFO + default "Phytec phyCORE-i.MX35" if MACH_PCM043 + default "Synertronixx scb9328" if MACH_SCB9328 + default "Garz+Fricke Neso" if MACH_NESO ++ default "Freescale i.MX51 PDK" if MACH_FREESCALE_MX51_PDK ++ default "Garz+Fricke Cupid" if MACH_GUF_CUPID + + config ARCH_HAS_FEC_IMX + bool + + config ARCH_IMX_INTERNAL_BOOT + bool "support internal boot mode" +- depends on ARCH_IMX25 || ARCH_IMX35 ++ depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 + + choice + depends on ARCH_IMX_INTERNAL_BOOT +@@ -94,6 +98,11 @@ config ARCH_IMX35 + select CPU_V6 + select ARCH_HAS_FEC_IMX + ++config ARCH_IMX51 ++ bool "i.MX51" ++ select CPU_V7 ++ select ARCH_HAS_FEC_IMX ++ + endchoice + + # ---------------------------------------------------------- +@@ -292,12 +301,36 @@ config MACH_PCM043 + Say Y here if you are using Phytec's phyCORE-i.MX35 (pcm043) equipped + with a Freescale i.MX35 Processor + ++config MACH_GUF_CUPID ++ bool "Garz+Fricke Cupid" ++ select HAVE_MMU ++ select MACH_HAS_LOWLEVEL_INIT ++ select ARCH_HAS_L2X0 ++ help ++ Say Y here if you are using the Garz+Fricke Neso board equipped ++ with a Freescale i.MX35 Processor ++ + endchoice + + endif + + # ---------------------------------------------------------- + ++if ARCH_IMX51 ++ ++choice ++ ++ prompt "i.MX51 Board Type" ++ ++config MACH_FREESCALE_MX51_PDK ++ bool "Freescale i.MX51 PDK" ++ select HAVE_MMU ++ select MACH_HAS_LOWLEVEL_INIT ++ ++endchoice ++ ++endif ++ + menu "Board specific settings " + + if MACH_PCM043 +diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile +index de62f7e..d000683 100644 +--- a/arch/arm/mach-imx/Makefile ++++ b/arch/arm/mach-imx/Makefile +@@ -5,8 +5,9 @@ obj-$(CONFIG_ARCH_IMX21) += speed-imx21.o imx21.o iomux-v1.o + obj-$(CONFIG_ARCH_IMX27) += speed-imx27.o imx27.o iomux-v1.o + obj-$(CONFIG_ARCH_IMX31) += speed-imx31.o imx31.o iomux-v2.o + obj-$(CONFIG_ARCH_IMX35) += speed-imx35.o imx35.o iomux-v3.o ++obj-$(CONFIG_ARCH_IMX51) += speed-imx51.o imx51.o iomux-v3.o + obj-$(CONFIG_IMX_CLKO) += clko.o + obj-$(CONFIG_IMX_IIM) += iim.o + obj-$(CONFIG_NAND_IMX) += nand.o + obj-y += speed.o +- ++obj-y += devices.o +diff --git a/arch/arm/mach-imx/clocksource.c b/arch/arm/mach-imx/clocksource.c +index a166038..5b1bad5 100644 +--- a/arch/arm/mach-imx/clocksource.c ++++ b/arch/arm/mach-imx/clocksource.c +@@ -40,7 +40,7 @@ + #define GPT(x) __REG(IMX_TIM1_BASE + (x)) + #define timer_base (IMX_TIM1_BASE) + +-uint64_t imx_clocksource_read(void) ++static uint64_t imx_clocksource_read(void) + { + return readl(timer_base + GPT_TCN); + } +@@ -76,6 +76,10 @@ static int clocksource_init (void) + PCCR0 |= PCCR0_GPT1_EN; + PCCR1 |= PCCR1_PERCLK1_EN; + #endif ++#ifdef CONFIG_ARCH_IMX25 ++ writel(readl(IMX_CCM_BASE + CCM_CGCR1) | (1 << 19), ++ IMX_CCM_BASE + CCM_CGCR1); ++#endif + + for (i = 0; i < 100; i++) + writel(0, timer_base + GPT_TCTL); /* We have no udelay by now */ +@@ -97,19 +101,34 @@ static int clocksource_init (void) + core_initcall(clocksource_init); + + /* ++ * Watchdog Registers ++ */ ++#ifdef CONFIG_ARCH_IMX1 ++#define WDOG_WCR 0x00 /* Watchdog Control Register */ ++#define WDOG_WSR 0x04 /* Watchdog Service Register */ ++#define WDOG_WSTR 0x08 /* Watchdog Status Register */ ++#define WDOG_WCR_WDE (1 << 0) ++#else ++#define WDOG_WCR 0x00 /* Watchdog Control Register */ ++#define WDOG_WSR 0x02 /* Watchdog Service Register */ ++#define WDOG_WSTR 0x04 /* Watchdog Status Register */ ++#define WDOG_WCR_WDE (1 << 2) ++#endif ++ ++/* + * Reset the cpu by setting up the watchdog timer and let it time out + */ +-void __noreturn reset_cpu (unsigned long ignored) ++void __noreturn reset_cpu (unsigned long addr) + { + /* Disable watchdog and set Time-Out field to 0 */ +- WCR = 0x0000; ++ writew(0x0, IMX_WDT_BASE + WDOG_WCR); + + /* Write Service Sequence */ +- WSR = 0x5555; +- WSR = 0xAAAA; ++ writew(0x5555, IMX_WDT_BASE + WDOG_WSR); ++ writew(0xaaaa, IMX_WDT_BASE + WDOG_WSR); + + /* Enable watchdog */ +- WCR = WCR_WDE; ++ writew(WDOG_WCR_WDE, IMX_WDT_BASE + WDOG_WCR); + + while (1); + /*NOTREACHED*/ +diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c +new file mode 100644 +index 0000000..0395b0e +--- /dev/null ++++ b/arch/arm/mach-imx/devices.c +@@ -0,0 +1,64 @@ ++#include <common.h> ++#include <driver.h> ++#include <mach/devices.h> ++ ++static struct device_d *imx_add_device(char *name, int id, void *base, int size, void *pdata) ++{ ++ struct device_d *dev; ++ ++ dev = xzalloc(sizeof(*dev)); ++ strcpy(dev->name,name); ++ dev->id = id; ++ dev->map_base = (unsigned long)base; ++ dev->size = size; ++ dev->platform_data = pdata; ++ ++ register_device(dev); ++ ++ return 0; ++} ++ ++struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata) ++{ ++ return imx_add_device("fec_imx", -1, base, 0x1000, pdata); ++} ++ ++struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata) ++{ ++ return imx_add_device("imx_spi", id, base, 0x1000, pdata); ++} ++ ++struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata) ++{ ++ return imx_add_device("i2c-imx", id, base, 0x1000, pdata); ++} ++ ++struct device_d *imx_add_uart(void *base, int id) ++{ ++ return imx_add_device("imx_serial", id, base, 0x1000, NULL); ++} ++ ++struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata) ++{ ++ return imx_add_device("imx_nand", -1, base, 0x1000, pdata); ++} ++ ++struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata) ++{ ++ return imx_add_device("imxfb", -1, base, 0x1000, pdata); ++} ++ ++struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata) ++{ ++ return imx_add_device("imx-ipu-fb", -1, base, 0x1000, pdata); ++} ++ ++struct device_d *imx_add_mmc(void *base, int id, void *pdata) ++{ ++ return imx_add_device("imx-mmc", id, base, 0x1000, pdata); ++} ++ ++struct device_d *imx_add_esdhc(void *base, int id, void *pdata) ++{ ++ return imx_add_device("imx-esdhc", id, base, 0x1000, pdata); ++} +diff --git a/arch/arm/mach-imx/gpio.c b/arch/arm/mach-imx/gpio.c +index c6a59a6..0a3e046 100644 +--- a/arch/arm/mach-imx/gpio.c ++++ b/arch/arm/mach-imx/gpio.c +@@ -27,6 +27,7 @@ + #include <errno.h> + #include <asm/io.h> + #include <mach/imx-regs.h> ++#include <mach/gpio.h> + + #if defined CONFIG_ARCH_IMX1 || defined CONFIG_ARCH_IMX21 || defined CONFIG_ARCH_IMX27 + #define GPIO_DR 0x1c +@@ -47,20 +48,20 @@ + #define GPIO_ISR 0x18 + #endif + +-extern void *imx_gpio_base[]; ++extern void __iomem *imx_gpio_base[]; + extern int imx_gpio_count; + +-static void *gpio_get_base(unsigned gpio) ++static void __iomem *gpio_get_base(unsigned gpio) + { + if (gpio >= imx_gpio_count) +- return 0; ++ return NULL; + + return imx_gpio_base[gpio / 32]; + } + + void gpio_set_value(unsigned gpio, int value) + { +- void *base = gpio_get_base(gpio); ++ void __iomem *base = gpio_get_base(gpio); + int shift = gpio % 32; + u32 val; + +@@ -79,7 +80,7 @@ void gpio_set_value(unsigned gpio, int value) + + int gpio_direction_input(unsigned gpio) + { +- void *base = gpio_get_base(gpio); ++ void __iomem *base = gpio_get_base(gpio); + int shift = gpio % 32; + u32 val; + +@@ -96,7 +97,7 @@ int gpio_direction_input(unsigned gpio) + + int gpio_direction_output(unsigned gpio, int value) + { +- void *base = gpio_get_base(gpio); ++ void __iomem *base = gpio_get_base(gpio); + int shift = gpio % 32; + u32 val; + +@@ -114,7 +115,7 @@ int gpio_direction_output(unsigned gpio, int value) + + int gpio_get_value(unsigned gpio) + { +- void *base = gpio_get_base(gpio); ++ void __iomem *base = gpio_get_base(gpio); + int shift = gpio % 32; + u32 val; + +diff --git a/arch/arm/mach-imx/imx51.c b/arch/arm/mach-imx/imx51.c +index 8c4fc11..075ed22 100644 +--- a/arch/arm/mach-imx/imx51.c ++++ b/arch/arm/mach-imx/imx51.c +@@ -15,7 +15,10 @@ + * MA 02111-1307 USA + */ + ++#include <init.h> + #include <common.h> ++#include <asm/io.h> ++#include <mach/imx51-regs.h> + + #include "gpio.h" + +@@ -28,3 +31,51 @@ void *imx_gpio_base[] = { + + int imx_gpio_count = ARRAY_SIZE(imx_gpio_base) * 32; + ++#define SI_REV 0x48 ++ ++static u32 mx51_silicon_revision; ++static char *mx51_rev_string = "unknown"; ++ ++int imx_silicon_revision(void) ++{ ++ return mx51_silicon_revision; ++} ++ ++static int query_silicon_revision(void) ++{ ++ void __iomem *rom = MX51_IROM_BASE_ADDR; ++ u32 rev; ++ ++ rev = readl(rom + SI_REV); ++ switch (rev) { ++ case 0x1: ++ mx51_silicon_revision = MX51_CHIP_REV_1_0; ++ mx51_rev_string = "1.0"; ++ break; ++ case 0x2: ++ mx51_silicon_revision = MX51_CHIP_REV_1_1; ++ mx51_rev_string = "1.1"; ++ break; ++ case 0x10: ++ mx51_silicon_revision = MX51_CHIP_REV_2_0; ++ mx51_rev_string = "2.0"; ++ break; ++ case 0x20: ++ mx51_silicon_revision = MX51_CHIP_REV_3_0; ++ mx51_rev_string = "3.0"; ++ break; ++ default: ++ mx51_silicon_revision = 0; ++ } ++ ++ return 0; ++} ++core_initcall(query_silicon_revision); ++ ++static int imx51_print_silicon_rev(void) ++{ ++ printf("detected i.MX51 rev %s\n", mx51_rev_string); ++ ++ return 0; ++} ++device_initcall(imx51_print_silicon_rev); +diff --git a/arch/arm/mach-imx/include/mach/clock-imx51.h b/arch/arm/mach-imx/include/mach/clock-imx51.h +new file mode 100644 +index 0000000..0dee7c3 +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/clock-imx51.h +@@ -0,0 +1,696 @@ ++/* ++ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. ++ */ ++ ++/* ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ ++#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ ++ ++/* PLL Register Offsets */ ++#define MX51_PLL_DP_CTL 0x00 ++#define MX51_PLL_DP_CONFIG 0x04 ++#define MX51_PLL_DP_OP 0x08 ++#define MX51_PLL_DP_MFD 0x0C ++#define MX51_PLL_DP_MFN 0x10 ++#define MX51_PLL_DP_MFNMINUS 0x14 ++#define MX51_PLL_DP_MFNPLUS 0x18 ++#define MX51_PLL_DP_HFS_OP 0x1C ++#define MX51_PLL_DP_HFS_MFD 0x20 ++#define MX51_PLL_DP_HFS_MFN 0x24 ++#define MX51_PLL_DP_MFN_TOGC 0x28 ++#define MX51_PLL_DP_DESTAT 0x2c ++ ++/* PLL Register Bit definitions */ ++#define MX51_PLL_DP_CTL_MUL_CTRL 0x2000 ++#define MX51_PLL_DP_CTL_DPDCK0_2_EN 0x1000 ++#define MX51_PLL_DP_CTL_DPDCK0_2_OFFSET 12 ++#define MX51_PLL_DP_CTL_ADE 0x800 ++#define MX51_PLL_DP_CTL_REF_CLK_DIV 0x400 ++#define MX51_PLL_DP_CTL_REF_CLK_SEL_MASK (3 << 8) ++#define MX51_PLL_DP_CTL_REF_CLK_SEL_OFFSET 8 ++#define MX51_PLL_DP_CTL_HFSM 0x80 ++#define MX51_PLL_DP_CTL_PRE 0x40 ++#define MX51_PLL_DP_CTL_UPEN 0x20 ++#define MX51_PLL_DP_CTL_RST 0x10 ++#define MX51_PLL_DP_CTL_RCP 0x8 ++#define MX51_PLL_DP_CTL_PLM 0x4 ++#define MX51_PLL_DP_CTL_BRM0 0x2 ++#define MX51_PLL_DP_CTL_LRF 0x1 ++ ++#define MX51_PLL_DP_CONFIG_BIST 0x8 ++#define MX51_PLL_DP_CONFIG_SJC_CE 0x4 ++#define MX51_PLL_DP_CONFIG_AREN 0x2 ++#define MX51_PLL_DP_CONFIG_LDREQ 0x1 ++ ++#define MX51_PLL_DP_OP_MFI_OFFSET 4 ++#define MX51_PLL_DP_OP_MFI_MASK (0xF << 4) ++#define MX51_PLL_DP_OP_PDF_OFFSET 0 ++#define MX51_PLL_DP_OP_PDF_MASK 0xF ++ ++#define MX51_PLL_DP_MFD_OFFSET 0 ++#define MX51_PLL_DP_MFD_MASK 0x07FFFFFF ++ ++#define MX51_PLL_DP_MFN_OFFSET 0x0 ++#define MX51_PLL_DP_MFN_MASK 0x07FFFFFF ++ ++#define MX51_PLL_DP_MFN_TOGC_TOG_DIS (1 << 17) ++#define MX51_PLL_DP_MFN_TOGC_TOG_EN (1 << 16) ++#define MX51_PLL_DP_MFN_TOGC_CNT_OFFSET 0x0 ++#define MX51_PLL_DP_MFN_TOGC_CNT_MASK 0xFFFF ++ ++#define MX51_PLL_DP_DESTAT_TOG_SEL (1 << 31) ++#define MX51_PLL_DP_DESTAT_MFN 0x07FFFFFF ++ ++/* Assuming 24MHz input clock with doubler ON */ ++/* MFI PDF */ ++#define MX51_PLL_DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) ++#define MX51_PLL_DP_MFD_850 (48 - 1) ++#define MX51_PLL_DP_MFN_850 41 ++ ++#define MX51_PLL_DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) ++#define MX51_PLL_DP_MFD_800 (3 - 1) ++#define MX51_PLL_DP_MFN_800 1 ++ ++#define MX51_PLL_DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) ++#define MX51_PLL_DP_MFD_700 (24 - 1) ++#define MX51_PLL_DP_MFN_700 7 ++ ++#define MX51_PLL_DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) ++#define MX51_PLL_DP_MFD_665 (96 - 1) ++#define MX51_PLL_DP_MFN_665 89 ++ ++#define MX51_PLL_DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) ++#define MX51_PLL_DP_MFD_532 (24 - 1) ++#define MX51_PLL_DP_MFN_532 13 ++ ++#define MX51_PLL_DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) ++#define MX51_PLL_DP_MFD_400 (3 - 1) ++#define MX51_PLL_DP_MFN_400 1 ++ ++#define MX51_PLL_DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) ++#define MX51_PLL_DP_MFD_216 (4 - 1) ++#define MX51_PLL_DP_MFN_216 3 ++ ++/* Register addresses of CCM*/ ++#define MX51_CCM_CCR 0x00 ++#define MX51_CCM_CCDR 0x04 ++#define MX51_CCM_CSR 0x08 ++#define MX51_CCM_CCSR 0x0C ++#define MX51_CCM_CACRR 0x10 ++#define MX51_CCM_CBCDR 0x14 ++#define MX51_CCM_CBCMR 0x18 ++#define MX51_CCM_CSCMR1 0x1C ++#define MX51_CCM_CSCMR2 0x20 ++#define MX51_CCM_CSCDR1 0x24 ++#define MX51_CCM_CS1CDR 0x28 ++#define MX51_CCM_CS2CDR 0x2C ++#define MX51_CCM_CDCDR 0x30 ++#define MX51_CCM_CHSCDR 0x34 ++#define MX51_CCM_CSCDR2 0x38 ++#define MX51_CCM_CSCDR3 0x3C ++#define MX51_CCM_CSCDR4 0x40 ++#define MX51_CCM_CWDR 0x44 ++#define MX51_CCM_CDHIPR 0x48 ++#define MX51_CCM_CDCR 0x4C ++#define MX51_CCM_CTOR 0x50 ++#define MX51_CCM_CLPCR 0x54 ++#define MX51_CCM_CISR 0x58 ++#define MX51_CCM_CIMR 0x5C ++#define MX51_CCM_CCOSR 0x60 ++#define MX51_CCM_CGPR 0x64 ++#define MX51_CCM_CCGR0 0x68 ++#define MX51_CCM_CCGR1 0x6C ++#define MX51_CCM_CCGR2 0x70 ++#define MX51_CCM_CCGR3 0x74 ++#define MX51_CCM_CCGR4 0x78 ++#define MX51_CCM_CCGR5 0x7C ++#define MX51_CCM_CCGR6 0x80 ++#define MX51_CCM_CMEOR 0x84 ++ ++/* Define the bits in register CCR */ ++#define MX51_CCM_CCR_COSC_EN (1 << 12) ++#define MX51_CCM_CCR_FPM_MULT_MASK (1 << 11) ++#define MX51_CCM_CCR_CAMP2_EN (1 << 10) ++#define MX51_CCM_CCR_CAMP1_EN (1 << 9) ++#define MX51_CCM_CCR_FPM_EN (1 << 8) ++#define MX51_CCM_CCR_OSCNT_OFFSET (0) ++#define MX51_CCM_CCR_OSCNT_MASK (0xFF) ++ ++/* Define the bits in register CCDR */ ++#define MX51_CCM_CCDR_HSC_HS_MASK (0x1 << 18) ++#define MX51_CCM_CCDR_IPU_HS_MASK (0x1 << 17) ++#define MX51_CCM_CCDR_EMI_HS_MASK (0x1 << 16) ++ ++/* Define the bits in register CSR */ ++#define MX51_CCM_CSR_COSR_READY (1 << 5) ++#define MX51_CCM_CSR_LVS_VALUE (1 << 4) ++#define MX51_CCM_CSR_CAMP2_READY (1 << 3) ++#define MX51_CCM_CSR_CAMP1_READY (1 << 2) ++#define MX51_CCM_CSR_FPM_READY (1 << 1) ++#define MX51_CCM_CSR_REF_EN_B (1 << 0) ++ ++/* Define the bits in register CCSR */ ++#define MX51_CCM_CCSR_LP_APM_SEL (0x1 << 9) ++#define MX51_CCM_CCSR_STEP_SEL_OFFSET (7) ++#define MX51_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) ++#define MX51_CCM_CCSR_PLL2_PODF_OFFSET (5) ++#define MX51_CCM_CCSR_PLL2_PODF_MASK (0x3 << 5) ++#define MX51_CCM_CCSR_PLL3_PODF_OFFSET (3) ++#define MX51_CCM_CCSR_PLL3_PODF_MASK (0x3 << 3) ++#define MX51_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2) ++#define MX51_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1) ++#define MX51_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0) ++ ++/* Define the bits in register CACRR */ ++#define MX51_CCM_CACRR_ARM_PODF_OFFSET (0) ++#define MX51_CCM_CACRR_ARM_PODF_MASK (0x7) ++ ++/* Define the bits in register CBCDR */ ++#define MX51_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) ++#define MX51_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) ++#define MX51_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) ++#define MX51_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) ++#define MX51_CCM_CBCDR_DDR_PODF_OFFSET (27) ++#define MX51_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) ++#define MX51_CCM_CBCDR_EMI_PODF_OFFSET (22) ++#define MX51_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) ++#define MX51_CCM_CBCDR_AXI_B_PODF_OFFSET (19) ++#define MX51_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) ++#define MX51_CCM_CBCDR_AXI_A_PODF_OFFSET (16) ++#define MX51_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) ++#define MX51_CCM_CBCDR_NFC_PODF_OFFSET (13) ++#define MX51_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) ++#define MX51_CCM_CBCDR_AHB_PODF_OFFSET (10) ++#define MX51_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) ++#define MX51_CCM_CBCDR_IPG_PODF_OFFSET (8) ++#define MX51_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) ++#define MX51_CCM_CBCDR_PERCLK_PRED1_OFFSET (6) ++#define MX51_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) ++#define MX51_CCM_CBCDR_PERCLK_PRED2_OFFSET (3) ++#define MX51_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) ++#define MX51_CCM_CBCDR_PERCLK_PODF_OFFSET (0) ++#define MX51_CCM_CBCDR_PERCLK_PODF_MASK (0x7) ++ ++/* Define the bits in register CBCMR */ ++#define MX51_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET (14) ++#define MX51_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) ++#define MX51_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET (12) ++#define MX51_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) ++#define MX51_CCM_CBCMR_DDR_CLK_SEL_OFFSET (10) ++#define MX51_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) ++#define MX51_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET (8) ++#define MX51_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) ++#define MX51_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET (6) ++#define MX51_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) ++#define MX51_CCM_CBCMR_GPU_CLK_SEL_OFFSET (4) ++#define MX51_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) ++#define MX51_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) ++#define MX51_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) ++#define MX51_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) ++#define MX51_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) ++ ++/* Define the bits in register CSCMR1 */ ++#define MX51_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET (30) ++#define MX51_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) ++#define MX51_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET (28) ++#define MX51_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) ++#define MX51_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET (26) ++#define MX51_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) ++#define MX51_CCM_CSCMR1_UART_CLK_SEL_OFFSET (24) ++#define MX51_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) ++#define MX51_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET (22) ++#define MX51_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) ++#define MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET (20) ++#define MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) ++#define MX51_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) ++#define MX51_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) ++#define MX51_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET (16) ++#define MX51_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) ++#define MX51_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) ++#define MX51_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) ++#define MX51_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET (12) ++#define MX51_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) ++#define MX51_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) ++#define MX51_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) ++#define MX51_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET (8) ++#define MX51_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) ++#define MX51_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) ++#define MX51_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) ++#define MX51_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET (4) ++#define MX51_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) ++#define MX51_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET (2) ++#define MX51_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) ++#define MX51_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) ++#define MX51_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL (0x1) ++ ++/* Define the bits in register CSCMR2 */ ++#define MX51_CCM_CSCMR2_DI_CLK_SEL_OFFSET(n) (26+n*3) ++#define MX51_CCM_CSCMR2_DI_CLK_SEL_MASK(n) (0x7 << (26+n*3)) ++#define MX51_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_OFFSET (24) ++#define MX51_CCM_CSCMR2_CSI_MCLK2_CLK_SEL_MASK (0x3 << 24) ++#define MX51_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_OFFSET (22) ++#define MX51_CCM_CSCMR2_CSI_MCLK1_CLK_SEL_MASK (0x3 << 22) ++#define MX51_CCM_CSCMR2_ESC_CLK_SEL_OFFSET (20) ++#define MX51_CCM_CSCMR2_ESC_CLK_SEL_MASK (0x3 << 20) ++#define MX51_CCM_CSCMR2_HSC2_CLK_SEL_OFFSET (18) ++#define MX51_CCM_CSCMR2_HSC2_CLK_SEL_MASK (0x3 << 18) ++#define MX51_CCM_CSCMR2_HSC1_CLK_SEL_OFFSET (16) ++#define MX51_CCM_CSCMR2_HSC1_CLK_SEL_MASK (0x3 << 16) ++#define MX51_CCM_CSCMR2_HSI2C_CLK_SEL_OFFSET (14) ++#define MX51_CCM_CSCMR2_HSI2C_CLK_SEL_MASK (0x3 << 14) ++#define MX51_CCM_CSCMR2_FIRI_CLK_SEL_OFFSET (12) ++#define MX51_CCM_CSCMR2_FIRI_CLK_SEL_MASK (0x3 << 12) ++#define MX51_CCM_CSCMR2_SIM_CLK_SEL_OFFSET (10) ++#define MX51_CCM_CSCMR2_SIM_CLK_SEL_MASK (0x3 << 10) ++#define MX51_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) ++#define MX51_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) ++#define MX51_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) ++#define MX51_CCM_CSCMR2_SPDIF1_COM (1 << 5) ++#define MX51_CCM_CSCMR2_SPDIF0_COM (1 << 4) ++#define MX51_CCM_CSCMR2_SPDIF1_CLK_SEL_OFFSET (2) ++#define MX51_CCM_CSCMR2_SPDIF1_CLK_SEL_MASK (0x3 << 2) ++#define MX51_CCM_CSCMR2_SPDIF0_CLK_SEL_OFFSET (0) ++#define MX51_CCM_CSCMR2_SPDIF0_CLK_SEL_MASK (0x3) ++ ++/* Define the bits in register CSCDR1 */ ++#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET (22) ++#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) ++#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET (19) ++#define MX51_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) ++#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET (16) ++#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) ++#define MX51_CCM_CSCDR1_PGC_CLK_PODF_OFFSET (14) ++#define MX51_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) ++#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET (11) ++#define MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) ++#define MX51_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET (8) ++#define MX51_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) ++#define MX51_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET (6) ++#define MX51_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) ++#define MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET (3) ++#define MX51_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) ++#define MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET (0) ++#define MX51_CCM_CSCDR1_UART_CLK_PODF_MASK (0x7) ++ ++/* Define the bits in register CS1CDR and CS2CDR */ ++#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PRED_OFFSET (22) ++#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PRED_MASK (0x7 << 22) ++#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PODF_OFFSET (16) ++#define MX51_CCM_CS1CDR_SSI_EXT1_CLK_PODF_MASK (0x3F << 16) ++#define MX51_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET (6) ++#define MX51_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) ++#define MX51_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET (0) ++#define MX51_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F) ++ ++#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PRED_OFFSET (22) ++#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PRED_MASK (0x7 << 22) ++#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PODF_OFFSET (16) ++#define MX51_CCM_CS2CDR_SSI_EXT2_CLK_PODF_MASK (0x3F << 16) ++#define MX51_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET (6) ++#define MX51_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) ++#define MX51_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET (0) ++#define MX51_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F) ++ ++/* Define the bits in register CDCDR */ ++#define MX51_CCM_CDCDR_TVE_CLK_PRED_OFFSET (28) ++#define MX51_CCM_CDCDR_TVE_CLK_PRED_MASK (0x7 << 28) ++#define MX51_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET (25) ++#define MX51_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) ++#define MX51_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET (19) ++#define MX51_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x3F << 19) ++#define MX51_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET (16) ++#define MX51_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 16) ++#define MX51_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET (9) ++#define MX51_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x3F << 9) ++#define MX51_CCM_CDCDR_DI_CLK_PRED_OFFSET (6) ++#define MX51_CCM_CDCDR_DI_CLK_PRED_MASK (0x7 << 6) ++#define MX51_CCM_CDCDR_USB_PHY_PRED_OFFSET (3) ++#define MX51_CCM_CDCDR_USB_PHY_PRED_MASK (0x7 << 3) ++#define MX51_CCM_CDCDR_USB_PHY_PODF_OFFSET (0) ++#define MX51_CCM_CDCDR_USB_PHY_PODF_MASK (0x7) ++ ++/* Define the bits in register CHSCCDR */ ++#define MX51_CCM_CHSCCDR_ESC_CLK_PRED_OFFSET (12) ++#define MX51_CCM_CHSCCDR_ESC_CLK_PRED_MASK (0x7 << 12) ++#define MX51_CCM_CHSCCDR_ESC_CLK_PODF_OFFSET (6) ++#define MX51_CCM_CHSCCDR_ESC_CLK_PODF_MASK (0x3F << 6) ++#define MX51_CCM_CHSCCDR_HSC2_CLK_PODF_OFFSET (3) ++#define MX51_CCM_CHSCCDR_HSC2_CLK_PODF_MASK (0x7 << 3) ++#define MX51_CCM_CHSCCDR_HSC1_CLK_PODF_OFFSET (0) ++#define MX51_CCM_CHSCCDR_HSC1_CLK_PODF_MASK (0x7) ++ ++/* Define the bits in register CSCDR2 */ ++#define MX51_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET (25) ++#define MX51_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) ++#define MX51_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET (19) ++#define MX51_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) ++#define MX51_CCM_CSCDR2_SIM_CLK_PRED_OFFSET (16) ++#define MX51_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) ++#define MX51_CCM_CSCDR2_SIM_CLK_PODF_OFFSET (9) ++#define MX51_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) ++#define MX51_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET (6) ++#define MX51_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) ++#define MX51_CCM_CSCDR2_SLIMBUS_PODF_OFFSET (0) ++#define MX51_CCM_CSCDR2_SLIMBUS_PODF_MASK (0x3F) ++ ++/* Define the bits in register CSCDR3 */ ++#define MX51_CCM_CSCDR3_HSI2C_CLK_PRED_OFFSET (16) ++#define MX51_CCM_CSCDR3_HSI2C_CLK_PRED_MASK (0x7 << 16) ++#define MX51_CCM_CSCDR3_HSI2C_CLK_PODF_OFFSET (9) ++#define MX51_CCM_CSCDR3_HSI2C_CLK_PODF_MASK (0x3F << 9) ++#define MX51_CCM_CSCDR3_FIRI_CLK_PRED_OFFSET (6) ++#define MX51_CCM_CSCDR3_FIRI_CLK_PRED_MASK (0x7 << 6) ++#define MX51_CCM_CSCDR3_FIRI_CLK_PODF_OFFSET (0) ++#define MX51_CCM_CSCDR3_FIRI_CLK_PODF_MASK (0x3F) ++ ++/* Define the bits in register CSCDR4 */ ++#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_OFFSET (16) ++#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PRED_MASK (0x7 << 16) ++#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_OFFSET (9) ++#define MX51_CCM_CSCDR4_CSI_MCLK2_CLK_PODF_MASK (0x3F << 9) ++#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_OFFSET (6) ++#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PRED_MASK (0x7 << 6) ++#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_OFFSET (0) ++#define MX51_CCM_CSCDR4_CSI_MCLK1_CLK_PODF_MASK (0x3F) ++ ++/* Define the bits in register CDHIPR */ ++#define MX51_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) ++#define MX51_CCM_CDHIPR_DDR_HF_CLK_SEL_BUSY (1 << 8) ++#define MX51_CCM_CDHIPR_DDR_PODF_BUSY (1 << 7) ++#define MX51_CCM_CDHIPR_EMI_CLK_SEL_BUSY (1 << 6) ++#define MX51_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) ++#define MX51_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY (1 << 4) ++#define MX51_CCM_CDHIPR_AHB_PODF_BUSY (1 << 3) ++#define MX51_CCM_CDHIPR_EMI_PODF_BUSY (1 << 2) ++#define MX51_CCM_CDHIPR_AXI_B_PODF_BUSY (1 << 1) ++#define MX51_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) ++ ++/* Define the bits in register CDCR */ ++#define MX51_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) ++#define MX51_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) ++#define MX51_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) ++ ++/* Define the bits in register CLPCR */ ++#define MX51_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) ++#define MX51_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) ++#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) ++#define MX51_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) ++#define MX51_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) ++#define MX51_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) ++#define MX51_CCM_CLPCR_BYPASS_RTIC_LPM_HS (0x1 << 17) ++#define MX51_CCM_CLPCR_BYPASS_RNGC_LPM_HS (0x1 << 16) ++#define MX51_CCM_CLPCR_COSC_PWRDOWN (0x1 << 11) ++#define MX51_CCM_CLPCR_STBY_COUNT_OFFSET (9) ++#define MX51_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) ++#define MX51_CCM_CLPCR_VSTBY (0x1 << 8) ++#define MX51_CCM_CLPCR_DIS_REF_OSC (0x1 << 7) ++#define MX51_CCM_CLPCR_SBYOS (0x1 << 6) ++#define MX51_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) ++#define MX51_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) ++#define MX51_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) ++#define MX51_CCM_CLPCR_LPM_OFFSET (0) ++#define MX51_CCM_CLPCR_LPM_MASK (0x3) ++ ++/* Define the bits in register CISR */ ++#define MX51_CCM_CISR_ARM_PODF_LOADED (0x1 << 25) ++#define MX51_CCM_CISR_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) ++#define MX51_CCM_CISR_AHB_PODF_LOADED (0x1 << 20) ++#define MX51_CCM_CISR_EMI_PODF_LOADED (0x1 << 19) ++#define MX51_CCM_CISR_AXI_B_PODF_LOADED (0x1 << 18) ++#define MX51_CCM_CISR_AXI_A_PODF_LOADED (0x1 << 17) ++#define MX51_CCM_CISR_DIVIDER_LOADED (0x1 << 16) ++#define MX51_CCM_CISR_COSC_READY (0x1 << 6) ++#define MX51_CCM_CISR_CKIH2_READY (0x1 << 5) ++#define MX51_CCM_CISR_CKIH_READY (0x1 << 4) ++#define MX51_CCM_CISR_FPM_READY (0x1 << 3) ++#define MX51_CCM_CISR_LRF_PLL3 (0x1 << 2) ++#define MX51_CCM_CISR_LRF_PLL2 (0x1 << 1) ++#define MX51_CCM_CISR_LRF_PLL1 (0x1) ++ ++/* Define the bits in register CIMR */ ++#define MX51_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 25) ++#define MX51_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) ++#define MX51_CCM_CIMR_MASK_EMI_PODF_LOADED (0x1 << 20) ++#define MX51_CCM_CIMR_MASK_AXI_C_PODF_LOADED (0x1 << 19) ++#define MX51_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) ++#define MX51_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) ++#define MX51_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) ++#define MX51_CCM_CIMR_MASK_COSC_READY (0x1 << 5) ++#define MX51_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) ++#define MX51_CCM_CIMR_MASK_FPM_READY (0x1 << 3) ++#define MX51_CCM_CIMR_MASK_LRF_PLL3 (0x1 << 2) ++#define MX51_CCM_CIMR_MASK_LRF_PLL2 (0x1 << 1) ++#define MX51_CCM_CIMR_MASK_LRF_PLL1 (0x1) ++ ++/* Define the bits in register CCOSR */ ++#define MX51_CCM_CCOSR_CKO2_EN_OFFSET (0x1 << 24) ++#define MX51_CCM_CCOSR_CKO2_DIV_OFFSET (21) ++#define MX51_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) ++#define MX51_CCM_CCOSR_CKO2_SEL_OFFSET (16) ++#define MX51_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) ++#define MX51_CCM_CCOSR_CKOL_EN (0x1 << 7) ++#define MX51_CCM_CCOSR_CKOL_DIV_OFFSET (4) ++#define MX51_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) ++#define MX51_CCM_CCOSR_CKOL_SEL_OFFSET (0) ++#define MX51_CCM_CCOSR_CKOL_SEL_MASK (0xF) ++ ++/* Define the bits in registers CGPR */ ++#define MX51_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (0x1 << 4) ++#define MX51_CCM_CGPR_FPM_SEL (0x1 << 3) ++#define MX51_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) ++#define MX51_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) ++ ++/* Define the bits in registers CCGRx */ ++#define MX51_CCM_CCGR_CG_MASK 0x3 ++#define MX51_CCM_CCGR_MOD_OFF 0x0 ++#define MX51_CCM_CCGR_MOD_ON 0x3 ++#define MX51_CCM_CCGR_MOD_IDLE 0x1 ++ ++#define MX51_CCM_CCGR0_CG15_OFFSET 30 ++#define MX51_CCM_CCGR0_CG15_MASK (0x3 << 30) ++#define MX51_CCM_CCGR0_CG14_OFFSET 28 ++#define MX51_CCM_CCGR0_CG14_MASK (0x3 << 28) ++#define MX51_CCM_CCGR0_CG13_OFFSET 26 ++#define MX51_CCM_CCGR0_CG13_MASK (0x3 << 26) ++#define MX51_CCM_CCGR0_CG12_OFFSET 24 ++#define MX51_CCM_CCGR0_CG12_MASK (0x3 << 24) ++#define MX51_CCM_CCGR0_CG11_OFFSET 22 ++#define MX51_CCM_CCGR0_CG11_MASK (0x3 << 22) ++#define MX51_CCM_CCGR0_CG10_OFFSET 20 ++#define MX51_CCM_CCGR0_CG10_MASK (0x3 << 20) ++#define MX51_CCM_CCGR0_CG9_OFFSET 18 ++#define MX51_CCM_CCGR0_CG9_MASK (0x3 << 18) ++#define MX51_CCM_CCGR0_CG8_OFFSET 16 ++#define MX51_CCM_CCGR0_CG8_MASK (0x3 << 16) ++#define MX51_CCM_CCGR0_CG7_OFFSET 14 ++#define MX51_CCM_CCGR0_CG6_OFFSET 12 ++#define MX51_CCM_CCGR0_CG5_OFFSET 10 ++#define MX51_CCM_CCGR0_CG5_MASK (0x3 << 10) ++#define MX51_CCM_CCGR0_CG4_OFFSET 8 ++#define MX51_CCM_CCGR0_CG4_MASK (0x3 << 8) ++#define MX51_CCM_CCGR0_CG3_OFFSET 6 ++#define MX51_CCM_CCGR0_CG3_MASK (0x3 << 6) ++#define MX51_CCM_CCGR0_CG2_OFFSET 4 ++#define MX51_CCM_CCGR0_CG2_MASK (0x3 << 4) ++#define MX51_CCM_CCGR0_CG1_OFFSET 2 ++#define MX51_CCM_CCGR0_CG1_MASK (0x3 << 2) ++#define MX51_CCM_CCGR0_CG0_OFFSET 0 ++#define MX51_CCM_CCGR0_CG0_MASK 0x3 ++ ++#define MX51_CCM_CCGR1_CG15_OFFSET 30 ++#define MX51_CCM_CCGR1_CG14_OFFSET 28 ++#define MX51_CCM_CCGR1_CG13_OFFSET 26 ++#define MX51_CCM_CCGR1_CG12_OFFSET 24 ++#define MX51_CCM_CCGR1_CG11_OFFSET 22 ++#define MX51_CCM_CCGR1_CG10_OFFSET 20 ++#define MX51_CCM_CCGR1_CG9_OFFSET 18 ++#define MX51_CCM_CCGR1_CG8_OFFSET 16 ++#define MX51_CCM_CCGR1_CG7_OFFSET 14 ++#define MX51_CCM_CCGR1_CG6_OFFSET 12 ++#define MX51_CCM_CCGR1_CG5_OFFSET 10 ++#define MX51_CCM_CCGR1_CG4_OFFSET 8 ++#define MX51_CCM_CCGR1_CG3_OFFSET 6 ++#define MX51_CCM_CCGR1_CG2_OFFSET 4 ++#define MX51_CCM_CCGR1_CG1_OFFSET 2 ++#define MX51_CCM_CCGR1_CG0_OFFSET 0 ++ ++#define MX51_CCM_CCGR2_CG15_OFFSET 30 ++#define MX51_CCM_CCGR2_CG14_OFFSET 28 ++#define MX51_CCM_CCGR2_CG13_OFFSET 26 ++#define MX51_CCM_CCGR2_CG12_OFFSET 24 ++#define MX51_CCM_CCGR2_CG11_OFFSET 22 ++#define MX51_CCM_CCGR2_CG10_OFFSET 20 ++#define MX51_CCM_CCGR2_CG9_OFFSET 18 ++#define MX51_CCM_CCGR2_CG8_OFFSET 16 ++#define MX51_CCM_CCGR2_CG7_OFFSET 14 ++#define MX51_CCM_CCGR2_CG6_OFFSET 12 ++#define MX51_CCM_CCGR2_CG5_OFFSET 10 ++#define MX51_CCM_CCGR2_CG4_OFFSET 8 ++#define MX51_CCM_CCGR2_CG3_OFFSET 6 ++#define MX51_CCM_CCGR2_CG2_OFFSET 4 ++#define MX51_CCM_CCGR2_CG1_OFFSET 2 ++#define MX51_CCM_CCGR2_CG0_OFFSET 0 ++ ++#define MX51_CCM_CCGR3_CG15_OFFSET 30 ++#define MX51_CCM_CCGR3_CG14_OFFSET 28 ++#define MX51_CCM_CCGR3_CG13_OFFSET 26 ++#define MX51_CCM_CCGR3_CG12_OFFSET 24 ++#define MX51_CCM_CCGR3_CG11_OFFSET 22 ++#define MX51_CCM_CCGR3_CG10_OFFSET 20 ++#define MX51_CCM_CCGR3_CG9_OFFSET 18 ++#define MX51_CCM_CCGR3_CG8_OFFSET 16 ++#define MX51_CCM_CCGR3_CG7_OFFSET 14 ++#define MX51_CCM_CCGR3_CG6_OFFSET 12 ++#define MX51_CCM_CCGR3_CG5_OFFSET 10 ++#define MX51_CCM_CCGR3_CG4_OFFSET 8 ++#define MX51_CCM_CCGR3_CG3_OFFSET 6 ++#define MX51_CCM_CCGR3_CG2_OFFSET 4 ++#define MX51_CCM_CCGR3_CG1_OFFSET 2 ++#define MX51_CCM_CCGR3_CG0_OFFSET 0 ++ ++#define MX51_CCM_CCGR4_CG15_OFFSET 30 ++#define MX51_CCM_CCGR4_CG14_OFFSET 28 ++#define MX51_CCM_CCGR4_CG13_OFFSET 26 ++#define MX51_CCM_CCGR4_CG12_OFFSET 24 ++#define MX51_CCM_CCGR4_CG11_OFFSET 22 ++#define MX51_CCM_CCGR4_CG10_OFFSET 20 ++#define MX51_CCM_CCGR4_CG9_OFFSET 18 ++#define MX51_CCM_CCGR4_CG8_OFFSET 16 ++#define MX51_CCM_CCGR4_CG7_OFFSET 14 ++#define MX51_CCM_CCGR4_CG6_OFFSET 12 ++#define MX51_CCM_CCGR4_CG5_OFFSET 10 ++#define MX51_CCM_CCGR4_CG4_OFFSET 8 ++#define MX51_CCM_CCGR4_CG3_OFFSET 6 ++#define MX51_CCM_CCGR4_CG2_OFFSET 4 ++#define MX51_CCM_CCGR4_CG1_OFFSET 2 ++#define MX51_CCM_CCGR4_CG0_OFFSET 0 ++ ++#define MX51_CCM_CCGR5_CG15_OFFSET 30 ++#define MX51_CCM_CCGR5_CG14_OFFSET 28 ++#define MX51_CCM_CCGR5_CG14_MASK (0x3 << 28) ++#define MX51_CCM_CCGR5_CG13_OFFSET 26 ++#define MX51_CCM_CCGR5_CG13_MASK (0x3 << 26) ++#define MX51_CCM_CCGR5_CG12_OFFSET 24 ++#define MX51_CCM_CCGR5_CG12_MASK (0x3 << 24) ++#define MX51_CCM_CCGR5_CG11_OFFSET 22 ++#define MX51_CCM_CCGR5_CG11_MASK (0x3 << 22) ++#define MX51_CCM_CCGR5_CG10_OFFSET 20 ++#define MX51_CCM_CCGR5_CG10_MASK (0x3 << 20) ++#define MX51_CCM_CCGR5_CG9_OFFSET 18 ++#define MX51_CCM_CCGR5_CG9_MASK (0x3 << 18) ++#define MX51_CCM_CCGR5_CG8_OFFSET 16 ++#define MX51_CCM_CCGR5_CG8_MASK (0x3 << 16) ++#define MX51_CCM_CCGR5_CG7_OFFSET 14 ++#define MX51_CCM_CCGR5_CG7_MASK (0x3 << 14) ++#define MX51_CCM_CCGR5_CG6_OFFSET 12 ++#define MX51_CCM_CCGR5_CG5_OFFSET 10 ++#define MX51_CCM_CCGR5_CG4_OFFSET 8 ++#define MX51_CCM_CCGR5_CG3_OFFSET 6 ++#define MX51_CCM_CCGR5_CG2_OFFSET 4 ++#define MX51_CCM_CCGR5_CG2_MASK (0x3 << 4) ++#define MX51_CCM_CCGR5_CG1_OFFSET 2 ++#define MX51_CCM_CCGR5_CG0_OFFSET 0 ++#define MX51_CCM_CCGR6_CG7_OFFSET 14 ++#define MX51_CCM_CCGR6_CG7_MASK (0x3 << 14) ++#define MX51_CCM_CCGR6_CG6_OFFSET 12 ++#define MX51_CCM_CCGR6_CG6_MASK (0x3 << 12) ++#define MX51_CCM_CCGR6_CG5_OFFSET 10 ++#define MX51_CCM_CCGR6_CG5_MASK (0x3 << 10) ++#define MX51_CCM_CCGR6_CG4_OFFSET 8 ++#define MX51_CCM_CCGR6_CG4_MASK (0x3 << 8) ++#define MX51_CCM_CCGR6_CG3_OFFSET 6 ++#define MX51_CCM_CCGR6_CG2_OFFSET 4 ++#define MX51_CCM_CCGR6_CG1_OFFSET 2 ++#define MX51_CCM_CCGR6_CG0_OFFSET 0 ++ ++/* CORTEXA8 platform */ ++#define MX51_CORTEXA8_PLAT_PVID (MX51_CORTEXA8_BASE + 0x0) ++#define MX51_CORTEXA8_PLAT_GPC (MX51_CORTEXA8_BASE + 0x4) ++#define MX51_CORTEXA8_PLAT_PIC (MX51_CORTEXA8_BASE + 0x8) ++#define MX51_CORTEXA8_PLAT_LPC (MX51_CORTEXA8_BASE + 0xC) ++#define MX51_CORTEXA8_PLAT_NEON_LPC (MX51_CORTEXA8_BASE + 0x10) ++#define MX51_CORTEXA8_PLAT_ICGC (MX51_CORTEXA8_BASE + 0x14) ++#define MX51_CORTEXA8_PLAT_AMC (MX51_CORTEXA8_BASE + 0x18) ++#define MX51_CORTEXA8_PLAT_NMC (MX51_CORTEXA8_BASE + 0x20) ++#define MX51_CORTEXA8_PLAT_NMS (MX51_CORTEXA8_BASE + 0x24) ++ ++/* DVFS CORE */ ++#define MX51_DVFSTHRS (MX51_DVFS_CORE_BASE + 0x00) ++#define MX51_DVFSCOUN (MX51_DVFS_CORE_BASE + 0x04) ++#define MX51_DVFSSIG1 (MX51_DVFS_CORE_BASE + 0x08) ++#define MX51_DVFSSIG0 (MX51_DVFS_CORE_BASE + 0x0C) ++#define MX51_DVFSGPC0 (MX51_DVFS_CORE_BASE + 0x10) ++#define MX51_DVFSGPC1 (MX51_DVFS_CORE_BASE + 0x14) ++#define MX51_DVFSGPBT (MX51_DVFS_CORE_BASE + 0x18) ++#define MX51_DVFSEMAC (MX51_DVFS_CORE_BASE + 0x1C) ++#define MX51_DVFSCNTR (MX51_DVFS_CORE_BASE + 0x20) ++#define MX51_DVFSLTR0_0 (MX51_DVFS_CORE_BASE + 0x24) ++#define MX51_DVFSLTR0_1 (MX51_DVFS_CORE_BASE + 0x28) ++#define MX51_DVFSLTR1_0 (MX51_DVFS_CORE_BASE + 0x2C) ++#define MX51_DVFSLTR1_1 (MX51_DVFS_CORE_BASE + 0x30) ++#define MX51_DVFSPT0 (MX51_DVFS_CORE_BASE + 0x34) ++#define MX51_DVFSPT1 (MX51_DVFS_CORE_BASE + 0x38) ++#define MX51_DVFSPT2 (MX51_DVFS_CORE_BASE + 0x3C) ++#define MX51_DVFSPT3 (MX51_DVFS_CORE_BASE + 0x40) ++ ++/* GPC */ ++#define MX51_GPC_CNTR (MX51_GPC_BASE + 0x0) ++#define MX51_GPC_PGR (MX51_GPC_BASE + 0x4) ++#define MX51_GPC_VCR (MX51_GPC_BASE + 0x8) ++#define MX51_GPC_ALL_PU (MX51_GPC_BASE + 0xC) ++#define MX51_GPC_NEON (MX51_GPC_BASE + 0x10) ++#define MX51_GPC_PGR_ARMPG_OFFSET 8 ++#define MX51_GPC_PGR_ARMPG_MASK (3 << 8) ++ ++/* PGC */ ++#define MX51_PGC_IPU_PGCR (MX51_PGC_IPU_BASE + 0x0) ++#define MX51_PGC_IPU_PGSR (MX51_PGC_IPU_BASE + 0xC) ++#define MX51_PGC_VPU_PGCR (MX51_PGC_VPU_BASE + 0x0) ++#define MX51_PGC_VPU_PGSR (MX51_PGC_VPU_BASE + 0xC) ++#define MX51_PGC_GPU_PGCR (MX51_PGC_GPU_BASE + 0x0) ++#define MX51_PGC_GPU_PGSR (MX51_PGC_GPU_BASE + 0xC) ++ ++#define MX51_PGCR_PCR 1 ++#define MX51_SRPGCR_PCR 1 ++#define MX51_EMPGCR_PCR 1 ++#define MX51_PGSR_PSR 1 ++ ++ ++#define MX51_CORTEXA8_PLAT_LPC_DSM (1 << 0) ++#define MX51_CORTEXA8_PLAT_LPC_DBG_DSM (1 << 1) ++ ++/* SRPG */ ++#define MX51_SRPG_NEON_SRPGCR (MX51_SRPG_NEON_BASE + 0x0) ++#define MX51_SRPG_NEON_PUPSCR (MX51_SRPG_NEON_BASE + 0x4) ++#define MX51_SRPG_NEON_PDNSCR (MX51_SRPG_NEON_BASE + 0x8) ++ ++#define MX51_SRPG_ARM_SRPGCR (MX51_SRPG_ARM_BASE + 0x0) ++#define MX51_SRPG_ARM_PUPSCR (MX51_SRPG_ARM_BASE + 0x4) ++#define MX51_SRPG_ARM_PDNSCR (MX51_SRPG_ARM_BASE + 0x8) ++ ++#define MX51_SRPG_EMPGC0_SRPGCR (MX51_SRPG_EMPGC0_BASE + 0x0) ++#define MX51_SRPG_EMPGC0_PUPSCR (MX51_SRPG_EMPGC0_BASE + 0x4) ++#define MX51_SRPG_EMPGC0_PDNSCR (MX51_SRPG_EMPGC0_BASE + 0x8) ++ ++#define MX51_SRPG_EMPGC1_SRPGCR (MX51_SRPG_EMPGC1_BASE + 0x0) ++#define MX51_SRPG_EMPGC1_PUPSCR (MX51_SRPG_EMPGC1_BASE + 0x4) ++#define MX51_SRPG_EMPGC1_PDNSCR (MX51_SRPG_EMPGC1_BASE + 0x8) ++ ++#define MX51_SRPG_MEGAMIX_SRPGCR (MX51_SRPG_MEGAMIX_BASE + 0x0) ++#define MX51_SRPG_MEGAMIX_PUPSCR (MX51_SRPG_MEGAMIX_BASE + 0x4) ++#define MX51_SRPG_MEGAMIX_PDNSCR (MX51_SRPG_MEGAMIX_BASE + 0x8) ++ ++#define MX51_SRPGC_EMI_SRPGCR (MX51_SRPGC_EMI_BASE + 0x0) ++#define MX51_SRPGC_EMI_PUPSCR (MX51_SRPGC_EMI_BASE + 0x4) ++#define MX51_SRPGC_EMI_PDNSCR (MX51_SRPGC_EMI_BASE + 0x8) ++ ++#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ ++ ++ +diff --git a/arch/arm/mach-imx/include/mach/clock.h b/arch/arm/mach-imx/include/mach/clock.h +index 76ab4a5..5b590a2 100644 +--- a/arch/arm/mach-imx/include/mach/clock.h ++++ b/arch/arm/mach-imx/include/mach/clock.h +@@ -28,8 +28,11 @@ ulong imx_get_gptclk(void); + ulong imx_get_uartclk(void); + ulong imx_get_lcdclk(void); + ulong imx_get_i2cclk(void); ++ulong imx_get_mmcclk(void); + + int imx_clko_set_div(int div); + void imx_clko_set_src(int src); + ++void imx_dump_clocks(void); ++ + #endif /* __ASM_ARCH_CLOCK_H */ +diff --git a/arch/arm/mach-imx/include/mach/devices-imx21.h b/arch/arm/mach-imx/include/mach/devices-imx21.h +new file mode 100644 +index 0000000..1e1fbbd +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/devices-imx21.h +@@ -0,0 +1,33 @@ ++ ++#include <mach/devices.h> ++ ++static inline struct device_d *imx21_add_uart0(void) ++{ ++ return imx_add_uart((void *)IMX_UART1_BASE, 0); ++} ++ ++static inline struct device_d *imx21_add_uart1(void) ++{ ++ return imx_add_uart((void *)IMX_UART2_BASE, 1); ++} ++ ++static inline struct device_d *imx21_add_uart2(void) ++{ ++ return imx_add_uart((void *)IMX_UART3_BASE, 2); ++} ++ ++static inline struct device_d *imx21_add_uart3(void) ++{ ++ return imx_add_uart((void *)IMX_UART4_BASE, 3); ++} ++ ++static inline struct device_d *imx21_add_nand(struct imx_nand_platform_data *pdata) ++{ ++ return imx_add_nand((void *)0xDF003000, pdata); ++} ++ ++static inline struct device_d *imx21_add_fb(struct imx_fb_platform_data *pdata) ++{ ++ return imx_add_fb((void *)0x10021000, pdata); ++} ++ +diff --git a/arch/arm/mach-imx/include/mach/devices-imx25.h b/arch/arm/mach-imx/include/mach/devices-imx25.h +new file mode 100644 +index 0000000..87f5ba0 +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/devices-imx25.h +@@ -0,0 +1,38 @@ ++ ++#include <mach/devices.h> ++ ++static inline struct device_d *imx25_add_i2c0(struct i2c_platform_data *pdata) ++{ ++ return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); ++} ++ ++static inline struct device_d *imx25_add_uart0(void) ++{ ++ return imx_add_uart((void *)IMX_UART1_BASE, 0); ++} ++ ++static inline struct device_d *imx25_add_uart1(void) ++{ ++ return imx_add_uart((void *)IMX_UART2_BASE, 1); ++} ++ ++static inline struct device_d *imx25_add_nand(struct imx_nand_platform_data *pdata) ++{ ++ return imx_add_nand((void *)IMX_NFC_BASE, pdata); ++} ++ ++static inline struct device_d *imx25_add_fb(struct imx_fb_platform_data *pdata) ++{ ++ return imx_add_fb((void *)0x53fbc000, pdata); ++} ++ ++static inline struct device_d *imx25_add_fec(struct fec_platform_data *pdata) ++{ ++ return imx_add_fec((void *)IMX_FEC_BASE, pdata); ++} ++ ++static inline struct device_d *imx25_add_mmc0(void *pdata) ++{ ++ return imx_add_esdhc((void *)0x53fb4000, 0, pdata); ++} ++ +diff --git a/arch/arm/mach-imx/include/mach/devices-imx27.h b/arch/arm/mach-imx/include/mach/devices-imx27.h +new file mode 100644 +index 0000000..0511eb5 +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/devices-imx27.h +@@ -0,0 +1,54 @@ ++ ++#include <mach/devices.h> ++ ++static inline struct device_d *imx27_add_spi0(struct spi_imx_master *pdata) ++{ ++ return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata); ++} ++ ++static inline struct device_d *imx27_add_i2c0(struct i2c_platform_data *pdata) ++{ ++ return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); ++} ++ ++static inline struct device_d *imx27_add_uart0(void) ++{ ++ return imx_add_uart((void *)IMX_UART1_BASE, 0); ++} ++ ++static inline struct device_d *imx27_add_uart1(void) ++{ ++ return imx_add_uart((void *)IMX_UART2_BASE, 1); ++} ++ ++static inline struct device_d *imx27_add_uart2(void) ++{ ++ return imx_add_uart((void *)IMX_UART3_BASE, 2); ++} ++ ++static inline struct device_d *imx27_add_uart3(void) ++{ ++ return imx_add_uart((void *)IMX_UART4_BASE, 3); ++} ++ ++static inline struct device_d *imx27_add_nand(struct imx_nand_platform_data *pdata) ++{ ++ return imx_add_nand((void *)IMX_NFC_BASE, pdata); ++} ++ ++static inline struct device_d *imx27_add_fb(struct imx_fb_platform_data *pdata) ++{ ++ return imx_add_fb((void *)0x10021000, pdata); ++} ++ ++static inline struct device_d *imx27_add_fec(struct fec_platform_data *pdata) ++{ ++ return imx_add_fec((void *)IMX_FEC_BASE, pdata); ++} ++ ++static inline struct device_d *imx27_add_mmc0(void *pdata) ++{ ++ return imx_add_mmc((void *)0x10014000, 0, pdata); ++} ++ ++ +diff --git a/arch/arm/mach-imx/include/mach/devices-imx31.h b/arch/arm/mach-imx/include/mach/devices-imx31.h +new file mode 100644 +index 0000000..5dcea82 +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/devices-imx31.h +@@ -0,0 +1,35 @@ ++ ++#include <mach/imx-regs.h> ++#include <mach/devices.h> ++ ++#if 0 ++static inline struct device_d *imx31_add_spi0(struct spi_imx_master *pdata) ++{ ++ return imx_add_spi((void *)IMX_SPI1_BASE, 0, pdata); ++} ++ ++static inline struct device_d *imx31_add_spi1(struct spi_imx_master *pdata) ++{ ++ return imx_add_spi((void *)IMX_SPI2_BASE, 1, pdata); ++} ++#endif ++ ++static inline struct device_d *imx31_add_uart0(void) ++{ ++ return imx_add_uart((void *)IMX_UART1_BASE, 0); ++} ++ ++static inline struct device_d *imx31_add_uart1(void) ++{ ++ return imx_add_uart((void *)IMX_UART2_BASE, 1); ++} ++ ++static inline struct device_d *imx31_add_nand(struct imx_nand_platform_data *pdata) ++{ ++ return imx_add_nand((void *)0xb8000000, pdata); ++} ++ ++static inline struct device_d *imx31_add_fb(struct imx_ipu_fb_platform_data *pdata) ++{ ++ return imx_add_ipufb((void *)IPU_BASE, pdata); ++} +diff --git a/arch/arm/mach-imx/include/mach/devices-imx35.h b/arch/arm/mach-imx/include/mach/devices-imx35.h +new file mode 100644 +index 0000000..69f4b36 +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/devices-imx35.h +@@ -0,0 +1,57 @@ ++ ++#include <mach/devices.h> ++ ++static inline struct device_d *imx35_add_i2c0(struct i2c_platform_data *pdata) ++{ ++ return imx_add_i2c((void *)IMX_I2C1_BASE, 0, pdata); ++} ++ ++static inline struct device_d *imx35_add_i2c1(struct i2c_platform_data *pdata) ++{ ++ return imx_add_i2c((void *)IMX_I2C2_BASE, 1, pdata); ++} ++ ++static inline struct device_d *imx35_add_i2c2(struct i2c_platform_data *pdata) ++{ ++ return imx_add_i2c((void *)IMX_I2C3_BASE, 2, pdata); ++} ++ ++static inline struct device_d *imx35_add_uart0(void) ++{ ++ return imx_add_uart((void *)IMX_UART1_BASE, 0); ++} ++ ++static inline struct device_d *imx35_add_uart1(void) ++{ ++ return imx_add_uart((void *)IMX_UART2_BASE, 1); ++} ++ ++static inline struct device_d *imx35_add_nand(struct imx_nand_platform_data *pdata) ++{ ++ return imx_add_nand((void *)IMX_NFC_BASE, pdata); ++} ++ ++static inline struct device_d *imx35_add_fb(struct imx_ipu_fb_platform_data *pdata) ++{ ++ return imx_add_ipufb((void *)IMX_IPU_BASE, pdata); ++} ++ ++static inline struct device_d *imx35_add_fec(struct fec_platform_data *pdata) ++{ ++ return imx_add_fec((void *)IMX_FEC_BASE, pdata); ++} ++ ++static inline struct device_d *imx35_add_mmc0(void *pdata) ++{ ++ return imx_add_esdhc((void *)IMX_SDHC1_BASE, 0, pdata); ++} ++ ++static inline struct device_d *imx35_add_mmc1(void *pdata) ++{ ++ return imx_add_esdhc((void *)IMX_SDHC2_BASE, 1, pdata); ++} ++ ++static inline struct device_d *imx35_add_mmc2(void *pdata) ++{ ++ return imx_add_esdhc((void *)IMX_SDHC3_BASE, 2, pdata); ++} +diff --git a/arch/arm/mach-imx/include/mach/devices-imx51.h b/arch/arm/mach-imx/include/mach/devices-imx51.h +new file mode 100644 +index 0000000..a5deb5c +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/devices-imx51.h +@@ -0,0 +1,58 @@ ++ ++#include <mach/devices.h> ++ ++static inline struct device_d *imx51_add_spi0(struct spi_imx_master *pdata) ++{ ++ return imx_add_spi((void *)MX51_CSPI1_BASE_ADDR, 0, pdata); ++} ++ ++static inline struct device_d *imx51_add_spi1(struct spi_imx_master *pdata) ++{ ++ return imx_add_spi((void *)MX51_CSPI2_BASE_ADDR, 1, pdata); ++} ++ ++static inline struct device_d *imx51_add_spi2(struct spi_imx_master *pdata) ++{ ++ return imx_add_spi((void *)MX51_CSPI3_BASE_ADDR, 2, pdata); ++} ++ ++static inline struct device_d *imx51_add_i2c0(struct i2c_platform_data *pdata) ++{ ++ return imx_add_i2c((void *)MX51_I2C1_BASE_ADDR, 0, pdata); ++} ++ ++static inline struct device_d *imx51_add_i2c1(struct i2c_platform_data *pdata) ++{ ++ return imx_add_i2c((void *)MX51_I2C2_BASE_ADDR, 1, pdata); ++} ++ ++static inline struct device_d *imx51_add_uart0(void) ++{ ++ return imx_add_uart((void *)MX51_UART1_BASE_ADDR, 0); ++} ++ ++static inline struct device_d *imx51_add_uart1(void) ++{ ++ return imx_add_uart((void *)MX51_UART2_BASE_ADDR, 1); ++} ++ ++static inline struct device_d *imx51_add_fec(struct fec_platform_data *pdata) ++{ ++ return imx_add_fec((void *)MX51_MXC_FEC_BASE_ADDR, pdata); ++} ++ ++static inline struct device_d *imx51_add_mmc0(void *pdata) ++{ ++ return imx_add_esdhc((void *)MX51_MMC_SDHC1_BASE_ADDR, 0, pdata); ++} ++ ++static inline struct device_d *imx51_add_mmc1(void *pdata) ++{ ++ return imx_add_esdhc((void *)MX51_MMC_SDHC2_BASE_ADDR, 0, pdata); ++} ++ ++static inline struct device_d *imx51_add_nand(struct imx_nand_platform_data *pdata) ++{ ++ return imx_add_nand((void *)MX51_NFC_AXI_BASE_ADDR, pdata); ++} ++ +diff --git a/arch/arm/mach-imx/include/mach/devices.h b/arch/arm/mach-imx/include/mach/devices.h +new file mode 100644 +index 0000000..7338ac5 +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/devices.h +@@ -0,0 +1,18 @@ ++ ++#include <fec.h> ++#include <i2c/i2c.h> ++#include <mach/spi.h> ++#include <mach/imx-nand.h> ++#include <mach/imxfb.h> ++#include <mach/imx-ipu-fb.h> ++ ++struct device_d *imx_add_fec(void *base, struct fec_platform_data *pdata); ++struct device_d *imx_add_spi(void *base, int id, struct spi_imx_master *pdata); ++struct device_d *imx_add_i2c(void *base, int id, struct i2c_platform_data *pdata); ++struct device_d *imx_add_uart(void *base, int id); ++struct device_d *imx_add_nand(void *base, struct imx_nand_platform_data *pdata); ++struct device_d *imx_add_fb(void *base, struct imx_fb_platform_data *pdata); ++struct device_d *imx_add_ipufb(void *base, struct imx_ipu_fb_platform_data *pdata); ++struct device_d *imx_add_mmc(void *base, int id, void *pdata); ++struct device_d *imx_add_esdhc(void *base, int id, void *pdata); ++ +diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h +index d15f52b..fe74cb6 100644 +--- a/arch/arm/mach-imx/include/mach/esdctl.h ++++ b/arch/arm/mach-imx/include/mach/esdctl.h +@@ -18,9 +18,11 @@ + #define ESDCTL0_ROW13 (2 << 24) + #define ESDCTL0_ROW14 (3 << 24) + #define ESDCTL0_ROW15 (4 << 24) ++#define ESDCTL0_ROW_MASK (7 << 24) + #define ESDCTL0_COL8 (0 << 20) + #define ESDCTL0_COL9 (1 << 20) + #define ESDCTL0_COL10 (2 << 20) ++#define ESDCTL0_COL_MASK (3 << 20) + #define ESDCTL0_DSIZ_31_16 (0 << 16) + #define ESDCTL0_DSIZ_15_0 (1 << 16) + #define ESDCTL0_DSIZ_31_0 (2 << 16) +@@ -32,3 +34,89 @@ + #define ESDCTL0_FP (1 << 8) + #define ESDCTL0_BL (1 << 7) + ++#define ESDMISC_RST 0x00000002 ++#define ESDMISC_MDDR_EN 0x00000004 ++#define ESDMISC_MDDR_DIS 0x00000000 ++#define ESDMISC_MDDR_DL_RST 0x00000008 ++#define ESDMISC_MDDR_MDIS 0x00000010 ++#define ESDMISC_LHD 0x00000020 ++#define ESDMISC_SDRAMRDY 0x80000000 ++ ++#define ESDCFGx_tXP_MASK 0x00600000 ++#define ESDCFGx_tXP_1 0x00000000 ++#define ESDCFGx_tXP_2 0x00200000 ++#define ESDCFGx_tXP_3 0x00400000 ++#define ESDCFGx_tXP_4 0x00600000 ++ ++#define ESDCFGx_tWTR_MASK 0x00100000 ++#define ESDCFGx_tWTR_1 0x00000000 ++#define ESDCFGx_tWTR_2 0x00100000 ++ ++#define ESDCFGx_tRP_MASK 0x000c0000 ++#define ESDCFGx_tRP_1 0x00000000 ++#define ESDCFGx_tRP_2 0x00040000 ++#define ESDCFGx_tRP_3 0x00080000 ++#define ESDCFGx_tRP_4 0x000c0000 ++ ++ ++#define ESDCFGx_tMRD_MASK 0x00030000 ++#define ESDCFGx_tMRD_1 0x00000000 ++#define ESDCFGx_tMRD_2 0x00010000 ++#define ESDCFGx_tMRD_3 0x00020000 ++#define ESDCFGx_tMRD_4 0x00030000 ++ ++ ++#define ESDCFGx_tWR_MASK 0x00008000 ++#define ESDCFGx_tWR_1_2 0x00000000 ++#define ESDCFGx_tWR_2_3 0x00008000 ++ ++#define ESDCFGx_tRAS_MASK 0x00007000 ++#define ESDCFGx_tRAS_1 0x00000000 ++#define ESDCFGx_tRAS_2 0x00001000 ++#define ESDCFGx_tRAS_3 0x00002000 ++#define ESDCFGx_tRAS_4 0x00003000 ++#define ESDCFGx_tRAS_5 0x00004000 ++#define ESDCFGx_tRAS_6 0x00005000 ++#define ESDCFGx_tRAS_7 0x00006000 ++#define ESDCFGx_tRAS_8 0x00007000 ++ ++ ++#define ESDCFGx_tRRD_MASK 0x00000c00 ++#define ESDCFGx_tRRD_1 0x00000000 ++#define ESDCFGx_tRRD_2 0x00000400 ++#define ESDCFGx_tRRD_3 0x00000800 ++#define ESDCFGx_tRRD_4 0x00000c00 ++ ++ ++#define ESDCFGx_tCAS_MASK 0x00000300 ++#define ESDCFGx_tCAS_2 0x00000200 ++#define ESDCFGx_tCAS_3 0x00000300 ++ ++#define ESDCFGx_tRCD_MASK 0x00000070 ++#define ESDCFGx_tRCD_1 0x00000000 ++#define ESDCFGx_tRCD_2 0x00000010 ++#define ESDCFGx_tRCD_3 0x00000020 ++#define ESDCFGx_tRCD_4 0x00000030 ++#define ESDCFGx_tRCD_5 0x00000040 ++#define ESDCFGx_tRCD_6 0x00000050 ++#define ESDCFGx_tRCD_7 0x00000060 ++#define ESDCFGx_tRCD_8 0x00000070 ++ ++#define ESDCFGx_tRC_MASK 0x0000000f ++#define ESDCFGx_tRC_20 0x00000000 ++#define ESDCFGx_tRC_2 0x00000001 ++#define ESDCFGx_tRC_3 0x00000002 ++#define ESDCFGx_tRC_4 0x00000003 ++#define ESDCFGx_tRC_5 0x00000004 ++#define ESDCFGx_tRC_6 0x00000005 ++#define ESDCFGx_tRC_7 0x00000006 ++#define ESDCFGx_tRC_8 0x00000007 ++#define ESDCFGx_tRC_9 0x00000008 ++#define ESDCFGx_tRC_10 0x00000009 ++#define ESDCFGx_tRC_11 0x0000000a ++#define ESDCFGx_tRC_12 0x0000000b ++#define ESDCFGx_tRC_13 0x0000000c ++#define ESDCFGx_tRC_14 0x0000000d ++//#define ESDCFGx_tRC_14 0x0000000e // 15 seems to not exist ++#define ESDCFGx_tRC_16 0x0000000f ++ +diff --git a/arch/arm/mach-imx/include/mach/generic.h b/arch/arm/mach-imx/include/mach/generic.h +index 4b89838..9ca838b 100644 +--- a/arch/arm/mach-imx/include/mach/generic.h ++++ b/arch/arm/mach-imx/include/mach/generic.h +@@ -45,3 +45,9 @@ u64 imx_uid(void); + #define cpu_is_mx35() (0) + #endif + ++#ifdef CONFIG_ARCH_IMX51 ++#define cpu_is_mx51() (1) ++#else ++#define cpu_is_mx51() (0) ++#endif ++ +diff --git a/arch/arm/mach-imx/include/mach/imx-nand.h b/arch/arm/mach-imx/include/mach/imx-nand.h +index 06acddb..eb583a2 100644 +--- a/arch/arm/mach-imx/include/mach/imx-nand.h ++++ b/arch/arm/mach-imx/include/mach/imx-nand.h +@@ -8,8 +8,8 @@ void imx_nand_set_layout(int writesize, int datawidth); + + struct imx_nand_platform_data { + int width; +- int hw_ecc:1; +- int flash_bbt:1; ++ unsigned int hw_ecc:1; ++ unsigned int flash_bbt:1; + }; + #endif /* __ASM_ARCH_NAND_H */ + +diff --git a/arch/arm/mach-imx/include/mach/imx-regs.h b/arch/arm/mach-imx/include/mach/imx-regs.h +index 2cc49dd..605d320 100644 +--- a/arch/arm/mach-imx/include/mach/imx-regs.h ++++ b/arch/arm/mach-imx/include/mach/imx-regs.h +@@ -51,6 +51,8 @@ + # include <mach/imx35-regs.h> + #elif defined CONFIG_ARCH_IMX25 + # include <mach/imx25-regs.h> ++#elif defined CONFIG_ARCH_IMX51 ++#include <mach/imx51-regs.h> + #else + # error "unknown i.MX soc type" + #endif +diff --git a/arch/arm/mach-imx/include/mach/imx1-regs.h b/arch/arm/mach-imx/include/mach/imx1-regs.h +index 0d6fd92..f940cdb 100644 +--- a/arch/arm/mach-imx/include/mach/imx1-regs.h ++++ b/arch/arm/mach-imx/include/mach/imx1-regs.h +@@ -40,14 +40,6 @@ + #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) + #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) + +-/* Watchdog Registers*/ +-#define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +-#define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ +-#define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ +- +-/* important definition of some bits of WCR */ +-#define WCR_WDE 0x01 +- + /* SYSCTRL Registers */ + #define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */ + #define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */ +diff --git a/arch/arm/mach-imx/include/mach/imx21-regs.h b/arch/arm/mach-imx/include/mach/imx21-regs.h +index 6d64b81..a2c4d03 100644 +--- a/arch/arm/mach-imx/include/mach/imx21-regs.h ++++ b/arch/arm/mach-imx/include/mach/imx21-regs.h +@@ -72,14 +72,6 @@ + #define CS5L __REG(IMX_EIM_BASE + 0x2C) /* Chip Select 5 Lower Register */ + #define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ + +-/* Watchdog Registers*/ +-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +-#define WRSR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Reset Status Register */ +- +-/* important definition of some bits of WCR */ +-#define WCR_WDE 0x04 +- + /* PLL registers */ + #define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ + #define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ +diff --git a/arch/arm/mach-imx/include/mach/imx27-regs.h b/arch/arm/mach-imx/include/mach/imx27-regs.h +index f4354ba..e87d5bf 100644 +--- a/arch/arm/mach-imx/include/mach/imx27-regs.h ++++ b/arch/arm/mach-imx/include/mach/imx27-regs.h +@@ -82,14 +82,6 @@ + + #include "esdctl.h" + +-/* Watchdog Registers*/ +-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +-#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ +- +-/* important definition of some bits of WCR */ +-#define WCR_WDE 0x04 +- + /* PLL registers */ + #define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */ + #define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */ +@@ -227,14 +219,6 @@ + #define ESDCFG_TWTR (1 << 20) + #define ESDCFG_TXP(x) (((x) & 0x3) << 21) + +-#define ESDMISC_RST (1 << 1) +-#define ESDMISC_MDDREN (1 << 2) +-#define ESDMISC_MDDR_DL_RST (1 << 3) +-#define ESDMISC_MDDR_MDIS (1 << 4) +-#define ESDMISC_LHD (1 << 5) +-#define ESDMISC_MA10_SHARE (1 << 6) +-#define ESDMISC_SDRAM_RDY (1 << 6) +- + /* + * Definitions for the clocksource driver + */ +diff --git a/arch/arm/mach-imx/include/mach/imx31-regs.h b/arch/arm/mach-imx/include/mach/imx31-regs.h +index d2304ec..536bf0d 100644 +--- a/arch/arm/mach-imx/include/mach/imx31-regs.h ++++ b/arch/arm/mach-imx/include/mach/imx31-regs.h +@@ -120,16 +120,6 @@ + #endif + + /* +- * Watchdog Registers +- */ +-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +-#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ +- +-/* important definition of some bits of WCR */ +-#define WCR_WDE 0x04 +- +-/* + * Clock Controller Module (CCM) + */ + #define IMX_CCM_BASE 0x53f80000 +diff --git a/arch/arm/mach-imx/include/mach/imx35-regs.h b/arch/arm/mach-imx/include/mach/imx35-regs.h +index 5cfb788..75825e5 100644 +--- a/arch/arm/mach-imx/include/mach/imx35-regs.h ++++ b/arch/arm/mach-imx/include/mach/imx35-regs.h +@@ -51,6 +51,9 @@ + #define IMX_SDHC1_BASE 0x53FB4000 + #define IMX_SDHC2_BASE 0x53FB8000 + #define IMX_SDHC3_BASE 0x53FBC000 ++#define IMX_IPU_BASE 0x53FC0000 ++#define IMX_OTG_BASE 0x53FF4000 ++#define IMX_WDOG_BASE 0x53fdc000 + + /* + * Clock Controller Module (CCM) +@@ -73,6 +76,8 @@ + + #define CCM_CGR1_FEC_SHIFT 0 + #define CCM_CGR1_I2C1_SHIFT 10 ++#define CCM_CGR1_SDHC1_SHIFT 26 ++#define CCM_CGR2_USB_SHIFT 22 + + #define PDR0_AUTO_MUX_DIV(x) (((x) & 0x7) << 9) + #define PDR0_CCM_PER_AHB(x) (((x) & 0x7) << 12) +@@ -132,15 +137,5 @@ + #define TSTAT_CAPT (1<<1) /* Capture event */ + #define TSTAT_COMP (1) /* Compare event */ + +-/* +- * Watchdog Registers +- */ +-#define WCR __REG16(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ +-#define WSR __REG16(IMX_WDT_BASE + 0x02) /* Watchdog Service Register */ +-#define WSTR __REG16(IMX_WDT_BASE + 0x04) /* Watchdog Status Register */ +- +-/* important definition of some bits of WCR */ +-#define WCR_WDE 0x04 +- + #endif /* __ASM_ARCH_MX35_REGS_H */ + +diff --git a/arch/arm/mach-imx/include/mach/imx51-regs.h b/arch/arm/mach-imx/include/mach/imx51-regs.h +new file mode 100644 +index 0000000..2e6cacb +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/imx51-regs.h +@@ -0,0 +1,137 @@ ++#ifndef __MACH_IMX51_REGS_H ++#define __MACH_IMX51_REGS_H ++ ++#define IMX_TIM1_BASE 0x73fa0000 ++#define IMX_WDT_BASE 0x73f98000 ++#define IMX_IOMUXC_BASE 0x73fa8000 ++ ++#define GPT_TCTL 0x00 ++#define GPT_TPRER 0x04 ++#define GPT_TCMP 0x10 ++#define GPT_TCR 0x1c ++#define GPT_TCN 0x24 ++#define GPT_TSTAT 0x08 ++ ++/* Part 2: Bitfields */ ++#define TCTL_SWR (1<<15) /* Software reset */ ++#define TCTL_FRR (1<<9) /* Freerun / restart */ ++#define TCTL_CAP (3<<6) /* Capture Edge */ ++#define TCTL_OM (1<<5) /* output mode */ ++#define TCTL_IRQEN (1<<4) /* interrupt enable */ ++#define TCTL_CLKSOURCE (6) /* Clock source bit position */ ++#define TCTL_TEN (1) /* Timer enable */ ++#define TPRER_PRES (0xff) /* Prescale */ ++#define TSTAT_CAPT (1<<1) /* Capture event */ ++#define TSTAT_COMP (1) /* Compare event */ ++ ++#define MX51_IROM_BASE_ADDR 0x0 ++ ++/* ++ * AIPS 1 ++ */ ++#define MX51_AIPS1_BASE_ADDR 0x73F00000 ++ ++#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00080000) ++#define MX51_GPIO1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00084000) ++#define MX51_GPIO2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00088000) ++#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0008C000) ++#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00090000) ++#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00094000) ++#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x00098000) ++#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x0009C000) ++#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A0000) ++#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A4000) ++#define MX51_IOMUXC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000A8000) ++#define MX51_EPIT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000AC000) ++#define MX51_EPIT2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B0000) ++#define MX51_PWM1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B4000) ++#define MX51_PWM2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000B8000) ++#define MX51_UART1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000BC000) ++#define MX51_UART2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000C0000) ++#define MX51_SRC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D0000) ++#define MX51_CCM_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D4000) ++#define MX51_GPC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x000D8000) ++ ++/* ++ * AIPS 2 ++ */ ++#define MX51_AIPS2_BASE_ADDR 0x83F00000 ++ ++#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00080000) ++#define MX51_PLL2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00084000) ++#define MX51_PLL3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00088000) ++#define MX51_AHBMAX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00094000) ++#define MX51_IIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x00098000) ++#define MX51_CSU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x0009C000) ++#define MX51_ARM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A0000) ++#define MX51_OWIRE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A4000) ++#define MX51_FIRI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000A8000) ++#define MX51_CSPI2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000AC000) ++#define MX51_SDMA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B0000) ++#define MX51_SCC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B4000) ++#define MX51_ROMCP_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000B8000) ++#define MX51_RTIC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000BC000) ++#define MX51_CSPI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C0000) ++#define MX51_I2C2_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C4000) ++#define MX51_I2C1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000C8000) ++#define MX51_SSI1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000CC000) ++#define MX51_AUDMUX_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D0000) ++#define MX51_M4IF_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D8000) ++#define MX51_ESDCTL_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000D9000) ++#define MX51_WEIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DA000) ++#define MX51_NFC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DB000) ++#define MX51_EMI_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DBF00) ++#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000DC000) ++#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E0000) ++#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E4000) ++#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000E8000) ++#define MX51_MXC_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000EC000) ++#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F0000) ++#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F4000) ++#define MX51_SAHARA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x000F8000) ++ ++#define MX51_SPBA0_BASE_ADDR 0x70000000 ++#define MX51_MMC_SDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00004000) ++#define MX51_MMC_SDHC2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00008000) ++#define MX51_UART3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0000C000) ++#define MX51_CSPI1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00010000) ++#define MX51_SSI2_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00014000) ++#define MX51_MMC_SDHC3_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00020000) ++#define MX51_MMC_SDHC4_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00024000) ++#define MX51_SPDIF_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00028000) ++#define MX51_ATA_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00030000) ++#define MX51_SLIM_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00034000) ++#define MX51_HSI2C_DMA_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x00038000) ++#define MX51_SPBA_CTRL_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x0003C000) ++ ++#define MX51_NFC_AXI_BASE_ADDR 0xcfff0000 ++ ++/* ++ * Memory regions and CS ++ */ ++#define MX51_GPU_CTRL_BASE_ADDR 0x30000000 ++#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 ++#define MX51_CSD0_BASE_ADDR 0x90000000 ++#define MX51_CSD1_BASE_ADDR 0xA0000000 ++#define MX51_CS0_BASE_ADDR 0xB0000000 ++#define MX51_CS1_BASE_ADDR 0xB8000000 ++#define MX51_CS2_BASE_ADDR 0xC0000000 ++#define MX51_CS3_BASE_ADDR 0xC8000000 ++#define MX51_CS4_BASE_ADDR 0xCC000000 ++#define MX51_CS5_BASE_ADDR 0xCE000000 ++ ++/* silicon revisions specific to i.MX51 */ ++#define MX51_CHIP_REV_1_0 0x10 ++#define MX51_CHIP_REV_1_1 0x11 ++#define MX51_CHIP_REV_1_2 0x12 ++#define MX51_CHIP_REV_1_3 0x13 ++#define MX51_CHIP_REV_2_0 0x20 ++#define MX51_CHIP_REV_2_1 0x21 ++#define MX51_CHIP_REV_2_2 0x22 ++#define MX51_CHIP_REV_2_3 0x23 ++#define MX51_CHIP_REV_3_0 0x30 ++#define MX51_CHIP_REV_3_1 0x31 ++#define MX51_CHIP_REV_3_2 0x32 ++ ++#endif /* __MACH_IMX51_REGS_H */ ++ +diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/mach-imx/include/mach/imxfb.h +index 16b43ea..b71b7f4 100644 +--- a/arch/arm/mach-imx/include/mach/imxfb.h ++++ b/arch/arm/mach-imx/include/mach/imxfb.h +@@ -1,3 +1,6 @@ ++#ifndef __MACH_IMXFB_H ++#define __MACH_IMXFB_H ++ + /* + * This structure describes the machine which we are running on. + */ +@@ -80,6 +83,8 @@ struct imx_fb_platform_data { + + void set_imx_fb_info(struct imx_fb_platform_data *); + ++#endif /* __MACH_IMXFB_H */ ++ + /** + * @file + * @brief i.MX related framebuffer declarations +diff --git a/arch/arm/mach-imx/include/mach/iomux-mx25.h b/arch/arm/mach-imx/include/mach/iomux-mx25.h +index a290a33..a8ca8f1 100644 +--- a/arch/arm/mach-imx/include/mach/iomux-mx25.h ++++ b/arch/arm/mach-imx/include/mach/iomux-mx25.h +@@ -658,21 +658,21 @@ + #define MX25_PAD_RW__EIM_RW IOMUX_PAD(0x278, 0x6c, 0, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_RW__AUD4_TXFS IOMUX_PAD(0x278, 0x6c, 4, 0x474, 0, NO_PAD_CTRL) + #define MX25_PAD_RW__GPIO25 IOMUX_PAD(0x278, 0x6c, 5, 0, 0, NO_PAD_CTRL) +-#define MX25_PAD_SD1_CLK__CLK IOMUX_PAD(0x38c, 0x194, 0, 0, 0, NO_PAD_CTRL) ++#define MX25_PAD_SD1_CLK__CLK IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_CLK__MISO IOMUX_PAD(0x38c, 0x194, 1, 0x49c, 1, NO_PAD_CTRL) + #define MX25_PAD_SD1_CLK__RDATA3 IOMUX_PAD(0x38c, 0x194, 2, 0x510, 2, NO_PAD_CTRL) + #define MX25_PAD_SD1_CLK__SDMA_DBG_STAT_0 IOMUX_PAD(0x38c, 0x194, 4, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_CLK__GPIO24 IOMUX_PAD(0x38c, 0x194, 5, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_CLK__SLCDC_DATA1 IOMUX_PAD(0x38c, 0x194, 6, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_CLK__TRACE11 IOMUX_PAD(0x38c, 0x194, 7, 0, 0, NO_PAD_CTRL) +-#define MX25_PAD_SD1_CMD__CMD IOMUX_PAD(0x388, 0x190, 0, 0, 0, NO_PAD_CTRL) ++#define MX25_PAD_SD1_CMD__CMD IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_CMD__MOSI IOMUX_PAD(0x388, 0x190, 1, 0x4a0, 1, NO_PAD_CTRL) + #define MX25_PAD_SD1_CMD__RDATA2 IOMUX_PAD(0x388, 0x190, 2, 0x50c, 2, NO_PAD_CTRL) + #define MX25_PAD_SD1_CMD__SDMA_DBG_EVT_SEL IOMUX_PAD(0x388, 0x190, 4, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_CMD__GPIO23 IOMUX_PAD(0x388, 0x190, 5, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_CMD__SLCDC_DATA0 IOMUX_PAD(0x388, 0x190, 6, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_CMD__TRACE10 IOMUX_PAD(0x388, 0x190, 7, 0, 0, NO_PAD_CTRL) +-#define MX25_PAD_SD1_DATA0__DAT0 IOMUX_PAD(0x390, 0x198, 0, 0, 0, NO_PAD_CTRL) ++#define MX25_PAD_SD1_DATA0__DAT0 IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA0__SCLK IOMUX_PAD(0x390, 0x198, 1, 0x494, 1, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA0__TDATA2 IOMUX_PAD(0x390, 0x198, 2, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA0__AUD7_TXFS IOMUX_PAD(0x390, 0x198, 3, 0x47c, 0, NO_PAD_CTRL) +@@ -680,7 +680,7 @@ + #define MX25_PAD_SD1_DATA0__GPIO25 IOMUX_PAD(0x390, 0x198, 5, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA0__SLCDC_DATA2 IOMUX_PAD(0x390, 0x198, 6, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA0__TRACE12 IOMUX_PAD(0x390, 0x198, 7, 0, 0, NO_PAD_CTRL) +-#define MX25_PAD_SD1_DATA1__DAT1 IOMUX_PAD(0x394, 0x19c, 0, 0, 0, NO_PAD_CTRL) ++#define MX25_PAD_SD1_DATA1__DAT1 IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA1__RDY IOMUX_PAD(0x394, 0x19c, 1, 0x498, 1, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA1__TDATA3 IOMUX_PAD(0x394, 0x19c, 2, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA1__AUD7_RXD IOMUX_PAD(0x394, 0x19c, 3, 0x478, 0, NO_PAD_CTRL) +@@ -688,7 +688,7 @@ + #define MX25_PAD_SD1_DATA1__GPIO26 IOMUX_PAD(0x394, 0x19c, 5, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA1__SLCDC_DATA3 IOMUX_PAD(0x394, 0x19c, 6, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA1__TRACE13 IOMUX_PAD(0x394, 0x19c, 7, 0, 0, NO_PAD_CTRL) +-#define MX25_PAD_SD1_DATA2__DAT2 IOMUX_PAD(0x398, 0x1a0, 0, 0, 0, NO_PAD_CTRL) ++#define MX25_PAD_SD1_DATA2__DAT2 IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA2__SS0 IOMUX_PAD(0x398, 0x1a0, 1, 0x4a4, 1, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA2__RX_CLK IOMUX_PAD(0x398, 0x1a0, 2, 0x514, 2, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA2__AUD7_RXC IOMUX_PAD(0x398, 0x1a0, 3, 0, 0, NO_PAD_CTRL) +@@ -696,7 +696,7 @@ + #define MX25_PAD_SD1_DATA2__GPIO27 IOMUX_PAD(0x398, 0x1a0, 5, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA2__SLCDC_DATA4 IOMUX_PAD(0x398, 0x1a0, 6, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA2__TRACE14 IOMUX_PAD(0x398, 0x1a0, 7, 0, 0, NO_PAD_CTRL) +-#define MX25_PAD_SD1_DATA3__DAT3 IOMUX_PAD(0x39c, 0x1a4, 0, 0, 0, NO_PAD_CTRL) ++#define MX25_PAD_SD1_DATA3__DAT3 IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA3__SS1 IOMUX_PAD(0x39c, 0x1a4, 1, 0x4a8, 1, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA3__CRS IOMUX_PAD(0x39c, 0x1a4, 2, 0x508, 2, NO_PAD_CTRL) + #define MX25_PAD_SD1_DATA3__AUD7_RXFS IOMUX_PAD(0x39c, 0x1a4, 3, 0, 0, NO_PAD_CTRL) +diff --git a/arch/arm/mach-imx/include/mach/iomux-mx27.h b/arch/arm/mach-imx/include/mach/iomux-mx27.h +index 993b141..23e448b 100644 +--- a/arch/arm/mach-imx/include/mach/iomux-mx27.h ++++ b/arch/arm/mach-imx/include/mach/iomux-mx27.h +@@ -28,6 +28,12 @@ + #define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) + #define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) + #define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) ++#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) ++#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) ++#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) ++#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) ++#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) ++#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) + #define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) + #define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) + #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) +diff --git a/arch/arm/mach-imx/include/mach/iomux-mx35.h b/arch/arm/mach-imx/include/mach/iomux-mx35.h +index 8a56d86..ad7ff56 100644 +--- a/arch/arm/mach-imx/include/mach/iomux-mx35.h ++++ b/arch/arm/mach-imx/include/mach/iomux-mx35.h +@@ -815,42 +815,42 @@ + #define MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1 IOMUX_PAD(0x690, 0x22c, 6, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22 IOMUX_PAD(0x690, 0x22c, 7, 0x0, 0, NO_PAD_CTRL) + +-#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX35_PAD_SD1_CMD__ESDHC1_CMD IOMUX_PAD(0x694, 0x230, 0x10, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_CMD__MSHC_SCLK IOMUX_PAD(0x694, 0x230, 1, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC IOMUX_PAD(0x694, 0x230, 3, 0x924, 2, NO_PAD_CTRL) + #define MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4 IOMUX_PAD(0x694, 0x230, 4, 0x9b4, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_CMD__GPIO1_6 IOMUX_PAD(0x694, 0x230, 5, 0x858, 2, NO_PAD_CTRL) + #define MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL IOMUX_PAD(0x694, 0x230, 7, 0x0, 0, NO_PAD_CTRL) + +-#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX35_PAD_SD1_CLK__ESDHC1_CLK IOMUX_PAD(0x698, 0x234, 0x10, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_CLK__MSHC_BS IOMUX_PAD(0x698, 0x234, 1, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_CLK__IPU_DISPB_BCLK IOMUX_PAD(0x698, 0x234, 3, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5 IOMUX_PAD(0x698, 0x234, 4, 0x9b8, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_CLK__GPIO1_7 IOMUX_PAD(0x698, 0x234, 5, 0x85c, 2, NO_PAD_CTRL) + #define MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK IOMUX_PAD(0x698, 0x234, 7, 0x0, 0, NO_PAD_CTRL) + +-#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX35_PAD_SD1_DATA0__ESDHC1_DAT0 IOMUX_PAD(0x69c, 0x238, 0x10, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA0__MSHC_DATA_0 IOMUX_PAD(0x69c, 0x238, 1, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA0__IPU_DISPB_CS0 IOMUX_PAD(0x69c, 0x238, 3, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6 IOMUX_PAD(0x69c, 0x238, 4, 0x9bc, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA0__GPIO1_8 IOMUX_PAD(0x69c, 0x238, 5, 0x860, 2, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23 IOMUX_PAD(0x69c, 0x238, 7, 0x0, 0, NO_PAD_CTRL) + +-#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX35_PAD_SD1_DATA1__ESDHC1_DAT1 IOMUX_PAD(0x6a0, 0x23c, 0x10, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA1__MSHC_DATA_1 IOMUX_PAD(0x6a0, 0x23c, 1, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS IOMUX_PAD(0x6a0, 0x23c, 3, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0 IOMUX_PAD(0x6a0, 0x23c, 4, 0x9a4, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA1__GPIO1_9 IOMUX_PAD(0x6a0, 0x23c, 5, 0x864, 1, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24 IOMUX_PAD(0x6a0, 0x23c, 7, 0x0, 0, NO_PAD_CTRL) + +-#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX35_PAD_SD1_DATA2__ESDHC1_DAT2 IOMUX_PAD(0x6a4, 0x240, 0x10, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA2__MSHC_DATA_2 IOMUX_PAD(0x6a4, 0x240, 1, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA2__IPU_DISPB_WR IOMUX_PAD(0x6a4, 0x240, 3, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1 IOMUX_PAD(0x6a4, 0x240, 4, 0x9a8, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA2__GPIO1_10 IOMUX_PAD(0x6a4, 0x240, 5, 0x830, 1, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25 IOMUX_PAD(0x6a4, 0x240, 7, 0x0, 0, NO_PAD_CTRL) + +-#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX35_PAD_SD1_DATA3__ESDHC1_DAT3 IOMUX_PAD(0x6a8, 0x244, 0x10, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA3__MSHC_DATA_3 IOMUX_PAD(0x6a8, 0x244, 1, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA3__IPU_DISPB_RD IOMUX_PAD(0x6a8, 0x244, 3, 0x0, 0, NO_PAD_CTRL) + #define MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2 IOMUX_PAD(0x6a8, 0x244, 4, 0x9ac, 0, NO_PAD_CTRL) +diff --git a/arch/arm/mach-imx/include/mach/iomux-mx51.h b/arch/arm/mach-imx/include/mach/iomux-mx51.h +new file mode 100644 +index 0000000..2901ee6 +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/iomux-mx51.h +@@ -0,0 +1,330 @@ ++/* ++ * Copyright (C) 2009 by Sascha Hauer <s.hauer@pengutronix.de> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option, NO_PAD_CTRL) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, ++ * MA 02110-1301, USA. ++ */ ++ ++#ifndef __MACH_IOMUX_MX51_H__ ++#define __MACH_IOMUX_MX51_H__ ++ ++#include <mach/iomux-v3.h> ++ ++#define MX51_FEC_PAD_CTRL (PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRIVE_STRENGTH_HIGH) ++ ++/* ++ * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> ++ * If <padname> or <padmode> refers to a GPIO, it is named ++ * GPIO_<unit>_<num> see also iomux-v3.h ++ */ ++ ++/* PAD MUX ALT INPSE PATH */ ++#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7A8, 0x1C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7A8, 0x20, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7A8, 0x24, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7A8, 0x28, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7AC, 0x2C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7AC, 0x30, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7AC, 0x34, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7AC, 0x38, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7B0, 0x3C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7B0, 0x40, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7B0, 0x44, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7B0, 0x48, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7BC, 0x4C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7BC, 0x50, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7BC, 0x54, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7BC, 0x58, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3F0, 0x5C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3F4, 0x60, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3F8, 0x64, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3FC, 0x68, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40C, 0x78, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41C, 0x88, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42C, 0x98, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xA0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xA4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43C, 0xA8, 0, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xAC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xAC, 1, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xB0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xB4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44C, 0xB8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xBC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xC0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xC4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45C, 0xC8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xCC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xD0, 0, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xD4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x954, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46C, 0xD8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x95c, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xDC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xE0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xE4, 0, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47C, 0xE8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x960, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xEC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0x0ec, 3, 0x964, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xF0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xF4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x52C, 0xF4, 3, 0x950, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48C, 0xF8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xFC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4A0, 0x100, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4E4, 0x108, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4E8, 0x10C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4EC, 0x110, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4F0, 0x114, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4F4, 0x118, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4F8, 0x11C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4FC, 0x120, 0, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_RB4__NANDF_RB4 IOMUX_PAD(0x514, 0x12C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB5__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB6__FEC_RDATA0 IOMUX_PAD(0x5DC, 0x16C, 2, 0x958, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_RB7__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RB7__FEC_TX_ER IOMUX_PAD(0x5E0, 0x138, 2, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51C, 0x134, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0,MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52C, 0x144, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x974, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53C, 0x154, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54C, 0x164, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54C, 0x164, 2, 0x96c, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16C, 0, 0x0, 0, NO_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0, 0, MX51_FEC_PAD_CTRL) ++ ++#define MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55C, 0x174, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56C, 0x184, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57C, 0x194, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5BC, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5C0, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5C4, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5C8, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5CC, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5D0, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5D4, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5D8, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5DC, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5E0, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSI2_PKE0__CSI2_PKE0 IOMUX_PAD(0x81C, NON_MUX_I, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSPI1_SS0__CSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSPI1_SS1__CSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSPI1_RDY__CSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6A8, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6AC, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6B0, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6B4, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6B8, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6BC, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6C0, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6C4, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6C8, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77C, 0x374, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7B4, 0x3AC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7B8, 0x3B0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 0, NO_PAD_CTRL) ++#define MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL) ++#endif /* __MACH_IOMUX_MX51_H__ */ ++ +diff --git a/arch/arm/mach-imx/include/mach/iomux-v3.h b/arch/arm/mach-imx/include/mach/iomux-v3.h +index 1d660a0..198286a 100644 +--- a/arch/arm/mach-imx/include/mach/iomux-v3.h ++++ b/arch/arm/mach-imx/include/mach/iomux-v3.h +@@ -84,13 +84,17 @@ struct pad_desc { + #define PAD_CTL_OUTPUT_CMOS (0) + #define PAD_CTL_OUTPUT_OPEN_DRAIN (1 << 3) + +-#define PAD_CTL_DRIVE_STRENGTH_NORM (0) +-#define PAD_CTL_DRIVE_STRENGTH_HIGH (1 << 1) +-#define PAD_CTL_DRIVE_STRENGTH_MAX (2 << 1) ++#define PAD_CTL_DRIVE_STRENGTH_LOW (0 << 1) ++#define PAD_CTL_DRIVE_STRENGTH_MED (1 << 1) ++#define PAD_CTL_DRIVE_STRENGTH_HIGH (2 << 1) ++#define PAD_CTL_DRIVE_STRENGTH_MAX (3 << 1) + + #define PAD_CTL_SLEW_RATE_SLOW 0 + #define PAD_CTL_SLEW_RATE_FAST 1 + ++#define PAD_CTL_DRV_VOT_LOW (0 << 13) ++#define PAD_CTL_DRV_VOT_HIGH (1 << 13) ++ + /* + * setups a single pad: + * - reserves the pad so that it is not claimed by another driver +diff --git a/arch/arm/mach-imx/include/mach/usb.h b/arch/arm/mach-imx/include/mach/usb.h +new file mode 100644 +index 0000000..5d6670d +--- /dev/null ++++ b/arch/arm/mach-imx/include/mach/usb.h +@@ -0,0 +1,14 @@ ++#ifndef __MACH_USB_H_ ++#define __MACH_USB_H_ ++ ++/* configuration bits for i.MX25 and i.MX35 */ ++#define MX35_H1_SIC_SHIFT 21 ++#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT) ++#define MX35_H1_PM_BIT (1 << 8) ++#define MX35_H1_IPPUE_UP_BIT (1 << 7) ++#define MX35_H1_IPPUE_DOWN_BIT (1 << 6) ++#define MX35_H1_TLL_BIT (1 << 5) ++#define MX35_H1_USBTE_BIT (1 << 4) ++#define MXC_EHCI_INTERFACE_SINGLE_UNI (2 << 0) ++ ++#endif /* __MACH_USB_H_*/ +diff --git a/arch/arm/mach-imx/nand.c b/arch/arm/mach-imx/nand.c +index c228f96..c52b8b0 100644 +--- a/arch/arm/mach-imx/nand.c ++++ b/arch/arm/mach-imx/nand.c +@@ -95,6 +95,15 @@ void imx_nand_set_layout(int writesize, int datawidth) + FMCR = fmcr; + } + ++#elif defined CONFIG_ARCH_IMX51 ++ ++void imx_nand_set_layout(int writesize, int datawidth) ++{ ++ /* Just silence the compiler warning below. On i.MX51 we don't ++ * have external boot. ++ */ ++} ++ + #else + #warning using empty imx_nand_set_layout(). NAND flash will not work properly if not booting from it + +diff --git a/arch/arm/mach-imx/speed-imx25.c b/arch/arm/mach-imx/speed-imx25.c +index 9605674..cb28e9f 100644 +--- a/arch/arm/mach-imx/speed-imx25.c ++++ b/arch/arm/mach-imx/speed-imx25.c +@@ -82,7 +82,12 @@ unsigned long imx_get_i2cclk(void) + return imx_get_perclk(6); + } + +-int imx_dump_clocks(void) ++unsigned long imx_get_mmcclk(void) ++{ ++ return imx_get_perclk(3); ++} ++ ++void imx_dump_clocks(void) + { + printf("mpll: %10d Hz\n", imx_get_mpllclk()); + printf("upll: %10d Hz\n", imx_get_upllclk()); +@@ -92,7 +97,8 @@ int imx_dump_clocks(void) + printf("gpt: %10d Hz\n", imx_get_ipgclk()); + printf("nand: %10d Hz\n", imx_get_perclk(8)); + printf("lcd: %10d Hz\n", imx_get_perclk(7)); +- return 0; ++ printf("i2c: %10d Hz\n", imx_get_perclk(6)); ++ printf("sdhc1: %10d Hz\n", imx_get_perclk(3)); + } + + /* +diff --git a/arch/arm/mach-imx/speed-imx27.c b/arch/arm/mach-imx/speed-imx27.c +index cdcd419..0a92d29 100644 +--- a/arch/arm/mach-imx/speed-imx27.c ++++ b/arch/arm/mach-imx/speed-imx27.c +@@ -159,6 +159,11 @@ ulong imx_get_i2cclk(void) + return imx_get_ipgclk(); + } + ++ulong imx_get_mmcclk(void) ++{ ++ return imx_get_perclk2(); ++} ++ + void imx_dump_clocks(void) + { + uint32_t cid = CID; +diff --git a/arch/arm/mach-imx/speed-imx35.c b/arch/arm/mach-imx/speed-imx35.c +index c5a31c7..8937ef1 100644 +--- a/arch/arm/mach-imx/speed-imx35.c ++++ b/arch/arm/mach-imx/speed-imx35.c +@@ -19,6 +19,7 @@ + #include <mach/imx-regs.h> + #include <asm/io.h> + #include <mach/clock.h> ++#include <mach/generic.h> + #include <init.h> + + unsigned long imx_get_mpllclk(void) +@@ -27,7 +28,7 @@ unsigned long imx_get_mpllclk(void) + return imx_decode_pll(mpctl, CONFIG_MX35_HCLK_FREQ); + } + +-unsigned long imx_get_ppllclk(void) ++static unsigned long imx_get_ppllclk(void) + { + ulong ppctl = readl(IMX_CCM_BASE + CCM_PPCTL); + return imx_decode_pll(ppctl, CONFIG_MX35_HCLK_FREQ); +@@ -56,7 +57,7 @@ static struct arm_ahb_div clk_consumer[] = { + { .arm = 0, .ahb = 0, .sel = 0}, + }; + +-unsigned long imx_get_armclk(void) ++static unsigned long imx_get_armclk(void) + { + unsigned long pdr0 = readl(IMX_CCM_BASE + CCM_PDR0); + struct arm_ahb_div *aad; +@@ -83,7 +84,7 @@ unsigned long imx_get_ahbclk(void) + return fref / aad->ahb; + } + +-unsigned long imx_get_ipgclk(void) ++static unsigned long imx_get_ipgclk(void) + { + ulong clk = imx_get_ahbclk(); + +@@ -95,7 +96,7 @@ static unsigned long get_3_3_div(unsigned long in) + return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1); + } + +-unsigned long imx_get_ipg_perclk(void) ++static unsigned long imx_get_ipg_perclk(void) + { + ulong pdr0 = readl(IMX_CCM_BASE + CCM_PDR0); + ulong pdr4 = readl(IMX_CCM_BASE + CCM_PDR4); +@@ -163,6 +164,17 @@ unsigned long imx_get_uartclk(void) + return imx_get_ppllclk() / div; + } + ++unsigned long imx_get_mmcclk(void) ++{ ++ unsigned long pdr3 = readl(IMX_CCM_BASE + CCM_PDR3); ++ unsigned long div = get_3_3_div(pdr3); ++ ++ if (pdr3 & (1 << 6)) ++ return imx_get_armclk() / div; ++ else ++ return imx_get_ppllclk() / div; ++} ++ + ulong imx_get_fecclk(void) + { + return imx_get_ipgclk(); +@@ -183,6 +195,7 @@ void imx_dump_clocks(void) + printf("ipg: %10d Hz\n", imx_get_ipgclk()); + printf("ipg_per: %10d Hz\n", imx_get_ipg_perclk()); + printf("uart: %10d Hz\n", imx_get_uartclk()); ++ printf("sdhc1: %10d Hz\n", imx_get_mmcclk()); + } + + /* +diff --git a/arch/arm/mach-imx/speed-imx51.c b/arch/arm/mach-imx/speed-imx51.c +new file mode 100644 +index 0000000..9983297 +--- /dev/null ++++ b/arch/arm/mach-imx/speed-imx51.c +@@ -0,0 +1,190 @@ ++#include <common.h> ++#include <asm/io.h> ++#include <asm-generic/div64.h> ++#include <mach/imx51-regs.h> ++#include "mach/clock-imx51.h" ++ ++static u32 ccm_readl(u32 ofs) ++{ ++ return readl(MX51_CCM_BASE_ADDR + ofs); ++} ++ ++static unsigned long ckil_get_rate(void) ++{ ++ return 32768; ++} ++ ++static unsigned long osc_get_rate(void) ++{ ++ return 24000000; ++} ++ ++static unsigned long fpm_get_rate(void) ++{ ++ return ckil_get_rate() * 512; ++} ++ ++static unsigned long pll_get_rate(void __iomem *pllbase) ++{ ++ long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; ++ unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; ++ u64 temp; ++ unsigned long parent_rate; ++ ++ dp_ctl = readl(pllbase + MX51_PLL_DP_CTL); ++ ++ if ((dp_ctl & MX51_PLL_DP_CTL_REF_CLK_SEL_MASK) == 0) ++ parent_rate = fpm_get_rate(); ++ else ++ parent_rate = osc_get_rate(); ++ ++ pll_hfsm = dp_ctl & MX51_PLL_DP_CTL_HFSM; ++ dbl = dp_ctl & MX51_PLL_DP_CTL_DPDCK0_2_EN; ++ ++ if (pll_hfsm == 0) { ++ dp_op = readl(pllbase + MX51_PLL_DP_OP); ++ dp_mfd = readl(pllbase + MX51_PLL_DP_MFD); ++ dp_mfn = readl(pllbase + MX51_PLL_DP_MFN); ++ } else { ++ dp_op = readl(pllbase + MX51_PLL_DP_HFS_OP); ++ dp_mfd = readl(pllbase + MX51_PLL_DP_HFS_MFD); ++ dp_mfn = readl(pllbase + MX51_PLL_DP_HFS_MFN); ++ } ++ pdf = dp_op & MX51_PLL_DP_OP_PDF_MASK; ++ mfi = (dp_op & MX51_PLL_DP_OP_MFI_MASK) >> MX51_PLL_DP_OP_MFI_OFFSET; ++ mfi = (mfi <= 5) ? 5 : mfi; ++ mfd = dp_mfd & MX51_PLL_DP_MFD_MASK; ++ mfn = mfn_abs = dp_mfn & MX51_PLL_DP_MFN_MASK; ++ /* Sign extend to 32-bits */ ++ if (mfn >= 0x04000000) { ++ mfn |= 0xFC000000; ++ mfn_abs = -mfn; ++ } ++ ++ ref_clk = 2 * parent_rate; ++ if (dbl != 0) ++ ref_clk *= 2; ++ ++ ref_clk /= (pdf + 1); ++ temp = (u64)ref_clk * mfn_abs; ++ do_div(temp, mfd + 1); ++ if (mfn < 0) ++ temp = -temp; ++ temp = (ref_clk * mfi) + temp; ++ ++ return temp; ++} ++ ++static unsigned long pll1_main_get_rate(void) ++{ ++ return pll_get_rate((void __iomem *)MX51_PLL1_BASE_ADDR); ++} ++ ++static unsigned long pll2_sw_get_rate(void) ++{ ++ return pll_get_rate((void __iomem *)MX51_PLL2_BASE_ADDR); ++} ++ ++static unsigned long pll3_sw_get_rate(void) ++{ ++ return pll_get_rate((void __iomem *)MX51_PLL3_BASE_ADDR); ++} ++ ++static unsigned long get_rate_select(int select, ++ unsigned long (* get_rate1)(void), ++ unsigned long (* get_rate2)(void), ++ unsigned long (* get_rate3)(void), ++ unsigned long (* get_rate4)(void)) ++{ ++ switch (select) { ++ case 0: ++ return get_rate1() ? get_rate1() : 0; ++ case 1: ++ return get_rate2() ? get_rate2() : 0; ++ case 2: ++ return get_rate3 ? get_rate3() : 0; ++ case 3: ++ return get_rate4 ? get_rate4() : 0; ++ } ++ ++ return 0; ++} ++ ++unsigned long imx_get_uartclk(void) ++{ ++ u32 reg, prediv, podf; ++ unsigned long parent_rate; ++ ++ parent_rate = pll2_sw_get_rate(); ++ ++ reg = ccm_readl(MX51_CCM_CSCDR1); ++ prediv = ((reg & MX51_CCM_CSCDR1_UART_CLK_PRED_MASK) >> ++ MX51_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; ++ podf = ((reg & MX51_CCM_CSCDR1_UART_CLK_PODF_MASK) >> ++ MX51_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; ++ ++ return parent_rate / (prediv * podf); ++} ++ ++static unsigned long imx_get_ahbclk(void) ++{ ++ u32 reg, div; ++ ++ reg = ccm_readl(MX51_CCM_CBCDR); ++ div = ((reg >> 10) & 0x7) + 1; ++ ++ return pll2_sw_get_rate() / div; ++} ++ ++unsigned long imx_get_ipgclk(void) ++{ ++ u32 reg, div; ++ ++ reg = ccm_readl(MX51_CCM_CBCDR); ++ div = ((reg >> 8) & 0x3) + 1; ++ ++ return imx_get_ahbclk() / div; ++} ++ ++unsigned long imx_get_gptclk(void) ++{ ++ return imx_get_ipgclk(); ++} ++ ++unsigned long imx_get_fecclk(void) ++{ ++ return imx_get_ipgclk(); ++} ++ ++unsigned long imx_get_mmcclk(void) ++{ ++ u32 reg, prediv, podf, rate; ++ ++ reg = ccm_readl(MX51_CCM_CSCMR1); ++ reg &= MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK; ++ reg >>= MX51_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET; ++ rate = get_rate_select(reg, ++ pll1_main_get_rate, ++ pll2_sw_get_rate, ++ pll3_sw_get_rate, ++ NULL); ++ ++ reg = ccm_readl(MX51_CCM_CSCDR1); ++ prediv = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK) >> ++ MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET) + 1; ++ podf = ((reg & MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK) >> ++ MX51_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET) + 1; ++ ++ return rate / (prediv * podf); ++} ++ ++void imx_dump_clocks(void) ++{ ++ printf("pll1: %ld\n", pll1_main_get_rate()); ++ printf("pll2: %ld\n", pll2_sw_get_rate()); ++ printf("pll3: %ld\n", pll3_sw_get_rate()); ++ printf("uart: %ld\n", imx_get_uartclk()); ++ printf("ipg: %ld\n", imx_get_ipgclk()); ++ printf("fec: %ld\n", imx_get_fecclk()); ++ printf("gpt: %ld\n", imx_get_gptclk()); ++} +diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c +index e024733..750ace0 100644 +--- a/arch/arm/mach-imx/speed.c ++++ b/arch/arm/mach-imx/speed.c +@@ -24,6 +24,7 @@ + #include <asm-generic/div64.h> + #include <common.h> + #include <command.h> ++#include <mach/clock.h> + + /* + * get the system pll clock in Hz +diff --git a/arch/arm/mach-omap/arch-omap.dox b/arch/arm/mach-omap/arch-omap.dox +index df16b7b..9c90b4f 100644 +--- a/arch/arm/mach-omap/arch-omap.dox ++++ b/arch/arm/mach-omap/arch-omap.dox +@@ -50,7 +50,11 @@ All basic devices you'd like to register should be put here with postcore_initca + All OMAP common headers are located here. Where we have to incorporate a OMAP variant specific header, add a omapX_function_name.h. + @warning Do not add board specific header files/information here. Put them in mach-omap. + +-include/asm-arm/arch-omap/silicon.h contains includes for omapX-silicon.h which defines the base addresses for the peripherals on that platform. the usual convention is to use #define OMAP_SOMETHING_BASE to allow re-use. ++include/asm-arm/arch-omap/silicon.h contains includes for omapX-silicon.h which defines the base addresses for the peripherals on that platform. the usual convention is to use ++@code ++#define OMAP_SOMETHING_BASE ++@endcode ++to allow re-use. + + @section board_omap arch/arm/boards/omap directory guidelines + All Board specific files go here. In u-boot, we always had to use common config file which is shared by other drivers to get serial, ethernet baseaddress etc.. we can easily use the device_d structure to handle it with @a barebox. This is more like programming for Linux kernel - it is pretty easy. +diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c +index 9893145..f780794 100644 +--- a/arch/arm/mach-omap/omap3_generic.c ++++ b/arch/arm/mach-omap/omap3_generic.c +@@ -52,11 +52,11 @@ + * + * In case of crashes, reset the CPU + * +- * @param[in] addr -Cause of crash ++ * @param addr Cause of crash + * + * @return void + */ +-void __noreturn reset_cpu(ulong addr) ++void __noreturn reset_cpu(unsigned long addr) + { + /* FIXME: Enable WDT and cause reset */ + hang(); +diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig +index 2f47907..0f4d6e7 100644 +--- a/arch/arm/mach-s3c24xx/Kconfig ++++ b/arch/arm/mach-s3c24xx/Kconfig +@@ -5,6 +5,7 @@ config ARCH_TEXT_BASE + default 0x31fc0000 + + config BOARDINFO ++ default "Mini 2440" if MACH_MINI2440 + default "Digi A9M2440" if MACH_A9M2440 + default "Digi A9M2410" if MACH_A9M2410 + +@@ -37,6 +38,14 @@ config MACH_A9M2440 + Say Y here if you are using Digi's Connect Core 9M equipped + with a Samsung S3C2440 Processor + ++config MACH_MINI2440 ++ bool "Mini 2440" ++ select CPU_S3C2440 ++ select HAS_DM9000 ++ help ++ Say Y here if you are using Mini 2440 dev board equipped ++ with a Samsung S3C2440 Processor ++ + endchoice + + menu "Board specific settings " +diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile +index 1cc8a23..88d45fe 100644 +--- a/arch/arm/mach-s3c24xx/Makefile ++++ b/arch/arm/mach-s3c24xx/Makefile +@@ -1,2 +1,2 @@ +-obj-y += generic.o ++obj-y += generic.o gpio-s3c24x0.o + obj-$(CONFIG_S3C24XX_LOW_LEVEL_INIT) += lowlevel-init.o +diff --git a/arch/arm/mach-s3c24xx/gpio-s3c24x0.c b/arch/arm/mach-s3c24xx/gpio-s3c24x0.c +new file mode 100644 +index 0000000..3d5e5e5 +--- /dev/null ++++ b/arch/arm/mach-s3c24xx/gpio-s3c24x0.c +@@ -0,0 +1,169 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <errno.h> ++#include <asm/io.h> ++#include <mach/s3c24x0-iomap.h> ++#include <mach/gpio.h> ++ ++static const unsigned char group_offset[] = ++{ ++ 0x00, /* GPA */ ++ 0x10, /* GPB */ ++ 0x20, /* GPC */ ++ 0x30, /* GPD */ ++ 0x40, /* GPE */ ++ 0x50, /* GPF */ ++ 0x60, /* GPG */ ++ 0x70, /* GPH */ ++#ifdef CONFIG_CPU_S3C2440 ++ 0xd0, /* GPJ */ ++#endif ++}; ++ ++void gpio_set_value(unsigned gpio, int value) ++{ ++ unsigned group = gpio >> 5; ++ unsigned bit = gpio % 32; ++ unsigned offset; ++ uint32_t reg; ++ ++ offset = group_offset[group]; ++ ++ reg = readl(GPADAT + offset); ++ reg &= ~(1 << bit); ++ reg |= (!!value) << bit; ++ writel(reg, GPADAT + offset); ++} ++ ++int gpio_direction_input(unsigned gpio) ++{ ++ unsigned group = gpio >> 5; ++ unsigned bit = gpio % 32; ++ unsigned offset; ++ uint32_t reg; ++ ++ offset = group_offset[group]; ++ ++ reg = readl(GPACON + offset); ++ reg &= ~(0x3 << (bit << 1)); ++ writel(reg, GPACON + offset); ++ ++ return 0; ++} ++ ++ ++int gpio_direction_output(unsigned gpio, int value) ++{ ++ unsigned group = gpio >> 5; ++ unsigned bit = gpio % 32; ++ unsigned offset; ++ uint32_t reg; ++ ++ offset = group_offset[group]; ++ ++ /* value */ ++ gpio_set_value(gpio,value); ++ /* direction */ ++ if (group == 0) { /* GPA is special */ ++ reg = readl(GPACON); ++ reg &= ~(1 << bit); ++ writel(reg, GPACON); ++ } else { ++ reg = readl(GPACON + offset); ++ reg &= ~(0x3 << (bit << 1)); ++ reg |= 0x1 << (bit << 1); ++ writel(reg, GPACON + offset); ++ } ++ ++ return 0; ++} ++ ++int gpio_get_value(unsigned gpio) ++{ ++ unsigned group = gpio >> 5; ++ unsigned bit = gpio % 32; ++ unsigned offset; ++ uint32_t reg; ++ ++ if (group == 0) /* GPA is special: no input mode available */ ++ return -ENODEV; ++ ++ offset = group_offset[group]; ++ ++ /* value */ ++ reg = readl(GPADAT + offset); ++ ++ return !!(reg & (1 << bit)); ++} ++ ++void s3c_gpio_mode(unsigned gpio_mode) ++{ ++ unsigned group, func, bit, offset, gpio; ++ uint32_t reg; ++ ++ group = GET_GROUP(gpio_mode); ++ func = GET_FUNC(gpio_mode); ++ bit = GET_BIT(gpio_mode); ++ gpio = GET_GPIO_NO(gpio_mode); ++ ++ if (group == 0) { ++ /* GPA is special */ ++ switch (func) { ++ case 0: /* GPIO input */ ++ pr_debug("Cannot set GPA pin to GPIO input\n"); ++ break; ++ case 1: /* GPIO output */ ++ gpio_direction_output(bit, GET_GPIOVAL(gpio_mode)); ++ break; ++ default: ++ reg = readl(GPACON); ++ reg |= 1 << bit; ++ writel(reg, GPACON); ++ break; ++ } ++ return; ++ } ++ ++ offset = group_offset[group]; ++ ++ if (PU_PRESENT(gpio_mode)) { ++ reg = readl(GPACON + offset + 8); ++ if (GET_PU(gpio_mode)) ++ reg |= (1 << bit); /* set means _disabled_ */ ++ else ++ reg &= ~(1 << bit); ++ writel(reg, GPACON + offset + 8); ++ } ++ ++ switch (func) { ++ case 0: /* input */ ++ gpio_direction_input(gpio); ++ break; ++ case 1: /* output */ ++ gpio_direction_output(gpio, GET_GPIOVAL(gpio_mode)); ++ break; ++ case 2: /* function one */ ++ case 3: /* function two */ ++ reg = readl(GPACON + offset); ++ reg &= ~(0x3 << (bit << 1)); ++ reg |= func << (bit << 1); ++ writel(reg, GPACON + offset); ++ break; ++ } ++} +diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio.h b/arch/arm/mach-s3c24xx/include/mach/gpio.h +new file mode 100644 +index 0000000..37db4f5 +--- /dev/null ++++ b/arch/arm/mach-s3c24xx/include/mach/gpio.h +@@ -0,0 +1,31 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __ASM_MACH_GPIO_H ++#define __ASM_MACH_GPIO_H ++ ++#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2410) ++# include <mach/iomux-s3c24x0.h> ++#endif ++ ++void gpio_set_value(unsigned, int); ++int gpio_direction_input(unsigned); ++int gpio_direction_output(unsigned, int); ++int gpio_get_value(unsigned); ++void s3c_gpio_mode(unsigned); ++ ++#endif /* __ASM_MACH_GPIO_H */ +diff --git a/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h b/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h +new file mode 100644 +index 0000000..2c64a97 +--- /dev/null ++++ b/arch/arm/mach-s3c24xx/include/mach/iomux-s3c24x0.h +@@ -0,0 +1,426 @@ ++/* ++ * Copyright (C) 2010 Juergen Beisert ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __MACH_IOMUX_S3C24x0_H ++#define __MACH_IOMUX_S3C24x0_H ++ ++/* 3322222222221111111111 ++ * 10987654321098765432109876543210 ++ * ^^^^^_ Bit offset ++ * ^^^^______ Group Number ++ * ^^____________ Function ++ * ^______________ initial GPIO out value ++ * ^_______________ Pull up feature present ++ * ^________________ initial pull up setting ++ */ ++ ++ ++#define PIN(group,bit) (group * 32 + bit) ++#define FUNC(x) (((x) & 0x3) << 11) ++#define GET_FUNC(x) (((x) >> 11) & 0x3) ++#define GET_GROUP(x) (((x) >> 5) & 0xf) ++#define GET_BIT(x) (((x) & 0x1ff) % 32) ++#define GET_GPIOVAL(x) (((x) >> 13) & 0x1) ++#define GET_GPIO_NO(x) ((x & 0x1ff)) ++#define GPIO_OUT FUNC(1) ++#define GPIO_IN FUNC(0) ++#define GPIO_VAL(x) ((!!(x)) << 13) ++#define PU (1 << 14) ++#define PU_PRESENT(x) (!!((x) & (1 << 14))) ++#define ENABLE_PU (0 << 15) ++#define DISABLE_PU (1 << 15) ++#define GET_PU(x) (!!((x) & DISABLE_PU)) ++ ++/* ++ * Group 0: GPIO 0...31 ++ * Used GPIO: 0...22 ++ * These pins can also act as GPIO outputs ++ */ ++#define GPA0_ADDR0 (PIN(0,0) | FUNC(2)) ++#define GPA0_ADDR0_GPIO (PIN(0,0) | FUNC(0)) ++#define GPA1_ADDR16 (PIN(0,1) | FUNC(2)) ++#define GPA1_ADDR16_GPIO (PIN(0,1) | FUNC(0)) ++#define GPA2_ADDR17 (PIN(0,2) | FUNC(2)) ++#define GPA2_ADDR17_GPIO (PIN(0,2) | FUNC(0)) ++#define GPA3_ADDR18 (PIN(0,3) | FUNC(2)) ++#define GPA3_ADDR18_GPIO (PIN(0,3) | FUNC(0)) ++#define GPA4_ADDR19 (PIN(0,4) | FUNC(2)) ++#define GPA4_ADDR19_GPIO (PIN(0,4) | FUNC(0)) ++#define GPA5_ADDR20 (PIN(0,5) | FUNC(2)) ++#define GPA5_ADDR20_GPIO (PIN(0,5) | FUNC(0)) ++#define GPA6_ADDR21 (PIN(0,6) | FUNC(2)) ++#define GPA6_ADDR21_GPIO (PIN(0,6) | FUNC(0)) ++#define GPA7_ADDR22 (PIN(0,7) | FUNC(2)) ++#define GPA7_ADDR22_GPIO (PIN(0,7) | FUNC(0)) ++#define GPA8_ADDR23 (PIN(0,8) | FUNC(2)) ++#define GPA8_ADDR23_GPIO (PIN(0,8) | FUNC(0)) ++#define GPA9_ADDR24 (PIN(0,9) | FUNC(2)) ++#define GPA9_ADDR24_GPIO (PIN(0,9) | FUNC(0)) ++#define GPA10_ADDR25 (PIN(0,10) | FUNC(2)) ++#define GPA10_ADDR25_GPIO (PIN(0,10) | FUNC(0)) ++#define GPA11_ADDR26 (PIN(0,11) | FUNC(2)) ++#define GPA11_ADDR26_GPIO (PIN(0,11) | FUNC(0)) ++#define GPA12_NGCS1 (PIN(0,12) | FUNC(2)) ++#define GPA12_NGCS1_GPIO (PIN(0,12) | FUNC(0)) ++#define GPA13_NGCS2 (PIN(0,13) | FUNC(2)) ++#define GPA13_NGCS2_GPIO (PIN(0,13) | FUNC(0)) ++#define GPA14_NGCS3 (PIN(0,14) | FUNC(2)) ++#define GPA14_NGCS3_GPIO (PIN(0,14) | FUNC(0)) ++#define GPA15_NGCS4 (PIN(0,15) | FUNC(2)) ++#define GPA15_NGCS4_GPIO (PIN(0,15) | FUNC(0)) ++#define GPA16_NGCS5 (PIN(0,16) | FUNC(2)) ++#define GPA16_NGCS5_GPIO (PIN(0,16) | FUNC(0)) ++#define GPA17_CLE (PIN(0,17) | FUNC(2)) ++#define GPA17_CLE_GPIO (PIN(0,17) | FUNC(0)) ++#define GPA18_ALE (PIN(0,18) | FUNC(2)) ++#define GPA18_ALE_GPIO (PIN(0,18) | FUNC(0)) ++#define GPA19_NFWE (PIN(0,19) | FUNC(2)) ++#define GPA19_NFWE_GPIO (PIN(0,19) | FUNC(0)) ++#define GPA20_NFRE (PIN(0,20) | FUNC(2)) ++#define GPA20_NFRE_GPIO (PIN(0,20) | FUNC(0)) ++#define GPA21_NRSTOUT (PIN(0,21) | FUNC(2)) ++#define GPA21_NRSTOUT_GPIO (PIN(0,21) | FUNC(0)) ++#define GPA22_NFCE (PIN(0,22) | FUNC(2)) ++#define GPA22_NFCE_GPIO (PIN(0,22) | FUNC(0)) ++ ++/* ++ * Group 1: GPIO 32...63 ++ * Used GPIO: 0...10 ++ * these pins can also act as GPIO inputs/outputs ++ */ ++#define GPB0_TOUT0 (PIN(1,0) | FUNC(2) | PU) ++#define GPB0_GPIO (PIN(1,0) | FUNC(0) | PU) ++#define GPB1_TOUT1 (PIN(1,1) | FUNC(2) | PU) ++#define GPB1_GPIO (PIN(1,1) | FUNC(0) | PU) ++#define GPB2_TOUT2 (PIN(1,2) | FUNC(2) | PU) ++#define GPB2_GPIO (PIN(1,2) | FUNC(0) | PU) ++#define GPB3_TOUT3 (PIN(1,3) | FUNC(2) | PU) ++#define GPB3_GPIO (PIN(1,3) | FUNC(0) | PU) ++#define GPB4_TCLK0 (PIN(1,4) | FUNC(2) | PU) ++#define GPB4_GPIO (PIN(1,4) | FUNC(0) | PU) ++#define GPB5_NXBACK (PIN(1,5) | FUNC(2) | PU) ++#define GPB5_GPIO (PIN(1,5) | FUNC(0) | PU) ++#define GPB6_NXBREQ (PIN(1,6) | FUNC(2) | PU) ++#define GPB6_GPIO (PIN(1,6) | FUNC(0) | PU) ++#define GPB7_NXDACK1 (PIN(1,7) | FUNC(2) | PU) ++#define GPB7_GPIO (PIN(1,7) | FUNC(0) | PU) ++#define GPB8_NXDREQ1 (PIN(1,8) | FUNC(2) | PU) ++#define GPB8_GPIO (PIN(1,8) | FUNC(0) | PU) ++#define GPB9_NXDACK0 (PIN(1,9) | FUNC(2) | PU) ++#define GPB9_GPIO (PIN(1,9) | FUNC(0) | PU) ++#define GPB10_NXDREQ0 (PIN(1,10) | FUNC(2) | PU) ++#define GPB10_GPIO (PIN(1,10) | FUNC(0) | PU) ++ ++/* ++ * Group 1: GPIO 64...95 ++ * Used GPIO: 0...15 ++ * These pins can also act as GPIO inputs/outputs ++ */ ++#define GPC0_LEND (PIN(2,0) | FUNC(2) | PU) ++#define GPC0_GPIO (PIN(2,0) | FUNC(0) | PU) ++#define GPC1_VCLK (PIN(2,1) | FUNC(2) | PU) ++#define GPC1_GPIO (PIN(2,1) | FUNC(0) | PU) ++#define GPC2_VLINE (PIN(2,2) | FUNC(2) | PU) ++#define GPC2_GPIO (PIN(2,2) | FUNC(0) | PU) ++#define GPC3_VFRAME (PIN(2,3) | FUNC(2) | PU) ++#define GPC3_GPIO (PIN(2,3) | FUNC(0) | PU) ++#define GPC4_VM (PIN(2,4) | FUNC(2) | PU) ++#define GPC4_GPIO (PIN(2,4) | FUNC(0) | PU) ++#define GPC5_LPCOE (PIN(2,5) | FUNC(2) | PU) ++#define GPC5_GPIO (PIN(2,5) | FUNC(0) | PU) ++#define GPC6_LPCREV (PIN(2,6) | FUNC(2) | PU) ++#define GPC6_GPIO (PIN(2,6) | FUNC(0) | PU) ++#define GPC7_LPCREVB (PIN(2,7) | FUNC(2) | PU) ++#define GPC7_GPIO (PIN(2,7) | FUNC(0) | PU) ++#define GPC8_VD0 (PIN(2,8) | FUNC(2) | PU) ++#define GPC8_GPIO (PIN(2,8) | FUNC(0) | PU) ++#define GPC9_VD1 (PIN(2,9) | FUNC(2) | PU) ++#define GPC9_GPIO (PIN(2,9) | FUNC(0) | PU) ++#define GPC10_VD2 (PIN(2,10) | FUNC(2) | PU) ++#define GPC10_GPIO (PIN(2,10) | FUNC(0) | PU) ++#define GPC11_VD3 (PIN(2,11) | FUNC(2) | PU) ++#define GPC11_GPIO (PIN(2,11) | FUNC(0) | PU) ++#define GPC12_VD4 (PIN(2,12) | FUNC(2) | PU) ++#define GPC12_GPIO (PIN(2,12) | FUNC(0) | PU) ++#define GPC13_VD5 (PIN(2,13) | FUNC(2) | PU) ++#define GPC13_GPIO (PIN(2,13) | FUNC(0) | PU) ++#define GPC14_VD6 (PIN(2,14) | FUNC(2) | PU) ++#define GPC14_GPIO (PIN(2,14) | FUNC(0) | PU) ++#define GPC15_VD7 (PIN(2,15) | FUNC(2) | PU) ++#define GPC15_GPIO (PIN(2,15) | FUNC(0) | PU) ++ ++/* ++ * Group 1: GPIO 96...127 ++ * Used GPIO: 0...15 ++ * These pins can also act as GPIO inputs/outputs ++ */ ++#define GPD0_VD8 (PIN(3,0) | FUNC(2) | PU) ++#define GPD0_GPIO (PIN(3,0) | FUNC(0) | PU) ++#define GPD1_VD9 (PIN(3,1) | FUNC(2) | PU) ++#define GPD1_GPIO (PIN(3,1) | FUNC(0) | PU) ++#define GPD2_VD10 (PIN(3,2) | FUNC(2) | PU) ++#define GPD2_GPIO (PIN(3,2) | FUNC(0) | PU) ++#define GPD3_VD11 (PIN(3,3) | FUNC(2) | PU) ++#define GPD3_GPIO (PIN(3,3) | FUNC(0) | PU) ++#define GPD4_VD12 (PIN(3,4) | FUNC(2) | PU) ++#define GPD4_GPIO (PIN(3,4) | FUNC(0) | PU) ++#define GPD5_VD13 (PIN(3,5) | FUNC(2) | PU) ++#define GPD5_GPIO (PIN(3,5) | FUNC(0) | PU) ++#define GPD6_VD14 (PIN(3,6) | FUNC(2) | PU) ++#define GPD6_GPIO (PIN(3,6) | FUNC(0) | PU) ++#define GPD7_VD15 (PIN(3,7) | FUNC(2) | PU) ++#define GPD7_GPIO (PIN(3,7) | FUNC(0) | PU) ++#define GPD8_VD16 (PIN(3,8) | FUNC(2) | PU) ++#define GPD8_GPIO (PIN(3,8) | FUNC(0) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPD8_SPIMISO1 (PIN(3,8) | FUNC(3) | PU) ++#endif ++#define GPD9_VD17 (PIN(3,9) | FUNC(2) | PU) ++#define GPD9_GPIO (PIN(3,9) | FUNC(0) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPD9_SPIMOSI1 (PIN(3,9) | FUNC(3) | PU) ++#endif ++#define GPD10_VD18 (PIN(3,10) | FUNC(2) | PU) ++#define GPD10_GPIO (PIN(3,10) | FUNC(0) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPD10_SPICLK (PIN(3,10) | FUNC(3) | PU) ++#endif ++#define GPD11_VD19 (PIN(3,11) | FUNC(2) | PU) ++#define GPD11_GPIO (PIN(3,11) | FUNC(0) | PU) ++#define GPD12_VD20 (PIN(3,12) | FUNC(2) | PU) ++#define GPD12_GPIO (PIN(3,12) | FUNC(0) | PU) ++#define GPD13_VD21 (PIN(3,13) | FUNC(2) | PU) ++#define GPD13_GPIO (PIN(3,13) | FUNC(0) | PU) ++#define GPD14_VD22 (PIN(3,14) | FUNC(2) | PU) ++#define GPD14_GPIO (PIN(3,14) | FUNC(0) | PU) ++#define GPD14_NSS1 (PIN(3,14) | FUNC(3) | PU) ++#define GPD15_VD23 (PIN(3,15) | FUNC(2) | PU) ++#define GPD15_GPIO (PIN(3,15) | FUNC(0) | PU) ++#define GPD15_NSS0 (PIN(3,15) | FUNC(3) | PU) ++ ++/* ++ * Group 1: GPIO 128...159 ++ * Used GPIO: 0...15 ++ * These pins can also act as GPIO inputs/outputs ++ */ ++#define GPE0_I2SLRCK (PIN(4,0) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPE0_AC_SYNC (PIN(4,0) | FUNC(3) | PU) ++#endif ++#define GPE0_GPIO (PIN(4,0) | FUNC(0) | PU) ++#define GPE1_I2SSCLK (PIN(4,1) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPE1_AC_BIT_CLK (PIN(4,1) | FUNC(3) | PU) ++#endif ++#define GPE1_GPIO (PIN(4,1) | FUNC(0) | PU) ++#define GPE2_CDCLK (PIN(4,2) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPE2_AC_NRESET (PIN(4,2) | FUNC(3) | PU) ++#endif ++#define GPE2_GPIO (PIN(4,2) | FUNC(0) | PU) ++#define GPE3_I2SDI (PIN(4,3) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPE3_AC_SDATA_IN (PIN(4,3) | FUNC(3) | PU) ++#endif ++#ifdef CONFIG_CPU_S3C2410 ++# define GPE_NSS0 (PIN(4,3) | FUNC(3) | PU) ++#endif ++#define GPE3_GPIO (PIN(4,3) | FUNC(0) | PU) ++#define GPE4_I2SDO (PIN(4,4) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPE4_AC_SDATA_OUT (PIN(4,4) | FUNC(3) | PU) ++#endif ++#ifdef CONFIG_CPU_S3C2440 ++# define GPE4_I2SSDI (PIN(4,4) | FUNC(3) | PU) ++#endif ++#define GPE4_GPIO (PIN(4,4) | FUNC(0) | PU) ++#define GPE5_SDCLK (PIN(4,5) | FUNC(2) | PU) ++#define GPE5_GPIO (PIN(4,5) | FUNC(0) | PU) ++#define GPE6_SDCMD (PIN(4,6) | FUNC(2) | PU) ++#define GPE6_GPIO (PIN(4,6) | FUNC(0) | PU) ++#define GPE7_SDDAT0 (PIN(4,7) | FUNC(2) | PU) ++#define GPE7_GPIO (PIN(4,7) | FUNC(0) | PU) ++#define GPE8_SDDAT1 (PIN(4,8) | FUNC(2) | PU) ++#define GPE8_GPIO (PIN(4,8) | FUNC(0) | PU) ++#define GPE9_SDDAT2 (PIN(4,9) | FUNC(2) | PU) ++#define GPE9_GPIO (PIN(4,9) | FUNC(0) | PU) ++#define GPE10_SDDAT3 (PIN(4,10) | FUNC(2) | PU) ++#define GPE10_GPIO (PIN(4,10) | FUNC(0) | PU) ++#define GPE11_SPIMISO0 (PIN(4,11) | FUNC(2) | PU) ++#define GPE11_GPIO (PIN(4,11) | FUNC(0) | PU) ++#define GPE12_SPIMOSI0 (PIN(4,12) | FUNC(2) | PU) ++#define GPE12_GPIO (PIN(4,12) | FUNC(0) | PU) ++#define GPE13_SPICLK0 (PIN(4,13) | FUNC(2) | PU) ++#define GPE13_GPIO (PIN(4,13) | FUNC(0) | PU) ++#define GPE14_IICSCL (PIN(4,14) | FUNC(2)) /* no pullup option */ ++#define GPE14_GPIO (PIN(4,14) | FUNC(0)) /* no pullup option */ ++#define GPE15_IICSDA (PIN(4,15) | FUNC(2)) /* no pullup option */ ++#define GPE15_GPIO (PIN(4,15) | FUNC(0)) /* no pullup option */ ++ ++/* ++ * Group 1: GPIO 160...191 ++ * Used GPIO: 0...7 ++ * These pins can also act as GPIO inputs/outputs ++ */ ++#define GPF0_EINT0 (PIN(5,0) | FUNC(2) | PU) ++#define GPF0_GPIO (PIN(5,0) | FUNC(0) | PU) ++#define GPF1_EINT1 (PIN(5,1) | FUNC(2) | PU) ++#define GPF1_GPIO (PIN(5,1) | FUNC(0) | PU) ++#define GPF2_EINT2 (PIN(5,2) | FUNC(2) | PU) ++#define GPF2_GPIO (PIN(5,2) | FUNC(0) | PU) ++#define GPF3_EINT3 (PIN(5,3) | FUNC(2) | PU) ++#define GPF3_GPIO (PIN(5,3) | FUNC(0) | PU) ++#define GPF4_EINT4 (PIN(5,4) | FUNC(2) | PU) ++#define GPF4_GPIO (PIN(5,4) | FUNC(0) | PU) ++#define GPF5_EINT5 (PIN(5,5) | FUNC(2) | PU) ++#define GPF5_GPIO (PIN(5,5) | FUNC(0) | PU) ++#define GPF6_EINT6 (PIN(5,6) | FUNC(2) | PU) ++#define GPF6_GPIO (PIN(5,6) | FUNC(0) | PU) ++#define GPF7_EINT7 (PIN(5,7) | FUNC(2) | PU) ++#define GPF7_GPIO (PIN(5,7) | FUNC(0) | PU) ++ ++/* ++ * Group 1: GPIO 192..223 ++ * Used GPIO: 0...15 ++ * These pins can also act as GPIO inputs/outputs ++ */ ++#define GPG0_EINT8 (PIN(6,0) | FUNC(2) | PU) ++#define GPG0_GPIO (PIN(6,0) | FUNC(0) | PU) ++#define GPG1_EINT9 (PIN(6,1) | FUNC(2) | PU) ++#define GPG1_GPIO (PIN(6,1) | FUNC(0) | PU) ++#define GPG2_EINT10 (PIN(6,2) | FUNC(2) | PU) ++#define GPG2_NSS0 (PIN(6,2) | FUNC(3) | PU) ++#define GPG2_GPIO (PIN(6,2) | FUNC(0) | PU) ++#define GPG3_EINT11 (PIN(6,3) | FUNC(2) | PU) ++#define GPG3_NSS1 (PIN(6,3) | FUNC(3) | PU) ++#define GPG3_GPIO (PIN(6,3) | FUNC(0) | PU) ++#define GPG4_EINT12 (PIN(6,4) | FUNC(2) | PU) ++#define GPG4_LCD_PWREN (PIN(6,4) | FUNC(3) | PU) ++#define GPG4_GPIO (PIN(6,4) | FUNC(0) | PU) ++#define GPG5_EINT13 (PIN(6,5) | FUNC(2) | PU) ++#define GPG5_SPIMISO1 (PIN(6,5) | FUNC(3) | PU) ++#define GPG5_GPIO (PIN(6,5) | FUNC(0) | PU) ++#define GPG6_EINT14 (PIN(6,6) | FUNC(2) | PU) ++#define GPG6_SPIMOSI1 (PIN(6,6) | FUNC(3) | PU) ++#define GPG6_GPIO (PIN(6,6) | FUNC(0) | PU) ++#define GPG7_EINT15 (PIN(6,7) | FUNC(2) | PU) ++#define GPG7_SPICLK1 (PIN(6,7) | FUNC(3) | PU) ++#define GPG7_GPIO (PIN(6,7) | FUNC(0) | PU) ++#define GPG8_EINT16 (PIN(6,8) | FUNC(2) | PU) ++#define GPG8_GPIO (PIN(6,8) | FUNC(0) | PU) ++#define GPG9_EINT17 (PIN(6,9) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPG9_NRTS1 (PIN(6,9) | FUNC(3) | PU) ++#endif ++#define GPG9_GPIO (PIN(6,9) | FUNC(0) | PU) ++#define GPG10_EINT18 (PIN(6,10) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2440 ++# define GPG10_NCTS1 (PIN(6,10) | FUNC(3) | PU) ++#endif ++#define GPG10_GPIO (PIN(6,10) | FUNC(0) | PU) ++#define GPG11_EINT19 (PIN(6,11) | FUNC(2) | PU) ++#define GPG11_TCLK (PIN(6,11) | FUNC(3) | PU) ++#define GPG11_GPIO (PIN(6,11) | FUNC(0) | PU) ++#define GPG12_EINT20 (PIN(6,12) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2410 ++# define GPG12_XMON (PIN(6,12) | FUNC(3) | PU) ++#endif ++#define GPG12_GPIO (PIN(6,12) | FUNC(0) | PU) ++#define GPG13_EINT21 (PIN(6,13) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2410 ++# define GPG13_NXPON (PIN(6,13) | FUNC(3) | PU) ++#endif ++#define GPG13_GPIO (PIN(6,13) | FUNC(0) | PU) /* must be input in NAND boot mode */ ++#define GPG14_EINT22 (PIN(6,14) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2410 ++# define GPG14_YMON (PIN(6,14) | FUNC(3) | PU) ++#endif ++#define GPG14_GPIO (PIN(6,14) | FUNC(0) | PU) /* must be input in NAND boot mode */ ++#define GPG15_EINT23 (PIN(6,15) | FUNC(2) | PU) ++#ifdef CONFIG_CPU_S3C2410 ++# define GPG15_YPON (PIN(6,15) | FUNC(3) | PU) ++#endif ++#define GPG15_GPIO (PIN(6,15) | FUNC(0) | PU) /* must be input in NAND boot mode */ ++ ++/* ++ * Group 1: GPIO 224..255 ++ * Used GPIO: 0...15 ++ * These pins can also act as GPIO inputs/outputs ++ */ ++#define GPH0_NCTS0 (PIN(7,0) | FUNC(2) | PU) ++#define GPH0_GPIO (PIN(7,0) | FUNC(0) | PU) ++#define GPH1_NRTS0 (PIN(7,1) | FUNC(2) | PU) ++#define GPH1_GPIO (PIN(7,1) | FUNC(0) | PU) ++#define GPH2_TXD0 (PIN(7,2) | FUNC(2) | PU) ++#define GPH2_GPIO (PIN(7,2) | FUNC(0) | PU) ++#define GPH3_RXD0 (PIN(7,3) | FUNC(2) | PU) ++#define GPH3_GPIO (PIN(7,3) | FUNC(0) | PU) ++#define GPH4_TXD1 (PIN(7,4) | FUNC(2) | PU) ++#define GPH4_GPIO (PIN(7,4) | FUNC(0) | PU) ++#define GPH5_RXD1 (PIN(7,5) | FUNC(2) | PU) ++#define GPH5_GPIO (PIN(7,5) | FUNC(0) | PU) ++#define GPH6_TXD2 (PIN(7,6) | FUNC(2) | PU) ++#define GPH6_NRTS1 (PIN(7,6) | FUNC(3) | PU) ++#define GPH6_GPIO (PIN(7,6) | FUNC(0) | PU) ++#define GPH7_RXD2 (PIN(7,7) | FUNC(2) | PU) ++#define GPH7_NCTS1 (PIN(7,7) | FUNC(3) | PU) ++#define GPH7_GPIO (PIN(7,7) | FUNC(0) | PU) ++#define GPH8_UEXTCLK (PIN(7,8) | FUNC(2) | PU) ++#define GPH8_GPIO (PIN(7,8) | FUNC(0) | PU) ++#define GPH9_CLOCKOUT0 (PIN(7,9) | FUNC(2) | PU) ++#define GPH9_GPIO (PIN(7,9) | FUNC(0) | PU) ++#define GPH10_CLKOUT1 (PIN(7,10) | FUNC(2) | PU) ++#define GPH10_GPIO (PIN(7,10) | FUNC(0) | PU) ++ ++#ifdef CONFIG_CPU_S3C2440 ++/* ++ * Group 1: GPIO 256..287 ++ * Used GPIO: 0...12 ++ * These pins can also act as GPIO inputs/outputs ++ */ ++#define GPJ0_CAMDATA0 (PIN(8,0) | FUNC(2) | PU) ++#define GPJ0_GPIO (PIN(8,0) | FUNC(0) | PU) ++#define GPJ1_CAMDATA1 (PIN(8,1) | FUNC(2) | PU) ++#define GPJ1_GPIO (PIN(8,1) | FUNC(0) | PU) ++#define GPJ2_CAMDATA2 (PIN(8,2) | FUNC(2) | PU) ++#define GPJ2_GPIO (PIN(8,2) | FUNC(0) | PU) ++#define GPJ3_CAMDATA3 (PIN(8,3) | FUNC(2) | PU) ++#define GPJ3_GPIO (PIN(8,3) | FUNC(0) | PU) ++#define GPJ4_CAMDATA4 (PIN(8,4) | FUNC(2) | PU) ++#define GPJ4_GPIO (PIN(8,4) | FUNC(0) | PU) ++#define GPJ5_CAMDATA5 (PIN(8,5) | FUNC(2) | PU) ++#define GPJ5_GPIO (PIN(8,5) | FUNC(0) | PU) ++#define GPJ6_CAMDATA6 (PIN(8,6) | FUNC(2) | PU) ++#define GPJ6_GPIO (PIN(8,6) | FUNC(0) | PU) ++#define GPJ7_CAMDATA7 (PIN(8,7) | FUNC(2) | PU) ++#define GPJ7_GPIO (PIN(8,7) | FUNC(0) | PU) ++#define GPJ8_CAMPCLK (PIN(8,8) | FUNC(2) | PU) ++#define GPJ8_GPIO (PIN(8,8) | FUNC(0) | PU) ++#define GPJ9_CAMVSYNC (PIN(8,9) | FUNC(2) | PU) ++#define GPJ9_GPIO (PIN(8,9) | FUNC(0) | PU) ++#define GPJ10_CAMHREF (PIN(8,10) | FUNC(2) | PU) ++#define GPJ10_GPIO (PIN(8,10) | FUNC(0) | PU) ++#define GPJ11_CAMCLKOUT (PIN(8,11) | FUNC(2) | PU) ++#define GPJ11_GPIO (PIN(8,11) | FUNC(0) | PU) ++#define GPJ12_CAMRESET (PIN(8,12) | FUNC(0) | PU) ++#define GPJ12_GPIO (PIN(8,12) | FUNC(0) | PU) ++ ++#endif ++ ++#endif /* __MACH_IOMUX_S3C24x0_H */ +diff --git a/arch/arm/mach-s3c24xx/include/mach/mci.h b/arch/arm/mach-s3c24xx/include/mach/mci.h +new file mode 100644 +index 0000000..6ba8961 +--- /dev/null ++++ b/arch/arm/mach-s3c24xx/include/mach/mci.h +@@ -0,0 +1,46 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert, Pengutronix ++ * ++ * This code is partially based on u-boot code: ++ * ++ * Copyright 2008, Freescale Semiconductor, Inc ++ * Andy Fleming ++ * ++ * Based (loosely) on the Linux code ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __MACH_MMC_H_ ++#define __MACH_MMC_H_ ++ ++struct s3c_mci_platform_data { ++ unsigned caps; /**< supported operating modes (MMC_MODE_*) */ ++ unsigned voltages; /**< supported voltage range (MMC_VDD_*) */ ++ unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */ ++ unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */ ++ /* TODO */ ++ /* function to modify the voltage */ ++ /* function to switch the voltage */ ++ /* function to detect the presence of a SD card in the socket */ ++ unsigned gpio_detect; ++ unsigned detect_invert; ++}; ++ ++#endif /* __MACH_MMC_H_ */ +diff --git a/arch/arm/mach-stm/Kconfig b/arch/arm/mach-stm/Kconfig +new file mode 100644 +index 0000000..021919a +--- /dev/null ++++ b/arch/arm/mach-stm/Kconfig +@@ -0,0 +1,48 @@ ++if ARCH_STM ++ ++config ARCH_TEXT_BASE ++ hex ++ default 0x41000000 if MACH_MX23EVK ++ default 0x42000000 if MACH_CHUMBY ++ ++config BOARDINFO ++ default "Freescale i.MX23-EVK" if MACH_MX23EVK ++ default "Chumby Falconwing" if MACH_CHUMBY ++ ++comment "SigmaTel/Freescale i.MX System-on-Chip" ++ ++choice ++ prompt "Freescale i.MX Processor" ++ ++config ARCH_IMX23 ++ bool "i.MX23" ++ select CPU_ARM926T ++ ++endchoice ++ ++if ARCH_IMX23 ++ ++choice ++ prompt "i.MX23 Board Type" ++ ++config MACH_MX23EVK ++ bool "mx23-evk" ++ help ++ Say Y here if you are using the Freescale i.MX23-EVK board ++ ++config MACH_CHUMBY ++ bool "Chumby Falconwing" ++ select HAVE_MMU ++ help ++ Say Y here if you are using the "chumby one" aka falconwing from ++ Chumby Industries ++ ++endchoice ++ ++endif ++ ++menu "Board specific settings " ++ ++endmenu ++ ++endif +diff --git a/arch/arm/mach-stm/Makefile b/arch/arm/mach-stm/Makefile +new file mode 100644 +index 0000000..59d70b6 +--- /dev/null ++++ b/arch/arm/mach-stm/Makefile +@@ -0,0 +1,2 @@ ++obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o imx23.o iomux-imx23.o clocksource-imx23.o reset-imx23.o ++ +diff --git a/arch/arm/mach-stm/clocksource-imx23.c b/arch/arm/mach-stm/clocksource-imx23.c +new file mode 100644 +index 0000000..7c0268c +--- /dev/null ++++ b/arch/arm/mach-stm/clocksource-imx23.c +@@ -0,0 +1,82 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <clock.h> ++#include <notifier.h> ++#include <mach/imx-regs.h> ++#include <mach/clock.h> ++#include <asm/io.h> ++ ++#define TIMROTCTRL 0x00 ++#define TIMCTRL1 0x40 ++#define TIMCTRL1_SET 0x44 ++#define TIMCTRL1_CLR 0x48 ++#define TIMCTRL1_TOG 0x4c ++# define TIMCTRL_RELOAD (1 << 6) ++# define TIMCTRL_UPDATE (1 << 7) ++# define TIMCTRL_PRESCALE(x) ((x & 0x3) << 4) ++# define TIMCTRL_SELECT(x) (x & 0xf) ++#define TIMCOUNT1 0x50 ++ ++static const unsigned long timer_base = IMX_TIM1_BASE; ++ ++#define CLOCK_TICK_RATE (32000) ++ ++static uint64_t imx23_clocksource_read(void) ++{ ++ /* only the upper bits are the valid */ ++ return ~(readl(timer_base + TIMCOUNT1) >> 16); ++} ++ ++static struct clocksource cs = { ++ .read = imx23_clocksource_read, ++ .mask = 0x0000ffff, ++ .shift = 10, ++}; ++ ++static int imx23_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data) ++{ ++ cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE/*imx_get_xclk()*/, cs.shift); ++ return 0; ++} ++ ++static struct notifier_block imx23_clock_notifier = { ++ .notifier_call = imx23_clocksource_clock_change, ++}; ++ ++static int clocksource_init(void) ++{ ++ /* enable the whole timer block */ ++ writel(0x3e000000, timer_base + TIMROTCTRL); ++ /* setup general purpose timer 1 */ ++ writel(0x00000000, timer_base + TIMCTRL1); ++ writel(TIMCTRL_UPDATE, timer_base + TIMCTRL1); ++ writel(0x0000ffff, timer_base + TIMCOUNT1); ++ ++ writel(TIMCTRL_UPDATE | TIMCTRL_RELOAD | TIMCTRL_PRESCALE(0) | TIMCTRL_SELECT(8), timer_base + TIMCTRL1); ++ cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE/*imx_get_xclk()*/, cs.shift); ++ init_clock(&cs); ++ ++ clock_register_client(&imx23_clock_notifier); ++ return 0; ++} ++ ++core_initcall(clocksource_init); +diff --git a/arch/arm/mach-stm/imx23.c b/arch/arm/mach-stm/imx23.c +new file mode 100644 +index 0000000..14a4249 +--- /dev/null ++++ b/arch/arm/mach-stm/imx23.c +@@ -0,0 +1,35 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <command.h> ++ ++extern void imx_dump_clocks(void); ++ ++static int do_clocks(struct command *cmdtp, int argc, char *argv[]) ++{ ++ imx_dump_clocks(); ++ ++ return 0; ++} ++ ++BAREBOX_CMD_START(dump_clocks) ++ .cmd = do_clocks, ++ .usage = "show clock frequencies", ++BAREBOX_CMD_END +diff --git a/arch/arm/mach-stm/include/mach/clock.h b/arch/arm/mach-stm/include/mach/clock.h +new file mode 100644 +index 0000000..0e1a6d6 +--- /dev/null ++++ b/arch/arm/mach-stm/include/mach/clock.h +@@ -0,0 +1,34 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef ASM_ARCH_CLOCK_IMX23_H ++#define ASM_ARCH_CLOCK_IMX23_H ++ ++unsigned imx_get_mpllclk(void); ++unsigned imx_get_emiclk(void); ++unsigned imx_get_ioclk(void); ++unsigned imx_get_armclk(void); ++unsigned imx_get_hclk(void); ++unsigned imx_get_xclk(void); ++unsigned imx_get_sspclk(unsigned); ++unsigned imx_set_sspclk(unsigned, unsigned, int); ++unsigned imx_set_ioclk(unsigned); ++ ++#endif /* ASM_ARCH_CLOCK_IMX23_H */ ++ +diff --git a/arch/arm/mach-stm/include/mach/generic.h b/arch/arm/mach-stm/include/mach/generic.h +new file mode 100644 +index 0000000..3a552a8 +--- /dev/null ++++ b/arch/arm/mach-stm/include/mach/generic.h +@@ -0,0 +1,24 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifdef CONFIG_ARCH_IMX23 ++# define cpu_is_mx23() (1) ++#else ++# define cpu_is_mx23() (0) ++#endif +diff --git a/arch/arm/mach-stm/include/mach/gpio.h b/arch/arm/mach-stm/include/mach/gpio.h +new file mode 100644 +index 0000000..fa8263c +--- /dev/null ++++ b/arch/arm/mach-stm/include/mach/gpio.h +@@ -0,0 +1,29 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __ASM_MACH_GPIO_H ++#define __ASM_MACH_GPIO_H ++ ++#if defined CONFIG_ARCH_IMX23 ++# include <mach/iomux-imx23.h> ++#endif ++ ++void imx_gpio_mode(unsigned); ++ ++#endif /* __ASM_MACH_GPIO_H */ +diff --git a/arch/arm/mach-stm/include/mach/imx-regs.h b/arch/arm/mach-stm/include/mach/imx-regs.h +new file mode 100644 +index 0000000..40dc742 +--- /dev/null ++++ b/arch/arm/mach-stm/include/mach/imx-regs.h +@@ -0,0 +1,27 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef _IMX_REGS_H ++# define _IMX_REGS_H ++ ++#if defined CONFIG_ARCH_IMX23 ++# include <mach/imx23-regs.h> ++#endif ++ ++#endif /* _IMX_REGS_H */ +diff --git a/arch/arm/mach-stm/include/mach/imx23-regs.h b/arch/arm/mach-stm/include/mach/imx23-regs.h +new file mode 100644 +index 0000000..89ca453 +--- /dev/null ++++ b/arch/arm/mach-stm/include/mach/imx23-regs.h +@@ -0,0 +1,41 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, ++ * MA 02110-1301, USA. ++ */ ++ ++#ifndef __ASM_ARCH_MX23_REGS_H ++#define __ASM_ARCH_MX23_REGS_H ++ ++/* ++ * sanity check ++ */ ++#ifndef _IMX_REGS_H ++# error "Please do not include directly. Use imx-regs.h instead." ++#endif ++ ++#define IMX_MEMORY_BASE 0x40000000 ++#define IMX_UART1_BASE 0x8006c000 ++#define IMX_UART2_BASE 0x8006e000 ++#define IMX_DBGUART_BASE 0x80070000 ++#define IMX_TIM1_BASE 0x80068000 ++#define IMX_IOMUXC_BASE 0x80018000 ++#define IMX_WDT_BASE 0x8005c000 ++#define IMX_CCM_BASE 0x80040000 ++#define IMX_I2C1_BASE 0x80058000 ++#define IMX_SSP1_BASE 0x80010000 ++#define IMX_SSP2_BASE 0x80034000 ++ ++#endif /* __ASM_ARCH_MX23_REGS_H */ +diff --git a/arch/arm/mach-stm/include/mach/iomux-imx23.h b/arch/arm/mach-stm/include/mach/iomux-imx23.h +new file mode 100644 +index 0000000..bebaf56 +--- /dev/null ++++ b/arch/arm/mach-stm/include/mach/iomux-imx23.h +@@ -0,0 +1,424 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, ++ * MA 02110-1301, USA. ++ */ ++ ++/* 3322222222221111111111 ++ * 10987654321098765432109876543210 ++ * ^^^_ Register Number ++ * ^^^^____ Bit offset ++ * ^^________ Function ++ * ^__________ Drive strength feature present ++ * ^___________ Pull up / bit keeper present ++ * ^^____________ Drive strength setting ++ * ^______________ Pull up / bit keeper setting ++ * ^_______________ Voltage select present ++ * ^________________ Voltage selection ++ * ^____________________ direction if enabled as GPIO (1 = output) ++ * ^_____________________ initial output value if enabled as GPIO and configured as output ++ */ ++#ifndef __ASM_MACH_IOMUX_H ++#define __ASM_MACH_IOMUX_H ++ ++/* control pad's function */ ++#define FBIT_SHIFT (3) ++#define PORTF(bank,bit) (((bit) << FBIT_SHIFT) | (bank)) ++#define GET_PORTF(x) ((x) & 0x7) ++#define GET_FBITPOS(x) (((x) >> FBIT_SHIFT) & 0xf) ++#define GET_GPIO_NO(x) ((GET_PORTF(x) << 4) + GET_FBITPOS(m)) ++#define FUNC_SHIFT 7 ++#define FUNC(x) ((x) << FUNC_SHIFT) ++#define GET_FUNC(x) (((x) >> FUNC_SHIFT) & 3) ++#define IS_GPIO (3) ++ ++/* control pad's GPIO feature if enabled */ ++#define GPIO_OUT (1 << 19) ++#define GPIO_VALUE(x) ((x) << 20) ++#define GPIO_IN (0 << 19) ++#define GET_GPIODIR(x) (!!((x) & (1 << 19))) ++#define GET_GPIOVAL(x) (!!((x) & (1 << 20))) ++ ++/* control pad's drive strength */ ++#define SE (1 << 9) ++#define SE_PRESENT(x) (!!((x) & SE)) ++#define STRENGTH(x) ((x) << 11) ++#define S4MA 0 /* used to define a 4 mA drive strength */ ++#define S8MA 1 /* used to define a 8 mA drive strength */ ++#define S12MA 2 /* used to define a 12 mA drive strength */ ++#define S16MA 3 /* used to define a 16 mA drive strength, not all pads can drive this current! */ ++#define GET_STRENGTH(x) (((x) >> 11) & 0x3) ++ ++/* control pad's pull up / bit keeper feature */ ++#define PE (1 << 10) ++#define PE_PRESENT(x) (!!((x) & PE)) ++#define PULLUP(x) ((x) << 13) ++#define GET_PULLUP(x) (!!((x) & (1 << 13))) ++ ++/* control pad's voltage feature */ ++#define VE (1 << 14) ++#define VE_PRESENT(x) (!!((x) & VE)) ++#define VE_1_8V (0 << 15) ++#define VE_2_5V (0 << 15) /* don't ask my why, RTFM */ ++#define GET_VOLTAGE(x) (!!((x) & (1 << 15))) ++ ++/* Bank 0, pins 0 ... 15, GPIO pins 0 ... 15 */ ++#define GPMI_D15 (FUNC(0) | PORTF(0, 15) | SE | PE) ++#define GPMI_D15_AUART2_TX (FUNC(1) | PORTF(0, 15) | SE | PE) ++#define GPMI_D15_GPMI_CE3N (FUNC(2) | PORTF(0, 15) | SE | PE) ++#define GPMI_D15_GPIO (FUNC(3) | PORTF(0, 15) | SE | PE) ++#define GPMI_D14 (FUNC(0) | PORTF(0, 14) | SE) ++#define GPMI_D14_AUART2_RX (FUNC(1) | PORTF(0, 14) | SE) ++#define GPMI_D14_GPIO (FUNC(3) | PORTF(0, 14) | SE) ++#define GPMI_D13 (FUNC(0) | PORTF(0, 13) | SE) ++#define GPMI_D13_LCD_D23 (FUNC(1) | PORTF(0, 13) | SE) ++#define GPMI_D13_GPIO (FUNC(3) | PORTF(0, 13) | SE) ++#define GPMI_D12 (FUNC(0) | PORTF(0, 12) | SE) ++#define GPMI_D12_LCD_D22 (FUNC(1) | PORTF(0, 12) | SE) ++#define GPMI_D12_GPIO (FUNC(3) | PORTF(0, 12) | SE) ++#define GPMI_D11 (FUNC(0) | PORTF(0, 11) | SE | PE) ++#define GPMI_D11_LCD_D21 (FUNC(1) | PORTF(0, 11) | SE | PE) ++#define GPMI_D11_SSP1_D7 (FUNC(2) | PORTF(0, 11) | SE | PE) ++#define GPMI_D11_GPIO (FUNC(3) | PORTF(0, 11) | SE | PE) ++#define GPMI_D10 (FUNC(0) | PORTF(0, 10) | SE | PE) ++#define GPMI_D10_LCD_D20 (FUNC(1) | PORTF(0, 10) | SE | PE) ++#define GPMI_D10_SSP1_D6 (FUNC(2) | PORTF(0, 10) | SE | PE) ++#define GPMI_D10_GPIO (FUNC(3) | PORTF(0, 10) | SE | PE) ++#define GPMI_D09 (FUNC(0) | PORTF(0, 9) | SE | PE) ++#define GPMI_D09_LCD_D19 (FUNC(1) | PORTF(0, 9) | SE | PE) ++#define GPMI_D09_SSP1_D5 (FUNC(2) | PORTF(0, 9) | SE | PE) ++#define GPMI_D09_GPIO (FUNC(3) | PORTF(0, 9) | SE | PE) ++#define GPMI_D08 (FUNC(0) | PORTF(0, 8) | SE | PE) ++#define GPMI_D08_LCD_D18 (FUNC(1) | PORTF(0, 8) | SE | PE) ++#define GPMI_D08_SSP1_D4 (FUNC(2) | PORTF(0, 8) | SE | PE) ++#define GPMI_D08_GPIO (FUNC(3) | PORTF(0, 8) | SE | PE) ++#define GPMI_D07 (FUNC(0) | PORTF(0, 7) | SE | PE) ++#define GPMI_D07_LCD_D15 (FUNC(1) | PORTF(0, 7) | SE | PE) ++#define GPMI_D07_SSP2_D7 (FUNC(2) | PORTF(0, 7) | SE | PE) ++#define GPMI_D07_GPIO (FUNC(3) | PORTF(0, 7) | SE | PE) ++#define GPMI_D06 (FUNC(0) | PORTF(0, 6) | SE | PE) ++#define GPMI_D06_LCD_D14 (FUNC(1) | PORTF(0, 6) | SE | PE) ++#define GPMI_D06_SSP2_D6 (FUNC(2) | PORTF(0, 6) | SE | PE) ++#define GPMI_D06_GPIO (FUNC(3) | PORTF(0, 6) | SE | PE) ++#define GPMI_D05 (FUNC(0) | PORTF(0, 5) | SE | PE) ++#define GPMI_D05_LCD_D13 (FUNC(1) | PORTF(0, 5) | SE | PE) ++#define GPMI_D05_SSP2_D5 (FUNC(2) | PORTF(0, 5) | SE | PE) ++#define GPMI_D05_GPIO (FUNC(3) | PORTF(0, 5) | SE | PE) ++#define GPMI_D04 (FUNC(0) | PORTF(0, 4) | SE | PE) ++#define GPMI_D04_LCD_D12 (FUNC(1) | PORTF(0, 4) | SE | PE) ++#define GPMI_D04_SSP2_D4 (FUNC(2) | PORTF(0, 4) | SE | PE) ++#define GPMI_D04_GPIO (FUNC(3) | PORTF(0, 4) | SE | PE) ++#define GPMI_D03 (FUNC(0) | PORTF(0, 3) | SE | PE) ++#define GPMI_D03_LCD_D11 (FUNC(1) | PORTF(0, 3) | SE | PE) ++#define GPMI_D03_SSP2_D3 (FUNC(2) | PORTF(0, 3) | SE | PE) ++#define GPMI_D03_GPIO (FUNC(3) | PORTF(0, 3) | SE | PE) ++#define GPMI_D02 (FUNC(0) | PORTF(0, 2) | SE | PE) ++#define GPMI_D02_LCD_D10 (FUNC(1) | PORTF(0, 2) | SE | PE) ++#define GPMI_D02_SSP2_D2 (FUNC(2) | PORTF(0, 2) | SE | PE) ++#define GPMI_D02_GPIO (FUNC(3) | PORTF(0, 2) | SE | PE) ++#define GPMI_D01 (FUNC(0) | PORTF(0, 1) | SE | PE) ++#define GPMI_D01_LCD_D9 (FUNC(1) | PORTF(0, 1) | SE | PE) ++#define GPMI_D01_SSP2_D1 (FUNC(2) | PORTF(0, 1) | SE | PE) ++#define GPMI_D01_GPIO (FUNC(3) | PORTF(0, 1) | SE | PE) ++#define GPMI_D00 (FUNC(0) | PORTF(0, 0) | SE | PE) ++#define GPMI_D00_LCD_D8 (FUNC(1) | PORTF(0, 0) | SE | PE) ++#define GPMI_D00_SSP2_D0 (FUNC(2) | PORTF(0, 0) | SE | PE) ++#define GPMI_D00_GPIO (FUNC(3) | PORTF(0, 0) | SE | PE) ++ ++/* Bank 0, pins 16 ... 31 GPIO pins 16 ... 31 */ ++#define I2C_SDA (FUNC(0) | PORTF(1, 15) | SE) ++#define I2C_SDA_GPMI_CE2N (FUNC(1) | PORTF(1, 15) | SE) ++#define I2C_SDA_AUART1_RX (FUNC(2) | PORTF(1, 15) | SE) ++#define I2C_SDA_GPIO (FUNC(3) | PORTF(1, 15) | SE) ++#define I2C_CLK (FUNC(0) | PORTF(1, 14) | SE | PE) ++#define I2C_CLK_GPMI_RDY2 (FUNC(1) | PORTF(1, 14) | SE | PE) ++#define I2C_CLK_AUART1_TX (FUNC(2) | PORTF(1, 14) | SE | PE) ++#define I2C_CLK_GPIO (FUNC(3) | PORTF(1, 14) | SE | PE) ++#define AUART1_TX (FUNC(0) | PORTF(1, 13) | SE | PE) ++#define AUART1_TX_SSP1_D7 (FUNC(2) | PORTF(1, 13) | SE | PE) ++#define AUART1_TX_GPIO (FUNC(3) | PORTF(1, 13) | SE | PE) ++#define AUART1_RX (FUNC(0) | PORTF(1, 12) | SE | PE) ++#define AUART1_RX_SSP1_D6 (FUNC(2) | PORTF(1, 12) | SE | PE) ++#define AUART1_RX_GPIO (FUNC(3) | PORTF(1, 12) | SE | PE) ++#define AUART1_RTS (FUNC(0) | PORTF(1, 11) | SE | PE) ++#define AUART1_RTS_SSP1_D5 (FUNC(2) | PORTF(1, 11) | SE | PE) ++#define AUART1_RTS_GPIO (FUNC(3) | PORTF(1, 11) | SE | PE) ++#define AUART1_CTS (FUNC(0) | PORTF(1, 10) | SE | PE) ++#define AUART1_CTS_SSP1_D4 (FUNC(2) | PORTF(1, 10) | SE | PE) ++#define AUART1_CTS_GPIO (FUNC(3) | PORTF(1, 10) | SE | PE) ++#define GPMI_RDN (FUNC(0) | PORTF(1, 9) | SE) ++#define GPMI_RDN_GPIO (FUNC(3) | PORTF(1, 9) | SE) ++#define GPMI_WRN (FUNC(0) | PORTF(1, 8) | SE) ++#define GPMI_WRN_SSP2_SCK (FUNC(2) | PORTF(1, 8) | SE) ++#define GPMI_WRN_GPIO (FUNC(3) | PORTF(1, 8) | SE) ++#define GPMI_WPM (FUNC(0) | PORTF(1, 7) | SE) ++#define GPMI_WPM_GPIO (FUNC(3) | PORTF(1, 7) | SE) ++#define GPMI_RDY3 (FUNC(0) | PORTF(1, 6) | SE | PE) ++#define GPMI_RDY3_GPIO (FUNC(3) | PORTF(1, 6) | SE | PE) ++#define GPMI_RDY2 (FUNC(0) | PORTF(1, 5) | SE | PE) ++#define GPMI_RDY2_GPIO (FUNC(3) | PORTF(1, 5) | SE | PE) ++#define GPMI_RDY1 (FUNC(0) | PORTF(1, 4) | SE | PE) ++#define GPMI_RDY1_SSP2_CMD (FUNC(2) | PORTF(1, 4) | SE | PE) ++#define GPMI_RDY1_GPIO (FUNC(3) | PORTF(1, 4) | SE | PE) ++#define GPMI_RDY0 (FUNC(0) | PORTF(1, 3) | SE | PE) ++#define GPMI_RDY0_SSP2_DETECT (FUNC(2) | PORTF(1, 3) | SE | PE) ++#define GPMI_RDY0_GPIO (FUNC(3) | PORTF(1, 3) | SE | PE) ++#define GPMI_CE2N (FUNC(0) | PORTF(1, 2) | SE | PE) ++#define GPMI_CE2N_GPIO (FUNC(3) | PORTF(1, 2) | SE | PE) ++#define GPMI_ALE (FUNC(0) | PORTF(1, 1) | SE) ++#define GPMI_ALE_LCD_D17 (FUNC(1) | PORTF(1, 1) | SE) ++#define GPMI_ALE_GPIO (FUNC(3) | PORTF(1, 1) | SE) ++#define GPMI_CLE (FUNC(0) | PORTF(1, 0) | SE) ++#define GPMI_CLE_LCD_D16 (FUNC(1) | PORTF(1, 1) | SE) ++#define GPMI_CLE_GPIO (FUNC(3) | PORTF(1, 0) | SE) ++ ++/* Bank 1, pins 0 ... 15 GPIO pins 32 ... 47 */ ++#define LCD_D15 (FUNC(0) | PORTF(2, 15) | SE) ++#define LCD_D15_ETM_DA7 (FUNC(1) | PORTF(2, 15) | SE) ++#define LCD_D15_SAIF1_SDATA1 (FUNC(2) | PORTF(2, 15) | SE) ++#define LCD_D15_GPIO (FUNC(3) | PORTF(2, 15) | SE) ++#define LCD_D14 (FUNC(0) | PORTF(2, 14) | SE) ++#define LCD_D14_ETM_DA6 (FUNC(1) | PORTF(2, 14) | SE) ++#define LCD_D14_SAIF1_SDATA2 (FUNC(2) | PORTF(2, 14) | SE) ++#define LCD_D14_GPIO (FUNC(3) | PORTF(2, 14) | SE) ++#define LCD_D13 (FUNC(0) | PORTF(2, 13) | SE) ++#define LCD_D13_ETM_DA5 (FUNC(1) | PORTF(2, 13) | SE) ++#define LCD_D13_SAIF2_SDATA2 (FUNC(2) | PORTF(2, 13) | SE) ++#define LCD_D13_GPIO (FUNC(3) | PORTF(2, 13) | SE) ++#define LCD_D12 (FUNC(0) | PORTF(2, 12) | SE) ++#define LCD_D12_ETM_DA4 (FUNC(1) | PORTF(2, 12) | SE) ++#define LCD_D12_SAIF2_SDATA1 (FUNC(2) | PORTF(2, 12) | SE) ++#define LCD_D12_GPIO (FUNC(3) | PORTF(2, 12) | SE) ++#define LCD_D11 (FUNC(0) | PORTF(2, 11) | SE) ++#define LCD_D11_ETM_DA3 (FUNC(1) | PORTF(2, 11) | SE) ++#define LCD_D11_SAIF_LRCLK (FUNC(2) | PORTF(2, 11) | SE) ++#define LCD_D11_GPIO (FUNC(3) | PORTF(2, 11) | SE) ++#define LCD_D10 (FUNC(0) | PORTF(2, 10) | SE) ++#define LCD_D10_ETM_DA2 (FUNC(1) | PORTF(2, 10) | SE) ++#define LCD_D10_SAIF_BITCLK (FUNC(2) | PORTF(2, 10) | SE) ++#define LCD_D10_GPIO (FUNC(3) | PORTF(2, 10) | SE) ++#define LCD_D9 (FUNC(0) | PORTF(2, 9) | SE) ++#define LCD_D9_ETM_DA1 (FUNC(1) | PORTF(2, 9) | SE) ++#define LCD_D9_SAIF1_SDATA0 (FUNC(2) | PORTF(2, 9) | SE) ++#define LCD_D9_GPIO (FUNC(3) | PORTF(2, 9) | SE) ++#define LCD_D8 (FUNC(0) | PORTF(2, 8) | SE) ++#define LCD_D8_ETM_DA0 (FUNC(1) | PORTF(2, 8) | SE) ++#define LCD_D8_SAIF2_SDATA0 (FUNC(2) | PORTF(2, 8) | SE) ++#define LCD_D8_GPIO (FUNC(3) | PORTF(2, 8) | SE) ++#define LCD_D7 (FUNC(0) | PORTF(2, 7) | SE) ++#define LCD_D7_ETM_DA15 (FUNC(1) | PORTF(2, 7) | SE) ++#define LCD_D7_GPIO (FUNC(3) | PORTF(2, 7) | SE) ++#define LCD_D6 (FUNC(0) | PORTF(2, 6) | SE) ++#define LCD_D6_ETM_DA14 (FUNC(1) | PORTF(2, 6) | SE) ++#define LCD_D6_GPIO (FUNC(3) | PORTF(2, 6) | SE) ++#define LCD_D5 (FUNC(0) | PORTF(2, 5) | SE) ++#define LCD_D5_ETM_DA13 (FUNC(1) | PORTF(2, 5) | SE) ++#define LCD_D5_GPIO (FUNC(3) | PORTF(2, 5) | SE) ++#define LCD_D4 (FUNC(0) | PORTF(2, 4) | SE) ++#define LCD_D4_ETM_DA12 (FUNC(1) | PORTF(2, 4) | SE) ++#define LCD_D4_GPIO (FUNC(3) | PORTF(2, 4) | SE) ++#define LCD_D3 (FUNC(0) | PORTF(2, 3) | SE) ++#define LCD_D3_ETM_DA11 (FUNC(1) | PORTF(2, 3) | SE) ++#define LCD_D3_GPIO (FUNC(3) | PORTF(2, 3) | SE) ++#define LCD_D2 (FUNC(0) | PORTF(2, 2) | SE) ++#define LCD_D2_ETM_DA10 (FUNC(1) | PORTF(2, 2) | SE) ++#define LCD_D2_GPIO (FUNC(3) | PORTF(2, 2) | SE) ++#define LCD_D1 (FUNC(0) | PORTF(2, 1) | SE) ++#define LCD_D1_ETM_DA9 (FUNC(1) | PORTF(2, 1) | SE) ++#define LCD_D1_GPIO (FUNC(3) | PORTF(2, 1) | SE) ++#define LCD_D0 (FUNC(0) | PORTF(2, 0) | SE) ++#define LCD_D0_ETM_DA8 (FUNC(1) | PORTF(2, 0) | SE) ++#define LCD_D0_GPIO (FUNC(3) | PORTF(2, 0) | SE) ++ ++/* Bank 1, pins 16 ... 30 GPIO pins 48 ... 63 */ ++#define PWM4 (FUNC(0) | PORTF(3, 14) | SE) ++#define PWM4_ETM_CLK (FUNC(1) | PORTF(3, 14) | SE) ++#define PWM4_AUART1_RTS (FUNC(2) | PORTF(3, 14) | SE) ++#define PWM4_GPIO (FUNC(3) | PORTF(3, 14) | SE) ++#define PWM3 (FUNC(0) | PORTF(3, 13) | SE) ++#define PWM3_ETM_TCTL (FUNC(1) | PORTF(3, 13) | SE) ++#define PWM3_AUART1_CTS (FUNC(2) | PORTF(3, 13) | SE) ++#define PWM3_GPIO (FUNC(3) | PORTF(3, 13) | SE) ++#define PWM2 (FUNC(0) | PORTF(3, 12) | SE | PE) ++#define PWM2_GPMI_READY3 (FUNC(1) | PORTF(3, 12) | SE | PE) ++#define PWM2_GPIO (FUNC(3) | PORTF(3, 12) | SE | PE) ++#define PWM1 (FUNC(0) | PORTF(3, 11) | SE) ++#define PWM1_TIMROT2 (FUNC(1) | PORTF(3, 11) | SE) ++#define PWM1_DUART_TX (FUNC(2) | PORTF(3, 11) | SE) ++#define PWM1_GPIO (FUNC(3) | PORTF(3, 11) | SE) ++#define PWM0 (FUNC(0) | PORTF(3, 10) | SE) ++#define PWM0_TIMROT1 (FUNC(1) | PORTF(3, 10) | SE) ++#define PWM0_DUART_RX (FUNC(2) | PORTF(3, 10) | SE) ++#define PWM0_GPIO (FUNC(3) | PORTF(3, 10) | SE) ++#define LCD_VSYNC (FUNC(0) | PORTF(3, 9) | SE) ++#define LCD_VSYNC_LCD_BUSY (FUNC(1) | PORTF(3, 9) | SE) ++#define LCD_VSYNC_GPIO (FUNC(3) | PORTF(3, 9) | SE) ++#define LCD_HSYNC (FUNC(0) | PORTF(3, 8) | SE) ++#define LCD_HSYNC_I2C_SD (FUNC(1) | PORTF(3, 8) | SE) ++#define LCD_HSYNC_GPIO (FUNC(3) | PORTF(3, 8) | SE) ++#define LCD_ENABE (FUNC(0) | PORTF(3, 7) | SE) ++#define LCD_ENABE_I2C_CLK (FUNC(1) | PORTF(3, 7) | SE) ++#define LCD_ENABE_GPIO (FUNC(3) | PORTF(3, 7) | SE) ++#define LCD_DOTCLOCK (FUNC(0) | PORTF(3, 6) | SE | PE) ++#define LCD_DOTCLOCK_GPMI_READY3 (FUNC(1) | PORTF(3, 6) | SE | PE) ++#define LCD_DOTCLOCK_GPIO (FUNC(3) | PORTF(3, 6) | SE | PE) ++#define LCD_CS (FUNC(0) | PORTF(3, 5) | SE) ++#define LCD_CS_GPIO (FUNC(3) | PORTF(3, 5) | SE) ++#define LCD_WR (FUNC(0) | PORTF(3, 4) | SE) ++#define LCD_WR_GPIO (FUNC(3) | PORTF(3, 4) | SE) ++#define LCD_RS (FUNC(0) | PORTF(3, 3) | SE) ++#define LCD_RS_ETM_TCLK (FUNC(1) | PORTF(3, 3) | SE) ++#define LCD_RS_GPIO (FUNC(3) | PORTF(3, 3) | SE) ++#define LCD_RESET (FUNC(0) | PORTF(3, 2) | SE | PE) ++#define LCD_RESET_ETM_TCTL (FUNC(1) | PORTF(3, 2) | SE | PE) ++#define LCD_RESET_GPMI_CE3N (FUNC(2) | PORTF(3, 2) | SE | PE) ++#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 2) | SE | PE) ++#define LCD_D17 (FUNC(0) | PORTF(3, 1) | SE) ++#define LCD_D17_GPIO (FUNC(3) | PORTF(3, 1) | SE) ++#define LCD_D16 (FUNC(0) | PORTF(3, 0) | SE) ++#define LCD_D16_SAIF_ALT_BITCLK (FUNC(2) | PORTF(3, 0) | SE) ++#define LCD_D16_GPIO (FUNC(3) | PORTF(3, 0) | SE) ++ ++/* Bank 2, pins 0 ... 15 GPIO pins 64 ... 79 */ ++#define EMI_A6 (FUNC(0) | PORTF(4, 15) | SE | VE) ++#define EMI_A6_GPIO (FUNC(3) | PORTF(4, 15) | SE | VE) ++#define EMI_A5 (FUNC(0) | PORTF(4, 14) | SE | VE) ++#define EMI_A5_GPIO (FUNC(3) | PORTF(4, 14) | SE | VE) ++#define EMI_A4 (FUNC(0) | PORTF(4, 13) | SE | VE) ++#define EMI_A4_GPIO (FUNC(3) | PORTF(4, 13) | SE | VE) ++#define EMI_A3 (FUNC(0) | PORTF(4, 12) | SE | VE) ++#define EMI_A3_GPIO (FUNC(3) | PORTF(4, 12) | SE | VE) ++#define EMI_A2 (FUNC(0) | PORTF(4, 11) | SE | VE) ++#define EMI_A2_GPIO (FUNC(3) | PORTF(4, 11) | SE | VE) ++#define EMI_A1 (FUNC(0) | PORTF(4, 10) | SE | VE) ++#define EMI_A1_GPIO (FUNC(3) | PORTF(4, 10) | SE | VE) ++#define EMI_A0 (FUNC(0) | PORTF(4, 9) | SE | VE) ++#define EMI_A0_GPIO (FUNC(3) | PORTF(4, 9) | SE | VE) ++#define ROTARYB (FUNC(0) | PORTF(4, 8) | SE | PE) ++#define ROTARYB_AUART2_CTS (FUNC(1) | PORTF(4, 8) | SE | PE) ++#define ROTARYB_GPMI_CE3N (FUNC(2) | PORTF(4, 8) | SE | PE) ++#define ROTARYB_GPIO (FUNC(3) | PORTF(4, 8) | SE | PE) ++#define ROTARYA (FUNC(0) | PORTF(4, 7) | SE) ++#define ROTARYA_AUART2_RTS (FUNC(1) | PORTF(4, 7) | SE) ++#define ROTARYA_SPDIF (FUNC(2) | PORTF(4, 7) | SE) ++#define ROTARYA_GPIO (FUNC(3) | PORTF(4, 7) | SE) ++#define SSP1_SCK (FUNC(0) | PORTF(4, 6) | SE) ++#define SSP1_SCK_ALT_JTAG_TRST (FUNC(2) | PORTF(4, 6) | SE) ++#define SSP1_SCK_GPIO (FUNC(3) | PORTF(4, 6) | SE) ++#define SSP1_DATA3 (FUNC(0) | PORTF(4, 5) | SE | PE) ++#define SSP1_DATA3_ALT_JTAG_TMS (FUNC(2) | PORTF(4, 5) | SE | PE) ++#define SSP1_DATA3_GPIO (FUNC(3) | PORTF(4, 5) | SE | PE) ++#define SSP1_DATA2 (FUNC(0) | PORTF(4, 4) | SE | PE) ++#define SSP1_DATA2_I2C_SD (FUNC(1) | PORTF(4, 4) | SE | PE) ++#define SSP1_DATA2_ALT_JTAG_RTCK (FUNC(2) | PORTF(4, 4) | SE | PE) ++#define SSP1_DATA2_GPIO (FUNC(3) | PORTF(4, 4) | SE | PE) ++#define SSP1_DATA1 (FUNC(0) | PORTF(4, 3) | SE | PE) ++#define SSP1_DATA1_I2C_CLK (FUNC(1) | PORTF(4, 3) | SE | PE) ++#define SSP1_DATA1_ALT_JTAG_TCK (FUNC(2) | PORTF(4, 3) | SE | PE) ++#define SSP1_DATA1_GPIO (FUNC(3) | PORTF(4, 3) | SE | PE) ++#define SSP1_DATA0 (FUNC(0) | PORTF(4, 2) | SE | PE) ++#define SSP1_DATA0_ALT_JTAG_TDI (FUNC(2) | PORTF(4, 2) | SE | PE) ++#define SSP1_DATA0_GPIO (FUNC(3) | PORTF(4, 2) | SE | PE) ++#define SSP1_DETECT (FUNC(0) | PORTF(4, 1) | SE | PE) ++#define SSP1_DETECT_GPMI_CE3N (FUNC(1) | PORTF(4, 1) | SE | PE) ++#define SSP1_DETECT_USB_ID (FUNC(2) | PORTF(4, 1) | SE | PE) ++#define SSP1_DETECT_GPIO (FUNC(3) | PORTF(4, 1) | SE | PE) ++#define SSP1_CMD (FUNC(0) | PORTF(4, 0) | SE | PE) ++#define SSP1_CMD_JTAG_TDO (FUNC(2) | PORTF(4, 0) | SE | PE) ++#define SSP1_CMD_GPIO (FUNC(3) | PORTF(4, 0) | SE | PE) ++ ++/* Bank 2, pins 16 ... 31 GPIO pins 80 ... 95 */ ++#define EMI_WEN (FUNC(0) | PORTF(5, 15) | SE | VE) ++#define EMI_WEN_GPIO (FUNC(3) | PORTF(5, 15) | SE | VE) ++#define EMI_RASN (FUNC(0) | PORTF(5, 14) | SE | VE) ++#define EMI_RASN_GPIO (FUNC(3) | PORTF(5, 14) | SE | VE) ++#define EMI_CKE (FUNC(0) | PORTF(5, 13) | SE | VE) ++#define EMI_CKE_GPIO (FUNC(3) | PORTF(5, 13) | SE | VE) ++#define GPMI_CE0N (FUNC(0) | PORTF(5, 12) | SE) ++#define GPMI_CE0N_GPIO (FUNC(3) | PORTF(5, 12) | SE) ++#define GPMI_CE1N (FUNC(0) | PORTF(5, 11) | SE | PE) ++#define GPMI_CE1N_GPIO (FUNC(3) | PORTF(5, 11) | SE | PE) ++#define EMI_CE1N (FUNC(0) | PORTF(5, 10) | SE | VE | PE) ++#define EMI_CE1N_GPIO (FUNC(3) | PORTF(5, 10) | SE | VE | PE) ++#define EMI_CE0N (FUNC(0) | PORTF(5, 9) | SE | VE) ++#define EMI_CE0N_GPIO (FUNC(3) | PORTF(5, 9) | SE | VE) ++#define EMI_CASN (FUNC(0) | PORTF(5, 8) | SE | VE) ++#define EMI_CASN_GPIO (FUNC(3) | PORTF(5, 8) | SE | VE) ++#define EMI_BA1 (FUNC(0) | PORTF(5, 7) | SE | VE) ++#define EMI_BA1_GPIO (FUNC(3) | PORTF(5, 7) | SE | VE) ++#define EMI_BA0 (FUNC(0) | PORTF(5, 6) | SE | VE) ++#define EMI_BA0_GPIO (FUNC(3) | PORTF(5, 6) | SE | VE) ++#define EMI_A12 (FUNC(0) | PORTF(5, 5) | SE | VE) ++#define EMI_A12_GPIO (FUNC(3) | PORTF(5, 5) | SE | VE) ++#define EMI_A11 (FUNC(0) | PORTF(5, 4) | SE | VE) ++#define EMI_A11_GPIO (FUNC(3) | PORTF(5, 4) | SE | VE) ++#define EMI_A10 (FUNC(0) | PORTF(5, 3) | SE | VE) ++#define EMI_A10_GPIO (FUNC(3) | PORTF(5, 3) | SE | VE) ++#define EMI_A9 (FUNC(0) | PORTF(5, 2) | SE | VE) ++#define EMI_A9_GPIO (FUNC(3) | PORTF(5, 2) | SE | VE) ++#define EMI_A8 (FUNC(0) | PORTF(5, 1) | SE | VE) ++#define EMI_A8_GPIO (FUNC(3) | PORTF(5, 1) | SE | VE) ++#define EMI_A7 (FUNC(0) | PORTF(5, 0) | SE | VE) ++#define EMI_A7_GPIO (FUNC(3) | PORTF(5, 0) | SE | VE) ++ ++/* Bank 3, pins 0 ... 15 GPIO pins 96 ... 111 */ ++#define EMI_D15 (FUNC(0) | PORTF(6, 15) | SE | VE | PE) ++#define EMI_D15_DISABLED (FUNC(3) | PORTF(6, 15) | SE | VE | PE) ++#define EMI_D14 (FUNC(0) | PORTF(6, 14) | SE | VE | PE) ++#define EMI_D14_DISABLED (FUNC(3) | PORTF(6, 14) | SE | VE | PE) ++#define EMI_D13 (FUNC(0) | PORTF(6, 13) | SE | VE | PE) ++#define EMI_D13_DISABLED (FUNC(3) | PORTF(6, 13) | SE | VE | PE) ++#define EMI_D12 (FUNC(0) | PORTF(6, 12) | SE | VE | PE) ++#define EMI_D12_DISABLED (FUNC(3) | PORTF(6, 12) | SE | VE | PE) ++#define EMI_D11 (FUNC(0) | PORTF(6, 11) | SE | VE | PE) ++#define EMI_D11_DISABLED (FUNC(3) | PORTF(6, 11) | SE | VE | PE) ++#define EMI_D10 (FUNC(0) | PORTF(6, 10) | SE | VE | PE) ++#define EMI_D10_DISABLED (FUNC(3) | PORTF(6, 10) | SE | VE | PE) ++#define EMI_D9 (FUNC(0) | PORTF(6, 9) | SE | VE | PE) ++#define EMI_D9_DISABLED (FUNC(3) | PORTF(6, 9) | SE | VE | PE) ++#define EMI_D8 (FUNC(0) | PORTF(6, 8) | SE | VE | PE) ++#define EMI_D8_DISABLED (FUNC(3) | PORTF(6, 8) | SE | VE | PE) ++#define EMI_D7 (FUNC(0) | PORTF(6, 7) | SE | VE | PE) ++#define EMI_D7_DISABLED (FUNC(3) | PORTF(6, 7) | SE | VE | PE) ++#define EMI_D6 (FUNC(0) | PORTF(6, 6) | SE | VE | PE) ++#define EMI_D6_DISABLED (FUNC(3) | PORTF(6, 6) | SE | VE | PE) ++#define EMI_D5 (FUNC(0) | PORTF(6, 5) | SE | VE | PE) ++#define EMI_D5_DISABLED (FUNC(3) | PORTF(6, 5) | SE | VE | PE) ++#define EMI_D4 (FUNC(0) | PORTF(6, 4) | SE | VE | PE) ++#define EMI_D4_DISABLED (FUNC(3) | PORTF(6, 4) | SE | VE | PE) ++#define EMI_D3 (FUNC(0) | PORTF(6, 3) | SE | VE | PE) ++#define EMI_D3_DISABLED (FUNC(3) | PORTF(6, 3) | SE | VE | PE) ++#define EMI_D2 (FUNC(0) | PORTF(6, 2) | SE | VE | PE) ++#define EMI_D2_DISABLED (FUNC(3) | PORTF(6, 2) | SE | VE | PE) ++#define EMI_D1 (FUNC(0) | PORTF(6, 1) | SE | VE | PE) ++#define EMI_D1_DISABLED (FUNC(3) | PORTF(6, 1) | SE | VE | PE) ++#define EMI_D0 (FUNC(0) | PORTF(6, 0) | SE | VE | PE) ++#define EMI_D0_DISABLED (FUNC(3) | PORTF(6, 0) | SE | VE | PE) ++ ++/* Bank 3, pins 16 ... 21 GPIO pins 112 ... 117 */ ++#define EMI_CLKN (FUNC(0) | PORTF(7, 5) | SE | VE) ++#define EMI_CLKN_DISABLED (FUNC(3) | PORTF(7, 5) | SE | VE) ++#define EMI_CLK (FUNC(0) | PORTF(7, 4) | SE | VE) ++#define EMI_CLK_DISABLED (FUNC(3) | PORTF(7, 4) | SE | VE) ++#define EMI_DQS1 (FUNC(0) | PORTF(7, 3) | SE | VE) ++#define EMI_DQS1_DISABLED (FUNC(3) | PORTF(7, 3) | SE | VE) ++#define EMI_DQS0 (FUNC(0) | PORTF(7, 2) | SE | VE) ++#define EMI_DQS0_DISABLED (FUNC(3) | PORTF(7, 2) | SE | VE) ++#define EMI_DQM1 (FUNC(0) | PORTF(7, 1) | SE | VE | PE) ++#define EMI_DQM1_DISABLED (FUNC(3) | PORTF(7, 1) | SE | VE | PE) ++#define EMI_DQM0 (FUNC(0) | PORTF(7, 0) | SE | VE | PE) ++#define EMI_DQM0_DISABLED (FUNC(3) | PORTF(7, 0) | SE | VE | PE) ++ ++#endif /* __ASM_MACH_IOMUX_H */ +diff --git a/arch/arm/mach-stm/include/mach/mci.h b/arch/arm/mach-stm/include/mach/mci.h +new file mode 100644 +index 0000000..b924908 +--- /dev/null ++++ b/arch/arm/mach-stm/include/mach/mci.h +@@ -0,0 +1,32 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __MACH_MMC_H ++#define __MACH_MMC_H ++ ++struct stm_mci_platform_data { ++ unsigned caps; /**< supported operating modes (MMC_MODE_*) */ ++ unsigned voltages; /**< supported voltage range (MMC_VDD_*) */ ++ unsigned f_min; /**< min operating frequency in Hz (0 -> no limit) */ ++ unsigned f_max; /**< max operating frequency in Hz (0 -> no limit) */ ++ /* TODO */ ++ /* function to modify the voltage */ ++ /* function to switch the voltage */ ++ /* function to detect the presence of a SD card in the socket */ ++}; ++ ++#endif /* __MACH_MMC_H */ +diff --git a/arch/arm/mach-stm/iomux-imx23.c b/arch/arm/mach-stm/iomux-imx23.c +new file mode 100644 +index 0000000..b0f4046 +--- /dev/null ++++ b/arch/arm/mach-stm/iomux-imx23.c +@@ -0,0 +1,117 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <gpio.h> ++#include <asm/io.h> ++#include <mach/imx-regs.h> ++ ++#define HW_PINCTRL_CTRL 0x000 ++#define HW_PINCTRL_MUXSEL0 0x100 ++#define HW_PINCTRL_DRIVE0 0x200 ++#define HW_PINCTRL_PULL0 0x400 ++#define HW_PINCTRL_DOUT0 0x500 ++#define HW_PINCTRL_DIN0 0x600 ++#define HW_PINCTRL_DOE0 0x700 ++ ++static uint32_t calc_mux_reg(uint32_t no) ++{ ++ /* each register controls 16 pads */ ++ return ((no >> 4) << 4) + HW_PINCTRL_MUXSEL0; ++} ++ ++static uint32_t calc_strength_reg(uint32_t no) ++{ ++ /* each register controls 8 pads */ ++ return ((no >> 3) << 4) + HW_PINCTRL_DRIVE0; ++} ++ ++static uint32_t calc_pullup_reg(uint32_t no) ++{ ++ /* each register controls 32 pads */ ++ return ((no >> 5) << 4) + HW_PINCTRL_PULL0; ++} ++ ++static uint32_t calc_output_enable_reg(uint32_t no) ++{ ++ /* each register controls 32 pads */ ++ return ((no >> 5) << 4) + HW_PINCTRL_DOE0; ++} ++ ++static uint32_t calc_output_reg(uint32_t no) ++{ ++ /* each register controls 32 pads */ ++ return ((no >> 5) << 4) + HW_PINCTRL_DOUT0; ++} ++ ++/** ++ * @param[in] m One of the defines from iomux-mx23.h to configure *one* pin ++ */ ++void imx_gpio_mode(unsigned m) ++{ ++ uint32_t reg_offset, gpio_pin, reg; ++ ++ gpio_pin = GET_GPIO_NO(m); ++ ++ /* configure the pad to its function (always) */ ++ reg_offset = calc_mux_reg(gpio_pin); ++ reg = readl(IMX_IOMUXC_BASE + reg_offset) & ~(0x3 << ((gpio_pin % 16) << 1)); ++ reg |= GET_FUNC(m) << ((gpio_pin % 16) << 1); ++ writel(reg, IMX_IOMUXC_BASE + reg_offset); ++ ++ /* some pins are disabled when configured for GPIO */ ++ if ((gpio_pin > 95) && (GET_FUNC(m) == IS_GPIO)) { ++ printf("Cannot configure pad %d to GPIO\n", gpio_pin); ++ return; ++ } ++ ++ if (SE_PRESENT(m)) { ++ reg_offset = calc_strength_reg(gpio_pin); ++ reg = readl(IMX_IOMUXC_BASE + reg_offset) & ~(0x3 << ((gpio_pin % 8) << 2)); ++ reg |= GET_STRENGTH(m) << ((gpio_pin % 8) << 2); ++ writel(reg, IMX_IOMUXC_BASE + reg_offset); ++ } ++ ++ if (VE_PRESENT(m)) { ++ reg_offset = calc_strength_reg(gpio_pin); ++ if (GET_VOLTAGE(m) == 1) ++ writel(0x1 << (((gpio_pin % 8) << 2) + 2), IMX_IOMUXC_BASE + reg_offset + 4); ++ else ++ writel(0x1 << (((gpio_pin % 8) << 2) + 2), IMX_IOMUXC_BASE + reg_offset + 8); ++ } ++ ++ if (PE_PRESENT(m)) { ++ reg_offset = calc_pullup_reg(gpio_pin); ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + (GET_PULLUP(m) == 1 ? 4 : 8)); ++ } ++ ++ if (GET_FUNC(m) == IS_GPIO) { ++ if (GET_GPIODIR(m) == 1) { ++ /* first set the output value */ ++ reg_offset = calc_output_reg(gpio_pin); ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + (GET_GPIOVAL(m) == 1 ? 4 : 8)); ++ /* then the direction */ ++ reg_offset = calc_output_enable_reg(gpio_pin); ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + 4); ++ } else { ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + 8); ++ } ++ } ++} +diff --git a/arch/arm/mach-stm/reset-imx23.c b/arch/arm/mach-stm/reset-imx23.c +new file mode 100644 +index 0000000..b35f796 +--- /dev/null ++++ b/arch/arm/mach-stm/reset-imx23.c +@@ -0,0 +1,61 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <notifier.h> ++#include <mach/imx-regs.h> ++#include <asm/io.h> ++ ++#define HW_RTC_CTRL 0x000 ++# define BM_RTC_CTRL_WATCHDOGEN (1 << 4) ++#define HW_RTC_CTRL_SET 0x004 ++#define HW_RTC_CTRL_CLR 0x008 ++#define HW_RTC_CTRL_TOG 0x00C ++ ++#define HW_RTC_WATCHDOG 0x050 ++#define HW_RTC_WATCHDOG_SET 0x054 ++#define HW_RTC_WATCHDOG_CLR 0x058 ++#define HW_RTC_WATCHDOG_TOG 0x05C ++ ++#define WDOG_COUNTER_RATE 1000 /* 1 kHz clock */ ++ ++#define HW_RTC_PERSISTENT1 0x070 ++# define BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER 0x80000000 ++#define HW_RTC_PERSISTENT1_SET 0x074 ++#define HW_RTC_PERSISTENT1_CLR 0x078 ++#define HW_RTC_PERSISTENT1_TOG 0x07C ++ ++/* ++ * Reset the cpu by setting up the watchdog timer and let it time out ++ * ++ * TODO There is a much easier way to reset the CPU: Refer bit 2 in ++ * the HW_CLKCTRL_RESET register, data sheet page 106/4-30 ++ */ ++void __noreturn reset_cpu (unsigned long addr) ++{ ++ writel(WDOG_COUNTER_RATE, IMX_WDT_BASE + HW_RTC_WATCHDOG); ++ writel(BM_RTC_CTRL_WATCHDOGEN, IMX_WDT_BASE + HW_RTC_CTRL_SET); ++ writel(BV_RTC_PERSISTENT1_GENERAL__RTC_FORCE_UPDATER, IMX_WDT_BASE + HW_RTC_PERSISTENT1); ++ ++ while (1) ++ ; ++ /*NOTREACHED*/ ++} ++EXPORT_SYMBOL(reset_cpu); +diff --git a/arch/arm/mach-stm/speed-imx23.c b/arch/arm/mach-stm/speed-imx23.c +new file mode 100644 +index 0000000..7418ad5 +--- /dev/null ++++ b/arch/arm/mach-stm/speed-imx23.c +@@ -0,0 +1,280 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This code is based partially on code of: ++ * ++ * (c) 2008 Embedded Alley Solutions, Inc. ++ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <asm/io.h> ++#include <mach/imx-regs.h> ++#include <mach/generic.h> ++#include <mach/clock.h> ++ ++/* Note: all clock frequencies are returned in kHz */ ++ ++#define HW_CLKCTRL_PLLCTRL0 0x000 ++#define HW_CLKCTRL_PLLCTRL1 0x010 ++#define HW_CLKCTRL_CPU 0x20 ++# define GET_CPU_XTAL_DIV(x) (((x) >> 16) & 0x3ff) ++# define GET_CPU_PLL_DIV(x) ((x) & 0x3f) ++#define HW_CLKCTRL_HBUS 0x30 ++#define HW_CLKCTRL_XBUS 0x40 ++#define HW_CLKCTRL_XTAL 0x050 ++#define HW_CLKCTRL_PIX 0x060 ++/* note: no set/clear register! */ ++#define HW_CLKCTRL_SSP 0x070 ++/* note: no set/clear register! */ ++# define CLKCTRL_SSP_CLKGATE (1 << 31) ++# define CLKCTRL_SSP_BUSY (1 << 29) ++# define CLKCTRL_SSP_DIV_MASK 0x1ff ++# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) ++# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) ++#define HW_CLKCTRL_GPMI 0x080 ++/* note: no set/clear register! */ ++#define HW_CLKCTRL_SPDIF 0x090 ++/* note: no set/clear register! */ ++#define HW_CLKCTRL_EMI 0xa0 ++/* note: no set/clear register! */ ++# define CLKCTRL_EMI_CLKGATE (1 << 31) ++# define GET_EMI_XTAL_DIV(x) (((x) >> 8) & 0xf) ++# define GET_EMI_PLL_DIV(x) ((x) & 0x3f) ++#define HW_CLKCTRL_SAIF 0x0c0 ++#define HW_CLKCTRL_TV 0x0d0 ++#define HW_CLKCTRL_ETM 0x0e0 ++#define HW_CLKCTRL_FRAC 0xf0 ++# define CLKCTRL_FRAC_CLKGATEIO (1 << 31) ++# define GET_IOFRAC(x) (((x) >> 24) & 0x3f) ++# define SET_IOFRAC(x) (((x) & 0x3f) << 24) ++# define CLKCTRL_FRAC_CLKGATEPIX (1 << 23) ++# define GET_PIXFRAC(x) (((x) >> 16) & 0x3f) ++# define CLKCTRL_FRAC_CLKGATEEMI (1 << 15) ++# define GET_EMIFRAC(x) (((x) >> 8) & 0x3f) ++# define CLKCTRL_FRAC_CLKGATECPU (1 << 7) ++# define GET_CPUFRAC(x) ((x) & 0x3f) ++#define HW_CLKCTRL_FRAC1 0x100 ++#define HW_CLKCTRL_CLKSEQ 0x110 ++# define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) ++# define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) ++# define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) ++# define CLKCTRL_CLKSEQ_BYPASS_SSP (1 << 5) ++# define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) ++#define HW_CLKCTRL_RESET 0x120 ++#define HW_CLKCTRL_STATUS 0x130 ++#define HW_CLKCTRL_VERSION 0x140 ++ ++unsigned imx_get_mpllclk(void) ++{ ++ /* the main PLL runs at 480 MHz */ ++ return 480U * 1000U; ++} ++ ++unsigned imx_get_xtalclk(void) ++{ ++ /* the external reference runs at 24 MHz */ ++ return 24U * 1000U; ++} ++ ++/* used for the SDRAM controller */ ++unsigned imx_get_emiclk(void) ++{ ++ uint32_t reg; ++ unsigned rate; ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_EMI) & CLKCTRL_EMI_CLKGATE) ++ return 0U; /* clock is off */ ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_EMI) ++ return imx_get_xtalclk() / GET_EMI_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)); ++ ++ rate = imx_get_mpllclk(); ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC); ++ if (!(reg & CLKCTRL_FRAC_CLKGATEEMI)) { ++ rate *= 18U; ++ rate /= GET_EMIFRAC(reg); ++ } ++ ++ return rate / GET_EMI_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)); ++} ++ ++/* ++ * Source of ssp, gpmi, ir ++ */ ++unsigned imx_get_ioclk(void) ++{ ++ uint32_t reg; ++ unsigned rate = imx_get_mpllclk(); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC); ++ if (reg & CLKCTRL_FRAC_CLKGATEIO) ++ return 0U; /* clock is off */ ++ ++ rate *= 18U; ++ rate /= GET_IOFRAC(reg); ++ return rate; ++} ++ ++/** ++ * Setup a new frequency to the IOCLK domain. ++ * @param nc New frequency in [kHz] ++ * ++ * The FRAC divider for the IOCLK must be between 18 (* 18/18) and 35 (* 18/35) ++ */ ++unsigned imx_set_ioclk(unsigned nc) ++{ ++ uint32_t reg; ++ unsigned div; ++ ++ div = imx_get_mpllclk(); ++ div *= 18U; ++ div += nc >> 1; ++ div /= nc; ++ if (div > 0x3f) ++ div = 0x3f; ++ /* mask the current settings */ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC) & ~(SET_IOFRAC(0x3f)); ++ writel(reg | SET_IOFRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC); ++ /* enable the IO clock at its new frequency */ ++ writel(CLKCTRL_FRAC_CLKGATEIO, IMX_CCM_BASE + HW_CLKCTRL_FRAC + 8); ++ ++ return imx_get_ioclk(); ++} ++ ++/* this is CPU core clock */ ++unsigned imx_get_armclk(void) ++{ ++ uint32_t reg; ++ unsigned rate; ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_CPU) ++ return imx_get_xtalclk() / GET_CPU_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC); ++ if (reg & CLKCTRL_FRAC_CLKGATECPU) ++ return 0U; /* should not possible, shouldn't it? */ ++ ++ rate = imx_get_mpllclk(); ++ rate *= 18U; ++ rate /= GET_CPUFRAC(reg); ++ ++ return rate / GET_CPU_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)); ++} ++ ++/* this is the AHB and APBH bus clock */ ++unsigned imx_get_hclk(void) ++{ ++ unsigned rate = imx_get_armclk(); ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) { ++ rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; ++ rate >>= 5U; /* / 32 */ ++ } else ++ rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; ++ return rate; ++} ++ ++/* ++ * Source of UART, debug UART, audio, PWM, dri, timer, digctl ++ */ ++unsigned imx_get_xclk(void) ++{ ++ unsigned rate = imx_get_xtalclk(); /* runs from the 24 MHz crystal reference */ ++ ++ return rate / (readl(IMX_CCM_BASE + HW_CLKCTRL_XBUS) & 0x3ff); ++} ++ ++/* 'index' gets ignored on i.MX23 */ ++unsigned imx_get_sspclk(unsigned index) ++{ ++ unsigned rate; ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_CLKGATE) ++ return 0U; /* clock is off */ ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_SSP) ++ rate = imx_get_xtalclk(); ++ else ++ rate = imx_get_ioclk(); ++ ++ return rate / GET_SSP_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_SSP)); ++} ++ ++/** ++ * @param index Unit index (ignored on i.MX23) ++ * @param nc New frequency in [kHz] ++ * @param high != 0 if ioclk should be the source ++ * @return The new possible frequency in [kHz] ++ */ ++unsigned imx_set_sspclk(unsigned index, unsigned nc, int high) ++{ ++ uint32_t reg; ++ unsigned ssp_div; ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & ~CLKCTRL_SSP_CLKGATE; ++ /* Datasheet says: Do not change the DIV setting if the clock is off */ ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_SSP); ++ /* Wait while clock is gated */ ++ while (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_CLKGATE) ++ ; ++ ++ if (high) ++ ssp_div = imx_get_ioclk(); ++ else ++ ssp_div = imx_get_xtalclk(); ++ ++ if (nc > ssp_div) { ++ printf("Cannot setup SSP unit clock to %u Hz, base clock is only %u Hz\n", nc, ssp_div); ++ ssp_div = 1U; ++ } else { ++ ssp_div += nc - 1U; ++ ssp_div /= nc; ++ if (ssp_div > CLKCTRL_SSP_DIV_MASK) ++ ssp_div = CLKCTRL_SSP_DIV_MASK; ++ } ++ ++ /* Set new divider value */ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & ~CLKCTRL_SSP_DIV_MASK; ++ writel(reg | SET_SSP_DIV(ssp_div), IMX_CCM_BASE + HW_CLKCTRL_SSP); ++ ++ /* Wait until new divider value is set */ ++ while (readl(IMX_CCM_BASE + HW_CLKCTRL_SSP) & CLKCTRL_SSP_BUSY) ++ ; ++ ++ if (high) ++ /* switch to ioclock */ ++ writel(CLKCTRL_CLKSEQ_BYPASS_SSP, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 8); ++ else ++ /* switch to 24 MHz crystal */ ++ writel(CLKCTRL_CLKSEQ_BYPASS_SSP, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 4); ++ ++ return imx_get_sspclk(index); ++} ++ ++void imx_dump_clocks(void) ++{ ++ printf("mpll: %10u kHz\n", imx_get_mpllclk()); ++ printf("arm: %10u kHz\n", imx_get_armclk()); ++ printf("ioclk: %10u kHz\n", imx_get_ioclk()); ++ printf("emiclk: %10u kHz\n", imx_get_emiclk()); ++ printf("hclk: %10u kHz\n", imx_get_hclk()); ++ printf("xclk: %10u kHz\n", imx_get_xclk()); ++ printf("ssp: %10u kHz\n", imx_get_sspclk(0)); ++} +diff --git a/arch/blackfin/lib/cpu.c b/arch/blackfin/lib/cpu.c +index f96d22d..aed0864 100644 +--- a/arch/blackfin/lib/cpu.c ++++ b/arch/blackfin/lib/cpu.c +@@ -32,7 +32,7 @@ + #include <asm/cpu.h> + #include <init.h> + +-void __noreturn reset_cpu(ulong ignored) ++void __noreturn reset_cpu(unsigned long addr) + { + icache_disable(); + +diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig +deleted file mode 100644 +index c9608da..0000000 +--- a/arch/m68k/Kconfig ++++ /dev/null +@@ -1,182 +0,0 @@ +-# +-# Default location of link barebox Image on M68k/Coldfire +-# +-config ARCH_TEXT_BASE +- hex +- default 0x07f00000 if MACH_MCF54xx +- default 0x07f00000 if MACH_MCF5445x +- help +- Vector table for M68k and barebox Link Address +- +- On M68k/Coldfire cores all exceptions and interrupts are routed through +- a vector array. This vector is by default at address 0x0000_0000, but +- can be moved to any other 1MB aligned address. +- +- We take advantage of this to move barebox out of low memory. Some BDM +- debuggers won't like a moved vector base and might need tweaking to +- work. +- +- Note: Respect alignment restrictions for TEXT_BASE, which must be +- 1MB aligned (VBR register constrain). +- +-# +-# Internal configurations +-# +-config BOARDINFO +- default "konzeptpark UKD Prototype with Phycore MCF5485" if MACH_KPUKDR1 +- default "konzeptpark UKD Prototype with Phycore MCF5475 NUM" if MACH_KPUKDR1_NUM +- default "konzeptpark UKD Revision 2 with Phycore MCF5485" if MACH_KPUKDR2 +- default "konzeptpark UKD Revision 2 with Phycore MCF5475 NUM" if MACH_KPUKDR2_NUM +- default "Phytec Baseboard with Phycore MCF5485" if MACH_PCM982_5485 +- default "Phytec Baseboard with Phycore MCF5475" if MACH_PCM982_5475 +- default "Phytec Baseboard with Phycore MCF5475 NUM" if MACH_PCM982_5475_NUM +- default "Phytec Baseboard with Phycore MCF54455" if MACH_PCM982_54455 +- default "!No boardinfo string set!" +- +-config HAS_EARLY_INIT +- bool +- default n +- +-config BOARD_LINKER_SCRIPT +- bool +- default n +- +-config GENERIC_LINKER_SCRIPT +- bool +- default y +- depends on !BOARD_LINKER_SCRIPT +- +-config M68K +- bool +- select HAS_KALLSYMS +- select HAS_MODULES +- default y +- +-config MCFV4E +- bool +- +-config MCFV4M +- bool +- +-config ARCH_MCF54xx +- bool +- select MCFV4E +- +-config ARCH_MCF5445x +- bool +- select MCFV4M +- +-# +-# Board selection +-# +-choice +- prompt "Select your board" +- +-config MACH_KPUKDR1 +- bool "konzeptpark UKD R1 + phyCore MCF5485" +- select HAS_CFI +- select ARCH_MCF54xx +- help +- Say Y here if you are using the konzeptpark UKD R1 with a +- Phytec Phycore PCM-024 equipped with a Freescale MC5485 Processor +- +-config MACH_KPUKDR1_NUM +- bool "konzeptpark UKD R1 + phyCore MCF5475 NUM" +- select HAS_CFI +- select ARCH_MCF54xx +- select MACH_HAS_LOWLEVEL_INIT +- help +- Say Y here if you are using the konzeptpark UKD R1 with a +- Phytec Phycore PCM-024-NUM equipped with a Freescale MC5475 Processor +- +-config MACH_KPUKDR2 +- bool "konzeptpark UKD R2 + phyCore MCF5485" +- select HAS_CFI +- select ARCH_MCF54xx +- help +- Say Y here if you are using the konzeptpark UKD R2 with a +- Phytec Phycore PCM-024 equipped with a Freescale MC5485 Processor +- +-config MACH_KPUKDR2_NUM +- bool "konzeptpark UKD R2 + phyCore MCF5475 NUM" +- select HAS_CFI +- select ARCH_MCF54xx +- help +- Say Y here if you are using the konzeptpark UKD R2 with a +- Phytec Phycore PCM-024-NUM equipped with a Freescale MC5475 Processor +- +-config MACH_PCM982_5485 +- bool "Phytec pcm982 + phyCore MCF5485" +- select HAS_CFI +- select ARCH_MCF54xx +- select MACH_HAS_LOWLEVEL_INIT +- help +- Say Y here if you are using the Phytec Phycore PCM-024 equipped +- with a Freescale MC5485 Processor +- +-config MACH_PCM982_5475 +- bool "Phytec pcm982 + phyCore MCF5475" +- select HAS_CFI +- select ARCH_MCF54xx +- select MACH_HAS_LOWLEVEL_INIT +- help +- Say Y here if you are using the Phytec Phycore PCM-024 equipped +- with a Freescale MC5475 Processor +- +-config MACH_PCM982_5475_NUM +- bool "Phytec pcm982 + phyCore MCF5475 NUM" +- select HAS_CFI +- select ARCH_MCF54xx +- select MACH_HAS_LOWLEVEL_INIT +- help +- Say Y here if you are using the Phytec Phycore PCM-024 equipped +- with a Freescale MC5475 Processor (NUM Variant) +- +-config MACH_PCM982_54455 +- bool "Phytec pcm982 + phyCore MCF54455 (experimental)" +- select HAS_CFI +- select ARCH_MCF5445x +- help +- Say Y here if you are using the Phytec Phycore PCM-mcf54455 equipped +- with a Freescale MC54455 Processor (experimental) +- +-endchoice +- +-# +-# M68k/Coldfire Subarch Configuration +-# +-source arch/m68k/mach-mcfv4e/Kconfig +- +-menu "M68k/Coldfire specific Linux boot settings" +- +-config CMDLINE_TAG +- bool "Send commandline to kernel" +- default y +- help +- If you want to start a 2.6 kernel say y here. +- +-config SETUP_MEMORY_TAGS +- bool "send memory definition to kernel" +- default y +- help +- If you want to start a 2.6 kernel say y here. +- +-config INITRD_TAG +- bool "send initrd params to kernel" +- default n +- help +- If you want to start a 2.6 kernel and use an +- initrd image say y here. +- +-endmenu +- +-# +-# Common barebox options +-# +- +-source common/Kconfig +-source commands/Kconfig +-source net/Kconfig +-source drivers/Kconfig +-source fs/Kconfig +-source lib/Kconfig +diff --git a/arch/m68k/Makefile b/arch/m68k/Makefile +deleted file mode 100644 +index 86afb24..0000000 +--- a/arch/m68k/Makefile ++++ /dev/null +@@ -1,82 +0,0 @@ +-# +-# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +-# See file CREDITS for list of people who contributed to this project. +-# +-# This file is part of barebox. +-# +-# barebox is free software: you can redistribute it and/or modify +-# it under the terms of the GNU General Public License as published by +-# the Free Software Foundation, either version 3 of the License, or +-# (at your option) any later version. +-# +-# barebox is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with barebox. If not, see <http://www.gnu.org/licenses/>. +-# +- +-CPPFLAGS += -isystem $(gccincdir) -fno-strict-aliasing +- +- +-machine-$(CONFIG_ARCH_MCF54xx) := mcfv4e +-board-$(CONFIG_MACH_KPUKDR1) := kp_ukd_r1 +-board-$(CONFIG_MACH_KPUKDR1_NUM) := kp_ukd_r1_num +-board-$(CONFIG_MACH_KPUKDR2) := kp_ukd_r2 +-board-$(CONFIG_MACH_KPUKDR2_NUM) := kp_ukd_r2_num +-board-$(CONFIG_MACH_PCM982_5485) := phycore_mcf54xx +-board-$(CONFIG_MACH_PCM982_5475) := phycore_mcf54xx +-board-$(CONFIG_MACH_PCM982_5475_NUM) := phycore_mcf54xx_num +-board-$(CONFIG_MACH_PCM982_54455) := phycore_mcf5445x +- +-cpu-$(CONFIG_MCFV4E) := mcfv4e +-cpu-$(CONFIG_MCFV4M) := mcfv4m +- +-TEXT_BASE = $(CONFIG_TEXT_BASE) +- +-CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -P +-AFLAGS += -gdwarf-2 -save-temps +-# FIXME - remove overide +-CFLAGS += -msoft-float -mcfv4e -gdwarf-2 -feliminate-unused-debug-types \ +- -fmerge-all-constants +-# Incompatible code in barebox for -std=c99 +-LDFLAGS_barebox :=-L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc +-# --verbose --stats +- +-machdirs := $(patsubst %,arch/m68k/mach-%/,$(machine-y)) +- +-ifeq ($(KBUILD_SRC),) +-CPPFLAGS += $(patsubst %,-I%include,$(machdirs)) +-else +-CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs)) +-endif +- +- +-all: $(KBUILD_IMAGE) +- +-archprepare: maketools +- +-PHONY += maketools +- +- +-ifneq ($(board-y),) +-BOARD := arch/m68k/boards/$(board-y)/ +-else +-BOARD := +-endif +- +-ifneq ($(machine-y),) +-MACH := arch/m68k/mach-$(machine-y)/ +-else +-MACH := +-endif +- +-common-y += $(BOARD) $(MACH) +-common-y += arch/m68k/lib/ arch/m68k/cpu/ +- +-lds-$(CONFIG_GENERIC_LINKER_SCRIPT) := arch/m68k/lib/barebox.lds +-lds-$(CONFIG_BOARD_LINKER_SCRIPT) := $(BOARD)/barebox.lds +- +-CLEAN_FILES += arch/m68k/lib/barebox.lds +diff --git a/arch/m68k/boards/kp_ukd_r1_num/Makefile b/arch/m68k/boards/kp_ukd_r1_num/Makefile +deleted file mode 100644 +index 65f2a02..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/Makefile ++++ /dev/null +@@ -1,31 +0,0 @@ +-# +-# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +-# See file CREDITS for list of people who contributed to this project. +-# +-# This file is part of barebox. +-# +-# barebox is free software: you can redistribute it and/or modify +-# it under the terms of the GNU General Public License as published by +-# the Free Software Foundation, either version 3 of the License, or +-# (at your option) any later version. +-# +-# barebox is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with barebox. If not, see <http://www.gnu.org/licenses/>. +-# +- +-# The build system allows to split everything into distinct files covering an +-# separate issue. Use that! +- +-# Board specific callbacks and initialisations +- +-obj-y += lowlevel_init.o +-obj-y += highlevel_init.o +-obj-y += kp_ukd_r1_num.o +- +-obj-y += pci-stubs.o +- +diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update b/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update +deleted file mode 100644 +index 014bce3..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/_update ++++ /dev/null +@@ -1,36 +0,0 @@ +-#!/bin/sh +- +-if [ -z "$part" -o -z "$image" ]; then +- echo "define \$part and \$image" +- exit 1 +-fi +- +-if [ ! -e "$part" ]; then +- echo "Partition $part does not exist" +- exit 1 +-fi +- +-if [ $# = 1 ]; then +- image=$1 +-fi +- +-if [ x$ip = xdhcp ]; then +- dhcp +-fi +- +-ping $eth0.serverip +-if [ $? -ne 0 ] ; then +- echo "update aborted" +- exit 1 +-fi +- +-unprotect $part +- +-echo +-echo "erasing partition $part" +-erase $part +- +-echo +-echo "flashing $image to $part" +-echo +-tftp $image $part +diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot b/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot +deleted file mode 100644 +index c9fcbac..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/boot ++++ /dev/null +@@ -1,38 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-if [ x$1 = xflash ]; then +- root=flash +- kernel=flash +-fi +- +-if [ x$1 = xnet ]; then +- root=net +- kernel=net +-fi +- +-if [ x$ip = xdhcp ]; then +- bootargs="$bootargs ip=dhcp" +-else +- bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +-fi +- +-if [ x$root = xflash ]; then +- bootargs="$bootargs root=$rootpart rootfstype=jffs2" +-else +- bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot" +-fi +- +-bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" +- +-if [ $kernel = net ]; then +- if [ x$ip = xdhcp ]; then +- dhcp +- fi +- tftp $uimage uImage || exit 1 +- bootm uImage +-else +- bootm /dev/nor0.kernel +-fi +- +diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/init b/arch/m68k/boards/kp_ukd_r1_num/env/bin/init +deleted file mode 100644 +index 48e2139..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/init ++++ /dev/null +@@ -1,20 +0,0 @@ +-#!/bin/sh +- +-PATH=/env/bin +-export PATH +- +-. /env/config +-addpart /dev/nor0 $mtdparts +- +-echo +-echo -n "Hit any key to stop autoboot: " +-timeout -a $autoboot_timeout +-if [ $? != 0 ]; then +- echo +- echo "type update_kernel [<imagename>] to update kernel into flash" +- echo "type udate_root [<imagename>] to update rootfs into flash" +- echo +- exit +-fi +- +-boot +\ No newline at end of file +diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop +deleted file mode 100644 +index 24e76cb..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pcidmaloop ++++ /dev/null +@@ -1,14 +0,0 @@ +-pci stat +-pci stat -c +-while true; do +- pci readm 32 0xA1000000 32 -s +- pci readm 32 0xA2000000 256 -s +- pci dmatx 2000 a2000100 128 -s +- pci writem 32 0xa2000100 0x12345678 4 -s +- pci readm 32 0xA3000000 256 -s +- pci dmatx 2000 a3000040 128 -s +- pci writem 32 0xa3000100 0x12345678 4 -s +- pci readm 32 0xA4000000 16 -s +- pci dmatx 2000 a4000080 4 -s +- pci writem 32 0xa4000080 0x12345678 4 -s +-done +diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop b/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop +deleted file mode 100644 +index 4a804f9..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/pciloop ++++ /dev/null +@@ -1,13 +0,0 @@ +-pci stat +-pci stat -c +-while true; do +- pci readm 32 0xA1000000 32 -s +- pci readm 32 0xA2000000 256 -s +- pci writem 32 0xa2000100 0x12345678 4 -s +- pci readm 32 0xA3000000 256 -s +- pci writem 32 0xa3000100 0x12345678 4 -s +- pci readm 32 0xA4000000 16 -s +- pci writem 32 0xa4000080 0x12345678 4 -s +- +-# pci dmatx 2000 a3000040 128 -s +-done +diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel +deleted file mode 100644 +index 1ad95fc..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_kernel ++++ /dev/null +@@ -1,8 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-image=$uimage +-part=/dev/nor0.kernel +- +-. /env/bin/_update $1 +diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root b/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root +deleted file mode 100644 +index b757a5b..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/env/bin/update_root ++++ /dev/null +@@ -1,8 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-image=$jffs2 +-part=/dev/nor0.root +- +-. /env/bin/_update $1 +diff --git a/arch/m68k/boards/kp_ukd_r1_num/env/config b/arch/m68k/boards/kp_ukd_r1_num/env/config +deleted file mode 100644 +index 14958ba..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/env/config ++++ /dev/null +@@ -1,32 +0,0 @@ +-#!/bin/sh +- +-# can be either 'net' or 'flash' +-kernel=net +-root=net +- +-# use 'dhcp' todo dhcp in barebox and in kernel +-ip=dhcp +- +-# +-# setup default ethernet address +-# +-eth0.ipaddr=192.168.0.99 +-eth0.netmask=255.255.255.0 +-eth0.gateway=192.168.0.110 +-eth0.serverip=192.168.0.110 +- +-uimage=uImage-mcf5475 +-jffs2=root-mcf5475-ptx.jffs2 +- +-autoboot_timeout=3 +- +-#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs" +-nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3" +-bootargs="console=ttyS0 rw initcall_debug debug" +- +-# +-# setup the partitions in the main flash +-# +-mtdparts=512k(self),256k(env),3M(kernel),-(root) +-rootpart="/dev/mtdblock3" +- +diff --git a/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c b/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c +deleted file mode 100644 +index 3a88cd6..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/highlevel_init.c ++++ /dev/null +@@ -1,124 +0,0 @@ +-/* +- * (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @brief This file contains high-level init functions. +- * +- */ +-#include <common.h> +-#include <reloc.h> +-#include <config.h> +-#include <mach/mcf54xx-regs.h> +- +-static void board_gpio_init(void) +-{ +- /* +- * Enable Ethernet signals so that, if a cable is plugged into +- * the ports, the lines won't be floating and potentially cause +- * erroneous transmissions +- */ +- MCF_GPIO_PAR_FECI2CIRQ = 0 +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; +-} +- +- +-static void board_psc_init(void) +-{ +-#if (CFG_EARLY_UART_PORT == 0) +- MCF_GPIO_PAR_PSC0 = (0 +-#ifdef HARDWARE_FLOW_CONTROL +- | MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS +- | MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS +-#endif +- | MCF_GPIO_PAR_PSC0_PAR_TXD0 +- | MCF_GPIO_PAR_PSC0_PAR_RXD0); +-#elif (CFG_EARLY_UART_PORT == 1) +- MCF_GPIO_PAR_PSC1 = (0 +-#ifdef HARDWARE_FLOW_CONTROL +- | MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS +- | MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS +-#endif +- | MCF_GPIO_PAR_PSC1_PAR_TXD1 +- | MCF_GPIO_PAR_PSC1_PAR_RXD1); +-#elif (CFG_EARLY_UART_PORT == 2) +- MCF_GPIO_PAR_PSC2 = (0 +-#ifdef HARDWARE_FLOW_CONTROL +- | MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS +- | MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS +-#endif +- | MCF_GPIO_PAR_PSC2_PAR_TXD2 +- | MCF_GPIO_PAR_PSC2_PAR_RXD2); +-#elif (CFG_EARLY_UART_PORT == 3) +- MCF_GPIO_PAR_PSC3 = (0 +-#ifdef HARDWARE_FLOW_CONTROL +- | MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS +- | MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS +-#endif +- | MCF_GPIO_PAR_PSC3_PAR_TXD3 +- | MCF_GPIO_PAR_PSC3_PAR_RXD3); +-#else +-#error "Invalid CFG_EARLY_UART_PORT setting" +-#endif +- +- /* Put PSC in UART mode */ +- MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART; +- +- /* Call generic UART initialization */ +-// mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud()); +-} +- +- +-/** Do board specific early init +- * +- * @note We run at link address now, you can now call other code +- */ +-void board_init_highlevel(void) +-{ +- /* Initialize platform specific GPIOs */ +- board_gpio_init(); +- +- /* Init UART GPIOs and Modes */ +- board_psc_init(); +- +- /* Setup the early init data */ +-#ifdef CONFIG_HAS_EARLY_INIT +- early_init(); +-#endif +- /* Configure the early debug output facility */ +-#ifdef CONFIG_DEBUG_LL +- early_debug_init(); +-#endif +-} +- +-/** Provide address of early debug low-level output +- * +- * @todo Should return real address for UART register map. +- */ +-void *get_early_console_base(const char *name) +-{ +- return (void*)1 + CFG_EARLY_UART_PORT; +-} +diff --git a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c +deleted file mode 100644 +index 7475ab3..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.c ++++ /dev/null +@@ -1,160 +0,0 @@ +-/* +- * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +- +-#include <common.h> +-#include <init.h> +-#include <driver.h> +-#include <fec.h> +-#include <environment.h> +-#include <mach/mcf54xx-regs.h> +-//#include <mach/gpio.h> +-#include <mach/clocks.h> +-#include <asm/io.h> +-#include <partition.h> +- +-/* +- * Return board clock in MHz FIXME move to clocks file +- */ +-ulong mcfv4e_get_bus_clk(void) +-{ +- return CFG_SYSTEM_CORE_CLOCK; +-} +-/* +- * Up to 64MiB NOR type flash, connected to +- * CS line 0, data width is 32 bit +- */ +-static struct device_d cfi_dev = { +- .id = -1, +- .name = "cfi_flash", +- .map_base = CFG_FLASH_ADDRESS, +- .size = CFG_FLASH_SIZE, +-}; +- +-/* +- * up to 2MiB static RAM type memory, connected +- * to CS4, data width is 16 bit +- */ +-//static struct device_d sram_dev = { +-// .id = -1, +-// .name = "sram", +-//FIXME .map_base = IMX_CS4_BASE, +-//FIXME .size = IMX_CS4_RANGE, /* area size */ +-//}; +- +-/* +- * ?MiB NAND type flash, data width 8 bit +- */ +-//static struct device_d nand_dev = { +-// .id = -1, +-// .name = "cfi_flash_nand", +-// .map_base = 0xfc000000, /* FIXME */ +-// .size = 32 * 1024 * 1024, /* FIXME */ +-//}; +- +- +-/* +- * Build in FastEthernetControllers (FECs) +- */ +-static struct fec_platform_data fec_info = { +- .xcv_type = MII100, +-}; +- +-static struct device_d network_dev0 = { +- .id = -1, +- .name = "fec_mcf54xx", +- .map_base = MCF_FEC_ADDR(0), +- .size = MCF_FEC_SIZE(0), /* area size */ +- .platform_data = &fec_info, +-}; +-static struct device_d network_dev1 = { +- .id = -1, +- .name = "fec_mcf54xx", +- .map_base = MCF_FEC_ADDR(1), +- .size = MCF_FEC_SIZE(1), /* area size */ +- .platform_data = &fec_info, +-}; +- +-/* +- * 128MiB of SDRAM, data width is 32 bit +- */ +-static struct memory_platform_data ram_pdata = { +- .name = "ram0", +- .flags = DEVFS_RDWR, +-}; +- +-static struct device_d sdram_dev = { +- .id = -1, +- .name = "mem", +- .map_base = CFG_SDRAM_ADDRESS, +- .size = CFG_SDRAM_SIZE, +- .platform_data = &ram_pdata, +-}; +- +-static int mcfv4e_devices_init(void) +-{ +- printf("Setting up board devices...\n"); +- +- /* setup pins for I2C2 (for EEPROM, RTC) */ +-//FIXME imx_gpio_mode(MUX_CSPI2_MOSI_I2C2_SCL); +-//FIXME imx_gpio_mode(MUX_CSPI2_MISO_I2C2_SCL); +- +- register_device(&cfi_dev); +- +- /* +- * Create partitions that should be +- * not touched by any regular user +- */ +- devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0"); /* ourself */ +- devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0"); /* environment */ +- protect_file("/dev/env0", 1); +- +- //register_device(&sram_dev); +- //register_device(&nand_dev); +- +- register_device(&network_dev0); +- //register_device(&network_dev1); +- +- register_device(&sdram_dev); +- +- return 0; +-} +- +-device_initcall(mcfv4e_devices_init); +- +-static struct device_d mcfv4e_serial_device = { +- .id = -1, +- .name = "mcfv4e_serial", +- .map_base = 1+CFG_EARLY_UART_PORT, +- .size = 16 * 1024, +-}; +- +-static int mcfv4e_console_init(void) +-{ +- /* init gpios for serial port */ +- +- /* Already set in lowlevel_init.c */ +- +- register_device(&mcfv4e_serial_device); +- return 0; +-} +- +-console_initcall(mcfv4e_console_init); +- +diff --git a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox b/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox +deleted file mode 100644 +index ca0fcbc..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/kp_ukd_r1_num.dox ++++ /dev/null +@@ -1,13 +0,0 @@ +-/** @page kp_ukd_r1 konzeptpark MCB2 Prototype Board +- +-This target is based on a PhyTec PhyCore MCF54x5 NUM CPU. The card is shipped with: +- +-- up to 64MiB NOR type Flash Memory +-- 128MiB synchronous dynamic RAM +-- PCI USB 2.0 Host +-- PCCard Controller +-- MiniPCI Parallel +-- MiniPCIe (USB lane only) +-- ... +- +-*/ +diff --git a/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c b/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c +deleted file mode 100644 +index b3de505..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/lowlevel_init.c ++++ /dev/null +@@ -1,183 +0,0 @@ +-/* +- * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @brief This file contains ... +- * +- */ +-#include <common.h> +-#include <config.h> +-#include <mach/mcf54xx-regs.h> +- +-/** Initialize board specific very early inits +- * +- * @note This code is not allowed to call other code - just init +- * your Chipselects and SDRAM stuff here! +- */ +-void board_init_lowlevel(void) +-{ +- /* +- * The phyCORE-MCF548x has a 32MB or 64MB boot flash. +- * The is a CF Card and ControlRegs on CS1 and CS2 +- */ +- +- /* Setup SysGlue Chip-Select */ +- MCF_FBCS_CSAR5 = MCF_FBCS_CSAR_BA(CFG_SYSGLUE_ADDRESS); +- +- MCF_FBCS_CSCR5 = (MCF_FBCS_CSCR_PS_32 +- | MCF_FBCS_CSCR_AA +- | MCF_FBCS_CSCR_ASET(1) +- | MCF_FBCS_CSCR_WS(CFG_SYSGLUE_WAIT_STATES)); +- +- MCF_FBCS_CSMR5 = (MCF_FBCS_CSMR_BAM_16M +- | MCF_FBCS_CSMR_V); +- +- /* Setup boot flash chip-select */ +- MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS); +- +- MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32 +- | MCF_FBCS_CSCR_AA +- | MCF_FBCS_CSCR_ASET(1) +- | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES)); +- +- MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M +- | MCF_FBCS_CSMR_V); +- +- /* +- * Check to see if the SDRAM has already been initialized +- * by a run control tool +- */ +- if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) +- { +- /* +- * Basic configuration and initialization +- */ +- // 0x000002AA +- MCF_SDRAMC_SDRAMDS = (0 +- | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- ); +- +- // 0x0000001A +- MCF_SDRAMC_CS0CFG = (0 +- | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS) +- | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE) +- ); +- +- MCF_SDRAMC_CS1CFG = 0; +- MCF_SDRAMC_CS2CFG = 0; +- MCF_SDRAMC_CS3CFG = 0; +- +- // 0x73611730 +- MCF_SDRAMC_SDCFG1 = (0 +- | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5)) +- | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1)) +- | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2)) +- | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) +- | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) +- | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) +- | MCF_SDRAMC_SDCFG1_WTLAT(3) +- ); +- +- // 0x46770000 +- MCF_SDRAMC_SDCFG2 = (0 +- | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2) +- | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR) +- | MCF_SDRAMC_SDCFG2_BRD2WT(7) +- | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1) +- ); +- +- /* +- * Precharge and enable write to SDMR +- */ +- // 0xE10B0002 +- MCF_SDRAMC_SDCR = (0 +- | MCF_SDRAMC_SDCR_MODE_EN +- | MCF_SDRAMC_SDCR_CKE +- | MCF_SDRAMC_SDCR_DDR +- | MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1 +- | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5)) +- | MCF_SDRAMC_SDCR_IPALL +- ); +- +- /* +- * Write extended mode register +- */ +- // 0x40010000 +- MCF_SDRAMC_SDMR = (0 +- | MCF_SDRAMC_SDMR_BNKAD_LEMR +- | MCF_SDRAMC_SDMR_AD(0x0) +- | MCF_SDRAMC_SDMR_CMD +- ); +- +- /* +- * Write mode register and reset DLL +- */ +- // 0x048d0000 +- MCF_SDRAMC_SDMR = (0 +- | MCF_SDRAMC_SDMR_BNKAD_LMR +- | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD) +- | MCF_SDRAMC_SDMR_CMD +- ); +- +- /* +- * Execute a PALL command +- */ +- // 0xE10B0002 +- MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; +- +- /* +- * Perform two REF cycles +- */ +- // 0xE10B0004 +- MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; +- MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; +- +- /* +- * Write mode register and clear reset DLL +- */ +- // 0x008D0000 +- MCF_SDRAMC_SDMR = (0 +- | MCF_SDRAMC_SDMR_BNKAD_LMR +- | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD) +- | MCF_SDRAMC_SDMR_CMD +- ); +- +- /* +- * Enable auto refresh and lock SDMR +- */ +- // 0x610B0000 +- MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; +- +- // 0x710B0F00 +- MCF_SDRAMC_SDCR |= (0 +- | MCF_SDRAMC_SDCR_REF +- | MCF_SDRAMC_SDCR_DQS_OE(0xF) +- ); +- } +-} +- +-/** @file +- * +- * Target specific early chipselect and SDRAM init. +- */ +diff --git a/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c b/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c +deleted file mode 100644 +index b7ab7c7..0000000 +--- a/arch/m68k/boards/kp_ukd_r1_num/pci-stubs.c ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * (C) 2007,2008 Carsten Schlote <schlote@vahanus.net> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @brief This file contains callbacks for the PCI subsystem +- * +- */ +-#include <common.h> +-#include <config.h> +- +- +-/** Returns mapping from PCI slot to CPU irq for the target board +- * @return Coldfire IRQ vector number, or -1 for no irq +- */ +-int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin) +-{ +- int rc = -1; +- switch (slot) +- { +- case 16 : break; +- case 17 ... 21 : rc = 64 + 7; break; // Eport IRQ7 +- } +- return rc; +-} +diff --git a/arch/m68k/boards/phycore_mcf54xx/Makefile b/arch/m68k/boards/phycore_mcf54xx/Makefile +deleted file mode 100644 +index 054123f..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/Makefile ++++ /dev/null +@@ -1,31 +0,0 @@ +-# +-# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +-# See file CREDITS for list of people who contributed to this project. +-# +-# This file is part of barebox. +-# +-# barebox is free software: you can redistribute it and/or modify +-# it under the terms of the GNU General Public License as published by +-# the Free Software Foundation, either version 3 of the License, or +-# (at your option) any later version. +-# +-# barebox is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with barebox. If not, see <http://www.gnu.org/licenses/>. +-# +- +-# The build system allows to split everything into distinct files covering an +-# separate issue. Use that! +- +-# Board specific callbacks and initialisations +- +-obj-y += lowlevel_init.o +-obj-y += highlevel_init.o +-obj-y += phyCore_MCF54xx.o +- +-obj-y += pci-stubs.o +- +diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/_update b/arch/m68k/boards/phycore_mcf54xx/env/bin/_update +deleted file mode 100644 +index 014bce3..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/env/bin/_update ++++ /dev/null +@@ -1,36 +0,0 @@ +-#!/bin/sh +- +-if [ -z "$part" -o -z "$image" ]; then +- echo "define \$part and \$image" +- exit 1 +-fi +- +-if [ ! -e "$part" ]; then +- echo "Partition $part does not exist" +- exit 1 +-fi +- +-if [ $# = 1 ]; then +- image=$1 +-fi +- +-if [ x$ip = xdhcp ]; then +- dhcp +-fi +- +-ping $eth0.serverip +-if [ $? -ne 0 ] ; then +- echo "update aborted" +- exit 1 +-fi +- +-unprotect $part +- +-echo +-echo "erasing partition $part" +-erase $part +- +-echo +-echo "flashing $image to $part" +-echo +-tftp $image $part +diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/boot b/arch/m68k/boards/phycore_mcf54xx/env/bin/boot +deleted file mode 100644 +index c9fcbac..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/env/bin/boot ++++ /dev/null +@@ -1,38 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-if [ x$1 = xflash ]; then +- root=flash +- kernel=flash +-fi +- +-if [ x$1 = xnet ]; then +- root=net +- kernel=net +-fi +- +-if [ x$ip = xdhcp ]; then +- bootargs="$bootargs ip=dhcp" +-else +- bootargs="$bootargs ip=$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:::" +-fi +- +-if [ x$root = xflash ]; then +- bootargs="$bootargs root=$rootpart rootfstype=jffs2" +-else +- bootargs="$bootargs root=/dev/nfs nfsroot=$eth0.serverip:$nfsroot" +-fi +- +-bootargs="$bootargs mtdparts=physmap-flash.0:$mtdparts" +- +-if [ $kernel = net ]; then +- if [ x$ip = xdhcp ]; then +- dhcp +- fi +- tftp $uimage uImage || exit 1 +- bootm uImage +-else +- bootm /dev/nor0.kernel +-fi +- +diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/init b/arch/m68k/boards/phycore_mcf54xx/env/bin/init +deleted file mode 100644 +index 48e2139..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/env/bin/init ++++ /dev/null +@@ -1,20 +0,0 @@ +-#!/bin/sh +- +-PATH=/env/bin +-export PATH +- +-. /env/config +-addpart /dev/nor0 $mtdparts +- +-echo +-echo -n "Hit any key to stop autoboot: " +-timeout -a $autoboot_timeout +-if [ $? != 0 ]; then +- echo +- echo "type update_kernel [<imagename>] to update kernel into flash" +- echo "type udate_root [<imagename>] to update rootfs into flash" +- echo +- exit +-fi +- +-boot +\ No newline at end of file +diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop b/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop +deleted file mode 100644 +index 24e76cb..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/env/bin/pcidmaloop ++++ /dev/null +@@ -1,14 +0,0 @@ +-pci stat +-pci stat -c +-while true; do +- pci readm 32 0xA1000000 32 -s +- pci readm 32 0xA2000000 256 -s +- pci dmatx 2000 a2000100 128 -s +- pci writem 32 0xa2000100 0x12345678 4 -s +- pci readm 32 0xA3000000 256 -s +- pci dmatx 2000 a3000040 128 -s +- pci writem 32 0xa3000100 0x12345678 4 -s +- pci readm 32 0xA4000000 16 -s +- pci dmatx 2000 a4000080 4 -s +- pci writem 32 0xa4000080 0x12345678 4 -s +-done +diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop b/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop +deleted file mode 100644 +index 4a804f9..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/env/bin/pciloop ++++ /dev/null +@@ -1,13 +0,0 @@ +-pci stat +-pci stat -c +-while true; do +- pci readm 32 0xA1000000 32 -s +- pci readm 32 0xA2000000 256 -s +- pci writem 32 0xa2000100 0x12345678 4 -s +- pci readm 32 0xA3000000 256 -s +- pci writem 32 0xa3000100 0x12345678 4 -s +- pci readm 32 0xA4000000 16 -s +- pci writem 32 0xa4000080 0x12345678 4 -s +- +-# pci dmatx 2000 a3000040 128 -s +-done +diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel +deleted file mode 100644 +index 1ad95fc..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_kernel ++++ /dev/null +@@ -1,8 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-image=$uimage +-part=/dev/nor0.kernel +- +-. /env/bin/_update $1 +diff --git a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root b/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root +deleted file mode 100644 +index b757a5b..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/env/bin/update_root ++++ /dev/null +@@ -1,8 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-image=$jffs2 +-part=/dev/nor0.root +- +-. /env/bin/_update $1 +diff --git a/arch/m68k/boards/phycore_mcf54xx/env/config b/arch/m68k/boards/phycore_mcf54xx/env/config +deleted file mode 100644 +index 5855062..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/env/config ++++ /dev/null +@@ -1,32 +0,0 @@ +-#!/bin/sh +- +-# can be either 'net' or 'flash' +-kernel=net +-root=net +- +-# use 'dhcp' todo dhcp in barebox and in kernel +-ip=dhcp +- +-# +-# setup default ethernet address +-# +-eth0.ipaddr=192.168.0.99 +-eth0.netmask=255.255.255.0 +-eth0.gateway=192.168.0.110 +-eth0.serverip=192.168.0.110 +- +-uimage=uImage-mcf5485 +-jffs2=root-mcf5485-ptx.jffs2 +- +-autoboot_timeout=3 +- +-#nfsroot="/home/cschlote/src/bitshrine/ltib/rootfs" +-nfsroot="/home/cschlote/src/pengutronics/ptxdist-project-KP-UKD/root-debug,v3" +-bootargs="console=ttyS0 rw initcall_debug debug" +- +-# +-# setup the partitions in the main flash +-# +-mtdparts=512k(self),256k(env),3M(kernel),-(root) +-rootpart="/dev/mtdblock3" +- +diff --git a/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c b/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c +deleted file mode 100644 +index 3a88cd6..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/highlevel_init.c ++++ /dev/null +@@ -1,124 +0,0 @@ +-/* +- * (C) 2007,2008 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @brief This file contains high-level init functions. +- * +- */ +-#include <common.h> +-#include <reloc.h> +-#include <config.h> +-#include <mach/mcf54xx-regs.h> +- +-static void board_gpio_init(void) +-{ +- /* +- * Enable Ethernet signals so that, if a cable is plugged into +- * the ports, the lines won't be floating and potentially cause +- * erroneous transmissions +- */ +- MCF_GPIO_PAR_FECI2CIRQ = 0 +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; +-} +- +- +-static void board_psc_init(void) +-{ +-#if (CFG_EARLY_UART_PORT == 0) +- MCF_GPIO_PAR_PSC0 = (0 +-#ifdef HARDWARE_FLOW_CONTROL +- | MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS +- | MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS +-#endif +- | MCF_GPIO_PAR_PSC0_PAR_TXD0 +- | MCF_GPIO_PAR_PSC0_PAR_RXD0); +-#elif (CFG_EARLY_UART_PORT == 1) +- MCF_GPIO_PAR_PSC1 = (0 +-#ifdef HARDWARE_FLOW_CONTROL +- | MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS +- | MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS +-#endif +- | MCF_GPIO_PAR_PSC1_PAR_TXD1 +- | MCF_GPIO_PAR_PSC1_PAR_RXD1); +-#elif (CFG_EARLY_UART_PORT == 2) +- MCF_GPIO_PAR_PSC2 = (0 +-#ifdef HARDWARE_FLOW_CONTROL +- | MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS +- | MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS +-#endif +- | MCF_GPIO_PAR_PSC2_PAR_TXD2 +- | MCF_GPIO_PAR_PSC2_PAR_RXD2); +-#elif (CFG_EARLY_UART_PORT == 3) +- MCF_GPIO_PAR_PSC3 = (0 +-#ifdef HARDWARE_FLOW_CONTROL +- | MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS +- | MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS +-#endif +- | MCF_GPIO_PAR_PSC3_PAR_TXD3 +- | MCF_GPIO_PAR_PSC3_PAR_RXD3); +-#else +-#error "Invalid CFG_EARLY_UART_PORT setting" +-#endif +- +- /* Put PSC in UART mode */ +- MCF_PSC_SICR(CFG_EARLY_UART_PORT) = MCF_PSC_SICR_SIM_UART; +- +- /* Call generic UART initialization */ +-// mcf5xxx_uart_init(DBUG_UART_PORT, board_get_baud()); +-} +- +- +-/** Do board specific early init +- * +- * @note We run at link address now, you can now call other code +- */ +-void board_init_highlevel(void) +-{ +- /* Initialize platform specific GPIOs */ +- board_gpio_init(); +- +- /* Init UART GPIOs and Modes */ +- board_psc_init(); +- +- /* Setup the early init data */ +-#ifdef CONFIG_HAS_EARLY_INIT +- early_init(); +-#endif +- /* Configure the early debug output facility */ +-#ifdef CONFIG_DEBUG_LL +- early_debug_init(); +-#endif +-} +- +-/** Provide address of early debug low-level output +- * +- * @todo Should return real address for UART register map. +- */ +-void *get_early_console_base(const char *name) +-{ +- return (void*)1 + CFG_EARLY_UART_PORT; +-} +diff --git a/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c b/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c +deleted file mode 100644 +index 2837e3e..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/lowlevel_init.c ++++ /dev/null +@@ -1,194 +0,0 @@ +-/* +- * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @brief This file contains ... +- * +- */ +-#include <common.h> +-#include <config.h> +-#include <mach/mcf54xx-regs.h> +- +-/** Initialize board specific very early inits +- * +- * @note This code is not allowed to call other code - just init +- * your Chipselects and SDRAM stuff here! +- */ +-void board_init_lowlevel(void) +-{ +- /* +- * The phyCORE-MCF548x has a 32MB or 64MB boot flash. +- * The is a CF Card and ControlRegs on CS1 and CS2 +- */ +- +- /* Setup SysGlue Chip-Select for user IOs */ +- MCF_FBCS_CSAR2 = MCF_FBCS_CSAR_BA(CFG_XPLD_ADDRESS); +- +- MCF_FBCS_CSCR2 = (MCF_FBCS_CSCR_PS_16 +- | MCF_FBCS_CSCR_AA +- | MCF_FBCS_CSCR_ASET(1) +- | MCF_FBCS_CSCR_WS(CFG_XPLD_WAIT_STATES)); +- +- MCF_FBCS_CSMR2 = (MCF_FBCS_CSMR_BAM_16M +- | MCF_FBCS_CSMR_V); +- +- /* Setup SysGlue Chip-Select for CFCARD */ +- MCF_FBCS_CSAR1 = MCF_FBCS_CSAR_BA(CFG_CFCARD_ADDRESS); +- +- MCF_FBCS_CSCR1 = (MCF_FBCS_CSCR_PS_16 +- | MCF_FBCS_CSCR_AA +- | MCF_FBCS_CSCR_ASET(1) +- | MCF_FBCS_CSCR_WS(CFG_CFCARD_WAIT_STATES)); +- +- MCF_FBCS_CSMR1 = (MCF_FBCS_CSMR_BAM_16M +- | MCF_FBCS_CSMR_V); +- +- /* Setup boot flash chip-select */ +- MCF_FBCS_CSAR0 = MCF_FBCS_CSAR_BA(CFG_FLASH_ADDRESS); +- +- MCF_FBCS_CSCR0 = (MCF_FBCS_CSCR_PS_32 +- | MCF_FBCS_CSCR_AA +- | MCF_FBCS_CSCR_ASET(1) +- | MCF_FBCS_CSCR_WS(CFG_FLASH_WAIT_STATES)); +- +- MCF_FBCS_CSMR0 = (MCF_FBCS_CSMR_BAM_32M +- | MCF_FBCS_CSMR_V); +- +- /* +- * Check to see if the SDRAM has already been initialized +- * by a run control tool +- */ +- if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)) +- { +- /* +- * Basic configuration and initialization +- */ +- // 0x000002AA +- MCF_SDRAMC_SDRAMDS = (0 +- | MCF_SDRAMC_SDRAMDS_SB_E(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- | MCF_SDRAMC_SDRAMDS_SB_C(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- | MCF_SDRAMC_SDRAMDS_SB_A(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- | MCF_SDRAMC_SDRAMDS_SB_S(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- | MCF_SDRAMC_SDRAMDS_SB_D(MCF_SDRAMC_SDRAMDS_DRIVE_8MA) +- ); +- +- // 0x0000001A +- MCF_SDRAMC_CS0CFG = (0 +- | MCF_SDRAMC_CSnCFG_CSBA(CFG_SDRAM_ADDRESS) +- | MCF_SDRAMC_CSnCFG_CSSZ(MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE) +- ); +- +- MCF_SDRAMC_CS1CFG = 0; +- MCF_SDRAMC_CS2CFG = 0; +- MCF_SDRAMC_CS3CFG = 0; +- +- // 0x73611730 +- MCF_SDRAMC_SDCFG1 = (0 +- | MCF_SDRAMC_SDCFG1_SRD2RW((unsigned int)((CFG_SDRAM_CASL + CFG_SDRAM_BL / 2 + 1) + 0.5)) +- | MCF_SDRAMC_SDCFG1_SWT2RD((unsigned int) (CFG_SDRAM_TWR + 1)) +- | MCF_SDRAMC_SDCFG1_RDLAT((unsigned int)((CFG_SDRAM_CASL * 2) + 2)) +- | MCF_SDRAMC_SDCFG1_ACT2RW((unsigned int)(((CFG_SDRAM_TRCD / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) +- | MCF_SDRAMC_SDCFG1_PRE2ACT((unsigned int)(((CFG_SDRAM_TRP / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) +- | MCF_SDRAMC_SDCFG1_REF2ACT((unsigned int)(((CFG_SDRAM_TRFC / CFG_SYSTEM_CORE_PERIOD) - 1) + 0.5)) +- | MCF_SDRAMC_SDCFG1_WTLAT(3) +- ); +- +- // 0x46770000 +- MCF_SDRAMC_SDCFG2 = (0 +- | MCF_SDRAMC_SDCFG2_BRD2PRE(CFG_SDRAM_BL / 2) +- | MCF_SDRAMC_SDCFG2_BWT2RW(CFG_SDRAM_BL / 2 + CFG_SDRAM_TWR) +- | MCF_SDRAMC_SDCFG2_BRD2WT(7) +- | MCF_SDRAMC_SDCFG2_BL(CFG_SDRAM_BL - 1) +- ); +- +- /* +- * Precharge and enable write to SDMR +- */ +- // 0xE10B0002 +- MCF_SDRAMC_SDCR = (0 +- | MCF_SDRAMC_SDCR_MODE_EN +- | MCF_SDRAMC_SDCR_CKE +- | MCF_SDRAMC_SDCR_DDR +- | MCF_SDRAMC_SDCR_MUX(1) // 13 x 10 x 2 ==> MUX=1 +- | MCF_SDRAMC_SDCR_RCNT((int)(((CFG_SDRAM_TREFI / (CFG_SYSTEM_CORE_PERIOD * 64)) - 1) + 0.5)) +- | MCF_SDRAMC_SDCR_IPALL +- ); +- +- /* +- * Write extended mode register +- */ +- // 0x40010000 +- MCF_SDRAMC_SDMR = (0 +- | MCF_SDRAMC_SDMR_BNKAD_LEMR +- | MCF_SDRAMC_SDMR_AD(0x0) +- | MCF_SDRAMC_SDMR_CMD +- ); +- +- /* +- * Write mode register and reset DLL +- */ +- // 0x048d0000 +- MCF_SDRAMC_SDMR = (0 +- | MCF_SDRAMC_SDMR_BNKAD_LMR +- | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_RESET_DLL | CFG_SDRAM_MOD) +- | MCF_SDRAMC_SDMR_CMD +- ); +- +- /* +- * Execute a PALL command +- */ +- // 0xE10B0002 +- MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL; +- +- /* +- * Perform two REF cycles +- */ +- // 0xE10B0004 +- MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; +- MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF; +- +- /* +- * Write mode register and clear reset DLL +- */ +- // 0x008D0000 +- MCF_SDRAMC_SDMR = (0 +- | MCF_SDRAMC_SDMR_BNKAD_LMR +- | MCF_SDRAMC_SDMR_AD(CFG_SDRAM_MOD) +- | MCF_SDRAMC_SDMR_CMD +- ); +- +- /* +- * Enable auto refresh and lock SDMR +- */ +- // 0x610B0000 +- MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_MODE_EN; +- +- // 0x710B0F00 +- MCF_SDRAMC_SDCR |= (0 +- | MCF_SDRAMC_SDCR_REF +- | MCF_SDRAMC_SDCR_DQS_OE(0xF) +- ); +- } +-} +- +-/** @file +- * +- * Target specific early chipselect and SDRAM init. +- */ +\ No newline at end of file +diff --git a/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c b/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c +deleted file mode 100644 +index b7ab7c7..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/pci-stubs.c ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * (C) 2007,2008 Carsten Schlote <schlote@vahanus.net> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @brief This file contains callbacks for the PCI subsystem +- * +- */ +-#include <common.h> +-#include <config.h> +- +- +-/** Returns mapping from PCI slot to CPU irq for the target board +- * @return Coldfire IRQ vector number, or -1 for no irq +- */ +-int mcfv4e_pci_gethostirq(uint8_t slot, uint8_t irqpin) +-{ +- int rc = -1; +- switch (slot) +- { +- case 16 : break; +- case 17 ... 21 : rc = 64 + 7; break; // Eport IRQ7 +- } +- return rc; +-} +diff --git a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c +deleted file mode 100644 +index 3744950..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.c ++++ /dev/null +@@ -1,139 +0,0 @@ +-/* +- * (C) 2007 konzeptpark, Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @brief This file contains ... +- * +- */ +-#include <common.h> +-#include <init.h> +-#include <driver.h> +-#include <fec.h> +-#include <environment.h> +-#include <mach/mcf54xx-regs.h> +-#include <mach/clocks.h> +-#include <asm/io.h> +-#include <partition.h> +- +-/* +- * Return board clock in MHz FIXME move to clocks file +- */ +-ulong mcfv4e_get_bus_clk(void) +-{ +- return CFG_SYSTEM_CORE_CLOCK; +-} +- +-/* +- * Up to 64MiB NOR type flash, connected to +- * CS line 0, data width is 32 bit +- */ +-static struct device_d cfi_dev = +-{ +- .id = -1, +- .name = "cfi_flash", +- .map_base = CFG_FLASH_ADDRESS, +- .size = CFG_FLASH_SIZE, +-}; +- +-/* +- * Build in FastEthernetControllers (FECs) +- */ +-static struct fec_platform_data fec_info = +-{ +- .xcv_type = MII100, +-}; +- +-static struct device_d network_dev0 = +-{ +- .id = -1, +- .name = "fec_mcf54xx", +- .map_base = MCF_FEC_ADDR(0), +- .size = MCF_FEC_SIZE(0), /* area size */ +- .platform_data = &fec_info, +-}; +-static struct device_d network_dev1 = +-{ +- .id = -1, +- .name = "fec_mcf54xx", +- .map_base = MCF_FEC_ADDR(1), +- .size = MCF_FEC_SIZE(1), /* area size */ +- .platform_data = &fec_info, +-}; +- +-/* +- * 128MiB of SDRAM, data width is 32 bit +- */ +-static struct memory_platform_data ram_pdata = { +- .name = "ram0", +- .flags = DEVFS_RDWR, +-}; +- +-static struct device_d sdram_dev = +-{ +- .id = -1, +- .name = "mem", +- .map_base = CFG_SDRAM_ADDRESS, +- .size = CFG_SDRAM_SIZE, +- .platform_data = &ram_pdata, +-}; +- +-static int mcfv4e_devices_init(void) +-{ +- printf("FIXME - setup board devices...\n"); +- +- register_device(&cfi_dev); +- +- /* +- * Create partitions that should be +- * not touched by any regular user +- */ +- devfs_add_partition("nor0", 0x00000, 0x80000, PARTITION_FIXED, "self0"); /* ourself */ +- devfs_add_partition("nor0", 0x80000, 0x40000, PARTITION_FIXED, "env0"); /* environment */ +- protect_file("/dev/env0", 1); +- +- register_device(&network_dev0); +- //register_device(&network_dev1); +- +- register_device(&sdram_dev); +- +- return 0; +-} +- +-device_initcall(mcfv4e_devices_init); +- +-static struct device_d mcfv4e_serial_device = +-{ +- .id = -1, +- .name = "mcfv4e_serial", +- .map_base = 1 + CFG_EARLY_UART_PORT, +- .size = 16 * 1024, +-}; +- +-static int mcfv4e_console_init(void) +-{ +- /* init gpios for serial port */ +- +- /* Already set in lowlevel_init.c */ +- +- register_device(&mcfv4e_serial_device); +- return 0; +-} +- +-console_initcall(mcfv4e_console_init); +diff --git a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox b/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox +deleted file mode 100644 +index 36dd0ad..0000000 +--- a/arch/m68k/boards/phycore_mcf54xx/phyCore_MCF54xx.dox ++++ /dev/null +@@ -1,14 +0,0 @@ +- +-/** @page phycore_mcf54xx Phytec's phyCORE-MCF54x5 +- +-This target is based on a PhyTec PhyCore MCF54x5 CPU module. The card is shipped with: +- +-- up to 64MiB NOR type Flash Memory +-- 128MiB synchronous dynamic RAM +-- PCI USB 2.0 Host +-- PCCard Controller +-- MiniPCI Parallel +-- MiniPCIe (USB lane only) +-- ... +- +-*/ +diff --git a/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig b/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig +deleted file mode 100644 +index 14c6d78..0000000 +--- a/arch/m68k/configs/phycore_kpukdr1_5475num_defconfig ++++ /dev/null +@@ -1,36 +0,0 @@ +-CONFIG_MACH_KPUKDR1_NUM=y +-CONFIG_INITRD_TAG=y +-CONFIG_BROKEN=y +-CONFIG_EXPERIMENTAL=y +-CONFIG_LONGHELP=y +-CONFIG_CMDLINE_EDITING=y +-CONFIG_AUTO_COMPLETE=y +-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/kp_ukd_r1_num/env/" +-CONFIG_DEBUG_INFO=y +-CONFIG_ENABLE_DEVICE_NOISE=y +-CONFIG_CMD_EDIT=y +-CONFIG_CMD_SLEEP=y +-CONFIG_CMD_SAVEENV=y +-CONFIG_CMD_LOADENV=y +-CONFIG_CMD_EXPORT=y +-CONFIG_CMD_PRINTENV=y +-CONFIG_CMD_READLINE=y +-CONFIG_CMD_MEMINFO=y +-CONFIG_CMD_CRC=y +-CONFIG_CMD_MTEST=y +-CONFIG_CMD_MTEST_ALTERNATIVE=y +-CONFIG_CMD_FLASH=y +-CONFIG_CMD_BOOTM_ZLIB=y +-CONFIG_CMD_BOOTM_BZLIB=y +-CONFIG_CMD_BOOTM_SHOW_TYPE=y +-CONFIG_CMD_RESET=y +-CONFIG_CMD_GO=y +-CONFIG_CMD_TIMEOUT=y +-CONFIG_CMD_PARTITION=y +-CONFIG_NET=y +-CONFIG_NET_DHCP=y +-CONFIG_NET_PING=y +-CONFIG_NET_TFTP=y +-CONFIG_DRIVER_CFI=y +-CONFIG_CFI_BUFFER_WRITE=y +-CONFIG_FS_CRAMFS=y +diff --git a/arch/m68k/configs/phycore_mcf54xx_defconfig b/arch/m68k/configs/phycore_mcf54xx_defconfig +deleted file mode 100644 +index f0d9fc2..0000000 +--- a/arch/m68k/configs/phycore_mcf54xx_defconfig ++++ /dev/null +@@ -1,36 +0,0 @@ +-CONFIG_MACH_PCM982_5485=y +-CONFIG_INITRD_TAG=y +-CONFIG_BROKEN=y +-CONFIG_EXPERIMENTAL=y +-CONFIG_LONGHELP=y +-CONFIG_CMDLINE_EDITING=y +-CONFIG_AUTO_COMPLETE=y +-CONFIG_DEFAULT_ENVIRONMENT_PATH="arch/m68k/boards/phycore_mcf54xx/env" +-CONFIG_DEBUG_INFO=y +-CONFIG_ENABLE_DEVICE_NOISE=y +-CONFIG_CMD_EDIT=y +-CONFIG_CMD_SLEEP=y +-CONFIG_CMD_SAVEENV=y +-CONFIG_CMD_LOADENV=y +-CONFIG_CMD_EXPORT=y +-CONFIG_CMD_PRINTENV=y +-CONFIG_CMD_READLINE=y +-CONFIG_CMD_MEMINFO=y +-CONFIG_CMD_CRC=y +-CONFIG_CMD_MTEST=y +-CONFIG_CMD_MTEST_ALTERNATIVE=y +-CONFIG_CMD_FLASH=y +-CONFIG_CMD_BOOTM_ZLIB=y +-CONFIG_CMD_BOOTM_BZLIB=y +-CONFIG_CMD_BOOTM_SHOW_TYPE=y +-CONFIG_CMD_RESET=y +-CONFIG_CMD_GO=y +-CONFIG_CMD_TIMEOUT=y +-CONFIG_CMD_PARTITION=y +-CONFIG_NET=y +-CONFIG_NET_DHCP=y +-CONFIG_NET_PING=y +-CONFIG_NET_TFTP=y +-CONFIG_DRIVER_CFI=y +-CONFIG_CFI_BUFFER_WRITE=y +-CONFIG_FS_CRAMFS=y +diff --git a/arch/m68k/cpu/Makefile b/arch/m68k/cpu/Makefile +deleted file mode 100644 +index 2e434af..0000000 +--- a/arch/m68k/cpu/Makefile ++++ /dev/null +@@ -1,41 +0,0 @@ +-# +-# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +-# See file CREDITS for list of people who contributed to this project. +-# +-# This file is part of barebox. +-# +-# barebox is free software: you can redistribute it and/or modify +-# it under the terms of the GNU General Public License as published by +-# the Free Software Foundation, either version 3 of the License, or +-# (at your option) any later version. +-# +-# barebox is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with barebox. If not, see <http://www.gnu.org/licenses/>. +-# +- +-obj-y += cpu.o +-obj-y += interrupts.o +- +-# +-# Support code for early IO over BDM wigglers +-# +- +-# obj-y += early_init_support.o +- +-# +-# Support for relocated early initdata +-# +-obj-$(CONFIG_HAS_EARLY_INIT) += early_init_support.o +- +-# +-# Startup codes - try to merge them into single file! +-# +-obj-$(CONFIG_ARCH_MCF54xx) += start-mcfv4e.o +-obj-$(CONFIG_ARCH_MCF5445x) += start-mcfv4m.o +- +-start-mcfv4e.o : start-mcfv4e.s +\ No newline at end of file +diff --git a/arch/m68k/cpu/cpu.c b/arch/m68k/cpu/cpu.c +deleted file mode 100644 +index 9268785..0000000 +--- a/arch/m68k/cpu/cpu.c ++++ /dev/null +@@ -1,185 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * A few helper functions for M6kK/Coldfire +- */ +-#include <common.h> +-#include <command.h> +-#include <init.h> +-#include <proc/processor.h> // FIXME -stup place +-#include <mach/mcf54xx-regs.h> +- +-static uint32_t CACR_shadow = MCF5XXX_CACR_BEC; +- +-/* +- * Reset init value := 0x010C0100 +- * MCF5XXX_CACR_DCINVA +- * MCF5XXX_CACR_BEC +- * MCF5XXX_CACR_BCINVA +- * MCF5XXX_CACR_ICINVA +- */ +- +-/** +- * Enable processor's instruction cache +- */ +-void icache_enable (void) +-{ +- CACR_shadow |= MCF5XXX_CACR_IEC; +- mcf5xxx_wr_cacr( CACR_shadow ); +-} +- +-/** +- * Disable processor's instruction cache +- */ +-void icache_disable (void) +-{ +- CACR_shadow &= ~MCF5XXX_CACR_IEC; +- mcf5xxx_wr_cacr( CACR_shadow ); +-} +- +-/** +- * Detect processor's current instruction cache status +- * @return 0=disabled, 1=enabled +- */ +-int icache_status (void) +-{ +- return (CACR_shadow & MCF5XXX_CACR_IEC)?1:0; +-} +- +-/** +- * Enable processor's data cache +- */ +-void dcache_enable (void) +-{ +- CACR_shadow |= MCF5XXX_CACR_DEC; +- mcf5xxx_wr_cacr( CACR_shadow ); +-} +- +-/** +- * Disable processor's data cache +- */ +-void dcache_disable (void) +-{ +- CACR_shadow &= ~MCF5XXX_CACR_DEC; +- mcf5xxx_wr_cacr( CACR_shadow ); +-} +- +-/** +- * Detect processor's current instruction cache status +- * @return 0=disabled, 1=enabled +- */ +-int dcache_status (void) +-{ +- return (CACR_shadow & MCF5XXX_CACR_DEC)?1:0; +-} +- +-/** +- * Flush CPU caches to memory +- */ +-void cpu_cache_flush(void) +-{ +- uint32_t way, set; +- void *addr; +- +- for ( way=0; way < 4; way++ ) { +- addr = (void*)way; +- for ( set=0; set < 512; set++ ) { +- mcf5xxx_cpushl_bc ( addr ); +- addr += 0x10; +- } +- } +-} +- +-/** +- * Flush CPU caches to memory and disable them. +- */ +-void cpu_cache_disable(void) +-{ +- uint32_t lastipl; +- +- lastipl = asm_set_ipl( 7 ); +- +- cpu_cache_flush(); +- mcf5xxx_wr_acr0( 0 ); +- mcf5xxx_wr_acr1( 0 ); +- mcf5xxx_wr_acr2( 0 ); +- mcf5xxx_wr_acr3( 0 ); +- +- CACR_shadow &= ~MCF5XXX_CACR_IEC; +- CACR_shadow &= ~MCF5XXX_CACR_DEC; +- mcf5xxx_wr_cacr( CACR_shadow | (MCF5XXX_CACR_DCINVA|MCF5XXX_CACR_ICINVA)); +- +- lastipl = asm_set_ipl( lastipl ); +-} +- +-/** +- * Prepare a "clean" CPU for Linux to run +- * @return 0 (always) +- * +- * This function is called by the generic barebox part just before we call +- * Linux. It prepares the processor for Linux. +- */ +-int cleanup_before_linux (void) +-{ +- /* +- * we never enable dcache so we do not need to disable +- * it. Linux can be called with icache enabled, so just +- * do nothing here +- */ +- +- /* flush I/D-cache */ +- cpu_cache_disable(); +- +- /* reenable icache */ +- icache_enable(); +- return (0); +-} +-/** @page m68k_boot_preparation Linux Preparation on M68k/Coldfire +- * +- * For M68K we never enable data cache so we do not need to disable it again. +- * +- * Linux can be called with instruction cache enabled. As this is the +- * default setting we are running in barebox, there's no special preparation +- * required. +- */ +- +- +-/** Early init of Coldfire V4E CPU +- */ +-static int cpu_init (void) +-{ +- /* Enable ICache - branch cache is already on */ +- icache_enable(); +- +- /* +- * setup up stacks if necessary +- * setup other CPU specifics here to prepare +- * handling of exceptions and interrupts +- */ +-#ifdef CONFIG_USE_IRQ +- printf("Prepare CPU interrupts for handlers\n"); +- mcf_interrupts_initialize(); +-#endif +- +- return 0; +-} +- +-core_initcall(cpu_init); +diff --git a/arch/m68k/cpu/cw_console_io.c b/arch/m68k/cpu/cw_console_io.c +deleted file mode 100644 +index 417a1b4..0000000 +--- a/arch/m68k/cpu/cw_console_io.c ++++ /dev/null +@@ -1,116 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Debug output stubs over BDM for Codewarrior +- */ +-#include <common.h> +-#include <command.h> +-#include <console.h> +-#include <reloc.h> +-#include <init.h> +- +-#ifdef CONFIG_HAS_EARLY_INIT +- +- +-#if 0 // FIXME - make a CW debug port serial driver for barebox +- +-/* +- * The result of an I/O command can be any one of the following. +- */ +-typedef enum DSIOResult +-{ +- kDSIONoError = 0x00, +- kDSIOError = 0x01, +- kDSIOEOF = 0x02 +-} DSIOResult; +- +-/* +- * MessageCommandID +- */ +-typedef enum MessageCommandID +-{ +- /* +- * target->host support commands +- */ +- +- kDSWriteFile = 0xD0, /* L2 L3 */ +- kDSReadFile = 0xD1 /* L2 L3 */ +- +-} MessageCommandID; +- +- +-enum DSIOResult TransferData( +- MessageCommandID msg, +- unsigned char *buffer, int size, +- int * txsize +-) +-{ +- enum DSIOResult iores = kDSIOError; +- unsigned long sized2=0; +- +- /* -- Call codewarrior stub -- */ +- __asm__ __volatile__ ( +-" move.l %[cmd],%%d0 \n" +-" move.l #0,%%d1 \n" +-" move.l %[size],%%d2 \n" +-" move.l %[buffer],%%d3 \n" +-" trap #14 \n" +-" move.l %%d1,%[txsize] \n" +-" move.l %%d0,%[res] \n" +- : [res] "=r" (iores), [txsize] "=g" (sized2) +- : [cmd] "g" (msg), [size] "g" (size), [buffer] "g" (buffer) +- : "d2","d3" ); +- +- if (txsize!=NULL) *txsize=sized2; +- return iores; +-} +- +-void *get_early_console_base(const char *name) +-{ +- return (void*)0xdeadbeef; +-} +- +-static unsigned char early_iobuffer[80]; +-static int early_iobuffer_cnt; +- +-void early_console_putc(void *base, char c) +-{ +- early_iobuffer[early_iobuffer_cnt++] = c; +- if ( ( early_iobuffer_cnt >= sizeof(early_iobuffer)) || +- (c == '\n') ) +- { +- TransferData(kDSWriteFile,early_iobuffer,early_iobuffer_cnt, NULL); +- early_iobuffer_cnt = 0; +- } +-} +- +-void early_console_init(void *base, int baudrate) +-{ +- early_iobuffer_cnt = 0; +-} +- +-//void early_console_start(const char *name, int baudrate) +-//{ +-//} +- +-#endif +- +-#endif +diff --git a/arch/m68k/cpu/early_init_support.c b/arch/m68k/cpu/early_init_support.c +deleted file mode 100644 +index be4a9e4..0000000 +--- a/arch/m68k/cpu/early_init_support.c ++++ /dev/null +@@ -1,41 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Early InitData support routines +- */ +-#include <common.h> +-#include <command.h> +-#include <console.h> +-#include <reloc.h> +-#include <init.h> +- +-#ifdef CONFIG_HAS_EARLY_INIT +- +-/** Returns relocation offset to early init data +- */ +-unsigned long reloc_offset(void) +-{ +- //extern char __early_init_data_begin[]; +- //FIXME: return (unsigned long)init_data_ptr - (unsigned long)__early_init_data_begin; +- return 0; +-} +- +-#endif +diff --git a/arch/m68k/cpu/interrupts.c b/arch/m68k/cpu/interrupts.c +deleted file mode 100644 +index 4e1ff12..0000000 +--- a/arch/m68k/cpu/interrupts.c ++++ /dev/null +@@ -1,246 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Interrupt routines and supporting code for Coldfire V4E +- */ +-#include <common.h> +-#include <asm/ptrace.h> +-#include <mach/mcf54xx-regs.h> +- +-#ifdef CONFIG_USE_IRQ +-void enable_interrupts(void) +-{ +- asm_set_ipl(0); +-} +- +-int disable_interrupts(void) +-{ +- return asm_set_ipl(7) ? 1 : 0; +-} +-#endif +- +-/** +- */ +-static void mcf_bad_mode (void) +-{ +- panic ("Resetting CPU ...\n"); +- mdelay(3000); +- reset_cpu (0); +-} +- +-/** +- */ +-static void mcf_show_regs (struct pt_regs *regs) +-{ +- unsigned long flags; +- flags = condition_codes (regs); +- +- printf ("pc : [<%08lx>]\n" +- "sp : %08lx fp : %08lx\n", +- instruction_pointer (regs), +- regs->M68K_sp, regs->M68K_a6); +- +- printf ("d0-d3 : %08lx %08lx %08lx %08lx\n", +- regs->M68K_d0, regs->M68K_d1, regs->M68K_d2, regs->M68K_d3); +- printf ("d3-d7 : %08lx %08lx %08lx %08lx\n", +- regs->M68K_d3, regs->M68K_d4, regs->M68K_d5, regs->M68K_d6); +- +- printf ("a0-d3 : %08lx %08lx %08lx %08lx\n", +- regs->M68K_a0, regs->M68K_a1, regs->M68K_a2, regs->M68K_a3); +- printf ("a3-d7 : %08lx %08lx %08lx %08lx\n", +- regs->M68K_a3, regs->M68K_a4, regs->M68K_a5, regs->M68K_a6); +- +- printf ("fp0 : %08lx%08lx fp1 : %08lx%08lx\n", +- regs->M68K_fp0+1, regs->M68K_fp0, regs->M68K_fp1+1, regs->M68K_fp1); +- printf ("fp2 : %08lx%08lx fp3 : %08lx%08lx\n", +- regs->M68K_fp2+1, regs->M68K_fp2, regs->M68K_fp3+1, regs->M68K_fp3); +- printf ("fp4 : %08lx%08lx fp5 : %08lx%08lx\n", +- regs->M68K_fp4+1, regs->M68K_fp4, regs->M68K_fp5+1, regs->M68K_fp5); +- printf ("fp6 : %08lx%08lx fp7 : %08lx%08lx\n", +- regs->M68K_fp6+1, regs->M68K_fp6, regs->M68K_fp7+1, regs->M68K_fp7); +- +- printf ("Flags: %c%c%c%c", +- flags & CC_X_BIT ? 'X' : 'x', +- flags & CC_N_BIT ? 'N' : 'n', +- flags & CC_Z_BIT ? 'Z' : 'z', +- flags & CC_V_BIT ? 'V' : 'v', +- flags & CC_C_BIT ? 'C' : 'c' ); +- +- printf (" IRQs %s (%0x) Mode %s\n", +- interrupts_enabled (regs) ? "on" : "off", interrupts_enabled (regs), +- user_mode (regs) ? "user" : "supervisor"); +-} +- +-void mcf_execute_exception_handler (struct pt_regs *pt_regs) +-{ +- printf ("unhandled exception\n"); +- mcf_show_regs (pt_regs); +- mcf_bad_mode (); +-} +- +-#ifndef CONFIG_USE_IRQ +- +-void mcf_execute_irq_handler (struct pt_regs *pt_regs, int vector) +-{ +- printf ("interrupt request\n"); +- mcf_show_regs (pt_regs); +- mcf_bad_mode (); +-} +- +-#else +- +-#ifndef CONFIG_MAX_ISR_HANDLERS +-#define CONFIG_MAX_ISR_HANDLERS (20) +-#endif +- +-typedef struct +-{ +- int vector; +- int (*handler)(void *, void *); +- void *hdev; +- void *harg; +-} +-mcfv4e_irq_handler_s; +- +-mcfv4e_irq_handler_s irq_handler_table[CONFIG_MAX_ISR_HANDLERS]; +- +-/** Initialize an empty interrupt handler list +- */ +-void mcf_interrupts_initialize (void) +-{ +- int index; +- for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++) +- { +- irq_handler_table[index].vector = 0; +- irq_handler_table[index].handler = 0; +- irq_handler_table[index].hdev = 0; +- irq_handler_table[index].harg = 0; +- } +-} +- +-/** Add an interrupt handler to the handler list +- * +- * @param vector : M68k exception/interrupt vector number +- * @param handler : Pointer to handler function +- * @param hdev : Handler specific data +- * @param harg : Handler specific arg +- */ +-int mcf_interrupts_register_handler( +- int vector, +- int (*handler)(void *, void *), void *hdev, void *harg) +-{ +- /* +- * This function places an interrupt handler in the ISR table, +- * thereby registering it so that the low-level handler may call it. +- * +- * The two parameters are intended for the first arg to be a +- * pointer to the device itself, and the second a pointer to a data +- * structure used by the device driver for that particular device. +- */ +- int index; +- +- if ((vector == 0) || (handler == NULL)) +- { +- return 0; +- } +- +- for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++) +- { +- if (irq_handler_table[index].vector == vector) +- { +- /* only one entry of each type per vector */ +- return 0; +- } +- +- if (irq_handler_table[index].vector == 0) +- { +- irq_handler_table[index].vector = vector; +- irq_handler_table[index].handler = handler; +- irq_handler_table[index].hdev = hdev; +- irq_handler_table[index].harg = harg; +- return 1; +- } +- } +- return 0; /* no available slots */ +-} +- +-/** Remove an interrupt handler from the handler list +- * +- * @param type : FIXME +- * @param handler : Pointer of handler function to remove. +- */ +-void mcf_interrupts_remove_handler (int type ,int (*handler)(void *, void *)) +-{ +- /* +- * This routine removes from the ISR table all +- * entries that matches 'handler'. +- */ +- int index; +- +- for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++) +- { +- if (irq_handler_table[index].handler == handler) +- { +- irq_handler_table[index].vector = 0; +- irq_handler_table[index].handler = 0; +- irq_handler_table[index].hdev = 0; +- irq_handler_table[index].harg = 0; +- } +- } +-} +- +-/** Traverse list of registered interrupts and call matching handlers. +- * +- * @param pt_regs : Pointer to saved register context +- * @param vector : M68k exception/interrupt vector number +- */ +-int mcf_execute_irq_handler (struct pt_regs *pt_regs, int vector) +-{ +- /* +- * This routine searches the ISR table for an entry that matches +- * 'vector'. If one is found, then 'handler' is executed. +- */ +- int index, retval = 0; +- +- /* +- * Try to locate a user-registered Interrupt Service Routine handler. +- */ +- for (index = 0; index < CONFIG_MAX_ISR_HANDLERS; index++) +- { +- if (irq_handler_table[index].handler == NULL) +- { +- printf("\nFault: No handler for IRQ vector %ld found.\n", vector); +- break; +- } +- if (irq_handler_table[index].vector == vector) +- { +- if (irq_handler_table[index].handler(irq_handler_table[index].hdev,irq_handler_table[index].harg)) +- { +- retval = 1; +- break; +- } +- } +- } +- +- return retval; +-} +- +-#endif +diff --git a/arch/m68k/cpu/start-mcfv4e.S b/arch/m68k/cpu/start-mcfv4e.S +deleted file mode 100644 +index df9ee4d..0000000 +--- a/arch/m68k/cpu/start-mcfv4e.S ++++ /dev/null +@@ -1,677 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Resetcode and exception/interrupt shells for Coldfire V4E +- * +- * This file contains the common startup code for use on at least Coldfire +- * V4E cores: +- * - MCF547x +- * - MCF548x +- */ +-#include <config.h> +- +- .section ".vectors","a" +- +-/* +- * Define some addresses from your board configuration file +- */ +- .equ __MBAR,CFG_MBAR_ADDRESS +- .globl __MBAR +- +- .equ __CORE_SRAM0,CFG_CORE0_SRAM_ADDRESS +- .equ __CORE_SRAM0_SIZE,CFG_CORE0_SRAM_SIZE +- +- .equ __CORE_SRAM1,CFG_CORE1_SRAM_ADDRESS +- .equ __CORE_SRAM1_SIZE,CFG_CORE1_SRAM_SIZE +- +- /* +- * Preload stack pointer with end of Core SRAM - useable _after_ you have +- * setup the MBR register in reset code! +- * +- * The upper 4 LW of the Core SRAM are left spare - it can be used as +- * fixed address temporay storage in the code below (ok, well also to +- * fix up stack traces in the debugger) +- * +- * So we have a stack usable for C code, before we even started SDRAM! +- */ +- .equ ___SP_INIT,__CORE_SRAM1+__CORE_SRAM1_SIZE-16 +- +-/* +- * Vector table for M68k and barebox Link Address +- * +- * On M68k/Coldfire cores all exceptions and interrupts are routed through +- * a vector array. This vector is by default at address 0x0000_0000, but +- * can be moved to any other 1MB aligned address. +- * +- * We take advantage of this to move barebox out of low memory. Some BDM +- * debuggers won't like a moved vector base and might need tweaking to +- * work. +- * +- * Note: Respect alignment restrictions for TEXT_BASE, which must be +- * 1MB aligned. +- */ +- +- .globl _barebox_start +-_barebox_start: +- +-VECTOR_TABLE: +-_VECTOR_TABLE: +-INITSP: .long ___SP_INIT /* Initial SP */ +-INITPC: .long 0x410 /* Initial PC */ +-vector02: .long _asm_exception_handler /* Access Error */ +-vector03: .long _asm_exception_handler /* Address Error */ +-vector04: .long _asm_exception_handler /* Illegal Instruction */ +-vector05: .long _asm_exception_handler /* Divide by Zero */ +-vector06: .long _asm_exception_handler /* Reserved */ +-vector07: .long _asm_exception_handler /* Reserved */ +-vector08: .long _asm_exception_handler /* Privilege Violation */ +-vector09: .long _asm_exception_handler /* Trace */ +-vector0A: .long _asm_exception_handler /* Unimplemented A-Line */ +-vector0B: .long _asm_exception_handler /* Unimplemented F-Line */ +-vector0C: .long _asm_exception_handler /* Non-PC Brkpt Debug Int */ +-vector0D: .long _asm_exception_handler /* PC Brkpt Debug Int */ +-vector0E: .long _asm_exception_handler /* Format Error */ +-vector0F: .long _asm_exception_handler /* Unitialized Int */ +-vector10: .long _asm_exception_handler /* Reserved */ +-vector11: .long _asm_exception_handler /* Reserved */ +-vector12: .long _asm_exception_handler /* Reserved */ +-vector13: .long _asm_exception_handler /* Reserved */ +-vector14: .long _asm_exception_handler /* Reserved */ +-vector15: .long _asm_exception_handler /* Reserved */ +-vector16: .long _asm_exception_handler /* Reserved */ +-vector17: .long _asm_exception_handler /* Reserved */ +-vector18: .long _asm_exception_handler /* Spurious Interrupt */ +-vector19: .long _asm_isr_handler /* Autovector Level 1 */ +-vector1A: .long _asm_isr_handler /* Autovector Level 2 */ +-vector1B: .long _asm_isr_handler /* Autovector Level 3 */ +-vector1C: .long _asm_isr_handler /* Autovector Level 4 */ +-vector1D: .long _asm_isr_handler /* Autovector Level 5 */ +-vector1E: .long _asm_isr_handler /* Autovector Level 6 */ +-vector1F: .long _asm_isr_handler /* Autovector Level 7 */ +-vector20: .long _asm_exception_handler /* TRAP #0 */ +-vector21: .long _asm_exception_handler /* TRAP #1 */ +-vector22: .long _asm_exception_handler /* TRAP #2 */ +-vector23: .long _asm_exception_handler /* TRAP #3 */ +-vector24: .long _asm_exception_handler /* TRAP #4 */ +-vector25: .long _asm_exception_handler /* TRAP #5 */ +-vector26: .long _asm_exception_handler /* TRAP #6 */ +-vector27: .long _asm_exception_handler /* TRAP #7 */ +-vector28: .long _asm_exception_handler /* TRAP #8 */ +-vector29: .long _asm_exception_handler /* TRAP #9 */ +-vector2A: .long _asm_exception_handler /* TRAP #10 */ +-vector2B: .long _asm_exception_handler /* TRAP #11 */ +-vector2C: .long _asm_exception_handler /* TRAP #12 */ +-vector2D: .long _asm_exception_handler /* TRAP #13 */ +-vector2E: .long _asm_exception_handler /* TRAP #14 */ +-vector2F: .long _dbug_sc_handler /* TRAP #15 - System Call */ +-vector30: .long _asm_exception_handler /* Reserved */ +-vector31: .long _asm_exception_handler /* Reserved */ +-vector32: .long _asm_exception_handler /* Reserved */ +-vector33: .long _asm_exception_handler /* Reserved */ +-vector34: .long _asm_exception_handler /* Reserved */ +-vector35: .long _asm_exception_handler /* Reserved */ +-vector36: .long _asm_exception_handler /* Reserved */ +-vector37: .long _asm_exception_handler /* Reserved */ +-vector38: .long _asm_exception_handler /* Reserved */ +-vector39: .long _asm_exception_handler /* Reserved */ +-vector3A: .long _asm_exception_handler /* Reserved */ +-vector3B: .long _asm_exception_handler /* Reserved */ +-vector3C: .long _asm_exception_handler /* Reserved */ +-vector3D: .long _asm_exception_handler /* Unsupported Instruction */ +-vector3E: .long _asm_exception_handler /* Reserved */ +-vector3F: .long _asm_exception_handler /* Reserved */ +-vector40: .long _asm_isr_handler /* User Defined Interrupts */ +-vector41: .long _asm_isr_handler +-vector42: .long _asm_isr_handler +-vector43: .long _asm_isr_handler +-vector44: .long _asm_isr_handler +-vector45: .long _asm_isr_handler +-vector46: .long _asm_isr_handler +-vector47: .long _asm_isr_handler +-vector48: .long _asm_isr_handler +-vector49: .long _asm_isr_handler +-vector4A: .long _asm_isr_handler +-vector4B: .long _asm_isr_handler +-vector4C: .long _asm_isr_handler +-vector4D: .long _asm_isr_handler +-vector4E: .long _asm_isr_handler +-vector4F: .long _asm_isr_handler +-vector50: .long _asm_isr_handler +-vector51: .long _asm_isr_handler +-vector52: .long _asm_isr_handler +-vector53: .long _asm_isr_handler +-vector54: .long _asm_isr_handler +-vector55: .long _asm_isr_handler +-vector56: .long _asm_isr_handler +-vector57: .long _asm_isr_handler +-vector58: .long _asm_isr_handler +-vector59: .long _asm_isr_handler +-vector5A: .long _asm_isr_handler +-vector5B: .long _asm_isr_handler +-vector5C: .long _asm_isr_handler +-vector5D: .long _asm_isr_handler +-vector5E: .long _asm_isr_handler +-vector5F: .long _asm_isr_handler +-vector60: .long _asm_isr_handler +-vector61: .long _asm_isr_handler +-vector62: .long _asm_isr_handler +-vector63: .long _asm_isr_handler +-vector64: .long _asm_isr_handler +-vector65: .long _asm_isr_handler +-vector66: .long _asm_isr_handler +-vector67: .long _asm_isr_handler +-vector68: .long _asm_isr_handler +-vector69: .long _asm_isr_handler +-vector6A: .long _asm_isr_handler +-vector6B: .long _asm_isr_handler +-vector6C: .long _asm_isr_handler +-vector6D: .long _asm_isr_handler +-vector6E: .long _asm_isr_handler +-vector6F: .long _asm_isr_handler +-vector70: .long _asm_isr_handler +-vector71: .long _asm_isr_handler +-vector72: .long _asm_isr_handler +-vector73: .long _asm_isr_handler +-vector74: .long _asm_isr_handler +-vector75: .long _asm_isr_handler +-vector76: .long _asm_isr_handler +-vector77: .long _asm_isr_handler +-vector78: .long _asm_isr_handler +-vector79: .long _asm_isr_handler +-vector7A: .long _asm_isr_handler +-vector7B: .long _asm_isr_handler +-vector7C: .long _asm_isr_handler +-vector7D: .long _asm_isr_handler +-vector7E: .long _asm_isr_handler +-vector7F: .long _asm_isr_handler +-vector80: .long _asm_isr_handler +-vector81: .long _asm_isr_handler +-vector82: .long _asm_isr_handler +-vector83: .long _asm_isr_handler +-vector84: .long _asm_isr_handler +-vector85: .long _asm_isr_handler +-vector86: .long _asm_isr_handler +-vector87: .long _asm_isr_handler +-vector88: .long _asm_isr_handler +-vector89: .long _asm_isr_handler +-vector8A: .long _asm_isr_handler +-vector8B: .long _asm_isr_handler +-vector8C: .long _asm_isr_handler +-vector8D: .long _asm_isr_handler +-vector8E: .long _asm_isr_handler +-vector8F: .long _asm_isr_handler +-vector90: .long _asm_isr_handler +-vector91: .long _asm_isr_handler +-vector92: .long _asm_isr_handler +-vector93: .long _asm_isr_handler +-vector94: .long _asm_isr_handler +-vector95: .long _asm_isr_handler +-vector96: .long _asm_isr_handler +-vector97: .long _asm_isr_handler +-vector98: .long _asm_isr_handler +-vector99: .long _asm_isr_handler +-vector9A: .long _asm_isr_handler +-vector9B: .long _asm_isr_handler +-vector9C: .long _asm_isr_handler +-vector9D: .long _asm_isr_handler +-vector9E: .long _asm_isr_handler +-vector9F: .long _asm_isr_handler +-vectorA0: .long _asm_isr_handler +-vectorA1: .long _asm_isr_handler +-vectorA2: .long _asm_isr_handler +-vectorA3: .long _asm_isr_handler +-vectorA4: .long _asm_isr_handler +-vectorA5: .long _asm_isr_handler +-vectorA6: .long _asm_isr_handler +-vectorA7: .long _asm_isr_handler +-vectorA8: .long _asm_isr_handler +-vectorA9: .long _asm_isr_handler +-vectorAA: .long _asm_isr_handler +-vectorAB: .long _asm_isr_handler +-vectorAC: .long _asm_isr_handler +-vectorAD: .long _asm_isr_handler +-vectorAE: .long _asm_isr_handler +-vectorAF: .long _asm_isr_handler +-vectorB0: .long _asm_isr_handler +-vectorB1: .long _asm_isr_handler +-vectorB2: .long _asm_isr_handler +-vectorB3: .long _asm_isr_handler +-vectorB4: .long _asm_isr_handler +-vectorB5: .long _asm_isr_handler +-vectorB6: .long _asm_isr_handler +-vectorB7: .long _asm_isr_handler +-vectorB8: .long _asm_isr_handler +-vectorB9: .long _asm_isr_handler +-vectorBA: .long _asm_isr_handler +-vectorBB: .long _asm_isr_handler +-vectorBC: .long _asm_isr_handler +-vectorBD: .long _asm_isr_handler +-vectorBE: .long _asm_isr_handler +-vectorBF: .long _asm_isr_handler +-vectorC0: .long _asm_isr_handler +-vectorC1: .long _asm_isr_handler +-vectorC2: .long _asm_isr_handler +-vectorC3: .long _asm_isr_handler +-vectorC4: .long _asm_isr_handler +-vectorC5: .long _asm_isr_handler +-vectorC6: .long _asm_isr_handler +-vectorC7: .long _asm_isr_handler +-vectorC8: .long _asm_isr_handler +-vectorC9: .long _asm_isr_handler +-vectorCA: .long _asm_isr_handler +-vectorCB: .long _asm_isr_handler +-vectorCC: .long _asm_isr_handler +-vectorCD: .long _asm_isr_handler +-vectorCE: .long _asm_isr_handler +-vectorCF: .long _asm_isr_handler +-vectorD0: .long _asm_isr_handler +-vectorD1: .long _asm_isr_handler +-vectorD2: .long _asm_isr_handler +-vectorD3: .long _asm_isr_handler +-vectorD4: .long _asm_isr_handler +-vectorD5: .long _asm_isr_handler +-vectorD6: .long _asm_isr_handler +-vectorD7: .long _asm_isr_handler +-vectorD8: .long _asm_isr_handler +-vectorD9: .long _asm_isr_handler +-vectorDA: .long _asm_isr_handler +-vectorDB: .long _asm_isr_handler +-vectorDC: .long _asm_isr_handler +-vectorDD: .long _asm_isr_handler +-vectorDE: .long _asm_isr_handler +-vectorDF: .long _asm_isr_handler +-vectorE0: .long _asm_isr_handler +-vectorE1: .long _asm_isr_handler +-vectorE2: .long _asm_isr_handler +-vectorE3: .long _asm_isr_handler +-vectorE4: .long _asm_isr_handler +-vectorE5: .long _asm_isr_handler +-vectorE6: .long _asm_isr_handler +-vectorE7: .long _asm_isr_handler +-vectorE8: .long _asm_isr_handler +-vectorE9: .long _asm_isr_handler +-vectorEA: .long _asm_isr_handler +-vectorEB: .long _asm_isr_handler +-vectorEC: .long _asm_isr_handler +-vectorED: .long _asm_isr_handler +-vectorEE: .long _asm_isr_handler +-vectorEF: .long _asm_isr_handler +-vectorF0: .long _asm_isr_handler +-vectorF1: .long _asm_isr_handler +-vectorF2: .long _asm_isr_handler +-vectorF3: .long _asm_isr_handler +-vectorF4: .long _asm_isr_handler +-vectorF5: .long _asm_isr_handler +-vectorF6: .long _asm_isr_handler +-vectorF7: .long _asm_isr_handler +-vectorF8: .long _asm_isr_handler +-vectorF9: .long _asm_isr_handler +-vectorFA: .long _asm_isr_handler +-vectorFB: .long _asm_isr_handler +-vectorFC: .long _asm_isr_handler +-vectorFD: .long _asm_isr_handler +-vectorFE: .long _asm_isr_handler +-vectorFF: .long _asm_isr_handler +- +-/* +- * Leave some bytes spare here for CW debugger (console IO stuff) +- */ +- .rept 4 +- .long 0xdeadbeef +- .endr +- +-/** @func reset Startup Code (reset vector) +- * +- * The vector array is mapped to address 0 at reset and SP and PC are +- * fetched from adress 0 and 4. +- * +- * For debugger uploads this image will reside in the middle of RAM, leaving +- * as much memory for other stuff in low memory available, e.g. Linux and +- * an init ramdisk. +- * +- * For real system resets, the boot rom is mapped to all addresses in +- * system, as long as somebody sets up the CS. Now the trick part until +- * relocation to RAM is that we must code at the start of your bootrom +- * - all link addresses are wrong, so we need the reloc.h stuff to find the +- * right address. +- * +- * The following things happen here: +- * * do important init, like SDRAM, only if we don't start from memory! +- * * setup Memory and board specific bits prior to relocation. +- * * Setup stack +- * * relocate barebox to ram +- * +- */ +- .globl _start +-_start: +- .global reset +-reset: +- /* Mask all IRQs */ +- move.w #0x2700,%sr +- +- /* Initialize MBAR - keep D0/D1 registers */ +- move.l #__MBAR,%d2 +- movec %d2,%MBAR +- nop +- +- /* Initialize RAMBAR0 - locate it on the data bus */ +- move.l #__CORE_SRAM0,%d2 +- add.l #0x21,%d2 +- movec %d2,%RAMBAR0 +- nop +- +- /* Initialize RAMBAR1 - locate it on the data bus */ +- move.l #__CORE_SRAM1,%d2 +- add.l #0x21,%d2 +- movec %d2,%RAMBAR1 +- nop +- +- /* Point Stack Pointer into Core SRAM temporarily */ +- move.l #___SP_INIT,%d2 +- move.l %d2,%sp +- nop +- +- /* Invalidate the data, instruction, and branch caches */ +- /* Turn on the branch cache */ +- move.l #0x010C0100,%d2 +- movec %d2,%cacr +- nop +- +- /* Prepare stack top */ +- clr.l %sp@(0) +- move.l %d0,%sp@(4) +- move.l %d1,%sp@(8) +- clr.l %sp@(12) +- +- /* +- * This call is intended to give all developers a chance to use a +- * standard reset vector file, but also do some special things +- * required only on their specific CPU. +- */ +-#ifdef CONFIG_ARCH_HAS_LOWLEVEL_INIT +- bsr.l arch_init_lowlevel +- nop +-#endif +- /* +- * If the code vector table is not at TEXT_BASE and so this code +- * as well, jump to the address mirror at FLASH ROM start address +- * +- * So load your image to TEXT_BASE for debugging or flash a binary +- * image to your bootflash - code below will take proper action. +- */ +- lea.l %pc@(VECTOR_TABLE),%a0 +- move.l #TEXT_BASE,%a1 +- cmp.l %a0,%a1 +- beq.s saveland +- +- /* +- * Execution is not at TEXT_BASE. We assume entry to this code by +- * a hardware reset and change execution to address of _FLASH_ rom. +- */ +- lea.l %pc@(saveland),%a0 // Effective ! Address of label below +- move.l %a0,%d0 +- and.l #0x00ffffff,%d0 // Cut away address high byte +- move.l #CFG_FLASH_ADDRESS,%d1 // Get flash address +- and.l #0xff000000,%d1 // and just take base for CS0 +- or.l %d1,%d0 // Compose new address +- move.l %d0,%a0 +- jmp %a0@ // Jump to flash rom address! +- nop +- +- /* We now either in SDRAM or FLASH START addresses, save to +- change chip selects */ +-saveland: +- nop +- +- /* +- * Before relocating, we have to setup RAM timing +- * because memory timing is board-dependend, you will +- * find a lowlevel_init.[c|S] in your board directory. +- * +- * Do not jump/call other barebox code here! +- */ +-#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT +- bsr.l board_init_lowlevel +- nop +-#endif +- +- /* +- * relocate barebox Code to RAM (including copy of vectors) +- */ +-relocate: +- lea.l %pc@(VECTOR_TABLE),%a0 +- move.l #TEXT_BASE,%a1 +- move.l #__bss_start,%a3 +- cmp.l %a0,%a1 +- beq.s skip_relocate +- +- /* +- * Calculate number of long words, and copy them to RAM +- */ +- move.l %a3,%d2 +- sub.l %a1,%d2 +- asr.l #2,%d2 +-copy_loop: +- move.l %a0@+,%a1@+ +- subq.l #1,%d2 +- bne.s copy_loop +- +-skip_relocate: +- +- /* Clear BSS segment in RAM */ +-clear_bss: +- move.l #__bss_end,%a4 +- moveq.l #0,%d2 +-clear_loop: +- move.l %d2,%a3@+ +- cmp.l %a4,%a3 +- ble.s clear_loop +- +- /* +- * Relocate Vectors to memory start (address 0) +- * +- * NOTE: It could be at other places, but debuggers expect +- * this table to be at address 0. +- */ +-#ifdef CONFIG_COPY_LOWMEM_VECTORS +-reloc_vectors: +- lea.l %pc@(VECTOR_TABLE),%a0 +- move.l #0,%a1 +- cmp.l %a0,%a1 +- beq.s skip_copy_vectors +- +- move.l #0x100,%d2 +-copy_loop_vectors: +- move.l %a0@+,%a1@+ +- subq.l #1,%d2 +- bne.s copy_loop_vectors +-skip_copy_vectors: +-#endif +- +-#ifndef CONFIG_USE_LOWMEM_VECTORS +- move.l #TEXT_BASE,%d0 +- movec %d0,%vbr +- nop +-#endif +- +-#ifdef CONFIG_MACH_DO_LOWLEVEL_INIT +- /* +- * Call other half of initcode in relocated code +- * +- * You allowed to call other barebox code from here +- */ +- jsr.l board_init_highlevel +- nop +-#endif +- /* +- * Now jump to real link address and barebox entry point +- */ +- nop +- jmp.l start_barebox +- nop +- nop +- +-/* +- * Interrupt handling +- */ +- +-/* +- * IRQ stack frame. +- */ +-#define S_FRAME_SIZE 148 +- +-#define S_SP S_A7 +-#define S_SR 144 +-#define S_PC 140 +- +-#define S_FPIAR 136 +-#define S_FPSR 132 +-#define S_FPCR 128 +- +-#define S_FP7 120 +-#define S_FP6 112 +-#define S_FP5 104 +-#define S_FP4 96 +-#define S_FP3 88 +-#define S_FP2 80 +-#define S_FP1 72 +-#define S_FP0 64 +- +-#define S_A7 60 +-#define S_A6 56 +-#define S_A5 52 +-#define S_A4 48 +-#define S_A3 44 +-#define S_A2 40 +-#define S_A1 36 +-#define S_A0 32 +- +-#define S_D7 28 +-#define S_D6 24 +-#define S_D5 20 +-#define S_D4 16 +-#define S_D3 12 +-#define S_D2 8 +-#define S_D1 4 +-#define S_D0 0 +- +- +-/* +- * exception handlers +- */ +-#ifdef CONFIG_USE_IRQ +- .global _dbug_sc_handler +-_dbug_sc_handler: +- .global _asm_exception_handler +-_asm_exception_handler: +- move.w #0x2700,%sr /* Disable IRQs */ +- +- move.l %sp,___SP_INIT /* Remember on top of stack */ +- move.l #___SP_INIT,%sp /* Set stack to known area */ +- +- move.l %a0,%sp@- +- lea _asm_context,%a0 +- +- movem.l %d0-%d7/%a0-%a7,%a0@ +- +- fmovem %fp0-%fp7,%a0@(S_FP0) +- fmove.l %fpcr,%a0@(S_FPCR) +- fmove.l %fpsr,%a0@(S_FPSR) +- fmove.l %fpiar,%a0@(S_FPIAR) +- +- move.l %sp@+,%a0@(S_A0) +- move.l %sp@,%a1 +- move.l %a1,%a0@(S_SP) +- move.l %a1@(4),%a0@(S_PC) +- move.w %a1@(2),%a0@(S_SR) +- +- jsr cpu_cache_flush +- nop +- +- move.l %a1,%sp@- +- jsr mcf_execute_exception_handler +- +- +- lea _asm_context,%a0 +- move.l %a0@(S_SP),%sp +- +- move.l %a0@(S_D1),%d1 +- move.l %a0@(S_D0),%d0 +- move.l %a0@(S_A1),%a1 +- move.l %a0@(S_A0),%a0 +- +- rte +- nop +- nop +- +- .global _asm_isr_handler +-_asm_isr_handler: +- link %a6,#-16 +- movem.l %d0-%d1/%a0-%a1,%sp@ +- +- move.w %a6@(4),%d0 +- lsr.l #2,%d0 +- andi.l #0x0000FF,%d0 +- move.l %d0,%sp@- +- move.l #0,%a0 +- move.l %a0,%sp@- +- jsr mcf_execute_irq_handler +- lea %sp@(8),%sp +- cmpi.l #1,%d0 +- beq handled +- +-nothandled: +- movem.l %sp@,%d0-%d1/%a0-%a1 +- unlk %a6 +- jmp _asm_exception_handler +- nop +- +-handled: +- movem.l %sp@,%d0-%d1/%a0-%a1 +- unlk %a6 +- rte +- nop +- nop +- +-#else +- +- .global _dbug_sc_handler +-_dbug_sc_handler: +- .global _asm_exception_handler +-_asm_exception_handler: +- nop +- // FIXME - do something useful here +- rte +- +- .global _asm_isr_handler +-_asm_isr_handler: +- nop +- // FIXME - do something useful here +- rte +- +-#endif +- +- .data +-_asm_context: +- .space S_FRAME_SIZE,0x55 +- +- +- .end +diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h +deleted file mode 100644 +index efbe2b8..0000000 +--- a/arch/m68k/include/asm/atomic.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Declaration for atomic operations +- */ +- +-/* Empty dummy FIXME */ +diff --git a/arch/m68k/include/asm/barebox-m68k.h b/arch/m68k/include/asm/barebox-m68k.h +deleted file mode 100644 +index c1ee75e..0000000 +--- a/arch/m68k/include/asm/barebox-m68k.h ++++ /dev/null +@@ -1,40 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Arch dependant barebox defines +- */ +-#ifndef _BAREBOX_M68K_H_ +-#define _BAREBOX_M68K_H_ 1 +- +-/* for the following variables, see start.S */ +-//extern ulong _armboot_start; /* code start */ +-//extern ulong _bss_start; /* code + data end == BSS start */ +-//extern ulong _bss_end; /* BSS end */ +-//extern ulong IRQ_STACK_START; /* top of IRQ stack */ +- +-/* cpu/.../cpu.c */ +-int cleanup_before_linux(void); +- +-/* board/.../... */ +-//int board_init(void); +-//int dram_init (void); +- +-#endif /* _BAREBOX_M68K_H_ */ +diff --git a/arch/m68k/include/asm/barebox.h b/arch/m68k/include/asm/barebox.h +deleted file mode 100644 +index 568b288..0000000 +--- a/arch/m68k/include/asm/barebox.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @note This header file defines an interface to barebox. Including +- * this (unmodified) header file in another file is considered normal +- * use of barebox, and does *not* fall under the heading of "derived +- * work". +- */ +- +-#ifndef _BAREBOX_H_ +-#define _BAREBOX_H_ 1 +- +-//typedef struct bd_info {} bd_t; +- +-#endif /* _BAREBOX_H_ */ +diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h +deleted file mode 100644 +index fee64a4..0000000 +--- a/arch/m68k/include/asm/bitops.h ++++ /dev/null +@@ -1,141 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Bitops helper functions and defines for M68k +- * +- * bit 0 is the LSB of addr; bit 32 is the HSB. +- * +- * Please note that the code in this file should never be included +- * from user space. Many of these are not implemented in assembler +- * since they would be too costly. Also, they require priviledged +- * instructions (which are not available from user mode) to ensure +- * that they are atomic. +- */ +- +-#ifndef __ASM_M68K_BITOPS_H +-#define __ASM_M68K_BITOPS_H +- +-/* +- * Function prototypes to keep gcc -Wall happy. +- */ +-extern void set_bit(int nr, volatile void * addr); +- +-static inline void __set_bit(int nr, volatile void *addr) +-{ +- ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); +-} +- +-extern void clear_bit(int nr, volatile void * addr); +- +-static inline void __clear_bit(int nr, volatile void *addr) +-{ +- ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); +-} +- +-extern void change_bit(int nr, volatile void * addr); +- +-static inline void __change_bit(int nr, volatile void *addr) +-{ +- ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); +-} +- +-extern int test_and_set_bit(int nr, volatile void * addr); +- +-static inline int __test_and_set_bit(int nr, volatile void *addr) +-{ +- unsigned int mask = 1 << (nr & 7); +- unsigned int oldval; +- +- oldval = ((unsigned char *) addr)[nr >> 3]; +- ((unsigned char *) addr)[nr >> 3] = oldval | mask; +- return oldval & mask; +-} +- +-extern int test_and_clear_bit(int nr, volatile void * addr); +- +-static inline int __test_and_clear_bit(int nr, volatile void *addr) +-{ +- unsigned int mask = 1 << (nr & 7); +- unsigned int oldval; +- +- oldval = ((unsigned char *) addr)[nr >> 3]; +- ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; +- return oldval & mask; +-} +- +-extern int test_and_change_bit(int nr, volatile void * addr); +- +-static inline int __test_and_change_bit(int nr, volatile void *addr) +-{ +- unsigned int mask = 1 << (nr & 7); +- unsigned int oldval; +- +- oldval = ((unsigned char *) addr)[nr >> 3]; +- ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; +- return oldval & mask; +-} +- +-extern int find_first_zero_bit(void * addr, unsigned size); +-extern int find_next_zero_bit(void * addr, int size, int offset); +- +-/* +- * This routine doesn't need to be atomic. +- */ +-static inline int test_bit(int nr, const void * addr) +-{ +- return ((unsigned char *) addr)[nr >> 3] & (1U << (nr & 7)); +-} +- +-/* +- * ffz = Find First Zero in word. Undefined if no zero exists, +- * so code should check against ~0UL first.. +- */ +-static inline unsigned long ffz(unsigned long word) +-{ +- int k; +- +- word = ~word; +- k = 31; +- if (word & 0x0000ffff) { k -= 16; word <<= 16; } +- if (word & 0x00ff0000) { k -= 8; word <<= 8; } +- if (word & 0x0f000000) { k -= 4; word <<= 4; } +- if (word & 0x30000000) { k -= 2; word <<= 2; } +- if (word & 0x40000000) { k -= 1; } +- return k; +-} +- +-#include <asm-generic/bitops/ffs.h> +-#include <asm-generic/bitops/hweight.h> +- +-#define ext2_set_bit test_and_set_bit +-#define ext2_clear_bit test_and_clear_bit +-#define ext2_test_bit test_bit +-#define ext2_find_first_zero_bit find_first_zero_bit +-#define ext2_find_next_zero_bit find_next_zero_bit +- +-/* Bitmap functions for the minix filesystem. */ +-#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +-#define minix_set_bit(nr,addr) set_bit(nr,addr) +-#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +-#define minix_test_bit(nr,addr) test_bit(nr,addr) +-#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) +- +-#endif /* __ASM_M68K_BITOPS_H */ +diff --git a/arch/m68k/include/asm/bootinfo.h b/arch/m68k/include/asm/bootinfo.h +deleted file mode 100644 +index a0bd27b..0000000 +--- a/arch/m68k/include/asm/bootinfo.h ++++ /dev/null +@@ -1,381 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Definition of the Linux/m68k boot information structure. +- * +- * Taken from Linux includes. See there for latest version, and update +- * if needed +- */ +-#ifndef _M68K_BOOTINFO_H +-#define _M68K_BOOTINFO_H +- +- +-/* +- * Bootinfo definitions +- * +- * This is an easily parsable and extendable structure containing all +- * information to be passed from the bootstrap to the kernel. +- * +- * This way I hope to keep all future changes back/forewards compatible. +- * Thus, keep your fingers crossed... +- * +- * This structure is copied right after the kernel bss by the bootstrap +- * routine. +- */ +- +-#ifndef __ASSEMBLY__ +- +-struct bi_record { +- unsigned short tag; /* tag ID */ +- unsigned short size; /* size of record (in bytes) */ +- unsigned long data[0]; /* data */ +-}; +- +-#endif /* __ASSEMBLY__ */ +- +- +-/* +- * Tag Definitions +- * +- * Machine independent tags start counting from 0x0000 +- * Machine dependent tags start counting from 0x8000 +- */ +- +-#define BI_LAST 0x0000 /* last record (sentinel) */ +-#define BI_MACHTYPE 0x0001 /* machine type (u_long) */ +-#define BI_CPUTYPE 0x0002 /* cpu type (u_long) */ +-#define BI_FPUTYPE 0x0003 /* fpu type (u_long) */ +-#define BI_MMUTYPE 0x0004 /* mmu type (u_long) */ +-#define BI_MEMCHUNK 0x0005 /* memory chunk address and size */ +- /* (struct mem_info) */ +-#define BI_RAMDISK 0x0006 /* ramdisk address and size */ +- /* (struct mem_info) */ +-#define BI_COMMAND_LINE 0x0007 /* kernel command line parameters */ +- /* (string) */ +- +-/* +- * Amiga-specific tags +- */ +- +-#define BI_AMIGA_MODEL 0x8000 /* model (u_long) */ +-#define BI_AMIGA_AUTOCON 0x8001 /* AutoConfig device */ +- /* (struct ConfigDev) */ +-#define BI_AMIGA_CHIP_SIZE 0x8002 /* size of Chip RAM (u_long) */ +-#define BI_AMIGA_VBLANK 0x8003 /* VBLANK frequency (u_char) */ +-#define BI_AMIGA_PSFREQ 0x8004 /* power supply frequency (u_char) */ +-#define BI_AMIGA_ECLOCK 0x8005 /* EClock frequency (u_long) */ +-#define BI_AMIGA_CHIPSET 0x8006 /* native chipset present (u_long) */ +-#define BI_AMIGA_SERPER 0x8007 /* serial port period (u_short) */ +- +-/* +- * Atari-specific tags +- */ +- +-#define BI_ATARI_MCH_COOKIE 0x8000 /* _MCH cookie from TOS (u_long) */ +-#define BI_ATARI_MCH_TYPE 0x8001 /* special machine type (u_long) */ +- /* (values are ATARI_MACH_* defines */ +- +-/* mch_cookie values (upper word) */ +-#define ATARI_MCH_ST 0 +-#define ATARI_MCH_STE 1 +-#define ATARI_MCH_TT 2 +-#define ATARI_MCH_FALCON 3 +- +-/* mch_type values */ +-#define ATARI_MACH_NORMAL 0 /* no special machine type */ +-#define ATARI_MACH_MEDUSA 1 /* Medusa 040 */ +-#define ATARI_MACH_HADES 2 /* Hades 040 or 060 */ +-#define ATARI_MACH_AB40 3 /* Afterburner040 on Falcon */ +- +-/* +- * VME-specific tags +- */ +- +-#define BI_VME_TYPE 0x8000 /* VME sub-architecture (u_long) */ +-#define BI_VME_BRDINFO 0x8001 /* VME board information (struct) */ +- +-/* BI_VME_TYPE codes */ +-#define VME_TYPE_TP34V 0x0034 /* Tadpole TP34V */ +-#define VME_TYPE_MVME147 0x0147 /* Motorola MVME147 */ +-#define VME_TYPE_MVME162 0x0162 /* Motorola MVME162 */ +-#define VME_TYPE_MVME166 0x0166 /* Motorola MVME166 */ +-#define VME_TYPE_MVME167 0x0167 /* Motorola MVME167 */ +-#define VME_TYPE_MVME172 0x0172 /* Motorola MVME172 */ +-#define VME_TYPE_MVME177 0x0177 /* Motorola MVME177 */ +-#define VME_TYPE_BVME4000 0x4000 /* BVM Ltd. BVME4000 */ +-#define VME_TYPE_BVME6000 0x6000 /* BVM Ltd. BVME6000 */ +- +-/* BI_VME_BRDINFO is a 32 byte struct as returned by the Bug code on +- * Motorola VME boards. Contains board number, Bug version, board +- * configuration options, etc. See include/asm/mvme16xhw.h for details. +- */ +- +- +-/* +- * Macintosh-specific tags (all u_long) +- */ +- +-#define BI_MAC_MODEL 0x8000 /* Mac Gestalt ID (model type) */ +-#define BI_MAC_VADDR 0x8001 /* Mac video base address */ +-#define BI_MAC_VDEPTH 0x8002 /* Mac video depth */ +-#define BI_MAC_VROW 0x8003 /* Mac video rowbytes */ +-#define BI_MAC_VDIM 0x8004 /* Mac video dimensions */ +-#define BI_MAC_VLOGICAL 0x8005 /* Mac video logical base */ +-#define BI_MAC_SCCBASE 0x8006 /* Mac SCC base address */ +-#define BI_MAC_BTIME 0x8007 /* Mac boot time */ +-#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */ +-#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */ +-#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */ +-#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */ +- +-/* +- * Macintosh hardware profile data - unused, see macintosh.h for +- * resonable type values +- */ +- +-#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */ +-#define BI_MAC_VIA2BASE 0x8011 /* Mac VIA2 base address (type varies) */ +-#define BI_MAC_VIA2TYPE 0x8012 /* Mac VIA2 type (VIA, RBV, OSS) */ +-#define BI_MAC_ADBTYPE 0x8013 /* Mac ADB interface type */ +-#define BI_MAC_ASCBASE 0x8014 /* Mac Apple Sound Chip base address */ +-#define BI_MAC_SCSI5380 0x8015 /* Mac NCR 5380 SCSI (base address, multi) */ +-#define BI_MAC_SCSIDMA 0x8016 /* Mac SCSI DMA (base address) */ +-#define BI_MAC_SCSI5396 0x8017 /* Mac NCR 53C96 SCSI (base address, multi) */ +-#define BI_MAC_IDETYPE 0x8018 /* Mac IDE interface type */ +-#define BI_MAC_IDEBASE 0x8019 /* Mac IDE interface base address */ +-#define BI_MAC_NUBUS 0x801a /* Mac Nubus type (none, regular, pseudo) */ +-#define BI_MAC_SLOTMASK 0x801b /* Mac Nubus slots present */ +-#define BI_MAC_SCCTYPE 0x801c /* Mac SCC serial type (normal, IOP) */ +-#define BI_MAC_ETHTYPE 0x801d /* Mac builtin ethernet type (Sonic, MACE */ +-#define BI_MAC_ETHBASE 0x801e /* Mac builtin ethernet base address */ +-#define BI_MAC_PMU 0x801f /* Mac power management / poweroff hardware */ +-#define BI_MAC_IOP_SWIM 0x8020 /* Mac SWIM floppy IOP */ +-#define BI_MAC_IOP_ADB 0x8021 /* Mac ADB IOP */ +- +-/* +- * Mac: compatibility with old booter data format (temporarily) +- * Fields unused with the new bootinfo can be deleted now; instead of +- * adding new fields the struct might be splitted into a hardware address +- * part and a hardware type part +- */ +- +-#ifndef __ASSEMBLY__ +- +-struct mac_booter_data +-{ +- unsigned long videoaddr; +- unsigned long videorow; +- unsigned long videodepth; +- unsigned long dimensions; +- unsigned long args; +- unsigned long boottime; +- unsigned long gmtbias; +- unsigned long bootver; +- unsigned long videological; +- unsigned long sccbase; +- unsigned long id; +- unsigned long memsize; +- unsigned long serialmf; +- unsigned long serialhsk; +- unsigned long serialgpi; +- unsigned long printmf; +- unsigned long printhsk; +- unsigned long printgpi; +- unsigned long cpuid; +- unsigned long rombase; +- unsigned long adbdelay; +- unsigned long timedbra; +-}; +- +-extern struct mac_booter_data +- mac_bi_data; +- +-#endif +- +-/* +- * Apollo-specific tags +- */ +- +-#define BI_APOLLO_MODEL 0x8000 /* model (u_long) */ +- +-/* +- * HP300-specific tags +- */ +- +-#define BI_HP300_MODEL 0x8000 /* model (u_long) */ +-#define BI_HP300_UART_SCODE 0x8001 /* UART select code (u_long) */ +-#define BI_HP300_UART_ADDR 0x8002 /* phys. addr of UART (u_long) */ +- +-/* +- * Stuff for bootinfo interface versioning +- * +- * At the start of kernel code, a 'struct bootversion' is located. +- * bootstrap checks for a matching version of the interface before booting +- * a kernel, to avoid user confusion if kernel and bootstrap don't work +- * together :-) +- * +- * If incompatible changes are made to the bootinfo interface, the major +- * number below should be stepped (and the minor reset to 0) for the +- * appropriate machine. If a change is backward-compatible, the minor +- * should be stepped. "Backwards-compatible" means that booting will work, +- * but certain features may not. +- */ +- +-#define BOOTINFOV_MAGIC 0x4249561A /* 'BIV^Z' */ +-#define MK_BI_VERSION(major,minor) (((major)<<16)+(minor)) +-#define BI_VERSION_MAJOR(v) (((v) >> 16) & 0xffff) +-#define BI_VERSION_MINOR(v) ((v) & 0xffff) +- +-#ifndef __ASSEMBLY__ +- +-struct bootversion { +- unsigned short branch; +- unsigned long magic; +- struct { +- unsigned long machtype; +- unsigned long version; +- } machversions[0]; +-}; +- +-#endif /* __ASSEMBLY__ */ +- +-#define AMIGA_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) +-#define ATARI_BOOTI_VERSION MK_BI_VERSION( 2, 1 ) +-#define MAC_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) +-#define MVME147_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) +-#define MVME16x_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) +-#define BVME6000_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) +-#define Q40_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) +-#define HP300_BOOTI_VERSION MK_BI_VERSION( 2, 0 ) +- +-#ifdef BOOTINFO_COMPAT_1_0 +- +-/* +- * Backwards compatibility with bootinfo interface version 1.0 +- */ +- +-#define COMPAT_AMIGA_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) +-#define COMPAT_ATARI_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) +-#define COMPAT_MAC_BOOTI_VERSION MK_BI_VERSION( 1, 0 ) +- +-#include <linux/zorro.h> +- +-#define COMPAT_NUM_AUTO 16 +- +-struct compat_bi_Amiga { +- int model; +- int num_autocon; +- struct ConfigDev autocon[COMPAT_NUM_AUTO]; +- unsigned long chip_size; +- unsigned char vblank; +- unsigned char psfreq; +- unsigned long eclock; +- unsigned long chipset; +- unsigned long hw_present; +-}; +- +-struct compat_bi_Atari { +- unsigned long hw_present; +- unsigned long mch_cookie; +-}; +- +-#ifndef __ASSEMBLY__ +- +-struct compat_bi_Macintosh +-{ +- unsigned long videoaddr; +- unsigned long videorow; +- unsigned long videodepth; +- unsigned long dimensions; +- unsigned long args; +- unsigned long boottime; +- unsigned long gmtbias; +- unsigned long bootver; +- unsigned long videological; +- unsigned long sccbase; +- unsigned long id; +- unsigned long memsize; +- unsigned long serialmf; +- unsigned long serialhsk; +- unsigned long serialgpi; +- unsigned long printmf; +- unsigned long printhsk; +- unsigned long printgpi; +- unsigned long cpuid; +- unsigned long rombase; +- unsigned long adbdelay; +- unsigned long timedbra; +-}; +- +-#endif +- +-struct compat_mem_info { +- unsigned long addr; +- unsigned long size; +-}; +- +-#define COMPAT_NUM_MEMINFO 4 +- +-#define COMPAT_CPUB_68020 0 +-#define COMPAT_CPUB_68030 1 +-#define COMPAT_CPUB_68040 2 +-#define COMPAT_CPUB_68060 3 +-#define COMPAT_FPUB_68881 5 +-#define COMPAT_FPUB_68882 6 +-#define COMPAT_FPUB_68040 7 +-#define COMPAT_FPUB_68060 8 +- +-#define COMPAT_CPU_68020 (1<<COMPAT_CPUB_68020) +-#define COMPAT_CPU_68030 (1<<COMPAT_CPUB_68030) +-#define COMPAT_CPU_68040 (1<<COMPAT_CPUB_68040) +-#define COMPAT_CPU_68060 (1<<COMPAT_CPUB_68060) +-#define COMPAT_CPU_MASK (31) +-#define COMPAT_FPU_68881 (1<<COMPAT_FPUB_68881) +-#define COMPAT_FPU_68882 (1<<COMPAT_FPUB_68882) +-#define COMPAT_FPU_68040 (1<<COMPAT_FPUB_68040) +-#define COMPAT_FPU_68060 (1<<COMPAT_FPUB_68060) +-#define COMPAT_FPU_MASK (0xfe0) +- +-#define COMPAT_CL_SIZE (256) +- +-struct compat_bootinfo { +- unsigned long machtype; +- unsigned long cputype; +- struct compat_mem_info memory[COMPAT_NUM_MEMINFO]; +- int num_memory; +- unsigned long ramdisk_size; +- unsigned long ramdisk_addr; +- char command_line[COMPAT_CL_SIZE]; +- union { +- struct compat_bi_Amiga bi_ami; +- struct compat_bi_Atari bi_ata; +- struct compat_bi_Macintosh bi_mac; +- } bi_un; +-}; +- +-#define bi_amiga bi_un.bi_ami +-#define bi_atari bi_un.bi_ata +-#define bi_mac bi_un.bi_mac +- +-#endif /* BOOTINFO_COMPAT_1_0 */ +- +- +-#endif /* _M68K_BOOTINFO_H */ +diff --git a/arch/m68k/include/asm/byteorder.h b/arch/m68k/include/asm/byteorder.h +deleted file mode 100644 +index 7a5fb61..0000000 +--- a/arch/m68k/include/asm/byteorder.h ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Define byte order of target +- * +- * M68K is always big-endian mode. +- * +- * When in big endian mode, byte accesses appear as: +- * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 +- * and word accesses (data or instruction) appear as: +- * d0...d31 +- */ +-#ifndef __ASM_M68K_BYTEORDER_H +-#define __ASM_M68K_BYTEORDER_H +- +- +-#include <asm/types.h> +- +-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +-# define __BYTEORDER_HAS_U64__ +-# define __SWAB_64_THRU_32__ +-#endif +-#include <linux/byteorder/big_endian.h> +- +-#endif +diff --git a/arch/m68k/include/asm/coldfire/mcf548x.h b/arch/m68k/include/asm/coldfire/mcf548x.h +deleted file mode 100644 +index 4bde42a..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x.h ++++ /dev/null +@@ -1,63 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF547X and MCF548X processors +- */ +-#ifndef __MCF548X_H__ +-#define __MCF548X_H__ +- +-/* +- * useful padding structure for register maps +- */ +-typedef struct +-{ +- vuint8_t a; +- vuint16_t b; +-} __attribute ((packed)) vuint24_t; +- +-/* +- * Include all internal hardware register macros and defines for this CPU. +- */ +-#include "asm/coldfire/mcf548x/mcf548x_fec.h" +-#include "asm/coldfire/mcf548x/mcf548x_siu.h" +-#include "asm/coldfire/mcf548x/mcf548x_ctm.h" +-#include "asm/coldfire/mcf548x/mcf548x_dspi.h" +-#include "asm/coldfire/mcf548x/mcf548x_eport.h" +-#include "asm/coldfire/mcf548x/mcf548x_fbcs.h" +-#include "asm/coldfire/mcf548x/mcf548x_gpio.h" +-#include "asm/coldfire/mcf548x/mcf548x_gpt.h" +-#include "asm/coldfire/mcf548x/mcf548x_i2c.h" +-#include "asm/coldfire/mcf548x/mcf548x_intc.h" +-#include "asm/coldfire/mcf548x/mcf548x_sdramc.h" +-#include "asm/coldfire/mcf548x/mcf548x_sec.h" +-#include "asm/coldfire/mcf548x/mcf548x_slt.h" +-#include "asm/coldfire/mcf548x/mcf548x_usb.h" +-#include "asm/coldfire/mcf548x/mcf548x_psc.h" +-#include "asm/coldfire/mcf548x/mcf548x_uart.h" +-#include "asm/coldfire/mcf548x/mcf548x_sram.h" +-#include "asm/coldfire/mcf548x/mcf548x_pci.h" +-#include "asm/coldfire/mcf548x/mcf548x_pciarb.h" +-#include "asm/coldfire/mcf548x/mcf548x_dma.h" +-#include "asm/coldfire/mcf548x/mcf548x_dma_ereq.h" +-#include "asm/coldfire/mcf548x/mcf548x_can.h" +-#include "asm/coldfire/mcf548x/mcf548x_xlbarb.h" +- +-#endif /* __MCF548X_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_can.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_can.h +deleted file mode 100644 +index bb53eaa..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_can.h ++++ /dev/null +@@ -1,159 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * CAN controllers +- */ +-#ifndef __MCF548X_CAN_H__ +-#define __MCF548X_CAN_H__ +- +-/* +- * FlexCAN Module (CAN) +- */ +- +-/* Register read/write macros */ +-#define MCF_CAN_CANMCR0 (*(vuint32_t*)(&__MBAR[0x00A000])) +-#define MCF_CAN_CANCTRL0 (*(vuint32_t*)(&__MBAR[0x00A004])) +-#define MCF_CAN_TIMER0 (*(vuint32_t*)(&__MBAR[0x00A008])) +-#define MCF_CAN_RXGMASK0 (*(vuint32_t*)(&__MBAR[0x00A010])) +-#define MCF_CAN_RX14MASK0 (*(vuint32_t*)(&__MBAR[0x00A014])) +-#define MCF_CAN_RX15MASK0 (*(vuint32_t*)(&__MBAR[0x00A018])) +-#define MCF_CAN_ERRCNT0 (*(vuint32_t*)(&__MBAR[0x00A01C])) +-#define MCF_CAN_ERRSTAT0 (*(vuint32_t*)(&__MBAR[0x00A020])) +-#define MCF_CAN_IMASK0 (*(vuint16_t*)(&__MBAR[0x00A02A])) +-#define MCF_CAN_IFLAG0 (*(vuint16_t*)(&__MBAR[0x00A032])) +-#define MCF_CAN_CANMCR1 (*(vuint32_t*)(&__MBAR[0x00A800])) +-#define MCF_CAN_CANCTRL1 (*(vuint32_t*)(&__MBAR[0x00A804])) +-#define MCF_CAN_TIMER1 (*(vuint32_t*)(&__MBAR[0x00A808])) +-#define MCF_CAN_RXGMASK1 (*(vuint32_t*)(&__MBAR[0x00A810])) +-#define MCF_CAN_RX14MASK1 (*(vuint32_t*)(&__MBAR[0x00A814])) +-#define MCF_CAN_RX15MASK1 (*(vuint32_t*)(&__MBAR[0x00A818])) +-#define MCF_CAN_ERRCNT1 (*(vuint32_t*)(&__MBAR[0x00A81C])) +-#define MCF_CAN_ERRSTAT1 (*(vuint32_t*)(&__MBAR[0x00A820])) +-#define MCF_CAN_IMASK1 (*(vuint16_t*)(&__MBAR[0x00A82A])) +-#define MCF_CAN_IFLAG1 (*(vuint16_t*)(&__MBAR[0x00A832])) +-#define MCF_CAN_CANMCR(x) (*(vuint32_t*)(&__MBAR[0x00A000+((x)*0x800)])) +-#define MCF_CAN_CANCTRL(x) (*(vuint32_t*)(&__MBAR[0x00A004+((x)*0x800)])) +-#define MCF_CAN_TIMER(x) (*(vuint32_t*)(&__MBAR[0x00A008+((x)*0x800)])) +-#define MCF_CAN_RXGMASK(x) (*(vuint32_t*)(&__MBAR[0x00A010+((x)*0x800)])) +-#define MCF_CAN_RX14MASK(x) (*(vuint32_t*)(&__MBAR[0x00A014+((x)*0x800)])) +-#define MCF_CAN_RX15MASK(x) (*(vuint32_t*)(&__MBAR[0x00A018+((x)*0x800)])) +-#define MCF_CAN_ERRCNT(x) (*(vuint32_t*)(&__MBAR[0x00A01C+((x)*0x800)])) +-#define MCF_CAN_ERRSTAT(x) (*(vuint32_t*)(&__MBAR[0x00A020+((x)*0x800)])) +-#define MCF_CAN_IMASK(x) (*(vuint16_t*)(&__MBAR[0x00A02A+((x)*0x800)])) +-#define MCF_CAN_IFLAG(x) (*(vuint16_t*)(&__MBAR[0x00A032+((x)*0x800)])) +- +-/* Bit definitions and macros for MCF_CAN_CANMCR */ +-#define MCF_CAN_CANMCR_MAXMB(x) (((x)&0x0000000F)<<0) +-#define MCF_CAN_CANMCR_SUPV (0x00800000) +-#define MCF_CAN_CANMCR_FRZACK (0x01000000) +-#define MCF_CAN_CANMCR_SOFTRST (0x02000000) +-#define MCF_CAN_CANMCR_HALT (0x10000000) +-#define MCF_CAN_CANMCR_FRZ (0x40000000) +-#define MCF_CAN_CANMCR_MDIS (0x80000000) +- +-/* Bit definitions and macros for MCF_CAN_CANCTRL */ +-#define MCF_CAN_CANCTRL_PROPSEG(x) (((x)&0x00000007)<<0) +-#define MCF_CAN_CANCTRL_LOM (0x00000008) +-#define MCF_CAN_CANCTRL_LBUF (0x00000010) +-#define MCF_CAN_CANCTRL_TSYNC (0x00000020) +-#define MCF_CAN_CANCTRL_BOFFREC (0x00000040) +-#define MCF_CAN_CANCTRL_SAMP (0x00000080) +-#define MCF_CAN_CANCTRL_LPB (0x00001000) +-#define MCF_CAN_CANCTRL_CLKSRC (0x00002000) +-#define MCF_CAN_CANCTRL_ERRMSK (0x00004000) +-#define MCF_CAN_CANCTRL_BOFFMSK (0x00008000) +-#define MCF_CAN_CANCTRL_PSEG2(x) (((x)&0x00000007)<<16) +-#define MCF_CAN_CANCTRL_PSEG1(x) (((x)&0x00000007)<<19) +-#define MCF_CAN_CANCTRL_RJW(x) (((x)&0x00000003)<<22) +-#define MCF_CAN_CANCTRL_PRESDIV(x) (((x)&0x000000FF)<<24) +- +-/* Bit definitions and macros for MCF_CAN_TIMER */ +-#define MCF_CAN_TIMER_TIMER(x) (((x)&0x0000FFFF)<<0) +- +-/* Bit definitions and macros for MCF_CAN_RXGMASK */ +-#define MCF_CAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0) +- +-/* Bit definitions and macros for MCF_CAN_RX14MASK */ +-#define MCF_CAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0) +- +-/* Bit definitions and macros for MCF_CAN_RX15MASK */ +-#define MCF_CAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0) +- +-/* Bit definitions and macros for MCF_CAN_ERRCNT */ +-#define MCF_CAN_ERRCNT_TXECTR(x) (((x)&0x000000FF)<<0) +-#define MCF_CAN_ERRCNT_RXECTR(x) (((x)&0x000000FF)<<8) +- +-/* Bit definitions and macros for MCF_CAN_ERRSTAT */ +-#define MCF_CAN_ERRSTAT_WAKINT (0x00000001) +-#define MCF_CAN_ERRSTAT_ERRINT (0x00000002) +-#define MCF_CAN_ERRSTAT_BOFFINT (0x00000004) +-#define MCF_CAN_ERRSTAT_FLTCONF(x) (((x)&0x00000003)<<4) +-#define MCF_CAN_ERRSTAT_TXRX (0x00000040) +-#define MCF_CAN_ERRSTAT_IDLE (0x00000080) +-#define MCF_CAN_ERRSTAT_RXWRN (0x00000100) +-#define MCF_CAN_ERRSTAT_TXWRN (0x00000200) +-#define MCF_CAN_ERRSTAT_STFERR (0x00000400) +-#define MCF_CAN_ERRSTAT_FRMERR (0x00000800) +-#define MCF_CAN_ERRSTAT_CRCERR (0x00001000) +-#define MCF_CAN_ERRSTAT_ACKERR (0x00002000) +-#define MCF_CAN_ERRSTAT_BITERR(x) (((x)&0x00000003)<<14) +-#define MCF_CAN_ERRSTAT_FLTCONF_ACTIVE (0x00000000) +-#define MCF_CAN_ERRSTAT_FLTCONF_PASSIVE (0x00000010) +-#define MCF_CAN_ERRSTAT_FLTCONF_BUSOFF (0x00000020) +- +-/* Bit definitions and macros for MCF_CAN_IMASK */ +-#define MCF_CAN_IMASK_BUF0M (0x0001) +-#define MCF_CAN_IMASK_BUF1M (0x0002) +-#define MCF_CAN_IMASK_BUF2M (0x0004) +-#define MCF_CAN_IMASK_BUF3M (0x0008) +-#define MCF_CAN_IMASK_BUF4M (0x0010) +-#define MCF_CAN_IMASK_BUF5M (0x0020) +-#define MCF_CAN_IMASK_BUF6M (0x0040) +-#define MCF_CAN_IMASK_BUF7M (0x0080) +-#define MCF_CAN_IMASK_BUF8M (0x0100) +-#define MCF_CAN_IMASK_BUF9M (0x0200) +-#define MCF_CAN_IMASK_BUF10M (0x0400) +-#define MCF_CAN_IMASK_BUF11M (0x0800) +-#define MCF_CAN_IMASK_BUF12M (0x1000) +-#define MCF_CAN_IMASK_BUF13M (0x2000) +-#define MCF_CAN_IMASK_BUF14M (0x4000) +-#define MCF_CAN_IMASK_BUF15M (0x8000) +- +-/* Bit definitions and macros for MCF_CAN_IFLAG */ +-#define MCF_CAN_IFLAG_BUF0I (0x0001) +-#define MCF_CAN_IFLAG_BUF1I (0x0002) +-#define MCF_CAN_IFLAG_BUF2I (0x0004) +-#define MCF_CAN_IFLAG_BUF3I (0x0008) +-#define MCF_CAN_IFLAG_BUF4I (0x0010) +-#define MCF_CAN_IFLAG_BUF5I (0x0020) +-#define MCF_CAN_IFLAG_BUF6I (0x0040) +-#define MCF_CAN_IFLAG_BUF7I (0x0080) +-#define MCF_CAN_IFLAG_BUF8I (0x0100) +-#define MCF_CAN_IFLAG_BUF9I (0x0200) +-#define MCF_CAN_IFLAG_BUF10I (0x0400) +-#define MCF_CAN_IFLAG_BUF11I (0x0800) +-#define MCF_CAN_IFLAG_BUF12I (0x1000) +-#define MCF_CAN_IFLAG_BUF13I (0x2000) +-#define MCF_CAN_IFLAG_BUF14I (0x4000) +-#define MCF_CAN_IFLAG_BUF15I (0x8000) +- +-#endif /* __MCF548X_CAN_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_ctm.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_ctm.h +deleted file mode 100644 +index 6c779ec..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_ctm.h ++++ /dev/null +@@ -1,88 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Common Timer Module +- */ +-#ifndef __MCF548X_CTM_H__ +-#define __MCF548X_CTM_H__ +- +-/* +- * Comm Timer Module (CTM) +- */ +- +-/* Register read/write macros */ +-#define MCF_CTM_CTCRF0 (*(vuint32_t*)(&__MBAR[0x007F00])) +-#define MCF_CTM_CTCRF1 (*(vuint32_t*)(&__MBAR[0x007F04])) +-#define MCF_CTM_CTCRF2 (*(vuint32_t*)(&__MBAR[0x007F08])) +-#define MCF_CTM_CTCRF3 (*(vuint32_t*)(&__MBAR[0x007F0C])) +-#define MCF_CTM_CTCRFn(x) (*(vuint32_t*)(&__MBAR[0x007F00+((x)*0x004)])) +-#define MCF_CTM_CTCRV4 (*(vuint32_t*)(&__MBAR[0x007F10])) +-#define MCF_CTM_CTCRV5 (*(vuint32_t*)(&__MBAR[0x007F14])) +-#define MCF_CTM_CTCRV6 (*(vuint32_t*)(&__MBAR[0x007F18])) +-#define MCF_CTM_CTCRV7 (*(vuint32_t*)(&__MBAR[0x007F1C])) +-#define MCF_CTM_CTCRVn(x) (*(vuint32_t*)(&__MBAR[0x007F10+((x)*0x004)])) +- +-/* Bit definitions and macros for MCF_CTM_CTCRFn */ +-#define MCF_CTM_CTCRFn_CRV(x) (((x)&0x0000FFFF)<<0) +-#define MCF_CTM_CTCRFn_S(x) (((x)&0x0000000F)<<16) +-#define MCF_CTM_CTCRFn_PCT(x) (((x)&0x00000007)<<20) +-#define MCF_CTM_CTCRFn_M (0x00800000) +-#define MCF_CTM_CTCRFn_IM (0x01000000) +-#define MCF_CTM_CTCRFn_I (0x80000000) +-#define MCF_CTM_CTCRFn_PCT_100 (0x00000000) +-#define MCF_CTM_CTCRFn_PCT_50 (0x00100000) +-#define MCF_CTM_CTCRFn_PCT_25 (0x00200000) +-#define MCF_CTM_CTCRFn_PCT_12p5 (0x00300000) +-#define MCF_CTM_CTCRFn_PCT_6p25 (0x00400000) +-#define MCF_CTM_CTCRFn_PCT_OFF (0x00500000) +-#define MCF_CTM_CTCRFn_S_CLK_1 (0x00000000) +-#define MCF_CTM_CTCRFn_S_CLK_2 (0x00010000) +-#define MCF_CTM_CTCRFn_S_CLK_4 (0x00020000) +-#define MCF_CTM_CTCRFn_S_CLK_8 (0x00030000) +-#define MCF_CTM_CTCRFn_S_CLK_16 (0x00040000) +-#define MCF_CTM_CTCRFn_S_CLK_32 (0x00050000) +-#define MCF_CTM_CTCRFn_S_CLK_64 (0x00060000) +-#define MCF_CTM_CTCRFn_S_CLK_128 (0x00070000) +-#define MCF_CTM_CTCRFn_S_CLK_256 (0x00080000) +- +-/* Bit definitions and macros for MCF_CTM_CTCRVn */ +-#define MCF_CTM_CTCRVn_CRV(x) (((x)&0x00FFFFFF)<<0) +-#define MCF_CTM_CTCRVn_PCT(x) (((x)&0x00000007)<<24) +-#define MCF_CTM_CTCRVn_M (0x08000000) +-#define MCF_CTM_CTCRVn_S(x) (((x)&0x0000000F)<<28) +-#define MCF_CTM_CTCRVn_S_CLK_1 (0x00000000) +-#define MCF_CTM_CTCRVn_S_CLK_2 (0x10000000) +-#define MCF_CTM_CTCRVn_S_CLK_4 (0x20000000) +-#define MCF_CTM_CTCRVn_S_CLK_8 (0x30000000) +-#define MCF_CTM_CTCRVn_S_CLK_16 (0x40000000) +-#define MCF_CTM_CTCRVn_S_CLK_32 (0x50000000) +-#define MCF_CTM_CTCRVn_S_CLK_64 (0x60000000) +-#define MCF_CTM_CTCRVn_S_CLK_128 (0x70000000) +-#define MCF_CTM_CTCRVn_S_CLK_256 (0x80000000) +-#define MCF_CTM_CTCRVn_PCT_100 (0x00000000) +-#define MCF_CTM_CTCRVn_PCT_50 (0x01000000) +-#define MCF_CTM_CTCRVn_PCT_25 (0x02000000) +-#define MCF_CTM_CTCRVn_PCT_12p5 (0x03000000) +-#define MCF_CTM_CTCRVn_PCT_6p25 (0x04000000) +-#define MCF_CTM_CTCRVn_PCT_OFF (0x05000000) +- +-#endif /* __MCF548X_CTM_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma.h +deleted file mode 100644 +index 4229c36..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma.h ++++ /dev/null +@@ -1,121 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Multichannel DMA +- */ +-#ifndef __MCF548X_DMA_H__ +-#define __MCF548X_DMA_H__ +- +-/* +- * Multi-Channel DMA (DMA) +- */ +- +-/* Register read/write macros */ +-#define MCF_DMA_DIPR (*(vuint32_t*)(&__MBAR[0x008014])) +-#define MCF_DMA_DIMR (*(vuint32_t*)(&__MBAR[0x008018])) +-#define MCF_DMA_IMCR (*(vuint32_t*)(&__MBAR[0x00805C])) +- +-/* Bit definitions and macros for MCF_DMA_DIPR */ +-#define MCF_DMA_DIPR_TASK0 (0x00000001) +-#define MCF_DMA_DIPR_TASK1 (0x00000002) +-#define MCF_DMA_DIPR_TASK2 (0x00000004) +-#define MCF_DMA_DIPR_TASK3 (0x00000008) +-#define MCF_DMA_DIPR_TASK4 (0x00000010) +-#define MCF_DMA_DIPR_TASK5 (0x00000020) +-#define MCF_DMA_DIPR_TASK6 (0x00000040) +-#define MCF_DMA_DIPR_TASK7 (0x00000080) +-#define MCF_DMA_DIPR_TASK8 (0x00000100) +-#define MCF_DMA_DIPR_TASK9 (0x00000200) +-#define MCF_DMA_DIPR_TASK10 (0x00000400) +-#define MCF_DMA_DIPR_TASK11 (0x00000800) +-#define MCF_DMA_DIPR_TASK12 (0x00001000) +-#define MCF_DMA_DIPR_TASK13 (0x00002000) +-#define MCF_DMA_DIPR_TASK14 (0x00004000) +-#define MCF_DMA_DIPR_TASK15 (0x00008000) +- +-/* Bit definitions and macros for MCF_DMA_DIMR */ +-#define MCF_DMA_DIMR_TASK0 (0x00000001) +-#define MCF_DMA_DIMR_TASK1 (0x00000002) +-#define MCF_DMA_DIMR_TASK2 (0x00000004) +-#define MCF_DMA_DIMR_TASK3 (0x00000008) +-#define MCF_DMA_DIMR_TASK4 (0x00000010) +-#define MCF_DMA_DIMR_TASK5 (0x00000020) +-#define MCF_DMA_DIMR_TASK6 (0x00000040) +-#define MCF_DMA_DIMR_TASK7 (0x00000080) +-#define MCF_DMA_DIMR_TASK8 (0x00000100) +-#define MCF_DMA_DIMR_TASK9 (0x00000200) +-#define MCF_DMA_DIMR_TASK10 (0x00000400) +-#define MCF_DMA_DIMR_TASK11 (0x00000800) +-#define MCF_DMA_DIMR_TASK12 (0x00001000) +-#define MCF_DMA_DIMR_TASK13 (0x00002000) +-#define MCF_DMA_DIMR_TASK14 (0x00004000) +-#define MCF_DMA_DIMR_TASK15 (0x00008000) +- +-/* Bit definitions and macros for MCF_DMA_IMCR */ +-#define MCF_DMA_IMCR_SRC16(x) (((x)&0x00000003)<<0) +-#define MCF_DMA_IMCR_SRC17(x) (((x)&0x00000003)<<2) +-#define MCF_DMA_IMCR_SRC18(x) (((x)&0x00000003)<<4) +-#define MCF_DMA_IMCR_SRC19(x) (((x)&0x00000003)<<6) +-#define MCF_DMA_IMCR_SRC20(x) (((x)&0x00000003)<<8) +-#define MCF_DMA_IMCR_SRC21(x) (((x)&0x00000003)<<10) +-#define MCF_DMA_IMCR_SRC22(x) (((x)&0x00000003)<<12) +-#define MCF_DMA_IMCR_SRC23(x) (((x)&0x00000003)<<14) +-#define MCF_DMA_IMCR_SRC24(x) (((x)&0x00000003)<<16) +-#define MCF_DMA_IMCR_SRC25(x) (((x)&0x00000003)<<18) +-#define MCF_DMA_IMCR_SRC26(x) (((x)&0x00000003)<<20) +-#define MCF_DMA_IMCR_SRC27(x) (((x)&0x00000003)<<22) +-#define MCF_DMA_IMCR_SRC28(x) (((x)&0x00000003)<<24) +-#define MCF_DMA_IMCR_SRC29(x) (((x)&0x00000003)<<26) +-#define MCF_DMA_IMCR_SRC30(x) (((x)&0x00000003)<<28) +-#define MCF_DMA_IMCR_SRC31(x) (((x)&0x00000003)<<30) +-#define MCF_DMA_IMCR_SRC16_FEC0RX (0x00000000) +-#define MCF_DMA_IMCR_SRC17_FEC0TX (0x00000000) +-#define MCF_DMA_IMCR_SRC18_FEC0RX (0x00000020) +-#define MCF_DMA_IMCR_SRC19_FEC0TX (0x00000080) +-#define MCF_DMA_IMCR_SRC20_FEC1RX (0x00000100) +-#define MCF_DMA_IMCR_SRC21_DREQ1 (0x00000000) +-#define MCF_DMA_IMCR_SRC21_FEC1TX (0x00000400) +-#define MCF_DMA_IMCR_SRC22_FEC0RX (0x00001000) +-#define MCF_DMA_IMCR_SRC23_FEC0TX (0x00004000) +-#define MCF_DMA_IMCR_SRC24_CTM0 (0x00010000) +-#define MCF_DMA_IMCR_SRC24_FEC1RX (0x00020000) +-#define MCF_DMA_IMCR_SRC25_CTM1 (0x00040000) +-#define MCF_DMA_IMCR_SRC25_FEC1TX (0x00080000) +-#define MCF_DMA_IMCR_SRC26_USBEP4 (0x00000000) +-#define MCF_DMA_IMCR_SRC26_CTM2 (0x00200000) +-#define MCF_DMA_IMCR_SRC27_USBEP5 (0x00000000) +-#define MCF_DMA_IMCR_SRC27_CTM3 (0x00800000) +-#define MCF_DMA_IMCR_SRC28_USBEP6 (0x00000000) +-#define MCF_DMA_IMCR_SRC28_CTM4 (0x01000000) +-#define MCF_DMA_IMCR_SRC28_DREQ1 (0x02000000) +-#define MCF_DMA_IMCR_SRC28_PSC2RX (0x03000000) +-#define MCF_DMA_IMCR_SRC29_DREQ1 (0x04000000) +-#define MCF_DMA_IMCR_SRC29_CTM5 (0x08000000) +-#define MCF_DMA_IMCR_SRC29_PSC2TX (0x0C000000) +-#define MCF_DMA_IMCR_SRC30_FEC1RX (0x00000000) +-#define MCF_DMA_IMCR_SRC30_CTM6 (0x10000000) +-#define MCF_DMA_IMCR_SRC30_PSC3RX (0x30000000) +-#define MCF_DMA_IMCR_SRC31_FEC1TX (0x00000000) +-#define MCF_DMA_IMCR_SRC31_CTM7 (0x80000000) +-#define MCF_DMA_IMCR_SRC31_PSC3TX (0xC0000000) +- +-#endif /* __MCF548X_DMA_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma_ereq.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma_ereq.h +deleted file mode 100644 +index 8eac58b..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dma_ereq.h ++++ /dev/null +@@ -1,62 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Multi-Channel DMA External Requests (DMA_EREQ) +- */ +-#ifndef __MCF548X_DMA_EREQ_H__ +-#define __MCF548X_DMA_EREQ_H__ +- +-/* +- * Multi-Channel DMA External Requests (DMA_EREQ) +- */ +- +-/* Register read/write macros */ +-#define MCF_DMA_EREQ_EREQBAR0 (*(vuint32_t*)(&__MBAR[0x000D00])) +-#define MCF_DMA_EREQ_EREQMASK0 (*(vuint32_t*)(&__MBAR[0x000D04])) +-#define MCF_DMA_EREQ_EREQCTRL0 (*(vuint32_t*)(&__MBAR[0x000D08])) +-#define MCF_DMA_EREQ_EREQBAR1 (*(vuint32_t*)(&__MBAR[0x000D10])) +-#define MCF_DMA_EREQ_EREQMASK1 (*(vuint32_t*)(&__MBAR[0x000D14])) +-#define MCF_DMA_EREQ_EREQCTRL1 (*(vuint32_t*)(&__MBAR[0x000D18])) +-#define MCF_DMA_EREQ_EREQBAR(x) (*(vuint32_t*)(&__MBAR[0x000D00+((x)*0x010)])) +-#define MCF_DMA_EREQ_EREQMASK(x) (*(vuint32_t*)(&__MBAR[0x000D04+((x)*0x010)])) +-#define MCF_DMA_EREQ_EREQCTRL(x) (*(vuint32_t*)(&__MBAR[0x000D08+((x)*0x010)])) +- +-/* Bit definitions and macros for MCF_DMA_EREQ_EREQCTRL */ +-#define MCF_DMA_EREQ_EREQCTRL_EN (0x00000001) +-#define MCF_DMA_EREQ_EREQCTRL_SYNC (0x00000002) +-#define MCF_DMA_EREQ_EREQCTRL_DACKWID(x) (((x)&0x00000003)<<2) +-#define MCF_DMA_EREQ_EREQCTRL_BSEL(x) (((x)&0x00000003)<<4) +-#define MCF_DMA_EREQ_EREQCTRL_MD(x) (((x)&0x00000003)<<6) +-#define MCF_DMA_EREQ_EREQCTRL_MD_IDLE (0x00000000) +-#define MCF_DMA_EREQ_EREQCTRL_MD_LEVEL (0x00000040) +-#define MCF_DMA_EREQ_EREQCTRL_MD_EDGE (0x00000080) +-#define MCF_DMA_EREQ_EREQCTRL_MD_PIPED (0x000000C0) +-#define MCF_DMA_EREQ_EREQCTRL_BSEL_MEM_WRITE (0x00000000) +-#define MCF_DMA_EREQ_EREQCTRL_BSEL_MEM_READ (0x00000010) +-#define MCF_DMA_EREQ_EREQCTRL_BSEL_PERIPH_WRITE (0x00000020) +-#define MCF_DMA_EREQ_EREQCTRL_BSEL_PERIPH_READ (0x00000030) +-#define MCF_DMA_EREQ_EREQCTRL_DACKWID_ONE (0x00000000) +-#define MCF_DMA_EREQ_EREQCTRL_DACKWID_TWO (0x00000004) +-#define MCF_DMA_EREQ_EREQCTRL_DACKWID_THREE (0x00000008) +-#define MCF_DMA_EREQ_EREQCTRL_DACKWID_FOUR (0x0000000C) +- +-#endif /* __MCF548X_DMA_EREQ_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dspi.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dspi.h +deleted file mode 100644 +index 889e75b..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_dspi.h ++++ /dev/null +@@ -1,155 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * DMA Serial Peripheral Interface (DSPI) +- */ +-#ifndef __MCF548X_DSPI_H__ +-#define __MCF548X_DSPI_H__ +- +-/* +- * DMA Serial Peripheral Interface (DSPI) +- */ +- +-/* Register read/write macros */ +-#define MCF_DSPI_DMCR (*(vuint32_t*)(&__MBAR[0x008A00])) +-#define MCF_DSPI_DTCR (*(vuint32_t*)(&__MBAR[0x008A08])) +-#define MCF_DSPI_DCTAR0 (*(vuint32_t*)(&__MBAR[0x008A0C])) +-#define MCF_DSPI_DCTAR1 (*(vuint32_t*)(&__MBAR[0x008A10])) +-#define MCF_DSPI_DCTAR2 (*(vuint32_t*)(&__MBAR[0x008A14])) +-#define MCF_DSPI_DCTAR3 (*(vuint32_t*)(&__MBAR[0x008A18])) +-#define MCF_DSPI_DCTAR4 (*(vuint32_t*)(&__MBAR[0x008A1C])) +-#define MCF_DSPI_DCTAR5 (*(vuint32_t*)(&__MBAR[0x008A20])) +-#define MCF_DSPI_DCTAR6 (*(vuint32_t*)(&__MBAR[0x008A24])) +-#define MCF_DSPI_DCTAR7 (*(vuint32_t*)(&__MBAR[0x008A28])) +-#define MCF_DSPI_DCTARn(x) (*(vuint32_t*)(&__MBAR[0x008A0C+((x)*0x004)])) +-#define MCF_DSPI_DSR (*(vuint32_t*)(&__MBAR[0x008A2C])) +-#define MCF_DSPI_DIRSR (*(vuint32_t*)(&__MBAR[0x008A30])) +-#define MCF_DSPI_DTFR (*(vuint32_t*)(&__MBAR[0x008A34])) +-#define MCF_DSPI_DRFR (*(vuint32_t*)(&__MBAR[0x008A38])) +-#define MCF_DSPI_DTFDR0 (*(vuint32_t*)(&__MBAR[0x008A3C])) +-#define MCF_DSPI_DTFDR1 (*(vuint32_t*)(&__MBAR[0x008A40])) +-#define MCF_DSPI_DTFDR2 (*(vuint32_t*)(&__MBAR[0x008A44])) +-#define MCF_DSPI_DTFDR3 (*(vuint32_t*)(&__MBAR[0x008A48])) +-#define MCF_DSPI_DTFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A3C+((x)*0x004)])) +-#define MCF_DSPI_DRFDR0 (*(vuint32_t*)(&__MBAR[0x008A7C])) +-#define MCF_DSPI_DRFDR1 (*(vuint32_t*)(&__MBAR[0x008A80])) +-#define MCF_DSPI_DRFDR2 (*(vuint32_t*)(&__MBAR[0x008A84])) +-#define MCF_DSPI_DRFDR3 (*(vuint32_t*)(&__MBAR[0x008A88])) +-#define MCF_DSPI_DRFDRn(x) (*(vuint32_t*)(&__MBAR[0x008A7C+((x)*0x004)])) +- +-/* Bit definitions and macros for MCF_DSPI_DMCR */ +-#define MCF_DSPI_DMCR_HALT (0x00000001) +-#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8) +-#define MCF_DSPI_DMCR_CRXF (0x00000400) +-#define MCF_DSPI_DMCR_CTXF (0x00000800) +-#define MCF_DSPI_DMCR_DRXF (0x00001000) +-#define MCF_DSPI_DMCR_DTXF (0x00002000) +-#define MCF_DSPI_DMCR_CSIS0 (0x00010000) +-#define MCF_DSPI_DMCR_CSIS2 (0x00040000) +-#define MCF_DSPI_DMCR_CSIS3 (0x00080000) +-#define MCF_DSPI_DMCR_CSIS5 (0x00200000) +-#define MCF_DSPI_DMCR_ROOE (0x01000000) +-#define MCF_DSPI_DMCR_PCSSE (0x02000000) +-#define MCF_DSPI_DMCR_MTFE (0x04000000) +-#define MCF_DSPI_DMCR_FRZ (0x08000000) +-#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28) +-#define MCF_DSPI_DMCR_CSCK (0x40000000) +-#define MCF_DSPI_DMCR_MSTR (0x80000000) +- +-/* Bit definitions and macros for MCF_DSPI_DTCR */ +-#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_DSPI_DCTARn */ +-#define MCF_DSPI_DCTARn_BR(x) (((x)&0x0000000F)<<0) +-#define MCF_DSPI_DCTARn_DT(x) (((x)&0x0000000F)<<4) +-#define MCF_DSPI_DCTARn_ASC(x) (((x)&0x0000000F)<<8) +-#define MCF_DSPI_DCTARn_CSSCK(x) (((x)&0x0000000F)<<12) +-#define MCF_DSPI_DCTARn_PBR(x) (((x)&0x00000003)<<16) +-#define MCF_DSPI_DCTARn_PDT(x) (((x)&0x00000003)<<18) +-#define MCF_DSPI_DCTARn_PASC(x) (((x)&0x00000003)<<20) +-#define MCF_DSPI_DCTARn_PCSSCK(x) (((x)&0x00000003)<<22) +-#define MCF_DSPI_DCTARn_LSBFE (0x01000000) +-#define MCF_DSPI_DCTARn_CPHA (0x02000000) +-#define MCF_DSPI_DCTARn_CPOL (0x04000000) +-#define MCF_DSPI_DCTARn_TRSZ(x) (((x)&0x0000000F)<<27) +-#define MCF_DSPI_DCTARn_PCSSCK_1CLK (0x00000000) +-#define MCF_DSPI_DCTARn_PCSSCK_3CLK (0x00400000) +-#define MCF_DSPI_DCTARn_PCSSCK_5CLK (0x00800000) +-#define MCF_DSPI_DCTARn_PCSSCK_7CLK (0x00A00000) +-#define MCF_DSPI_DCTARn_PASC_1CLK (0x00000000) +-#define MCF_DSPI_DCTARn_PASC_3CLK (0x00100000) +-#define MCF_DSPI_DCTARn_PASC_5CLK (0x00200000) +-#define MCF_DSPI_DCTARn_PASC_7CLK (0x00300000) +-#define MCF_DSPI_DCTARn_PDT_1CLK (0x00000000) +-#define MCF_DSPI_DCTARn_PDT_3CLK (0x00040000) +-#define MCF_DSPI_DCTARn_PDT_5CLK (0x00080000) +-#define MCF_DSPI_DCTARn_PDT_7CLK (0x000A0000) +-#define MCF_DSPI_DCTARn_PBR_1CLK (0x00000000) +-#define MCF_DSPI_DCTARn_PBR_3CLK (0x00010000) +-#define MCF_DSPI_DCTARn_PBR_5CLK (0x00020000) +-#define MCF_DSPI_DCTARn_PBR_7CLK (0x00030000) +- +-/* Bit definitions and macros for MCF_DSPI_DSR */ +-#define MCF_DSPI_DSR_RXPTR(x) (((x)&0x0000000F)<<0) +-#define MCF_DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4) +-#define MCF_DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8) +-#define MCF_DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12) +-#define MCF_DSPI_DSR_RFDF (0x00020000) +-#define MCF_DSPI_DSR_RFOF (0x00080000) +-#define MCF_DSPI_DSR_TFFF (0x02000000) +-#define MCF_DSPI_DSR_TFUF (0x08000000) +-#define MCF_DSPI_DSR_EOQF (0x10000000) +-#define MCF_DSPI_DSR_TXRXS (0x40000000) +-#define MCF_DSPI_DSR_TCF (0x80000000) +- +-/* Bit definitions and macros for MCF_DSPI_DIRSR */ +-#define MCF_DSPI_DIRSR_RFDFS (0x00010000) +-#define MCF_DSPI_DIRSR_RFDFE (0x00020000) +-#define MCF_DSPI_DIRSR_RFOFE (0x00080000) +-#define MCF_DSPI_DIRSR_TFFFS (0x01000000) +-#define MCF_DSPI_DIRSR_TFFFE (0x02000000) +-#define MCF_DSPI_DIRSR_TFUFE (0x08000000) +-#define MCF_DSPI_DIRSR_EOQFE (0x10000000) +-#define MCF_DSPI_DIRSR_TCFE (0x80000000) +- +-/* Bit definitions and macros for MCF_DSPI_DTFR */ +-#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF)<<0) +-#define MCF_DSPI_DTFR_CS0 (0x00010000) +-#define MCF_DSPI_DTFR_CS2 (0x00040000) +-#define MCF_DSPI_DTFR_CS3 (0x00080000) +-#define MCF_DSPI_DTFR_CS5 (0x00200000) +-#define MCF_DSPI_DTFR_CTCNT (0x04000000) +-#define MCF_DSPI_DTFR_EOQ (0x08000000) +-#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28) +-#define MCF_DSPI_DTFR_CONT (0x80000000) +- +-/* Bit definitions and macros for MCF_DSPI_DRFR */ +-#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF)<<0) +- +-/* Bit definitions and macros for MCF_DSPI_DTFDRn */ +-#define MCF_DSPI_DTFDRn_TXDATA(x) (((x)&0x0000FFFF)<<0) +-#define MCF_DSPI_DTFDRn_TXCMD(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_DSPI_DRFDRn */ +-#define MCF_DSPI_DRFDRn_RXDATA(x) (((x)&0x0000FFFF)<<0) +- +-#endif /* __MCF548X_DSPI_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_eport.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_eport.h +deleted file mode 100644 +index 94f724f..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_eport.h ++++ /dev/null +@@ -1,98 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Edge Port Module (EPORT) +- */ +-#ifndef __MCF548X_EPORT_H__ +-#define __MCF548X_EPORT_H__ +- +-/* +- * Edge Port Module (EPORT) +- */ +- +-/* Register read/write macros */ +-#define MCF_EPORT_EPPAR (*(vuint16_t*)(&__MBAR[0x000F00])) +-#define MCF_EPORT_EPDDR (*(vuint8_t *)(&__MBAR[0x000F04])) +-#define MCF_EPORT_EPIER (*(vuint8_t *)(&__MBAR[0x000F05])) +-#define MCF_EPORT_EPDR (*(vuint8_t *)(&__MBAR[0x000F08])) +-#define MCF_EPORT_EPPDR (*(vuint8_t *)(&__MBAR[0x000F09])) +-#define MCF_EPORT_EPFR (*(vuint8_t *)(&__MBAR[0x000F0C])) +- +-/* Bit definitions and macros for MCF_EPORT_EPPAR */ +-#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +-#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +-#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +-#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +-#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +-#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +-#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +-#define MCF_EPORT_EPPAR_EPPAx_LEVEL (0) +-#define MCF_EPORT_EPPAR_EPPAx_RISING (1) +-#define MCF_EPORT_EPPAR_EPPAx_FALLING (2) +-#define MCF_EPORT_EPPAR_EPPAx_BOTH (3) +- +-/* Bit definitions and macros for MCF_EPORT_EPDDR */ +-#define MCF_EPORT_EPDDR_EPDD1 (0x02) +-#define MCF_EPORT_EPDDR_EPDD2 (0x04) +-#define MCF_EPORT_EPDDR_EPDD3 (0x08) +-#define MCF_EPORT_EPDDR_EPDD4 (0x10) +-#define MCF_EPORT_EPDDR_EPDD5 (0x20) +-#define MCF_EPORT_EPDDR_EPDD6 (0x40) +-#define MCF_EPORT_EPDDR_EPDD7 (0x80) +- +-/* Bit definitions and macros for MCF_EPORT_EPIER */ +-#define MCF_EPORT_EPIER_EPIE1 (0x02) +-#define MCF_EPORT_EPIER_EPIE2 (0x04) +-#define MCF_EPORT_EPIER_EPIE3 (0x08) +-#define MCF_EPORT_EPIER_EPIE4 (0x10) +-#define MCF_EPORT_EPIER_EPIE5 (0x20) +-#define MCF_EPORT_EPIER_EPIE6 (0x40) +-#define MCF_EPORT_EPIER_EPIE7 (0x80) +- +-/* Bit definitions and macros for MCF_EPORT_EPDR */ +-#define MCF_EPORT_EPDR_EPD1 (0x02) +-#define MCF_EPORT_EPDR_EPD2 (0x04) +-#define MCF_EPORT_EPDR_EPD3 (0x08) +-#define MCF_EPORT_EPDR_EPD4 (0x10) +-#define MCF_EPORT_EPDR_EPD5 (0x20) +-#define MCF_EPORT_EPDR_EPD6 (0x40) +-#define MCF_EPORT_EPDR_EPD7 (0x80) +- +-/* Bit definitions and macros for MCF_EPORT_EPPDR */ +-#define MCF_EPORT_EPPDR_EPPD1 (0x02) +-#define MCF_EPORT_EPPDR_EPPD2 (0x04) +-#define MCF_EPORT_EPPDR_EPPD3 (0x08) +-#define MCF_EPORT_EPPDR_EPPD4 (0x10) +-#define MCF_EPORT_EPPDR_EPPD5 (0x20) +-#define MCF_EPORT_EPPDR_EPPD6 (0x40) +-#define MCF_EPORT_EPPDR_EPPD7 (0x80) +- +-/* Bit definitions and macros for MCF_EPORT_EPFR */ +-#define MCF_EPORT_EPFR_EPF1 (0x02) +-#define MCF_EPORT_EPFR_EPF2 (0x04) +-#define MCF_EPORT_EPFR_EPF3 (0x08) +-#define MCF_EPORT_EPFR_EPF4 (0x10) +-#define MCF_EPORT_EPFR_EPF5 (0x20) +-#define MCF_EPORT_EPFR_EPF6 (0x40) +-#define MCF_EPORT_EPFR_EPF7 (0x80) +- +-#endif /* __MCF548X_EPORT_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fbcs.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fbcs.h +deleted file mode 100644 +index 1e11944..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fbcs.h ++++ /dev/null +@@ -1,97 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * FlexBus Chip Selects (FBCS) +- */ +-#ifndef __MCF548X_FBCS_H__ +-#define __MCF548X_FBCS_H__ +- +-/* +- * FlexBus Chip Selects (FBCS) +- */ +- +-/* Register read/write macros */ +-#define MCF_FBCS_CSAR0 (*(vuint32_t*)(&__MBAR[0x000500])) +-#define MCF_FBCS_CSMR0 (*(vuint32_t*)(&__MBAR[0x000504])) +-#define MCF_FBCS_CSCR0 (*(vuint32_t*)(&__MBAR[0x000508])) +-#define MCF_FBCS_CSAR1 (*(vuint32_t*)(&__MBAR[0x00050C])) +-#define MCF_FBCS_CSMR1 (*(vuint32_t*)(&__MBAR[0x000510])) +-#define MCF_FBCS_CSCR1 (*(vuint32_t*)(&__MBAR[0x000514])) +-#define MCF_FBCS_CSAR2 (*(vuint32_t*)(&__MBAR[0x000518])) +-#define MCF_FBCS_CSMR2 (*(vuint32_t*)(&__MBAR[0x00051C])) +-#define MCF_FBCS_CSCR2 (*(vuint32_t*)(&__MBAR[0x000520])) +-#define MCF_FBCS_CSAR3 (*(vuint32_t*)(&__MBAR[0x000524])) +-#define MCF_FBCS_CSMR3 (*(vuint32_t*)(&__MBAR[0x000528])) +-#define MCF_FBCS_CSCR3 (*(vuint32_t*)(&__MBAR[0x00052C])) +-#define MCF_FBCS_CSAR4 (*(vuint32_t*)(&__MBAR[0x000530])) +-#define MCF_FBCS_CSMR4 (*(vuint32_t*)(&__MBAR[0x000534])) +-#define MCF_FBCS_CSCR4 (*(vuint32_t*)(&__MBAR[0x000538])) +-#define MCF_FBCS_CSAR5 (*(vuint32_t*)(&__MBAR[0x00053C])) +-#define MCF_FBCS_CSMR5 (*(vuint32_t*)(&__MBAR[0x000540])) +-#define MCF_FBCS_CSCR5 (*(vuint32_t*)(&__MBAR[0x000544])) +-#define MCF_FBCS_CSAR(x) (*(vuint32_t*)(&__MBAR[0x000500+((x)*0x00C)])) +-#define MCF_FBCS_CSMR(x) (*(vuint32_t*)(&__MBAR[0x000504+((x)*0x00C)])) +-#define MCF_FBCS_CSCR(x) (*(vuint32_t*)(&__MBAR[0x000508+((x)*0x00C)])) +- +-/* Bit definitions and macros for MCF_FBCS_CSAR */ +-#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) +- +-/* Bit definitions and macros for MCF_FBCS_CSMR */ +-#define MCF_FBCS_CSMR_V (0x00000001) +-#define MCF_FBCS_CSMR_WP (0x00000100) +-#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +-#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +-#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +-#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +-#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +-#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +-#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) +-#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) +-#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) +-#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) +-#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) +-#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) +-#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) +-#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) +-#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) +-#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) +-#define MCF_FBCS_CSMR_BAM_512K (0x00070000) +-#define MCF_FBCS_CSMR_BAM_256K (0x00030000) +-#define MCF_FBCS_CSMR_BAM_128K (0x00010000) +-#define MCF_FBCS_CSMR_BAM_64K (0x00000000) +- +-/* Bit definitions and macros for MCF_FBCS_CSCR */ +-#define MCF_FBCS_CSCR_BSTW (0x00000008) +-#define MCF_FBCS_CSCR_BSTR (0x00000010) +-#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) +-#define MCF_FBCS_CSCR_AA (0x00000100) +-#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) +-#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) +-#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) +-#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) +-#define MCF_FBCS_CSCR_SWSEN (0x00800000) +-#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) +-#define MCF_FBCS_CSCR_PS_8 (0x0040) +-#define MCF_FBCS_CSCR_PS_16 (0x0080) +-#define MCF_FBCS_CSCR_PS_32 (0x0000) +- +-#endif /* __MCF548X_FBCS_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fec.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fec.h +deleted file mode 100644 +index 738abd8..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_fec.h ++++ /dev/null +@@ -1,623 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Fast Ethernet Controller (FEC) +- */ +-#ifndef __MCF548X_FEC_H__ +-#define __MCF548X_FEC_H__ +- +-/* +- * Fast Ethernet Controller (FEC) +- */ +- +-/* Register read/write macros */ +-#define MCF_FEC_EIR0 (*(vuint32_t*)(&__MBAR[0x009004])) +-#define MCF_FEC_EIMR0 (*(vuint32_t*)(&__MBAR[0x009008])) +-#define MCF_FEC_ECR0 (*(vuint32_t*)(&__MBAR[0x009024])) +-#define MCF_FEC_MMFR0 (*(vuint32_t*)(&__MBAR[0x009040])) +-#define MCF_FEC_MSCR0 (*(vuint32_t*)(&__MBAR[0x009044])) +-#define MCF_FEC_MIBC0 (*(vuint32_t*)(&__MBAR[0x009064])) +-#define MCF_FEC_RCR0 (*(vuint32_t*)(&__MBAR[0x009084])) +-#define MCF_FEC_R_HASH0 (*(vuint32_t*)(&__MBAR[0x009088])) +-#define MCF_FEC_TCR0 (*(vuint32_t*)(&__MBAR[0x0090C4])) +-#define MCF_FEC_PALR0 (*(vuint32_t*)(&__MBAR[0x0090E4])) +-#define MCF_FEC_PAUR0 (*(vuint32_t*)(&__MBAR[0x0090E8])) +-#define MCF_FEC_OPD0 (*(vuint32_t*)(&__MBAR[0x0090EC])) +-#define MCF_FEC_IAUR0 (*(vuint32_t*)(&__MBAR[0x009118])) +-#define MCF_FEC_IALR0 (*(vuint32_t*)(&__MBAR[0x00911C])) +-#define MCF_FEC_GAUR0 (*(vuint32_t*)(&__MBAR[0x009120])) +-#define MCF_FEC_GALR0 (*(vuint32_t*)(&__MBAR[0x009124])) +-#define MCF_FEC_FECTFWR0 (*(vuint32_t*)(&__MBAR[0x009144])) +-#define MCF_FEC_FECRFDR0 (*(vuint32_t*)(&__MBAR[0x009184])) +-#define MCF_FEC_FECRFSR0 (*(vuint32_t*)(&__MBAR[0x009188])) +-#define MCF_FEC_FECRFCR0 (*(vuint32_t*)(&__MBAR[0x00918C])) +-#define MCF_FEC_FECRLRFP0 (*(vuint32_t*)(&__MBAR[0x009190])) +-#define MCF_FEC_FECRLWFP0 (*(vuint32_t*)(&__MBAR[0x009194])) +-#define MCF_FEC_FECRFAR0 (*(vuint32_t*)(&__MBAR[0x009198])) +-#define MCF_FEC_FECRFRP0 (*(vuint32_t*)(&__MBAR[0x00919C])) +-#define MCF_FEC_FECRFWP0 (*(vuint32_t*)(&__MBAR[0x0091A0])) +-#define MCF_FEC_FECTFDR0 (*(vuint32_t*)(&__MBAR[0x0091A4])) +-#define MCF_FEC_FECTFSR0 (*(vuint32_t*)(&__MBAR[0x0091A8])) +-#define MCF_FEC_FECTFCR0 (*(vuint32_t*)(&__MBAR[0x0091AC])) +-#define MCF_FEC_FECTLRFP0 (*(vuint32_t*)(&__MBAR[0x0091B0])) +-#define MCF_FEC_FECTLWFP0 (*(vuint32_t*)(&__MBAR[0x0091B4])) +-#define MCF_FEC_FECTFAR0 (*(vuint32_t*)(&__MBAR[0x0091B8])) +-#define MCF_FEC_FECTFRP0 (*(vuint32_t*)(&__MBAR[0x0091BC])) +-#define MCF_FEC_FECTFWP0 (*(vuint32_t*)(&__MBAR[0x0091C0])) +-#define MCF_FEC_FRST0 (*(vuint32_t*)(&__MBAR[0x0091C4])) +-#define MCF_FEC_CTCWR0 (*(vuint32_t*)(&__MBAR[0x0091C8])) +-#define MCF_FEC_RMON_T_DROP0 (*(vuint32_t*)(&__MBAR[0x009200])) +-#define MCF_FEC_RMON_T_PACKETS0 (*(vuint32_t*)(&__MBAR[0x009204])) +-#define MCF_FEC_RMON_T_BC_PKT0 (*(vuint32_t*)(&__MBAR[0x009208])) +-#define MCF_FEC_RMON_T_MC_PKT0 (*(vuint32_t*)(&__MBAR[0x00920C])) +-#define MCF_FEC_RMON_T_CRC_ALIGN0 (*(vuint32_t*)(&__MBAR[0x009210])) +-#define MCF_FEC_RMON_T_UNDERSIZE0 (*(vuint32_t*)(&__MBAR[0x009214])) +-#define MCF_FEC_RMON_T_OVERSIZE0 (*(vuint32_t*)(&__MBAR[0x009218])) +-#define MCF_FEC_RMON_T_FRAG0 (*(vuint32_t*)(&__MBAR[0x00921C])) +-#define MCF_FEC_RMON_T_JAB0 (*(vuint32_t*)(&__MBAR[0x009220])) +-#define MCF_FEC_RMON_T_COL0 (*(vuint32_t*)(&__MBAR[0x009224])) +-#define MCF_FEC_RMON_T_P640 (*(vuint32_t*)(&__MBAR[0x009228])) +-#define MCF_FEC_RMON_T_P65TO1270 (*(vuint32_t*)(&__MBAR[0x00922C])) +-#define MCF_FEC_RMON_T_P128TO2550 (*(vuint32_t*)(&__MBAR[0x009230])) +-#define MCF_FEC_RMON_T_P256TO5110 (*(vuint32_t*)(&__MBAR[0x009234])) +-#define MCF_FEC_RMON_T_P512TO10230 (*(vuint32_t*)(&__MBAR[0x009238])) +-#define MCF_FEC_RMON_T_P1024TO20470 (*(vuint32_t*)(&__MBAR[0x00923C])) +-#define MCF_FEC_RMON_T_P_GTE20480 (*(vuint32_t*)(&__MBAR[0x009240])) +-#define MCF_FEC_RMON_T_OCTETS0 (*(vuint32_t*)(&__MBAR[0x009244])) +-#define MCF_FEC_IEEE_T_DROP0 (*(vuint32_t*)(&__MBAR[0x009248])) +-#define MCF_FEC_IEEE_T_FRAME_OK0 (*(vuint32_t*)(&__MBAR[0x00924C])) +-#define MCF_FEC_IEEE_T_1COL0 (*(vuint32_t*)(&__MBAR[0x009250])) +-#define MCF_FEC_IEEE_T_MCOL0 (*(vuint32_t*)(&__MBAR[0x009254])) +-#define MCF_FEC_IEEE_T_DEF0 (*(vuint32_t*)(&__MBAR[0x009258])) +-#define MCF_FEC_IEEE_T_LCOL0 (*(vuint32_t*)(&__MBAR[0x00925C])) +-#define MCF_FEC_IEEE_T_EXCOL0 (*(vuint32_t*)(&__MBAR[0x009260])) +-#define MCF_FEC_IEEE_T_MACERR0 (*(vuint32_t*)(&__MBAR[0x009264])) +-#define MCF_FEC_IEEE_T_CSERR0 (*(vuint32_t*)(&__MBAR[0x009268])) +-#define MCF_FEC_IEEE_T_SQE0 (*(vuint32_t*)(&__MBAR[0x00926C])) +-#define MCF_FEC_IEEE_T_FDXFC0 (*(vuint32_t*)(&__MBAR[0x009270])) +-#define MCF_FEC_IEEE_T_OCTETS_OK0 (*(vuint32_t*)(&__MBAR[0x009274])) +-#define MCF_FEC_RMON_R_DROP0 (*(vuint32_t*)(&__MBAR[0x009280])) +-#define MCF_FEC_RMON_R_PACKETS0 (*(vuint32_t*)(&__MBAR[0x009284])) +-#define MCF_FEC_RMON_R_BC_PKT0 (*(vuint32_t*)(&__MBAR[0x009288])) +-#define MCF_FEC_RMON_R_MC_PKT0 (*(vuint32_t*)(&__MBAR[0x00928C])) +-#define MCF_FEC_RMON_R_CRC_ALIGN0 (*(vuint32_t*)(&__MBAR[0x009290])) +-#define MCF_FEC_RMON_R_UNDERSIZE0 (*(vuint32_t*)(&__MBAR[0x009294])) +-#define MCF_FEC_RMON_R_OVERSIZE0 (*(vuint32_t*)(&__MBAR[0x009298])) +-#define MCF_FEC_RMON_R_FRAG0 (*(vuint32_t*)(&__MBAR[0x00929C])) +-#define MCF_FEC_RMON_R_JAB0 (*(vuint32_t*)(&__MBAR[0x0092A0])) +-#define MCF_FEC_RMON_R_RESVD_00 (*(vuint32_t*)(&__MBAR[0x0092A4])) +-#define MCF_FEC_RMON_R_P640 (*(vuint32_t*)(&__MBAR[0x0092A8])) +-#define MCF_FEC_RMON_R_P65TO1270 (*(vuint32_t*)(&__MBAR[0x0092AC])) +-#define MCF_FEC_RMON_R_P128TO2550 (*(vuint32_t*)(&__MBAR[0x0092B0])) +-#define MCF_FEC_RMON_R_P256TO5110 (*(vuint32_t*)(&__MBAR[0x0092B4])) +-#define MCF_FEC_RMON_R_512TO10230 (*(vuint32_t*)(&__MBAR[0x0092B8])) +-#define MCF_FEC_RMON_R_1024TO20470 (*(vuint32_t*)(&__MBAR[0x0092BC])) +-#define MCF_FEC_RMON_R_P_GTE20480 (*(vuint32_t*)(&__MBAR[0x0092C0])) +-#define MCF_FEC_RMON_R_OCTETS0 (*(vuint32_t*)(&__MBAR[0x0092C4])) +-#define MCF_FEC_IEEE_R_DROP0 (*(vuint32_t*)(&__MBAR[0x0092C8])) +-#define MCF_FEC_IEEE_R_FRAME_OK0 (*(vuint32_t*)(&__MBAR[0x0092CC])) +-#define MCF_FEC_IEEE_R_CRC0 (*(vuint32_t*)(&__MBAR[0x0092D0])) +-#define MCF_FEC_IEEE_R_ALIGN0 (*(vuint32_t*)(&__MBAR[0x0092D4])) +-#define MCF_FEC_IEEE_R_MACERR0 (*(vuint32_t*)(&__MBAR[0x0092D8])) +-#define MCF_FEC_IEEE_R_FDXFC0 (*(vuint32_t*)(&__MBAR[0x0092DC])) +-#define MCF_FEC_IEEE_R_OCTETS_OK0 (*(vuint32_t*)(&__MBAR[0x0092E0])) +-#define MCF_FEC_EIR1 (*(vuint32_t*)(&__MBAR[0x009804])) +-#define MCF_FEC_EIMR1 (*(vuint32_t*)(&__MBAR[0x009808])) +-#define MCF_FEC_ECR1 (*(vuint32_t*)(&__MBAR[0x009824])) +-#define MCF_FEC_MMFR1 (*(vuint32_t*)(&__MBAR[0x009840])) +-#define MCF_FEC_MSCR1 (*(vuint32_t*)(&__MBAR[0x009844])) +-#define MCF_FEC_MIBC1 (*(vuint32_t*)(&__MBAR[0x009864])) +-#define MCF_FEC_RCR1 (*(vuint32_t*)(&__MBAR[0x009884])) +-#define MCF_FEC_R_HASH1 (*(vuint32_t*)(&__MBAR[0x009888])) +-#define MCF_FEC_TCR1 (*(vuint32_t*)(&__MBAR[0x0098C4])) +-#define MCF_FEC_PALR1 (*(vuint32_t*)(&__MBAR[0x0098E4])) +-#define MCF_FEC_PAUR1 (*(vuint32_t*)(&__MBAR[0x0098E8])) +-#define MCF_FEC_OPD1 (*(vuint32_t*)(&__MBAR[0x0098EC])) +-#define MCF_FEC_IAUR1 (*(vuint32_t*)(&__MBAR[0x009918])) +-#define MCF_FEC_IALR1 (*(vuint32_t*)(&__MBAR[0x00991C])) +-#define MCF_FEC_GAUR1 (*(vuint32_t*)(&__MBAR[0x009920])) +-#define MCF_FEC_GALR1 (*(vuint32_t*)(&__MBAR[0x009924])) +-#define MCF_FEC_FECTFWR1 (*(vuint32_t*)(&__MBAR[0x009944])) +-#define MCF_FEC_FECRFDR1 (*(vuint32_t*)(&__MBAR[0x009984])) +-#define MCF_FEC_FECRFSR1 (*(vuint32_t*)(&__MBAR[0x009988])) +-#define MCF_FEC_FECRFCR1 (*(vuint32_t*)(&__MBAR[0x00998C])) +-#define MCF_FEC_FECRLRFP1 (*(vuint32_t*)(&__MBAR[0x009990])) +-#define MCF_FEC_FECRLWFP1 (*(vuint32_t*)(&__MBAR[0x009994])) +-#define MCF_FEC_FECRFAR1 (*(vuint32_t*)(&__MBAR[0x009998])) +-#define MCF_FEC_FECRFRP1 (*(vuint32_t*)(&__MBAR[0x00999C])) +-#define MCF_FEC_FECRFWP1 (*(vuint32_t*)(&__MBAR[0x0099A0])) +-#define MCF_FEC_FECTFDR1 (*(vuint32_t*)(&__MBAR[0x0099A4])) +-#define MCF_FEC_FECTFSR1 (*(vuint32_t*)(&__MBAR[0x0099A8])) +-#define MCF_FEC_FECTFCR1 (*(vuint32_t*)(&__MBAR[0x0099AC])) +-#define MCF_FEC_FECTLRFP1 (*(vuint32_t*)(&__MBAR[0x0099B0])) +-#define MCF_FEC_FECTLWFP1 (*(vuint32_t*)(&__MBAR[0x0099B4])) +-#define MCF_FEC_FECTFAR1 (*(vuint32_t*)(&__MBAR[0x0099B8])) +-#define MCF_FEC_FECTFRP1 (*(vuint32_t*)(&__MBAR[0x0099BC])) +-#define MCF_FEC_FECTFWP1 (*(vuint32_t*)(&__MBAR[0x0099C0])) +-#define MCF_FEC_FRST1 (*(vuint32_t*)(&__MBAR[0x0099C4])) +-#define MCF_FEC_CTCWR1 (*(vuint32_t*)(&__MBAR[0x0099C8])) +-#define MCF_FEC_RMON_T_DROP1 (*(vuint32_t*)(&__MBAR[0x009A00])) +-#define MCF_FEC_RMON_T_PACKETS1 (*(vuint32_t*)(&__MBAR[0x009A04])) +-#define MCF_FEC_RMON_T_BC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A08])) +-#define MCF_FEC_RMON_T_MC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A0C])) +-#define MCF_FEC_RMON_T_CRC_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009A10])) +-#define MCF_FEC_RMON_T_UNDERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A14])) +-#define MCF_FEC_RMON_T_OVERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A18])) +-#define MCF_FEC_RMON_T_FRAG1 (*(vuint32_t*)(&__MBAR[0x009A1C])) +-#define MCF_FEC_RMON_T_JAB1 (*(vuint32_t*)(&__MBAR[0x009A20])) +-#define MCF_FEC_RMON_T_COL1 (*(vuint32_t*)(&__MBAR[0x009A24])) +-#define MCF_FEC_RMON_T_P641 (*(vuint32_t*)(&__MBAR[0x009A28])) +-#define MCF_FEC_RMON_T_P65TO1271 (*(vuint32_t*)(&__MBAR[0x009A2C])) +-#define MCF_FEC_RMON_T_P128TO2551 (*(vuint32_t*)(&__MBAR[0x009A30])) +-#define MCF_FEC_RMON_T_P256TO5111 (*(vuint32_t*)(&__MBAR[0x009A34])) +-#define MCF_FEC_RMON_T_P512TO10231 (*(vuint32_t*)(&__MBAR[0x009A38])) +-#define MCF_FEC_RMON_T_P1024TO20471 (*(vuint32_t*)(&__MBAR[0x009A3C])) +-#define MCF_FEC_RMON_T_P_GTE20481 (*(vuint32_t*)(&__MBAR[0x009A40])) +-#define MCF_FEC_RMON_T_OCTETS1 (*(vuint32_t*)(&__MBAR[0x009A44])) +-#define MCF_FEC_IEEE_T_DROP1 (*(vuint32_t*)(&__MBAR[0x009A48])) +-#define MCF_FEC_IEEE_T_FRAME_OK1 (*(vuint32_t*)(&__MBAR[0x009A4C])) +-#define MCF_FEC_IEEE_T_1COL1 (*(vuint32_t*)(&__MBAR[0x009A50])) +-#define MCF_FEC_IEEE_T_MCOL1 (*(vuint32_t*)(&__MBAR[0x009A54])) +-#define MCF_FEC_IEEE_T_DEF1 (*(vuint32_t*)(&__MBAR[0x009A58])) +-#define MCF_FEC_IEEE_T_LCOL1 (*(vuint32_t*)(&__MBAR[0x009A5C])) +-#define MCF_FEC_IEEE_T_EXCOL1 (*(vuint32_t*)(&__MBAR[0x009A60])) +-#define MCF_FEC_IEEE_T_MACERR1 (*(vuint32_t*)(&__MBAR[0x009A64])) +-#define MCF_FEC_IEEE_T_CSERR1 (*(vuint32_t*)(&__MBAR[0x009A68])) +-#define MCF_FEC_IEEE_T_SQE1 (*(vuint32_t*)(&__MBAR[0x009A6C])) +-#define MCF_FEC_IEEE_T_FDXFC1 (*(vuint32_t*)(&__MBAR[0x009A70])) +-#define MCF_FEC_IEEE_T_OCTETS_OK1 (*(vuint32_t*)(&__MBAR[0x009A74])) +-#define MCF_FEC_RMON_R_DROP1 (*(vuint32_t*)(&__MBAR[0x009A80])) +-#define MCF_FEC_RMON_R_PACKETS1 (*(vuint32_t*)(&__MBAR[0x009A84])) +-#define MCF_FEC_RMON_R_BC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A88])) +-#define MCF_FEC_RMON_R_MC_PKT1 (*(vuint32_t*)(&__MBAR[0x009A8C])) +-#define MCF_FEC_RMON_R_CRC_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009A90])) +-#define MCF_FEC_RMON_R_UNDERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A94])) +-#define MCF_FEC_RMON_R_OVERSIZE1 (*(vuint32_t*)(&__MBAR[0x009A98])) +-#define MCF_FEC_RMON_R_FRAG1 (*(vuint32_t*)(&__MBAR[0x009A9C])) +-#define MCF_FEC_RMON_R_JAB1 (*(vuint32_t*)(&__MBAR[0x009AA0])) +-#define MCF_FEC_RMON_R_RESVD_01 (*(vuint32_t*)(&__MBAR[0x009AA4])) +-#define MCF_FEC_RMON_R_P641 (*(vuint32_t*)(&__MBAR[0x009AA8])) +-#define MCF_FEC_RMON_R_P65TO1271 (*(vuint32_t*)(&__MBAR[0x009AAC])) +-#define MCF_FEC_RMON_R_P128TO2551 (*(vuint32_t*)(&__MBAR[0x009AB0])) +-#define MCF_FEC_RMON_R_P256TO5111 (*(vuint32_t*)(&__MBAR[0x009AB4])) +-#define MCF_FEC_RMON_R_512TO10231 (*(vuint32_t*)(&__MBAR[0x009AB8])) +-#define MCF_FEC_RMON_R_1024TO20471 (*(vuint32_t*)(&__MBAR[0x009ABC])) +-#define MCF_FEC_RMON_R_P_GTE20481 (*(vuint32_t*)(&__MBAR[0x009AC0])) +-#define MCF_FEC_RMON_R_OCTETS1 (*(vuint32_t*)(&__MBAR[0x009AC4])) +-#define MCF_FEC_IEEE_R_DROP1 (*(vuint32_t*)(&__MBAR[0x009AC8])) +-#define MCF_FEC_IEEE_R_FRAME_OK1 (*(vuint32_t*)(&__MBAR[0x009ACC])) +-#define MCF_FEC_IEEE_R_CRC1 (*(vuint32_t*)(&__MBAR[0x009AD0])) +-#define MCF_FEC_IEEE_R_ALIGN1 (*(vuint32_t*)(&__MBAR[0x009AD4])) +-#define MCF_FEC_IEEE_R_MACERR1 (*(vuint32_t*)(&__MBAR[0x009AD8])) +-#define MCF_FEC_IEEE_R_FDXFC1 (*(vuint32_t*)(&__MBAR[0x009ADC])) +-#define MCF_FEC_IEEE_R_OCTETS_OK1 (*(vuint32_t*)(&__MBAR[0x009AE0])) +-#define MCF_FEC_EIR(x) (*(vuint32_t*)(&__MBAR[0x009004+((x)*0x800)])) +-#define MCF_FEC_EIMR(x) (*(vuint32_t*)(&__MBAR[0x009008+((x)*0x800)])) +-#define MCF_FEC_ECR(x) (*(vuint32_t*)(&__MBAR[0x009024+((x)*0x800)])) +-#define MCF_FEC_MMFR(x) (*(vuint32_t*)(&__MBAR[0x009040+((x)*0x800)])) +-#define MCF_FEC_MSCR(x) (*(vuint32_t*)(&__MBAR[0x009044+((x)*0x800)])) +-#define MCF_FEC_MIBC(x) (*(vuint32_t*)(&__MBAR[0x009064+((x)*0x800)])) +-#define MCF_FEC_RCR(x) (*(vuint32_t*)(&__MBAR[0x009084+((x)*0x800)])) +-#define MCF_FEC_R_HASH(x) (*(vuint32_t*)(&__MBAR[0x009088+((x)*0x800)])) +-#define MCF_FEC_TCR(x) (*(vuint32_t*)(&__MBAR[0x0090C4+((x)*0x800)])) +-#define MCF_FEC_PALR(x) (*(vuint32_t*)(&__MBAR[0x0090E4+((x)*0x800)])) +-#define MCF_FEC_PAUR(x) (*(vuint32_t*)(&__MBAR[0x0090E8+((x)*0x800)])) +-#define MCF_FEC_OPD(x) (*(vuint32_t*)(&__MBAR[0x0090EC+((x)*0x800)])) +-#define MCF_FEC_IAUR(x) (*(vuint32_t*)(&__MBAR[0x009118+((x)*0x800)])) +-#define MCF_FEC_IALR(x) (*(vuint32_t*)(&__MBAR[0x00911C+((x)*0x800)])) +-#define MCF_FEC_GAUR(x) (*(vuint32_t*)(&__MBAR[0x009120+((x)*0x800)])) +-#define MCF_FEC_GALR(x) (*(vuint32_t*)(&__MBAR[0x009124+((x)*0x800)])) +-#define MCF_FEC_FECTFWR(x) (*(vuint32_t*)(&__MBAR[0x009144+((x)*0x800)])) +-#define MCF_FEC_FECRFDR(x) (*(vuint32_t*)(&__MBAR[0x009184+((x)*0x800)])) +-#define MCF_FEC_FECRFSR(x) (*(vuint32_t*)(&__MBAR[0x009188+((x)*0x800)])) +-#define MCF_FEC_FECRFCR(x) (*(vuint32_t*)(&__MBAR[0x00918C+((x)*0x800)])) +-#define MCF_FEC_FECRLRFP(x) (*(vuint32_t*)(&__MBAR[0x009190+((x)*0x800)])) +-#define MCF_FEC_FECRLWFP(x) (*(vuint32_t*)(&__MBAR[0x009194+((x)*0x800)])) +-#define MCF_FEC_FECRFAR(x) (*(vuint32_t*)(&__MBAR[0x009198+((x)*0x800)])) +-#define MCF_FEC_FECRFRP(x) (*(vuint32_t*)(&__MBAR[0x00919C+((x)*0x800)])) +-#define MCF_FEC_FECRFWP(x) (*(vuint32_t*)(&__MBAR[0x0091A0+((x)*0x800)])) +-#define MCF_FEC_FECTFDR(x) (*(vuint32_t*)(&__MBAR[0x0091A4+((x)*0x800)])) +-#define MCF_FEC_FECTFSR(x) (*(vuint32_t*)(&__MBAR[0x0091A8+((x)*0x800)])) +-#define MCF_FEC_FECTFCR(x) (*(vuint32_t*)(&__MBAR[0x0091AC+((x)*0x800)])) +-#define MCF_FEC_FECTLRFP(x) (*(vuint32_t*)(&__MBAR[0x0091B0+((x)*0x800)])) +-#define MCF_FEC_FECTLWFP(x) (*(vuint32_t*)(&__MBAR[0x0091B4+((x)*0x800)])) +-#define MCF_FEC_FECTFAR(x) (*(vuint32_t*)(&__MBAR[0x0091B8+((x)*0x800)])) +-#define MCF_FEC_FECTFRP(x) (*(vuint32_t*)(&__MBAR[0x0091BC+((x)*0x800)])) +-#define MCF_FEC_FECTFWP(x) (*(vuint32_t*)(&__MBAR[0x0091C0+((x)*0x800)])) +-#define MCF_FEC_FRST(x) (*(vuint32_t*)(&__MBAR[0x0091C4+((x)*0x800)])) +-#define MCF_FEC_CTCWR(x) (*(vuint32_t*)(&__MBAR[0x0091C8+((x)*0x800)])) +-#define MCF_FEC_RMON_T_DROP(x) (*(vuint32_t*)(&__MBAR[0x009200+((x)*0x800)])) +-#define MCF_FEC_RMON_T_PACKETS(x) (*(vuint32_t*)(&__MBAR[0x009204+((x)*0x800)])) +-#define MCF_FEC_RMON_T_BC_PKT(x) (*(vuint32_t*)(&__MBAR[0x009208+((x)*0x800)])) +-#define MCF_FEC_RMON_T_MC_PKT(x) (*(vuint32_t*)(&__MBAR[0x00920C+((x)*0x800)])) +-#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x009210+((x)*0x800)])) +-#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009214+((x)*0x800)])) +-#define MCF_FEC_RMON_T_OVERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009218+((x)*0x800)])) +-#define MCF_FEC_RMON_T_FRAG(x) (*(vuint32_t*)(&__MBAR[0x00921C+((x)*0x800)])) +-#define MCF_FEC_RMON_T_JAB(x) (*(vuint32_t*)(&__MBAR[0x009220+((x)*0x800)])) +-#define MCF_FEC_RMON_T_COL(x) (*(vuint32_t*)(&__MBAR[0x009224+((x)*0x800)])) +-#define MCF_FEC_RMON_T_P64(x) (*(vuint32_t*)(&__MBAR[0x009228+((x)*0x800)])) +-#define MCF_FEC_RMON_T_P65TO127(x) (*(vuint32_t*)(&__MBAR[0x00922C+((x)*0x800)])) +-#define MCF_FEC_RMON_T_P128TO255(x) (*(vuint32_t*)(&__MBAR[0x009230+((x)*0x800)])) +-#define MCF_FEC_RMON_T_P256TO511(x) (*(vuint32_t*)(&__MBAR[0x009234+((x)*0x800)])) +-#define MCF_FEC_RMON_T_P512TO1023(x) (*(vuint32_t*)(&__MBAR[0x009238+((x)*0x800)])) +-#define MCF_FEC_RMON_T_P1024TO2047(x) (*(vuint32_t*)(&__MBAR[0x00923C+((x)*0x800)])) +-#define MCF_FEC_RMON_T_P_GTE2048(x) (*(vuint32_t*)(&__MBAR[0x009240+((x)*0x800)])) +-#define MCF_FEC_RMON_T_OCTETS(x) (*(vuint32_t*)(&__MBAR[0x009244+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_DROP(x) (*(vuint32_t*)(&__MBAR[0x009248+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(vuint32_t*)(&__MBAR[0x00924C+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_1COL(x) (*(vuint32_t*)(&__MBAR[0x009250+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_MCOL(x) (*(vuint32_t*)(&__MBAR[0x009254+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_DEF(x) (*(vuint32_t*)(&__MBAR[0x009258+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_LCOL(x) (*(vuint32_t*)(&__MBAR[0x00925C+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_EXCOL(x) (*(vuint32_t*)(&__MBAR[0x009260+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_MACERR(x) (*(vuint32_t*)(&__MBAR[0x009264+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_CSERR(x) (*(vuint32_t*)(&__MBAR[0x009268+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_SQE(x) (*(vuint32_t*)(&__MBAR[0x00926C+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_FDXFC(x) (*(vuint32_t*)(&__MBAR[0x009270+((x)*0x800)])) +-#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(vuint32_t*)(&__MBAR[0x009274+((x)*0x800)])) +-#define MCF_FEC_RMON_R_DROP(x) (*(vuint32_t*)(&__MBAR[0x009280+((x)*0x800)])) +-#define MCF_FEC_RMON_R_PACKETS(x) (*(vuint32_t*)(&__MBAR[0x009284+((x)*0x800)])) +-#define MCF_FEC_RMON_R_BC_PKT(x) (*(vuint32_t*)(&__MBAR[0x009288+((x)*0x800)])) +-#define MCF_FEC_RMON_R_MC_PKT(x) (*(vuint32_t*)(&__MBAR[0x00928C+((x)*0x800)])) +-#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x009290+((x)*0x800)])) +-#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009294+((x)*0x800)])) +-#define MCF_FEC_RMON_R_OVERSIZE(x) (*(vuint32_t*)(&__MBAR[0x009298+((x)*0x800)])) +-#define MCF_FEC_RMON_R_FRAG(x) (*(vuint32_t*)(&__MBAR[0x00929C+((x)*0x800)])) +-#define MCF_FEC_RMON_R_JAB(x) (*(vuint32_t*)(&__MBAR[0x0092A0+((x)*0x800)])) +-#define MCF_FEC_RMON_R_RESVD_0(x) (*(vuint32_t*)(&__MBAR[0x0092A4+((x)*0x800)])) +-#define MCF_FEC_RMON_R_P64(x) (*(vuint32_t*)(&__MBAR[0x0092A8+((x)*0x800)])) +-#define MCF_FEC_RMON_R_P65TO127(x) (*(vuint32_t*)(&__MBAR[0x0092AC+((x)*0x800)])) +-#define MCF_FEC_RMON_R_P128TO255(x) (*(vuint32_t*)(&__MBAR[0x0092B0+((x)*0x800)])) +-#define MCF_FEC_RMON_R_P256TO511(x) (*(vuint32_t*)(&__MBAR[0x0092B4+((x)*0x800)])) +-#define MCF_FEC_RMON_R_512TO1023(x) (*(vuint32_t*)(&__MBAR[0x0092B8+((x)*0x800)])) +-#define MCF_FEC_RMON_R_1024TO2047(x) (*(vuint32_t*)(&__MBAR[0x0092BC+((x)*0x800)])) +-#define MCF_FEC_RMON_R_P_GTE2048(x) (*(vuint32_t*)(&__MBAR[0x0092C0+((x)*0x800)])) +-#define MCF_FEC_RMON_R_OCTETS(x) (*(vuint32_t*)(&__MBAR[0x0092C4+((x)*0x800)])) +-#define MCF_FEC_IEEE_R_DROP(x) (*(vuint32_t*)(&__MBAR[0x0092C8+((x)*0x800)])) +-#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(vuint32_t*)(&__MBAR[0x0092CC+((x)*0x800)])) +-#define MCF_FEC_IEEE_R_CRC(x) (*(vuint32_t*)(&__MBAR[0x0092D0+((x)*0x800)])) +-#define MCF_FEC_IEEE_R_ALIGN(x) (*(vuint32_t*)(&__MBAR[0x0092D4+((x)*0x800)])) +-#define MCF_FEC_IEEE_R_MACERR(x) (*(vuint32_t*)(&__MBAR[0x0092D8+((x)*0x800)])) +-#define MCF_FEC_IEEE_R_FDXFC(x) (*(vuint32_t*)(&__MBAR[0x0092DC+((x)*0x800)])) +-#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(vuint32_t*)(&__MBAR[0x0092E0+((x)*0x800)])) +- +-/* Bit definitions and macros for MCF_FEC_EIR */ +-#define MCF_FEC_EIR_RFERR (0x00020000) +-#define MCF_FEC_EIR_XFERR (0x00040000) +-#define MCF_FEC_EIR_XFUN (0x00080000) +-#define MCF_FEC_EIR_RL (0x00100000) +-#define MCF_FEC_EIR_LC (0x00200000) +-#define MCF_FEC_EIR_MII (0x00800000) +-#define MCF_FEC_EIR_TXF (0x08000000) +-#define MCF_FEC_EIR_GRA (0x10000000) +-#define MCF_FEC_EIR_BABT (0x20000000) +-#define MCF_FEC_EIR_BABR (0x40000000) +-#define MCF_FEC_EIR_HBERR (0x80000000) +-#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF) +- +-/* Bit definitions and macros for MCF_FEC_EIMR */ +-#define MCF_FEC_EIMR_RFERR (0x00020000) +-#define MCF_FEC_EIMR_XFERR (0x00040000) +-#define MCF_FEC_EIMR_XFUN (0x00080000) +-#define MCF_FEC_EIMR_RL (0x00100000) +-#define MCF_FEC_EIMR_LC (0x00200000) +-#define MCF_FEC_EIMR_MII (0x00800000) +-#define MCF_FEC_EIMR_TXF (0x08000000) +-#define MCF_FEC_EIMR_GRA (0x10000000) +-#define MCF_FEC_EIMR_BABT (0x20000000) +-#define MCF_FEC_EIMR_BABR (0x40000000) +-#define MCF_FEC_EIMR_HBERR (0x80000000) +-#define MCF_FEC_EIMR_MASK_ALL (0x00000000) +-#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF) +- +-/* Bit definitions and macros for MCF_FEC_ECR */ +-#define MCF_FEC_ECR_RESET (0x00000001) +-#define MCF_FEC_ECR_ETHER_EN (0x00000002) +- +-/* Bit definitions and macros for MCF_FEC_MMFR */ +-#define MCF_FEC_MMFR_DATA(x) (((x)&0x0000FFFF)<<0) +-#define MCF_FEC_MMFR_TA(x) (((x)&0x00000003)<<16) +-#define MCF_FEC_MMFR_RA(x) (((x)&0x0000001F)<<18) +-#define MCF_FEC_MMFR_PA(x) (((x)&0x0000001F)<<23) +-#define MCF_FEC_MMFR_OP(x) (((x)&0x00000003)<<28) +-#define MCF_FEC_MMFR_ST(x) (((x)&0x00000003)<<30) +-#define MCF_FEC_MMFR_ST_01 (0x40000000) +-#define MCF_FEC_MMFR_OP_READ (0x20000000) +-#define MCF_FEC_MMFR_OP_WRITE (0x10000000) +-#define MCF_FEC_MMFR_TA_10 (0x00020000) +- +-/* Bit definitions and macros for MCF_FEC_MSCR */ +-#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x0000003F)<<1) +-#define MCF_FEC_MSCR_DIS_PREAMBLE (0x00000080) +-#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<1) +-#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<1) +-#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<1) +-#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<1) +- +-/* Bit definitions and macros for MCF_FEC_MIBC */ +-#define MCF_FEC_MIBC_MIB_IDLE (0x40000000) +-#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000) +- +-/* Bit definitions and macros for MCF_FEC_RCR */ +-#define MCF_FEC_RCR_LOOP (0x00000001) +-#define MCF_FEC_RCR_DRT (0x00000002) +-#define MCF_FEC_RCR_MII_MODE (0x00000004) +-#define MCF_FEC_RCR_PROM (0x00000008) +-#define MCF_FEC_RCR_BC_REJ (0x00000010) +-#define MCF_FEC_RCR_FCE (0x00000020) +-#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x000007FF)<<16) +- +-/* Bit definitions and macros for MCF_FEC_R_HASH */ +-#define MCF_FEC_R_HASH_HASH(x) (((x)&0x0000003F)<<24) +-#define MCF_FEC_R_HASH_MULTCAST (0x40000000) +-#define MCF_FEC_R_HASH_FCE_DC (0x80000000) +- +-/* Bit definitions and macros for MCF_FEC_TCR */ +-#define MCF_FEC_TCR_GTS (0x00000001) +-#define MCF_FEC_TCR_HBC (0x00000002) +-#define MCF_FEC_TCR_FDEN (0x00000004) +-#define MCF_FEC_TCR_TFC_PAUSE (0x00000008) +-#define MCF_FEC_TCR_RFC_PAUSE (0x00000010) +- +-/* Bit definitions and macros for MCF_FEC_PAUR */ +-#define MCF_FEC_PAUR_TYPE(x) (((x)&0x0000FFFF)<<0) +-#define MCF_FEC_PAUR_PADDR2(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_FEC_OPD */ +-#define MCF_FEC_OPD_OP_PAUSE(x) (((x)&0x0000FFFF)<<0) +-#define MCF_FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_FEC_FECTFWR */ +-#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0x0000000F)<<0) +-#define MCF_FEC_FECTFWR_X_WMRK_64 (0x00000000) +-#define MCF_FEC_FECTFWR_X_WMRK_128 (0x00000001) +-#define MCF_FEC_FECTFWR_X_WMRK_192 (0x00000002) +-#define MCF_FEC_FECTFWR_X_WMRK_256 (0x00000003) +-#define MCF_FEC_FECTFWR_X_WMRK_320 (0x00000004) +-#define MCF_FEC_FECTFWR_X_WMRK_384 (0x00000005) +-#define MCF_FEC_FECTFWR_X_WMRK_448 (0x00000006) +-#define MCF_FEC_FECTFWR_X_WMRK_512 (0x00000007) +-#define MCF_FEC_FECTFWR_X_WMRK_576 (0x00000008) +-#define MCF_FEC_FECTFWR_X_WMRK_640 (0x00000009) +-#define MCF_FEC_FECTFWR_X_WMRK_704 (0x0000000A) +-#define MCF_FEC_FECTFWR_X_WMRK_768 (0x0000000B) +-#define MCF_FEC_FECTFWR_X_WMRK_832 (0x0000000C) +-#define MCF_FEC_FECTFWR_X_WMRK_896 (0x0000000D) +-#define MCF_FEC_FECTFWR_X_WMRK_960 (0x0000000E) +-#define MCF_FEC_FECTFWR_X_WMRK_1024 (0x0000000F) +- +-/* Bit definitions and macros for MCF_FEC_FECRFDR */ +-#define MCF_FEC_FECRFDR_ADDR0 ((void*)(&__MBAR[0x009184])) +-#define MCF_FEC_FECRFDR_ADDR1 ((void*)(&__MBAR[0x009984])) +-#define MCF_FEC_FECRFDR_ADDR(x) ((void*)(&__MBAR[0x009184+(0x800*ch)])) +- +-/* Bit definitions and macros for MCF_FEC_FECRFSR */ +-#define MCF_FEC_FECRFSR_EMT (0x00010000) +-#define MCF_FEC_FECRFSR_ALARM (0x00020000) +-#define MCF_FEC_FECRFSR_FU (0x00040000) +-#define MCF_FEC_FECRFSR_FR (0x00080000) +-#define MCF_FEC_FECRFSR_OF (0x00100000) +-#define MCF_FEC_FECRFSR_UF (0x00200000) +-#define MCF_FEC_FECRFSR_RXW (0x00400000) +-#define MCF_FEC_FECRFSR_FAE (0x00800000) +-#define MCF_FEC_FECRFSR_FRM(x) (((x)&0x0000000F)<<24) +-#define MCF_FEC_FECRFSR_IP (0x80000000) +- +-/* Bit definitions and macros for MCF_FEC_FECRFCR */ +-#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) +-#define MCF_FEC_FECRFCR_OF_MSK (0x00080000) +-#define MCF_FEC_FECRFCR_UF_MSK (0x00100000) +-#define MCF_FEC_FECRFCR_RXW_MSK (0x00200000) +-#define MCF_FEC_FECRFCR_FAE_MSK (0x00400000) +-#define MCF_FEC_FECRFCR_IP_MSK (0x00800000) +-#define MCF_FEC_FECRFCR_GR(x) (((x)&0x00000007)<<24) +-#define MCF_FEC_FECRFCR_FRM (0x08000000) +-#define MCF_FEC_FECRFCR_TIMER (0x10000000) +-#define MCF_FEC_FECRFCR_WFR (0x20000000) +-#define MCF_FEC_FECRFCR_WCTL (0x40000000) +- +-/* Bit definitions and macros for MCF_FEC_FECRLRFP */ +-#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECRLWFP */ +-#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECRFAR */ +-#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECRFRP */ +-#define MCF_FEC_FECRFRP_READ(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECRFWP */ +-#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECTFDR */ +-#define MCF_FEC_FECTFDR_TFCW_TC (0x04000000) +-#define MCF_FEC_FECTFDR_TFCW_ABC (0x02000000) +-#define MCF_FEC_FECTFDR_ADDR0 ((void*)(&__MBAR[0x0091A4])) +-#define MCF_FEC_FECTFDR_ADDR1 ((void*)(&__MBAR[0x0099A4])) +-#define MCF_FEC_FECTFDR_ADDR(x) ((void*)(&__MBAR[0x0091A4+(0x800*ch)])) +- +-/* Bit definitions and macros for MCF_FEC_FECTFSR */ +-#define MCF_FEC_FECTFSR_EMT (0x00010000) +-#define MCF_FEC_FECTFSR_ALARM (0x00020000) +-#define MCF_FEC_FECTFSR_FU (0x00040000) +-#define MCF_FEC_FECTFSR_FR (0x00080000) +-#define MCF_FEC_FECTFSR_OF (0x00100000) +-#define MCF_FEC_FECTFSR_UP (0x00200000) +-#define MCF_FEC_FECTFSR_FAE (0x00800000) +-#define MCF_FEC_FECTFSR_FRM(x) (((x)&0x0000000F)<<24) +-#define MCF_FEC_FECTFSR_TXW (0x40000000) +-#define MCF_FEC_FECTFSR_IP (0x80000000) +- +-/* Bit definitions and macros for MCF_FEC_FECTFCR */ +-#define MCF_FEC_FECTFCR_RESERVED (0x00200000) +-#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0x0000FFFF)<<0|0x00200000) +-#define MCF_FEC_FECTFCR_TXW_MSK (0x00240000) +-#define MCF_FEC_FECTFCR_OF_MSK (0x00280000) +-#define MCF_FEC_FECTFCR_UF_MSK (0x00300000) +-#define MCF_FEC_FECTFCR_FAE_MSK (0x00600000) +-#define MCF_FEC_FECTFCR_IP_MSK (0x00A00000) +-#define MCF_FEC_FECTFCR_GR(x) (((x)&0x00000007)<<24|0x00200000) +-#define MCF_FEC_FECTFCR_FRM (0x08200000) +-#define MCF_FEC_FECTFCR_TIMER (0x10200000) +-#define MCF_FEC_FECTFCR_WFR (0x20200000) +-#define MCF_FEC_FECTFCR_WCTL (0x40200000) +- +-/* Bit definitions and macros for MCF_FEC_FECTLRFP */ +-#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECTLWFP */ +-#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECTFAR */ +-#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECTFRP */ +-#define MCF_FEC_FECTFRP_READ(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FECTFWP */ +-#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_FEC_FRST */ +-#define MCF_FEC_FRST_RST_CTL (0x01000000) +-#define MCF_FEC_FRST_SW_RST (0x02000000) +- +-/* Bit definitions and macros for MCF_FEC_CTCWR */ +-#define MCF_FEC_CTCWR_TFCW (0x01000000) +-#define MCF_FEC_CTCWR_CRC (0x02000000) +- +- +-struct mcf54xx_fec +-{ +- vuint32_t RES0; +- vuint32_t eir; // 004 +- vuint32_t eimr; // 008 +- vuint32_t RES1[6]; +- vuint32_t ecr; // 024 +- vuint32_t RES2[6]; +- vuint32_t mmfr; // 040 +- vuint32_t mscr; // 044 +- vuint32_t RES3[7]; +- vuint32_t mibc; // 064 +- vuint32_t RES4[7]; +- vuint32_t rcr; // 084 +- vuint32_t r_hash; // 088 +- vuint32_t RES5[14]; +- vuint32_t tcr; // 0c4 +- vuint32_t RES6[7]; +- vuint32_t palr; // 0e4 +- vuint32_t paur; // 0e8 +- vuint32_t opd; // 0ec +- vuint32_t RES7[10]; +- vuint32_t iaur; // 118 +- vuint32_t ialr; // 11c +- vuint32_t gaur; // 120 +- vuint32_t galr; // 124 +- vuint32_t RES8[7]; +- vuint32_t fectfwr; // 144 +- vuint32_t RES8a[15]; +- vuint32_t fecrfdr; // 184 +- vuint32_t fecrfsr; // 188 +- vuint32_t fecrfcr; // 18c +- vuint32_t fecrlrfp; // 190 +- vuint32_t fecrlwfp; // 194 +- vuint32_t fecrfar; // 198 +- vuint32_t fecrfrp; // 19c +- vuint32_t fecrfwp; // 1a0 +- vuint32_t fectfdr; // 1a4 +- vuint32_t fectfsr; // 1a8 +- vuint32_t fectfcr; // 1ac +- vuint32_t fectlrfp; // 1b0 +- vuint32_t fectlwfp; // 1b4 +- vuint32_t fectfar; // 1b8 +- vuint32_t fectfrp; // 1bc +- vuint32_t fectfwp; // 1c0 +- vuint32_t frst; // 1c4 +- vuint32_t ctcwr; // 1c8 +- vuint32_t RES9[13]; +- +- /* MIB Counters Memory Map */ +- vuint32_t rmon_t_drop; // 200 +- vuint32_t rmon_t_packets; // 204 +- vuint32_t rmon_t_bc_pkt; // 208 +- vuint32_t rmon_t_mc_pkt; // 20C +- vuint32_t rmon_t_crc_align; // 210 +- vuint32_t rmon_t_undersize; // 214 +- vuint32_t rmon_t_oversize; // 218 +- vuint32_t rmon_t_frag; // 21C +- vuint32_t rmon_t_jab; // 220 +- vuint32_t rmon_t_col; // 224 +- vuint32_t rmon_t_p64; // 228 +- vuint32_t rmon_t_p65to127; // 22C +- vuint32_t rmon_t_p128to255; // 230 +- vuint32_t rmon_t_p256to511; // 234 +- vuint32_t rmon_t_p512to1023; // 238 +- vuint32_t rmon_t_p1024to2047; // 23C +- vuint32_t rmon_t_p_gte2048; // 240 +- vuint32_t rmon_t_octets; // 244 +- vuint32_t ieee_t_drop; // 248 +- vuint32_t ieee_t_frame_ok; // 24C +- vuint32_t ieee_t_1col; // 250 +- vuint32_t ieee_t_mcol; // 254 +- vuint32_t ieee_t_def; // 258 +- vuint32_t ieee_t_lcol; // 25C +- vuint32_t ieee_t_excol; // 260 +- vuint32_t ieee_t_macerr; // 264 +- vuint32_t ieee_t_cserr; // 268 +- vuint32_t ieee_t_sqe; // 26C +- vuint32_t ieee_t_fdxfc; // 270 +- vuint32_t ieee_t_octets_ok; // 274 +- vuint32_t RES10[2]; +- +- vuint32_t rmon_r_drop; // 280 +- vuint32_t rmon_r_packets; // 284 +- vuint32_t rmon_r_bc_pkt; // 288 +- vuint32_t rmon_r_mc_pkt; // 28C +- vuint32_t rmon_r_crc_align; // 290 +- vuint32_t rmon_r_undersize; // 294 +- vuint32_t rmon_r_oversize; // 298 +- vuint32_t rmon_r_frag; // 29C +- vuint32_t rmon_r_jab; // 2A0 +- vuint32_t rmon_r_resvd_0; // 2A4 +- vuint32_t rmon_r_p64; // 2A8 +- vuint32_t rmon_r_p65to127; // 2AC +- vuint32_t rmon_r_p128to255; // 2B0 +- vuint32_t rmon_r_p256to511; // 2B4 +- vuint32_t rmon_r_512to1023; // 2B8 +- vuint32_t rmon_r_1024to2047; // 2BC +- vuint32_t rmon_r_p_gte2048; // 2C0 +- vuint32_t rmon_r_octets; // 2C4 +- vuint32_t ieee_r_drop; // 2C8 +- vuint32_t ieee_r_frame_ok; // 2CC +- vuint32_t ieee_r_crc; // 2D0 +- vuint32_t ieee_r_align; // 2D4 +- vuint32_t ieee_r_macerr; // 2D8 +- vuint32_t ieee_r_fdxfc; // 2DC +- vuint32_t ieee_r_octets_ok; // 2e0 +-}; +- +-#define MCF_FEC_ADDR(ch) ((void*)(&__MBAR[0x009000+(0x800*ch)])) +-#define MCF_FEC_SIZE(ch) ((uint32_t)(0x800)) +- +-#endif /* __MCF548X_FEC_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpio.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpio.h +deleted file mode 100644 +index d220071..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpio.h ++++ /dev/null +@@ -1,708 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * General Purpose I/O (GPIO) +- */ +-#ifndef __MCF548X_GPIO_H__ +-#define __MCF548X_GPIO_H__ +- +-/* +- * General Purpose I/O (GPIO) +- */ +- +-/* Register read/write macros */ +-#define MCF_GPIO_PODR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A00])) +-#define MCF_GPIO_PODR_FBCS (*(vuint8_t *)(&__MBAR[0x000A01])) +-#define MCF_GPIO_PODR_DMA (*(vuint8_t *)(&__MBAR[0x000A02])) +-#define MCF_GPIO_PODR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A04])) +-#define MCF_GPIO_PODR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A05])) +-#define MCF_GPIO_PODR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A06])) +-#define MCF_GPIO_PODR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A07])) +-#define MCF_GPIO_PODR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A08])) +-#define MCF_GPIO_PODR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A09])) +-#define MCF_GPIO_PODR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A0A])) +-#define MCF_GPIO_PODR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A0C])) +-#define MCF_GPIO_PODR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A0D])) +-#define MCF_GPIO_PODR_DSPI (*(vuint8_t *)(&__MBAR[0x000A0E])) +-#define MCF_GPIO_PDDR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A10])) +-#define MCF_GPIO_PDDR_FBCS (*(vuint8_t *)(&__MBAR[0x000A11])) +-#define MCF_GPIO_PDDR_DMA (*(vuint8_t *)(&__MBAR[0x000A12])) +-#define MCF_GPIO_PDDR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A14])) +-#define MCF_GPIO_PDDR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A15])) +-#define MCF_GPIO_PDDR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A16])) +-#define MCF_GPIO_PDDR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A17])) +-#define MCF_GPIO_PDDR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A18])) +-#define MCF_GPIO_PDDR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A19])) +-#define MCF_GPIO_PDDR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A1A])) +-#define MCF_GPIO_PDDR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A1C])) +-#define MCF_GPIO_PDDR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A1D])) +-#define MCF_GPIO_PDDR_DSPI (*(vuint8_t *)(&__MBAR[0x000A1E])) +-#define MCF_GPIO_PPDSDR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A20])) +-#define MCF_GPIO_PPDSDR_FBCS (*(vuint8_t *)(&__MBAR[0x000A21])) +-#define MCF_GPIO_PPDSDR_DMA (*(vuint8_t *)(&__MBAR[0x000A22])) +-#define MCF_GPIO_PPDSDR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A24])) +-#define MCF_GPIO_PPDSDR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A25])) +-#define MCF_GPIO_PPDSDR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A26])) +-#define MCF_GPIO_PPDSDR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A27])) +-#define MCF_GPIO_PPDSDR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A28])) +-#define MCF_GPIO_PPDSDR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A29])) +-#define MCF_GPIO_PPDSDR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A2A])) +-#define MCF_GPIO_PPDSDR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A2C])) +-#define MCF_GPIO_PPDSDR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A2D])) +-#define MCF_GPIO_PPDSDR_DSPI (*(vuint8_t *)(&__MBAR[0x000A2E])) +-#define MCF_GPIO_PCLRR_FBCTL (*(vuint8_t *)(&__MBAR[0x000A30])) +-#define MCF_GPIO_PCLRR_FBCS (*(vuint8_t *)(&__MBAR[0x000A31])) +-#define MCF_GPIO_PCLRR_DMA (*(vuint8_t *)(&__MBAR[0x000A32])) +-#define MCF_GPIO_PCLRR_FEC0H (*(vuint8_t *)(&__MBAR[0x000A34])) +-#define MCF_GPIO_PCLRR_FEC0L (*(vuint8_t *)(&__MBAR[0x000A35])) +-#define MCF_GPIO_PCLRR_FEC1H (*(vuint8_t *)(&__MBAR[0x000A36])) +-#define MCF_GPIO_PCLRR_FEC1L (*(vuint8_t *)(&__MBAR[0x000A37])) +-#define MCF_GPIO_PCLRR_FECI2C (*(vuint8_t *)(&__MBAR[0x000A38])) +-#define MCF_GPIO_PCLRR_PCIBG (*(vuint8_t *)(&__MBAR[0x000A39])) +-#define MCF_GPIO_PCLRR_PCIBR (*(vuint8_t *)(&__MBAR[0x000A3A])) +-#define MCF_GPIO_PCLRR_PSC3PSC2 (*(vuint8_t *)(&__MBAR[0x000A3C])) +-#define MCF_GPIO_PCLRR_PSC1PSC0 (*(vuint8_t *)(&__MBAR[0x000A3D])) +-#define MCF_GPIO_PCLRR_DSPI (*(vuint8_t *)(&__MBAR[0x000A3E])) +-#define MCF_GPIO_PAR_FBCTL (*(vuint16_t*)(&__MBAR[0x000A40])) +-#define MCF_GPIO_PAR_FBCS (*(vuint8_t *)(&__MBAR[0x000A42])) +-#define MCF_GPIO_PAR_DMA (*(vuint8_t *)(&__MBAR[0x000A43])) +-#define MCF_GPIO_PAR_FECI2CIRQ (*(vuint16_t*)(&__MBAR[0x000A44])) +-#define MCF_GPIO_PAR_PCIBG (*(vuint16_t*)(&__MBAR[0x000A48])) +-#define MCF_GPIO_PAR_PCIBR (*(vuint16_t*)(&__MBAR[0x000A4A])) +-#define MCF_GPIO_PAR_PSC3 (*(vuint8_t *)(&__MBAR[0x000A4C])) +-#define MCF_GPIO_PAR_PSC2 (*(vuint8_t *)(&__MBAR[0x000A4D])) +-#define MCF_GPIO_PAR_PSC1 (*(vuint8_t *)(&__MBAR[0x000A4E])) +-#define MCF_GPIO_PAR_PSC0 (*(vuint8_t *)(&__MBAR[0x000A4F])) +-#define MCF_GPIO_PAR_DSPI (*(vuint16_t*)(&__MBAR[0x000A50])) +-#define MCF_GPIO_PAR_TIMER (*(vuint8_t *)(&__MBAR[0x000A52])) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */ +-#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x01) +-#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x02) +-#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x04) +-#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x08) +-#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10) +-#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20) +-#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40) +-#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */ +-#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x02) +-#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x04) +-#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x08) +-#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10) +-#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_DMA */ +-#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x01) +-#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x02) +-#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x04) +-#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x08) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */ +-#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x01) +-#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x02) +-#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x04) +-#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x08) +-#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10) +-#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20) +-#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40) +-#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */ +-#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x01) +-#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x02) +-#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x04) +-#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x08) +-#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10) +-#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20) +-#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40) +-#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */ +-#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x01) +-#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x02) +-#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x04) +-#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x08) +-#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10) +-#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20) +-#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40) +-#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */ +-#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x01) +-#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x02) +-#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x04) +-#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x08) +-#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10) +-#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20) +-#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40) +-#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) +-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) +-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) +-#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */ +-#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x01) +-#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x02) +-#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x04) +-#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x08) +-#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */ +-#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x01) +-#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x02) +-#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x04) +-#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x08) +-#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC2 */ +-#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC20 (0x01) +-#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC21 (0x02) +-#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC22 (0x04) +-#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC23 (0x08) +-#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC24 (0x10) +-#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC25 (0x20) +-#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC26 (0x40) +-#define MCF_GPIO_PODR_PSC3PSC2_PODR_PSC3PSC27 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC0 */ +-#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC00 (0x01) +-#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC01 (0x02) +-#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC02 (0x04) +-#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC03 (0x08) +-#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC04 (0x10) +-#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC05 (0x20) +-#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC06 (0x40) +-#define MCF_GPIO_PODR_PSC1PSC0_PODR_PSC1PSC07 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */ +-#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x01) +-#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x02) +-#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x04) +-#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x08) +-#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10) +-#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20) +-#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */ +-#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x01) +-#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x02) +-#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x04) +-#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x08) +-#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10) +-#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20) +-#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40) +-#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */ +-#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x02) +-#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x04) +-#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x08) +-#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10) +-#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */ +-#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x01) +-#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x02) +-#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x04) +-#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x08) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */ +-#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x01) +-#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x02) +-#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x04) +-#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x08) +-#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10) +-#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20) +-#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40) +-#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */ +-#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x01) +-#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x02) +-#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x04) +-#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x08) +-#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10) +-#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20) +-#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40) +-#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */ +-#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x01) +-#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x02) +-#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x04) +-#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x08) +-#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10) +-#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20) +-#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40) +-#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */ +-#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x01) +-#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x02) +-#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x04) +-#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x08) +-#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10) +-#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20) +-#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40) +-#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) +-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) +-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) +-#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */ +-#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x01) +-#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x02) +-#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x04) +-#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x08) +-#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */ +-#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x01) +-#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x02) +-#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x04) +-#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x08) +-#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC2 */ +-#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC20 (0x01) +-#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC21 (0x02) +-#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC22 (0x04) +-#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC23 (0x08) +-#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) +-#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) +-#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC26 (0x40) +-#define MCF_GPIO_PDDR_PSC3PSC2_PDDR_PSC3PSC27 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC0 */ +-#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC00 (0x01) +-#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) +-#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC02 (0x04) +-#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) +-#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC04 (0x10) +-#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC05 (0x20) +-#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC06 (0x40) +-#define MCF_GPIO_PDDR_PSC1PSC0_PDDR_PSC1PSC07 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */ +-#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x01) +-#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x02) +-#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x04) +-#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x08) +-#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10) +-#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20) +-#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */ +-#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x01) +-#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x02) +-#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x04) +-#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x08) +-#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10) +-#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20) +-#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40) +-#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */ +-#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x02) +-#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x04) +-#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x08) +-#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10) +-#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */ +-#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x01) +-#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x02) +-#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x04) +-#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x08) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */ +-#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x01) +-#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x02) +-#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x04) +-#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x08) +-#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10) +-#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20) +-#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40) +-#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */ +-#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x01) +-#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x02) +-#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x04) +-#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x08) +-#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10) +-#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20) +-#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40) +-#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */ +-#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x01) +-#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x02) +-#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x04) +-#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x08) +-#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10) +-#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20) +-#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40) +-#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */ +-#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x01) +-#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x02) +-#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x04) +-#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x08) +-#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10) +-#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20) +-#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40) +-#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) +-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) +-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) +-#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */ +-#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x01) +-#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x02) +-#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x04) +-#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x08) +-#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */ +-#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x01) +-#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x02) +-#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x04) +-#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x08) +-#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC2 */ +-#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC20 (0x01) +-#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC21 (0x02) +-#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC22 (0x04) +-#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC23 (0x08) +-#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC24 (0x10) +-#define MCF_GPIO_PPDSDR_PSC3PSC2_PDDR_PSC3PSC25 (0x20) +-#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC26 (0x40) +-#define MCF_GPIO_PPDSDR_PSC3PSC2_PPDSDR_PSC3PSC27 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC0 */ +-#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC00 (0x01) +-#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC01 (0x02) +-#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC02 (0x04) +-#define MCF_GPIO_PPDSDR_PSC1PSC0_PDDR_PSC1PSC03 (0x08) +-#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC04 (0x10) +-#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC05 (0x20) +-#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC06 (0x40) +-#define MCF_GPIO_PPDSDR_PSC1PSC0_PPDSDR_PSC1PSC07 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */ +-#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x01) +-#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x02) +-#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x04) +-#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x08) +-#define MCF_GPIO_PPDSDR_DSPI_PDDR_DSPI4 (0x10) +-#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20) +-#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */ +-#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x01) +-#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x02) +-#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x04) +-#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x08) +-#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10) +-#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20) +-#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40) +-#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */ +-#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x02) +-#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x04) +-#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x08) +-#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10) +-#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */ +-#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x01) +-#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x02) +-#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x04) +-#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x08) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */ +-#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x01) +-#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x02) +-#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x04) +-#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x08) +-#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10) +-#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20) +-#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40) +-#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */ +-#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x01) +-#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L1 (0x02) +-#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x04) +-#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x08) +-#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L4 (0x10) +-#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L5 (0x20) +-#define MCF_GPIO_PCLRR_FEC0L_PODR_FEC0L6 (0x40) +-#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */ +-#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x01) +-#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x02) +-#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x04) +-#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H3 (0x08) +-#define MCF_GPIO_PCLRR_FEC1H_PODR_FEC1H4 (0x10) +-#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20) +-#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40) +-#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */ +-#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x01) +-#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x02) +-#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x04) +-#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x08) +-#define MCF_GPIO_PCLRR_FEC1L_PODR_FEC1L4 (0x10) +-#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20) +-#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40) +-#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) +-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) +-#define MCF_GPIO_PCLRR_FECI2C_PODR_FECI2C2 (0x04) +-#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */ +-#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG0 (0x01) +-#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG1 (0x02) +-#define MCF_GPIO_PCLRR_PCIBG_PODR_PCIBG2 (0x04) +-#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x08) +-#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */ +-#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x01) +-#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x02) +-#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x04) +-#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR3 (0x08) +-#define MCF_GPIO_PCLRR_PCIBR_PODR_PCIBR4 (0x10) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC2 */ +-#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC20 (0x01) +-#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC21 (0x02) +-#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC22 (0x04) +-#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC23 (0x08) +-#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC24 (0x10) +-#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC25 (0x20) +-#define MCF_GPIO_PCLRR_PSC3PSC2_PODR_PSC3PSC26 (0x40) +-#define MCF_GPIO_PCLRR_PSC3PSC2_PCLRR_PSC3PSC27 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC0 */ +-#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC00 (0x01) +-#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC01 (0x02) +-#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC02 (0x04) +-#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC03 (0x08) +-#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC04 (0x10) +-#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC05 (0x20) +-#define MCF_GPIO_PCLRR_PSC1PSC0_PODR_PSC1PSC06 (0x40) +-#define MCF_GPIO_PCLRR_PSC1PSC0_PCLRR_PSC1PSC07 (0x80) +- +-/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */ +-#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x01) +-#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x02) +-#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x04) +-#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x08) +-#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10) +-#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20) +-#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_FBCTL */ +-#define MCF_GPIO_PAR_FBCTL_PAR_TS(x) (((x)&0x0003)<<0) +-#define MCF_GPIO_PAR_FBCTL_PAR_TA (0x0004) +-#define MCF_GPIO_PAR_FBCTL_PAR_RWB(x) (((x)&0x0003)<<4) +-#define MCF_GPIO_PAR_FBCTL_PAR_OE (0x0040) +-#define MCF_GPIO_PAR_FBCTL_PAR_BWE0 (0x0100) +-#define MCF_GPIO_PAR_FBCTL_PAR_BWE1 (0x0400) +-#define MCF_GPIO_PAR_FBCTL_PAR_BWE2 (0x1000) +-#define MCF_GPIO_PAR_FBCTL_PAR_BWE3 (0x4000) +-#define MCF_GPIO_PAR_FBCTL_PAR_TS_GPIO (0) +-#define MCF_GPIO_PAR_FBCTL_PAR_TS_TBST (2) +-#define MCF_GPIO_PAR_FBCTL_PAR_TS_TS (3) +-#define MCF_GPIO_PAR_FBCTL_PAR_RWB_GPIO (0x0000) +-#define MCF_GPIO_PAR_FBCTL_PAR_RWB_TBST (0x0020) +-#define MCF_GPIO_PAR_FBCTL_PAR_RWB_RWB (0x0030) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_FBCS */ +-#define MCF_GPIO_PAR_FBCS_PAR_CS1 (0x02) +-#define MCF_GPIO_PAR_FBCS_PAR_CS2 (0x04) +-#define MCF_GPIO_PAR_FBCS_PAR_CS3 (0x08) +-#define MCF_GPIO_PAR_FBCS_PAR_CS4 (0x10) +-#define MCF_GPIO_PAR_FBCS_PAR_CS5 (0x20) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_DMA */ +-#define MCF_GPIO_PAR_DMA_PAR_DREQ0(x) (((x)&0x03)<<0) +-#define MCF_GPIO_PAR_DMA_PAR_DREQ1(x) (((x)&0x03)<<2) +-#define MCF_GPIO_PAR_DMA_PAR_DACK0(x) (((x)&0x03)<<4) +-#define MCF_GPIO_PAR_DMA_PAR_DACK1(x) (((x)&0x03)<<6) +-#define MCF_GPIO_PAR_DMA_PAR_DACKx_GPIO (0) +-#define MCF_GPIO_PAR_DMA_PAR_DACKx_TOUT (2) +-#define MCF_GPIO_PAR_DMA_PAR_DACKx_DACK (3) +-#define MCF_GPIO_PAR_DMA_PAR_DREQx_GPIO (0) +-#define MCF_GPIO_PAR_DMA_PAR_DREQx_TIN (2) +-#define MCF_GPIO_PAR_DMA_PAR_DREQx_DREQ (3) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_FECI2CIRQ */ +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ5 (0x0001) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_IRQ6 (0x0002) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SCL (0x0004) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_SDA (0x0008) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x0003)<<6) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x0003)<<8) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII (0x0400) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E17 (0x0800) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC (0x1000) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII (0x4000) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E07 (0x8000) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_CANRX (0x0000) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x0200) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO (0x0300) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_CANTX (0x0000) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x0080) +-#define MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC (0x00C0) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_PCIBG */ +-#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x0003)<<0) +-#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x0003)<<2) +-#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x0003)<<4) +-#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x0003)<<6) +-#define MCF_GPIO_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x0003)<<8) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_PCIBR */ +-#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x0003)<<0) +-#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x0003)<<2) +-#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x0003)<<4) +-#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x0003)<<6) +-#define MCF_GPIO_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x0003)<<8) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_PSC3 */ +-#define MCF_GPIO_PAR_PSC3_PAR_TXD3 (0x04) +-#define MCF_GPIO_PAR_PSC3_PAR_RXD3 (0x08) +-#define MCF_GPIO_PAR_PSC3_PAR_RTS3(x) (((x)&0x03)<<4) +-#define MCF_GPIO_PAR_PSC3_PAR_CTS3(x) (((x)&0x03)<<6) +-#define MCF_GPIO_PAR_PSC3_PAR_CTS3_GPIO (0x00) +-#define MCF_GPIO_PAR_PSC3_PAR_CTS3_BCLK (0x80) +-#define MCF_GPIO_PAR_PSC3_PAR_CTS3_CTS (0xC0) +-#define MCF_GPIO_PAR_PSC3_PAR_RTS3_GPIO (0x00) +-#define MCF_GPIO_PAR_PSC3_PAR_RTS3_FSYNC (0x20) +-#define MCF_GPIO_PAR_PSC3_PAR_RTS3_RTS (0x30) +-#define MCF_GPIO_PAR_PSC3_PAR_CTS2_CANRX (0x40) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_PSC2 */ +-#define MCF_GPIO_PAR_PSC2_PAR_TXD2 (0x04) +-#define MCF_GPIO_PAR_PSC2_PAR_RXD2 (0x08) +-#define MCF_GPIO_PAR_PSC2_PAR_RTS2(x) (((x)&0x03)<<4) +-#define MCF_GPIO_PAR_PSC2_PAR_CTS2(x) (((x)&0x03)<<6) +-#define MCF_GPIO_PAR_PSC2_PAR_CTS2_GPIO (0x00) +-#define MCF_GPIO_PAR_PSC2_PAR_CTS2_BCLK (0x80) +-#define MCF_GPIO_PAR_PSC2_PAR_CTS2_CTS (0xC0) +-#define MCF_GPIO_PAR_PSC2_PAR_RTS2_GPIO (0x00) +-#define MCF_GPIO_PAR_PSC2_PAR_RTS2_CANTX (0x10) +-#define MCF_GPIO_PAR_PSC2_PAR_RTS2_FSYNC (0x20) +-#define MCF_GPIO_PAR_PSC2_PAR_RTS2_RTS (0x30) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_PSC1 */ +-#define MCF_GPIO_PAR_PSC1_PAR_TXD1 (0x04) +-#define MCF_GPIO_PAR_PSC1_PAR_RXD1 (0x08) +-#define MCF_GPIO_PAR_PSC1_PAR_RTS1(x) (((x)&0x03)<<4) +-#define MCF_GPIO_PAR_PSC1_PAR_CTS1(x) (((x)&0x03)<<6) +-#define MCF_GPIO_PAR_PSC1_PAR_CTS1_GPIO (0x00) +-#define MCF_GPIO_PAR_PSC1_PAR_CTS1_BCLK (0x80) +-#define MCF_GPIO_PAR_PSC1_PAR_CTS1_CTS (0xC0) +-#define MCF_GPIO_PAR_PSC1_PAR_RTS1_GPIO (0x00) +-#define MCF_GPIO_PAR_PSC1_PAR_RTS1_FSYNC (0x20) +-#define MCF_GPIO_PAR_PSC1_PAR_RTS1_RTS (0x30) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_PSC0 */ +-#define MCF_GPIO_PAR_PSC0_PAR_TXD0 (0x04) +-#define MCF_GPIO_PAR_PSC0_PAR_RXD0 (0x08) +-#define MCF_GPIO_PAR_PSC0_PAR_RTS0(x) (((x)&0x03)<<4) +-#define MCF_GPIO_PAR_PSC0_PAR_CTS0(x) (((x)&0x03)<<6) +-#define MCF_GPIO_PAR_PSC0_PAR_CTS0_GPIO (0x00) +-#define MCF_GPIO_PAR_PSC0_PAR_CTS0_BCLK (0x80) +-#define MCF_GPIO_PAR_PSC0_PAR_CTS0_CTS (0xC0) +-#define MCF_GPIO_PAR_PSC0_PAR_RTS0_GPIO (0x00) +-#define MCF_GPIO_PAR_PSC0_PAR_RTS0_FSYNC (0x20) +-#define MCF_GPIO_PAR_PSC0_PAR_RTS0_RTS (0x30) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_DSPI */ +-#define MCF_GPIO_PAR_DSPI_PAR_SOUT(x) (((x)&0x0003)<<0) +-#define MCF_GPIO_PAR_DSPI_PAR_SIN(x) (((x)&0x0003)<<2) +-#define MCF_GPIO_PAR_DSPI_PAR_SCK(x) (((x)&0x0003)<<4) +-#define MCF_GPIO_PAR_DSPI_PAR_CS0(x) (((x)&0x0003)<<6) +-#define MCF_GPIO_PAR_DSPI_PAR_CS2(x) (((x)&0x0003)<<8) +-#define MCF_GPIO_PAR_DSPI_PAR_CS3(x) (((x)&0x0003)<<10) +-#define MCF_GPIO_PAR_DSPI_PAR_CS5 (0x1000) +-#define MCF_GPIO_PAR_DSPI_PAR_CS3_GPIO (0x0000) +-#define MCF_GPIO_PAR_DSPI_PAR_CS3_CANTX (0x0400) +-#define MCF_GPIO_PAR_DSPI_PAR_CS3_TOUT (0x0800) +-#define MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS (0x0C00) +-#define MCF_GPIO_PAR_DSPI_PAR_CS2_GPIO (0x0000) +-#define MCF_GPIO_PAR_DSPI_PAR_CS2_CANTX (0x0100) +-#define MCF_GPIO_PAR_DSPI_PAR_CS2_TOUT (0x0200) +-#define MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS (0x0300) +-#define MCF_GPIO_PAR_DSPI_PAR_CS0_GPIO (0x0000) +-#define MCF_GPIO_PAR_DSPI_PAR_CS0_FSYNC (0x0040) +-#define MCF_GPIO_PAR_DSPI_PAR_CS0_RTS (0x0080) +-#define MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS (0x00C0) +-#define MCF_GPIO_PAR_DSPI_PAR_SCK_GPIO (0x0000) +-#define MCF_GPIO_PAR_DSPI_PAR_SCK_BCLK (0x0010) +-#define MCF_GPIO_PAR_DSPI_PAR_SCK_CTS (0x0020) +-#define MCF_GPIO_PAR_DSPI_PAR_SCK_SCK (0x0030) +-#define MCF_GPIO_PAR_DSPI_PAR_SIN_GPIO (0x0000) +-#define MCF_GPIO_PAR_DSPI_PAR_SIN_RXD (0x0008) +-#define MCF_GPIO_PAR_DSPI_PAR_SIN_SIN (0x000C) +-#define MCF_GPIO_PAR_DSPI_PAR_SOUT_GPIO (0x0000) +-#define MCF_GPIO_PAR_DSPI_PAR_SOUT_TXD (0x0002) +-#define MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT (0x0003) +- +-/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ +-#define MCF_GPIO_PAR_TIMER_PAR_TOUT2 (0x01) +-#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<1) +-#define MCF_GPIO_PAR_TIMER_PAR_TOUT3 (0x08) +-#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<4) +-#define MCF_GPIO_PAR_TIMER_PAR_TIN3_CANRX (0x00) +-#define MCF_GPIO_PAR_TIMER_PAR_TIN3_IRQ (0x20) +-#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN (0x30) +-#define MCF_GPIO_PAR_TIMER_PAR_TIN2_CANRX (0x00) +-#define MCF_GPIO_PAR_TIMER_PAR_TIN2_IRQ (0x04) +-#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN (0x06) +- +-#endif /* __MCF548X_GPIO_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpt.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpt.h +deleted file mode 100644 +index 4ec8fdf..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_gpt.h ++++ /dev/null +@@ -1,100 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * General Purpose Timers (GPT) +- */ +-#ifndef __MCF548X_GPT_H__ +-#define __MCF548X_GPT_H__ +- +-/* +- * General Purpose Timers (GPT) +- */ +- +-/* Register read/write macros */ +-#define MCF_GPT_GMS0 (*(vuint32_t*)(&__MBAR[0x000800])) +-#define MCF_GPT_GCIR0 (*(vuint32_t*)(&__MBAR[0x000804])) +-#define MCF_GPT_GPWM0 (*(vuint32_t*)(&__MBAR[0x000808])) +-#define MCF_GPT_GSR0 (*(vuint32_t*)(&__MBAR[0x00080C])) +-#define MCF_GPT_GMS1 (*(vuint32_t*)(&__MBAR[0x000810])) +-#define MCF_GPT_GCIR1 (*(vuint32_t*)(&__MBAR[0x000814])) +-#define MCF_GPT_GPWM1 (*(vuint32_t*)(&__MBAR[0x000818])) +-#define MCF_GPT_GSR1 (*(vuint32_t*)(&__MBAR[0x00081C])) +-#define MCF_GPT_GMS2 (*(vuint32_t*)(&__MBAR[0x000820])) +-#define MCF_GPT_GCIR2 (*(vuint32_t*)(&__MBAR[0x000824])) +-#define MCF_GPT_GPWM2 (*(vuint32_t*)(&__MBAR[0x000828])) +-#define MCF_GPT_GSR2 (*(vuint32_t*)(&__MBAR[0x00082C])) +-#define MCF_GPT_GMS3 (*(vuint32_t*)(&__MBAR[0x000830])) +-#define MCF_GPT_GCIR3 (*(vuint32_t*)(&__MBAR[0x000834])) +-#define MCF_GPT_GPWM3 (*(vuint32_t*)(&__MBAR[0x000838])) +-#define MCF_GPT_GSR3 (*(vuint32_t*)(&__MBAR[0x00083C])) +-#define MCF_GPT_GMS(x) (*(vuint32_t*)(&__MBAR[0x000800+((x)*0x010)])) +-#define MCF_GPT_GCIR(x) (*(vuint32_t*)(&__MBAR[0x000804+((x)*0x010)])) +-#define MCF_GPT_GPWM(x) (*(vuint32_t*)(&__MBAR[0x000808+((x)*0x010)])) +-#define MCF_GPT_GSR(x) (*(vuint32_t*)(&__MBAR[0x00080C+((x)*0x010)])) +- +-/* Bit definitions and macros for MCF_GPT_GMS */ +-#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0) +-#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4) +-#define MCF_GPT_GMS_IEN (0x00000100) +-#define MCF_GPT_GMS_OD (0x00000200) +-#define MCF_GPT_GMS_SC (0x00000400) +-#define MCF_GPT_GMS_CE (0x00001000) +-#define MCF_GPT_GMS_WDEN (0x00008000) +-#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16) +-#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20) +-#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24) +-#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000) +-#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000) +-#define MCF_GPT_GMS_OCT_PULSELO (0x00200000) +-#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000) +-#define MCF_GPT_GMS_ICT_ANY (0x00000000) +-#define MCF_GPT_GMS_ICT_RISE (0x00010000) +-#define MCF_GPT_GMS_ICT_FALL (0x00020000) +-#define MCF_GPT_GMS_ICT_PULSE (0x00030000) +-#define MCF_GPT_GMS_GPIO_INPUT (0x00000000) +-#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020) +-#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030) +-#define MCF_GPT_GMS_TMS_DISABLE (0x00000000) +-#define MCF_GPT_GMS_TMS_INCAPT (0x00000001) +-#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002) +-#define MCF_GPT_GMS_TMS_PWM (0x00000003) +-#define MCF_GPT_GMS_TMS_GPIO (0x00000004) +- +-/* Bit definitions and macros for MCF_GPT_GCIR */ +-#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0) +-#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_GPT_GPWM */ +-#define MCF_GPT_GPWM_LOAD (0x00000001) +-#define MCF_GPT_GPWM_PWMOP (0x00000100) +-#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_GPT_GSR */ +-#define MCF_GPT_GSR_CAPT (0x00000001) +-#define MCF_GPT_GSR_COMP (0x00000002) +-#define MCF_GPT_GSR_PWMP (0x00000004) +-#define MCF_GPT_GSR_TEXP (0x00000008) +-#define MCF_GPT_GSR_PIN (0x00000100) +-#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12) +-#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16) +- +-#endif /* __MCF548X_GPT_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_i2c.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_i2c.h +deleted file mode 100644 +index 9f54aae..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_i2c.h ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * I2C Module (I2C) +- */ +-#ifndef __MCF548X_I2C_H__ +-#define __MCF548X_I2C_H__ +- +-/* +- * I2C Module (I2C) +- */ +- +-/* Register read/write macros */ +-#define MCF_I2C_I2AR (*(vuint8_t *)(&__MBAR[0x008F00])) +-#define MCF_I2C_I2FDR (*(vuint8_t *)(&__MBAR[0x008F04])) +-#define MCF_I2C_I2CR (*(vuint8_t *)(&__MBAR[0x008F08])) +-#define MCF_I2C_I2SR (*(vuint8_t *)(&__MBAR[0x008F0C])) +-#define MCF_I2C_I2DR (*(vuint8_t *)(&__MBAR[0x008F10])) +-#define MCF_I2C_I2ICR (*(vuint8_t *)(&__MBAR[0x008F20])) +- +-/* Bit definitions and macros for MCF_I2C_I2AR */ +-#define MCF_I2C_I2AR_ADR(x) (((x)&0x7F)<<1) +- +-/* Bit definitions and macros for MCF_I2C_I2FDR */ +-#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0) +- +-/* Bit definitions and macros for MCF_I2C_I2CR */ +-#define MCF_I2C_I2CR_RSTA (0x04) +-#define MCF_I2C_I2CR_TXAK (0x08) +-#define MCF_I2C_I2CR_MTX (0x10) +-#define MCF_I2C_I2CR_MSTA (0x20) +-#define MCF_I2C_I2CR_IIEN (0x40) +-#define MCF_I2C_I2CR_IEN (0x80) +- +-/* Bit definitions and macros for MCF_I2C_I2SR */ +-#define MCF_I2C_I2SR_RXAK (0x01) +-#define MCF_I2C_I2SR_IIF (0x02) +-#define MCF_I2C_I2SR_SRW (0x04) +-#define MCF_I2C_I2SR_IAL (0x10) +-#define MCF_I2C_I2SR_IBB (0x20) +-#define MCF_I2C_I2SR_IAAS (0x40) +-#define MCF_I2C_I2SR_ICF (0x80) +- +-/* Bit definitions and macros for MCF_I2C_I2ICR */ +-#define MCF_I2C_I2ICR_IE (0x01) +-#define MCF_I2C_I2ICR_RE (0x02) +-#define MCF_I2C_I2ICR_TE (0x04) +-#define MCF_I2C_I2ICR_BNBE (0x08) +- +-#endif /* __MCF548X_I2C_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_intc.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_intc.h +deleted file mode 100644 +index fa3a2c9..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_intc.h ++++ /dev/null +@@ -1,329 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Interrupt Controller (INTC) +- */ +-#ifndef __MCF548X_INTC_H__ +-#define __MCF548X_INTC_H__ +- +-/* +- * Interrupt Controller (INTC) +- */ +- +-/* Register read/write macros */ +-#define MCF_INTC_IPRH (*(vuint32_t*)(&__MBAR[0x000700])) +-#define MCF_INTC_IPRL (*(vuint32_t*)(&__MBAR[0x000704])) +-#define MCF_INTC_IMRH (*(vuint32_t*)(&__MBAR[0x000708])) +-#define MCF_INTC_IMRL (*(vuint32_t*)(&__MBAR[0x00070C])) +-#define MCF_INTC_INTFRCH (*(vuint32_t*)(&__MBAR[0x000710])) +-#define MCF_INTC_INTFRCL (*(vuint32_t*)(&__MBAR[0x000714])) +-#define MCF_INTC_IRLR (*(vuint8_t *)(&__MBAR[0x000718])) +-#define MCF_INTC_IACKLPR (*(vuint8_t *)(&__MBAR[0x000719])) +-#define MCF_INTC_ICR0 (*(vuint8_t *)(&__MBAR[0x000740])) +-#define MCF_INTC_ICR1 (*(vuint8_t *)(&__MBAR[0x000741])) +-#define MCF_INTC_ICR2 (*(vuint8_t *)(&__MBAR[0x000742])) +-#define MCF_INTC_ICR3 (*(vuint8_t *)(&__MBAR[0x000743])) +-#define MCF_INTC_ICR4 (*(vuint8_t *)(&__MBAR[0x000744])) +-#define MCF_INTC_ICR5 (*(vuint8_t *)(&__MBAR[0x000745])) +-#define MCF_INTC_ICR6 (*(vuint8_t *)(&__MBAR[0x000746])) +-#define MCF_INTC_ICR7 (*(vuint8_t *)(&__MBAR[0x000747])) +-#define MCF_INTC_ICR8 (*(vuint8_t *)(&__MBAR[0x000748])) +-#define MCF_INTC_ICR9 (*(vuint8_t *)(&__MBAR[0x000749])) +-#define MCF_INTC_ICR10 (*(vuint8_t *)(&__MBAR[0x00074A])) +-#define MCF_INTC_ICR11 (*(vuint8_t *)(&__MBAR[0x00074B])) +-#define MCF_INTC_ICR12 (*(vuint8_t *)(&__MBAR[0x00074C])) +-#define MCF_INTC_ICR13 (*(vuint8_t *)(&__MBAR[0x00074D])) +-#define MCF_INTC_ICR14 (*(vuint8_t *)(&__MBAR[0x00074E])) +-#define MCF_INTC_ICR15 (*(vuint8_t *)(&__MBAR[0x00074F])) +-#define MCF_INTC_ICR16 (*(vuint8_t *)(&__MBAR[0x000750])) +-#define MCF_INTC_ICR17 (*(vuint8_t *)(&__MBAR[0x000751])) +-#define MCF_INTC_ICR18 (*(vuint8_t *)(&__MBAR[0x000752])) +-#define MCF_INTC_ICR19 (*(vuint8_t *)(&__MBAR[0x000753])) +-#define MCF_INTC_ICR20 (*(vuint8_t *)(&__MBAR[0x000754])) +-#define MCF_INTC_ICR21 (*(vuint8_t *)(&__MBAR[0x000755])) +-#define MCF_INTC_ICR22 (*(vuint8_t *)(&__MBAR[0x000756])) +-#define MCF_INTC_ICR23 (*(vuint8_t *)(&__MBAR[0x000757])) +-#define MCF_INTC_ICR24 (*(vuint8_t *)(&__MBAR[0x000758])) +-#define MCF_INTC_ICR25 (*(vuint8_t *)(&__MBAR[0x000759])) +-#define MCF_INTC_ICR26 (*(vuint8_t *)(&__MBAR[0x00075A])) +-#define MCF_INTC_ICR27 (*(vuint8_t *)(&__MBAR[0x00075B])) +-#define MCF_INTC_ICR28 (*(vuint8_t *)(&__MBAR[0x00075C])) +-#define MCF_INTC_ICR29 (*(vuint8_t *)(&__MBAR[0x00075D])) +-#define MCF_INTC_ICR30 (*(vuint8_t *)(&__MBAR[0x00075E])) +-#define MCF_INTC_ICR31 (*(vuint8_t *)(&__MBAR[0x00075F])) +-#define MCF_INTC_ICR32 (*(vuint8_t *)(&__MBAR[0x000760])) +-#define MCF_INTC_ICR33 (*(vuint8_t *)(&__MBAR[0x000761])) +-#define MCF_INTC_ICR34 (*(vuint8_t *)(&__MBAR[0x000762])) +-#define MCF_INTC_ICR35 (*(vuint8_t *)(&__MBAR[0x000763])) +-#define MCF_INTC_ICR36 (*(vuint8_t *)(&__MBAR[0x000764])) +-#define MCF_INTC_ICR37 (*(vuint8_t *)(&__MBAR[0x000765])) +-#define MCF_INTC_ICR38 (*(vuint8_t *)(&__MBAR[0x000766])) +-#define MCF_INTC_ICR39 (*(vuint8_t *)(&__MBAR[0x000767])) +-#define MCF_INTC_ICR40 (*(vuint8_t *)(&__MBAR[0x000768])) +-#define MCF_INTC_ICR41 (*(vuint8_t *)(&__MBAR[0x000769])) +-#define MCF_INTC_ICR42 (*(vuint8_t *)(&__MBAR[0x00076A])) +-#define MCF_INTC_ICR43 (*(vuint8_t *)(&__MBAR[0x00076B])) +-#define MCF_INTC_ICR44 (*(vuint8_t *)(&__MBAR[0x00076C])) +-#define MCF_INTC_ICR45 (*(vuint8_t *)(&__MBAR[0x00076D])) +-#define MCF_INTC_ICR46 (*(vuint8_t *)(&__MBAR[0x00076E])) +-#define MCF_INTC_ICR47 (*(vuint8_t *)(&__MBAR[0x00076F])) +-#define MCF_INTC_ICR48 (*(vuint8_t *)(&__MBAR[0x000770])) +-#define MCF_INTC_ICR49 (*(vuint8_t *)(&__MBAR[0x000771])) +-#define MCF_INTC_ICR50 (*(vuint8_t *)(&__MBAR[0x000772])) +-#define MCF_INTC_ICR51 (*(vuint8_t *)(&__MBAR[0x000773])) +-#define MCF_INTC_ICR52 (*(vuint8_t *)(&__MBAR[0x000774])) +-#define MCF_INTC_ICR53 (*(vuint8_t *)(&__MBAR[0x000775])) +-#define MCF_INTC_ICR54 (*(vuint8_t *)(&__MBAR[0x000776])) +-#define MCF_INTC_ICR55 (*(vuint8_t *)(&__MBAR[0x000777])) +-#define MCF_INTC_ICR56 (*(vuint8_t *)(&__MBAR[0x000778])) +-#define MCF_INTC_ICR57 (*(vuint8_t *)(&__MBAR[0x000779])) +-#define MCF_INTC_ICR58 (*(vuint8_t *)(&__MBAR[0x00077A])) +-#define MCF_INTC_ICR59 (*(vuint8_t *)(&__MBAR[0x00077B])) +-#define MCF_INTC_ICR60 (*(vuint8_t *)(&__MBAR[0x00077C])) +-#define MCF_INTC_ICR61 (*(vuint8_t *)(&__MBAR[0x00077D])) +-#define MCF_INTC_ICR62 (*(vuint8_t *)(&__MBAR[0x00077E])) +-#define MCF_INTC_ICR63 (*(vuint8_t *)(&__MBAR[0x00077F])) +-#define MCF_INTC_ICRn(x) (*(vuint8_t *)(&__MBAR[0x000740+((x)*0x001)])) +-#define MCF_INTC_SWIACK (*(vuint8_t *)(&__MBAR[0x0007E0])) +-#define MCF_INTC_L1IACK (*(vuint8_t *)(&__MBAR[0x0007E4])) +-#define MCF_INTC_L2IACK (*(vuint8_t *)(&__MBAR[0x0007E8])) +-#define MCF_INTC_L3IACK (*(vuint8_t *)(&__MBAR[0x0007EC])) +-#define MCF_INTC_L4IACK (*(vuint8_t *)(&__MBAR[0x0007F0])) +-#define MCF_INTC_L5IACK (*(vuint8_t *)(&__MBAR[0x0007F4])) +-#define MCF_INTC_L6IACK (*(vuint8_t *)(&__MBAR[0x0007F8])) +-#define MCF_INTC_L7IACK (*(vuint8_t *)(&__MBAR[0x0007FC])) +-#define MCF_INTC_LnIACK(x) (*(vuint8_t *)(&__MBAR[0x0007E4+((x)*0x004)])) +- +-/* Bit definitions and macros for MCF_INTC_IPRH */ +-#define MCF_INTC_IPRH_INT32 (0x00000001) +-#define MCF_INTC_IPRH_INT33 (0x00000002) +-#define MCF_INTC_IPRH_INT34 (0x00000004) +-#define MCF_INTC_IPRH_INT35 (0x00000008) +-#define MCF_INTC_IPRH_INT36 (0x00000010) +-#define MCF_INTC_IPRH_INT37 (0x00000020) +-#define MCF_INTC_IPRH_INT38 (0x00000040) +-#define MCF_INTC_IPRH_INT39 (0x00000080) +-#define MCF_INTC_IPRH_INT40 (0x00000100) +-#define MCF_INTC_IPRH_INT41 (0x00000200) +-#define MCF_INTC_IPRH_INT42 (0x00000400) +-#define MCF_INTC_IPRH_INT43 (0x00000800) +-#define MCF_INTC_IPRH_INT44 (0x00001000) +-#define MCF_INTC_IPRH_INT45 (0x00002000) +-#define MCF_INTC_IPRH_INT46 (0x00004000) +-#define MCF_INTC_IPRH_INT47 (0x00008000) +-#define MCF_INTC_IPRH_INT48 (0x00010000) +-#define MCF_INTC_IPRH_INT49 (0x00020000) +-#define MCF_INTC_IPRH_INT50 (0x00040000) +-#define MCF_INTC_IPRH_INT51 (0x00080000) +-#define MCF_INTC_IPRH_INT52 (0x00100000) +-#define MCF_INTC_IPRH_INT53 (0x00200000) +-#define MCF_INTC_IPRH_INT54 (0x00400000) +-#define MCF_INTC_IPRH_INT55 (0x00800000) +-#define MCF_INTC_IPRH_INT56 (0x01000000) +-#define MCF_INTC_IPRH_INT57 (0x02000000) +-#define MCF_INTC_IPRH_INT58 (0x04000000) +-#define MCF_INTC_IPRH_INT59 (0x08000000) +-#define MCF_INTC_IPRH_INT60 (0x10000000) +-#define MCF_INTC_IPRH_INT61 (0x20000000) +-#define MCF_INTC_IPRH_INT62 (0x40000000) +-#define MCF_INTC_IPRH_INT63 (0x80000000) +- +-/* Bit definitions and macros for MCF_INTC_IPRL */ +-#define MCF_INTC_IPRL_INT1 (0x00000002) +-#define MCF_INTC_IPRL_INT2 (0x00000004) +-#define MCF_INTC_IPRL_INT3 (0x00000008) +-#define MCF_INTC_IPRL_INT4 (0x00000010) +-#define MCF_INTC_IPRL_INT5 (0x00000020) +-#define MCF_INTC_IPRL_INT6 (0x00000040) +-#define MCF_INTC_IPRL_INT7 (0x00000080) +-#define MCF_INTC_IPRL_INT8 (0x00000100) +-#define MCF_INTC_IPRL_INT9 (0x00000200) +-#define MCF_INTC_IPRL_INT10 (0x00000400) +-#define MCF_INTC_IPRL_INT11 (0x00000800) +-#define MCF_INTC_IPRL_INT12 (0x00001000) +-#define MCF_INTC_IPRL_INT13 (0x00002000) +-#define MCF_INTC_IPRL_INT14 (0x00004000) +-#define MCF_INTC_IPRL_INT15 (0x00008000) +-#define MCF_INTC_IPRL_INT16 (0x00010000) +-#define MCF_INTC_IPRL_INT17 (0x00020000) +-#define MCF_INTC_IPRL_INT18 (0x00040000) +-#define MCF_INTC_IPRL_INT19 (0x00080000) +-#define MCF_INTC_IPRL_INT20 (0x00100000) +-#define MCF_INTC_IPRL_INT21 (0x00200000) +-#define MCF_INTC_IPRL_INT22 (0x00400000) +-#define MCF_INTC_IPRL_INT23 (0x00800000) +-#define MCF_INTC_IPRL_INT24 (0x01000000) +-#define MCF_INTC_IPRL_INT25 (0x02000000) +-#define MCF_INTC_IPRL_INT26 (0x04000000) +-#define MCF_INTC_IPRL_INT27 (0x08000000) +-#define MCF_INTC_IPRL_INT28 (0x10000000) +-#define MCF_INTC_IPRL_INT29 (0x20000000) +-#define MCF_INTC_IPRL_INT30 (0x40000000) +-#define MCF_INTC_IPRL_INT31 (0x80000000) +- +-/* Bit definitions and macros for MCF_INTC_IMRH */ +-#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) +-#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) +-#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) +-#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) +-#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) +-#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) +-#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) +-#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) +-#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) +-#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) +-#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) +-#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) +-#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) +-#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) +-#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) +-#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) +-#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) +-#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) +-#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) +-#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) +-#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) +-#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) +-#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) +-#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) +-#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) +-#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) +-#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) +-#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) +-#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +-#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +-#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +-#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) +- +-/* Bit definitions and macros for MCF_INTC_IMRL */ +-#define MCF_INTC_IMRL_MASKALL (0x00000001) +-#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) +-#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) +-#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) +-#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) +-#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) +-#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) +-#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) +-#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) +-#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) +-#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) +-#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) +-#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) +-#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) +-#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) +-#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) +-#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) +-#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) +-#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) +-#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) +-#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) +-#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) +-#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) +-#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) +-#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) +-#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) +-#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) +-#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) +-#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +-#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +-#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +-#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) +- +-/* Bit definitions and macros for MCF_INTC_INTFRCH */ +-#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) +-#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) +-#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) +-#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) +-#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) +-#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) +-#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) +-#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) +-#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) +-#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) +-#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) +-#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) +-#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) +-#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) +-#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) +-#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) +-#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) +-#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) +-#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) +-#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) +-#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) +-#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) +-#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) +-#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) +-#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) +-#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) +-#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) +-#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) +-#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +-#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +-#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +-#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) +- +-/* Bit definitions and macros for MCF_INTC_INTFRCL */ +-#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) +-#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) +-#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) +-#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) +-#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) +-#define MCF_INTC_INTFRCL_INT6 (0x00000040) +-#define MCF_INTC_INTFRCL_INT7 (0x00000080) +-#define MCF_INTC_INTFRCL_INT8 (0x00000100) +-#define MCF_INTC_INTFRCL_INT9 (0x00000200) +-#define MCF_INTC_INTFRCL_INT10 (0x00000400) +-#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) +-#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) +-#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) +-#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) +-#define MCF_INTC_INTFRCL_INT15 (0x00008000) +-#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) +-#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) +-#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) +-#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) +-#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) +-#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) +-#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) +-#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) +-#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) +-#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) +-#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) +-#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) +-#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +-#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +-#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +-#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) +- +-/* Bit definitions and macros for MCF_INTC_IRLR */ +-#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<1) +- +-/* Bit definitions and macros for MCF_INTC_IACKLPR */ +-#define MCF_INTC_IACKLPR_PRI(x) (((x)&0x0F)<<0) +-#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x07)<<4) +- +-/* Bit definitions and macros for MCF_INTC_ICRn */ +-#define MCF_INTC_ICRn_IP(x) (((x)&0x07)<<0) +-#define MCF_INTC_ICRn_IL(x) (((x)&0x07)<<3) +- +-#endif /* __MCF548X_INTC_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pci.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pci.h +deleted file mode 100644 +index 23c6743..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pci.h ++++ /dev/null +@@ -1,349 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * PCI Bus Controller (PCI) +- */ +-#ifndef __MCF548X_PCI_H__ +-#define __MCF548X_PCI_H__ +- +-/* +- * PCI Bus Controller (PCI) +- */ +-#define MCF_PCI_HDR_BASE (&__MBAR[0x000B00]) +- +-/* Register read/write macros */ +- +-/* type 0 header */ +-#define MCF_PCI_PCIIDR (*(vuint32_t*)(&__MBAR[0x000B00])) +-#define MCF_PCI_PCISCR (*(vuint32_t*)(&__MBAR[0x000B04])) +-#define MCF_PCI_PCICCRIR (*(vuint32_t*)(&__MBAR[0x000B08])) +-#define MCF_PCI_PCICR1 (*(vuint32_t*)(&__MBAR[0x000B0C])) +-#define MCF_PCI_PCIBAR0 (*(vuint32_t*)(&__MBAR[0x000B10])) +-#define MCF_PCI_PCIBAR1 (*(vuint32_t*)(&__MBAR[0x000B14])) +-#define MCF_PCI_PCISID (*(vuint32_t*)(&__MBAR[0x000B2c])) +-#define MCF_PCI_PCICR2 (*(vuint32_t*)(&__MBAR[0x000B3C])) +- +-/* Target Controls */ +-#define MCF_PCI_PCIGSCR (*(vuint32_t*)(&__MBAR[0x000B60])) +-#define MCF_PCI_PCITBATR0 (*(vuint32_t*)(&__MBAR[0x000B64])) +-#define MCF_PCI_PCITBATR1 (*(vuint32_t*)(&__MBAR[0x000B68])) +-#define MCF_PCI_PCITCR (*(vuint32_t*)(&__MBAR[0x000B6C])) +-#define MCF_PCI_PCIIW0BTAR (*(vuint32_t*)(&__MBAR[0x000B70])) +-#define MCF_PCI_PCIIW1BTAR (*(vuint32_t*)(&__MBAR[0x000B74])) +-#define MCF_PCI_PCIIW2BTAR (*(vuint32_t*)(&__MBAR[0x000B78])) +-#define MCF_PCI_PCIIWCR (*(vuint32_t*)(&__MBAR[0x000B80])) +-#define MCF_PCI_PCIICR (*(vuint32_t*)(&__MBAR[0x000B84])) +-#define MCF_PCI_PCIISR (*(vuint32_t*)(&__MBAR[0x000B88])) +-#define MCF_PCI_PCICAR (*(vuint32_t*)(&__MBAR[0x000BF8])) +-#define MCF_PCI_PCITPSR (*(vuint32_t*)(&__MBAR[0x008400])) +-#define MCF_PCI_PCITSAR (*(vuint32_t*)(&__MBAR[0x008404])) +-#define MCF_PCI_PCITTCR (*(vuint32_t*)(&__MBAR[0x008408])) +-#define MCF_PCI_PCITER (*(vuint32_t*)(&__MBAR[0x00840C])) +-#define MCF_PCI_PCITNAR (*(vuint32_t*)(&__MBAR[0x008410])) +-#define MCF_PCI_PCITLWR (*(vuint32_t*)(&__MBAR[0x008414])) +-#define MCF_PCI_PCITDCR (*(vuint32_t*)(&__MBAR[0x008418])) +-#define MCF_PCI_PCITSR (*(vuint32_t*)(&__MBAR[0x00841C])) +-#define MCF_PCI_PCITFDR (*(vuint32_t*)(&__MBAR[0x008440])) +-#define MCF_PCI_PCITFSR (*(vuint32_t*)(&__MBAR[0x008444])) +-#define MCF_PCI_PCITFCR (*(vuint32_t*)(&__MBAR[0x008448])) +-#define MCF_PCI_PCITFAR (*(vuint32_t*)(&__MBAR[0x00844C])) +-#define MCF_PCI_PCITFRPR (*(vuint32_t*)(&__MBAR[0x008450])) +-#define MCF_PCI_PCITFWPR (*(vuint32_t*)(&__MBAR[0x008454])) +-#define MCF_PCI_PCIRPSR (*(vuint32_t*)(&__MBAR[0x008480])) +-#define MCF_PCI_PCIRSAR (*(vuint32_t*)(&__MBAR[0x008484])) +-#define MCF_PCI_PCIRTCR (*(vuint32_t*)(&__MBAR[0x008488])) +-#define MCF_PCI_PCIRER (*(vuint32_t*)(&__MBAR[0x00848C])) +-#define MCF_PCI_PCIRNAR (*(vuint32_t*)(&__MBAR[0x008490])) +-#define MCF_PCI_PCIRDCR (*(vuint32_t*)(&__MBAR[0x008498])) +-#define MCF_PCI_PCIRSR (*(vuint32_t*)(&__MBAR[0x00849C])) +-#define MCF_PCI_PCIRFDR (*(vuint32_t*)(&__MBAR[0x0084C0])) +-#define MCF_PCI_PCIRFSR (*(vuint32_t*)(&__MBAR[0x0084C4])) +-#define MCF_PCI_PCIRFCR (*(vuint32_t*)(&__MBAR[0x0084C8])) +-#define MCF_PCI_PCIRFAR (*(vuint32_t*)(&__MBAR[0x0084CC])) +-#define MCF_PCI_PCIRFRPR (*(vuint32_t*)(&__MBAR[0x0084D0])) +-#define MCF_PCI_PCIRFWPR (*(vuint32_t*)(&__MBAR[0x0084D4])) +- +- +-/* +- * Type 0 Config Header Regs +- */ +- +-/* Bit definitions and macros for MCF_PCI_PCIIDR */ +-#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0) +-#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_PCI_PCISCR */ +-#define MCF_PCI_PCISCR_M (0x00000002) +-#define MCF_PCI_PCISCR_B (0x00000004) +-#define MCF_PCI_PCISCR_SP (0x00000008) +-#define MCF_PCI_PCISCR_MW (0x00000010) +-#define MCF_PCI_PCISCR_PER (0x00000040) +-#define MCF_PCI_PCISCR_S (0x00000100) +-#define MCF_PCI_PCISCR_F (0x00000200) +-#define MCF_PCI_PCISCR_C (0x00100000) +-#define MCF_PCI_PCISCR_66M (0x00200000) +-#define MCF_PCI_PCISCR_R (0x00400000) +-#define MCF_PCI_PCISCR_FC (0x00800000) +-#define MCF_PCI_PCISCR_DP (0x01000000) +-#define MCF_PCI_PCISCR_DT(x) (((x)&0x00000003)<<25) +-#define MCF_PCI_PCISCR_TS (0x08000000) +-#define MCF_PCI_PCISCR_TR (0x10000000) +-#define MCF_PCI_PCISCR_MA (0x20000000) +-#define MCF_PCI_PCISCR_SE (0x40000000) +-#define MCF_PCI_PCISCR_PE (0x80000000) +- +-/* Bit definitions and macros for MCF_PCI_PCICCRIR */ +-#define MCF_PCI_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0) +-#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8) +- +-/* Bit definitions and macros for MCF_PCI_PCICR1 */ +-#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0) +-#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8) +-#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16) +-#define MCF_PCI_PCICR1_BIST(x) (((x)&0x000000FF)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCIBAR0 */ +-#define MCF_PCI_PCIBAR0_IO (0x00000001) +-#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x00000003)<<1) +-#define MCF_PCI_PCIBAR0_PREF (0x00000008) +-#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x00003FFF)<<18) +- +-/* Bit definitions and macros for MCF_PCI_PCIBAR1 */ +-#define MCF_PCI_PCIBAR1_IO (0x00000001) +-#define MCF_PCI_PCIBAR1_PREF (0x00000008) +-#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x00000003)<<30) +- +-/* Bit definitions and macros for MCF_PCI_PCICR2 */ +-#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0) +-#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8) +-#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16) +-#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCIGSCR */ +-#define MCF_PCI_PCIGSCR_PR (0x00000001) +-#define MCF_PCI_PCIGSCR_SEE (0x00001000) +-#define MCF_PCI_PCIGSCR_PEE (0x00002000) +-#define MCF_PCI_PCIGSCR_SE (0x10000000) +-#define MCF_PCI_PCIGSCR_PE (0x20000000) +- +-/* +- * Target device controls +- */ +- +-/* Bit definitions and macros for MCF_PCI_PCITBATR0 */ +-#define MCF_PCI_PCITBATR0_EN (0x00000001) +-#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18) +- +-/* Bit definitions and macros for MCF_PCI_PCITBATR1 */ +-#define MCF_PCI_PCITBATR1_EN (0x00000001) +-#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30) +- +-/* Bit definitions and macros for MCF_PCI_PCITCR */ +-#define MCF_PCI_PCITCR_P (0x00010000) +-#define MCF_PCI_PCITCR_LD (0x01000000) +- +-/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */ +-#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8) +-#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16) +-#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */ +-#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8) +-#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16) +-#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */ +-#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8) +-#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16) +-#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCIIWCR */ +-#define MCF_PCI_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8) +-#define MCF_PCI_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16) +-#define MCF_PCI_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24) +-#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x01000000) +-#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000) +-#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000) +-#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x09000000) +-#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x00010000) +-#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000) +-#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000) +-#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x00090000) +-#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x00000100) +-#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300) +-#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500) +-#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x00000900) +- +-/* Bit definitions and macros for MCF_PCI_PCIICR */ +-#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0) +-#define MCF_PCI_PCIICR_TAE (0x01000000) +-#define MCF_PCI_PCIICR_IAE (0x02000000) +-#define MCF_PCI_PCIICR_REE (0x04000000) +- +-/* Bit definitions and macros for MCF_PCI_PCIISR */ +-#define MCF_PCI_PCIISR_TA (0x01000000) +-#define MCF_PCI_PCIISR_IA (0x02000000) +-#define MCF_PCI_PCIISR_RE (0x04000000) +- +-/* Bit definitions and macros for MCF_PCI_PCICAR */ +-#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x0000003F)<<2) +-#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8) +-#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11) +-#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16) +-#define MCF_PCI_PCICAR_E (0x80000000) +- +- +-/* +- * PCI Fifos +- */ +- +-/* Bit definitions and macros for MCF_PCI_PCITPSR */ +-#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_PCI_PCITTCR */ +-#define MCF_PCI_PCITTCR_DI (0x00000001) +-#define MCF_PCI_PCITTCR_W (0x00000010) +-#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8) +-#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) +-#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCITER */ +-#define MCF_PCI_PCITER_NE (0x00010000) +-#define MCF_PCI_PCITER_IAE (0x00020000) +-#define MCF_PCI_PCITER_TAE (0x00040000) +-#define MCF_PCI_PCITER_RE (0x00080000) +-#define MCF_PCI_PCITER_SE (0x00100000) +-#define MCF_PCI_PCITER_FEE (0x00200000) +-#define MCF_PCI_PCITER_ME (0x01000000) +-#define MCF_PCI_PCITER_BE (0x08000000) +-#define MCF_PCI_PCITER_CM (0x10000000) +-#define MCF_PCI_PCITER_RF (0x40000000) +-#define MCF_PCI_PCITER_RC (0x80000000) +- +-/* Bit definitions and macros for MCF_PCI_PCITDCR */ +-#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) +-#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_PCI_PCITSR */ +-#define MCF_PCI_PCITSR_IA (0x00010000) +-#define MCF_PCI_PCITSR_TA (0x00020000) +-#define MCF_PCI_PCITSR_RE (0x00040000) +-#define MCF_PCI_PCITSR_SE (0x00080000) +-#define MCF_PCI_PCITSR_FE (0x00100000) +-#define MCF_PCI_PCITSR_BE1 (0x00200000) +-#define MCF_PCI_PCITSR_BE2 (0x00400000) +-#define MCF_PCI_PCITSR_BE3 (0x00800000) +-#define MCF_PCI_PCITSR_NT (0x01000000) +- +-/* Bit definitions and macros for MCF_PCI_PCITFSR */ +-#define MCF_PCI_PCITFSR_EMT (0x00010000) +-#define MCF_PCI_PCITFSR_ALARM (0x00020000) +-#define MCF_PCI_PCITFSR_FU (0x00040000) +-#define MCF_PCI_PCITFSR_FR (0x00080000) +-#define MCF_PCI_PCITFSR_OF (0x00100000) +-#define MCF_PCI_PCITFSR_UF (0x00200000) +-#define MCF_PCI_PCITFSR_RXW (0x00400000) +- +-/* Bit definitions and macros for MCF_PCI_PCITFCR */ +-#define MCF_PCI_PCITFCR_OF_MSK (0x00080000) +-#define MCF_PCI_PCITFCR_UF_MSK (0x00100000) +-#define MCF_PCI_PCITFCR_RXW_MSK (0x00200000) +-#define MCF_PCI_PCITFCR_FAE_MSK (0x00400000) +-#define MCF_PCI_PCITFCR_IP_MSK (0x00800000) +-#define MCF_PCI_PCITFCR_GR(x) (((x)&0x00000007)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCITFAR */ +-#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0) +- +-/* Bit definitions and macros for MCF_PCI_PCITFRPR */ +-#define MCF_PCI_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_PCI_PCITFWPR */ +-#define MCF_PCI_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_PCI_PCIRPSR */ +-#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_PCI_PCIRTCR */ +-#define MCF_PCI_PCIRTCR_DI (0x00000001) +-#define MCF_PCI_PCIRTCR_W (0x00000010) +-#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8) +-#define MCF_PCI_PCIRTCR_FB (0x00001000) +-#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16) +-#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCIRER */ +-#define MCF_PCI_PCIRER_NE (0x00010000) +-#define MCF_PCI_PCIRER_IAE (0x00020000) +-#define MCF_PCI_PCIRER_TAE (0x00040000) +-#define MCF_PCI_PCIRER_RE (0x00080000) +-#define MCF_PCI_PCIRER_SE (0x00100000) +-#define MCF_PCI_PCIRER_FEE (0x00200000) +-#define MCF_PCI_PCIRER_ME (0x01000000) +-#define MCF_PCI_PCIRER_BE (0x08000000) +-#define MCF_PCI_PCIRER_CM (0x10000000) +-#define MCF_PCI_PCIRER_FE (0x20000000) +-#define MCF_PCI_PCIRER_RF (0x40000000) +-#define MCF_PCI_PCIRER_RC (0x80000000) +- +-/* Bit definitions and macros for MCF_PCI_PCIRDCR */ +-#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0) +-#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_PCI_PCIRSR */ +-#define MCF_PCI_PCIRSR_IA (0x00010000) +-#define MCF_PCI_PCIRSR_TA (0x00020000) +-#define MCF_PCI_PCIRSR_RE (0x00040000) +-#define MCF_PCI_PCIRSR_SE (0x00080000) +-#define MCF_PCI_PCIRSR_FE (0x00100000) +-#define MCF_PCI_PCIRSR_BE1 (0x00200000) +-#define MCF_PCI_PCIRSR_BE2 (0x00400000) +-#define MCF_PCI_PCIRSR_BE3 (0x00800000) +-#define MCF_PCI_PCIRSR_NT (0x01000000) +- +-/* Bit definitions and macros for MCF_PCI_PCIRFSR */ +-#define MCF_PCI_PCIRFSR_EMT (0x00010000) +-#define MCF_PCI_PCIRFSR_ALARM (0x00020000) +-#define MCF_PCI_PCIRFSR_FU (0x00040000) +-#define MCF_PCI_PCIRFSR_FR (0x00080000) +-#define MCF_PCI_PCIRFSR_OF (0x00100000) +-#define MCF_PCI_PCIRFSR_UF (0x00200000) +-#define MCF_PCI_PCIRFSR_RXW (0x00400000) +- +-/* Bit definitions and macros for MCF_PCI_PCIRFCR */ +-#define MCF_PCI_PCIRFCR_OF_MSK (0x00080000) +-#define MCF_PCI_PCIRFCR_UF_MSK (0x00100000) +-#define MCF_PCI_PCIRFCR_RXW_MSK (0x00200000) +-#define MCF_PCI_PCIRFCR_FAE_MSK (0x00400000) +-#define MCF_PCI_PCIRFCR_IP_MSK (0x00800000) +-#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x00000007)<<24) +- +-/* Bit definitions and macros for MCF_PCI_PCIRFAR */ +-#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0) +- +-/* Bit definitions and macros for MCF_PCI_PCIRFRPR */ +-#define MCF_PCI_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_PCI_PCIRFWPR */ +-#define MCF_PCI_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0) +- +-#endif /* __MCF548X_PCI_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pciarb.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pciarb.h +deleted file mode 100644 +index 8c11647..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_pciarb.h ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * PCI Arbiter Module (PCIARB) +- */ +-#ifndef __MCF548X_PCIARB_H__ +-#define __MCF548X_PCIARB_H__ +- +-/* +- * PCI Arbiter Module (PCIARB) +- */ +- +-/* Register read/write macros */ +-#define MCF_PCIARB_PACR (*(vuint32_t*)(&__MBAR[0x000C00])) +-#define MCF_PCIARB_PASR (*(vuint32_t*)(&__MBAR[0x000C04])) +- +-/* Bit definitions and macros for MCF_PCIARB_PACR */ +-#define MCF_PCIARB_PACR_INTMPRI (0x00000001) +-#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1) +-#define MCF_PCIARB_PACR_INTMINTEN (0x00010000) +-#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17) +-/* Not documented! +- * #define MCF_PCIARB_PACR_PKMD (0x40000000) +- */ +-#define MCF_PCIARB_PACR_DS (0x80000000) +- +-/* Bit definitions and macros for MCF_PCIARB_PASR */ +-#define MCF_PCIARB_PASR_ITLMBK (0x00010000) +-#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17) +- +-#endif /* __MCF548X_PCIARB_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_psc.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_psc.h +deleted file mode 100644 +index c685af8..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_psc.h ++++ /dev/null +@@ -1,486 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Programmable Serial Controller (PSC) +- */ +-#ifndef __MCF548X_PSC_H__ +-#define __MCF548X_PSC_H__ +- +-/* +- * Programmable Serial Controller (PSC) +- */ +- +-/* Register read/write macros */ +-#define MCF_PSC_MR0 (*(vuint8_t *)(&__MBAR[0x008600])) +-#define MCF_PSC_SR0 (*(vuint16_t*)(&__MBAR[0x008604])) +-#define MCF_PSC_CSR0 (*(vuint8_t *)(&__MBAR[0x008604])) +-#define MCF_PSC_CR0 (*(vuint8_t *)(&__MBAR[0x008608])) +-#define MCF_PSC_RB0 (*(vuint32_t*)(&__MBAR[0x00860C])) +-#define MCF_PSC_TB0 (*(vuint32_t*)(&__MBAR[0x00860C])) +-#define MCF_PSC_TB_8BIT0 (*(vuint32_t*)(&__MBAR[0x00860C])) +-#define MCF_PSC_TB_16BIT0 (*(vuint32_t*)(&__MBAR[0x00860C])) +-#define MCF_PSC_TB_AC970 (*(vuint32_t*)(&__MBAR[0x00860C])) +-#define MCF_PSC_IPCR0 (*(vuint8_t *)(&__MBAR[0x008610])) +-#define MCF_PSC_ACR0 (*(vuint8_t *)(&__MBAR[0x008610])) +-#define MCF_PSC_ISR0 (*(vuint16_t*)(&__MBAR[0x008614])) +-#define MCF_PSC_IMR0 (*(vuint16_t*)(&__MBAR[0x008614])) +-#define MCF_PSC_CTUR0 (*(vuint8_t *)(&__MBAR[0x008618])) +-#define MCF_PSC_CTLR0 (*(vuint8_t *)(&__MBAR[0x00861C])) +-#define MCF_PSC_IP0 (*(vuint8_t *)(&__MBAR[0x008634])) +-#define MCF_PSC_OPSET0 (*(vuint8_t *)(&__MBAR[0x008638])) +-#define MCF_PSC_OPRESET0 (*(vuint8_t *)(&__MBAR[0x00863C])) +-#define MCF_PSC_SICR0 (*(vuint8_t *)(&__MBAR[0x008640])) +-#define MCF_PSC_IRCR10 (*(vuint8_t *)(&__MBAR[0x008644])) +-#define MCF_PSC_IRCR20 (*(vuint8_t *)(&__MBAR[0x008648])) +-#define MCF_PSC_IRSDR0 (*(vuint8_t *)(&__MBAR[0x00864C])) +-#define MCF_PSC_IRMDR0 (*(vuint8_t *)(&__MBAR[0x008650])) +-#define MCF_PSC_IRFDR0 (*(vuint8_t *)(&__MBAR[0x008654])) +-#define MCF_PSC_RFCNT0 (*(vuint16_t*)(&__MBAR[0x008658])) +-#define MCF_PSC_TFCNT0 (*(vuint16_t*)(&__MBAR[0x00865C])) +-#define MCF_PSC_RFSR0 (*(vuint16_t*)(&__MBAR[0x008664])) +-#define MCF_PSC_TFSR0 (*(vuint16_t*)(&__MBAR[0x008684])) +-#define MCF_PSC_RFCR0 (*(vuint32_t*)(&__MBAR[0x008668])) +-#define MCF_PSC_TFCR0 (*(vuint32_t*)(&__MBAR[0x008688])) +-#define MCF_PSC_RFAR0 (*(vuint16_t*)(&__MBAR[0x00866E])) +-#define MCF_PSC_TFAR0 (*(vuint16_t*)(&__MBAR[0x00868E])) +-#define MCF_PSC_RFRP0 (*(vuint16_t*)(&__MBAR[0x008672])) +-#define MCF_PSC_TFRP0 (*(vuint16_t*)(&__MBAR[0x008692])) +-#define MCF_PSC_RFWP0 (*(vuint16_t*)(&__MBAR[0x008676])) +-#define MCF_PSC_TFWP0 (*(vuint16_t*)(&__MBAR[0x008696])) +-#define MCF_PSC_RLRFP0 (*(vuint16_t*)(&__MBAR[0x00867A])) +-#define MCF_PSC_TLRFP0 (*(vuint16_t*)(&__MBAR[0x00869A])) +-#define MCF_PSC_RLWFP0 (*(vuint16_t*)(&__MBAR[0x00867E])) +-#define MCF_PSC_TLWFP0 (*(vuint16_t*)(&__MBAR[0x00869E])) +-#define MCF_PSC_MR1 (*(vuint8_t *)(&__MBAR[0x008700])) +-#define MCF_PSC_SR1 (*(vuint16_t*)(&__MBAR[0x008704])) +-#define MCF_PSC_CSR1 (*(vuint8_t *)(&__MBAR[0x008704])) +-#define MCF_PSC_CR1 (*(vuint8_t *)(&__MBAR[0x008708])) +-#define MCF_PSC_RB1 (*(vuint32_t*)(&__MBAR[0x00870C])) +-#define MCF_PSC_TB1 (*(vuint32_t*)(&__MBAR[0x00870C])) +-#define MCF_PSC_TB_8BIT1 (*(vuint32_t*)(&__MBAR[0x00870C])) +-#define MCF_PSC_TB_16BIT1 (*(vuint32_t*)(&__MBAR[0x00870C])) +-#define MCF_PSC_TB_AC971 (*(vuint32_t*)(&__MBAR[0x00870C])) +-#define MCF_PSC_IPCR1 (*(vuint8_t *)(&__MBAR[0x008710])) +-#define MCF_PSC_ACR1 (*(vuint8_t *)(&__MBAR[0x008710])) +-#define MCF_PSC_ISR1 (*(vuint16_t*)(&__MBAR[0x008714])) +-#define MCF_PSC_IMR1 (*(vuint16_t*)(&__MBAR[0x008714])) +-#define MCF_PSC_CTUR1 (*(vuint8_t *)(&__MBAR[0x008718])) +-#define MCF_PSC_CTLR1 (*(vuint8_t *)(&__MBAR[0x00871C])) +-#define MCF_PSC_IP1 (*(vuint8_t *)(&__MBAR[0x008734])) +-#define MCF_PSC_OPSET1 (*(vuint8_t *)(&__MBAR[0x008738])) +-#define MCF_PSC_OPRESET1 (*(vuint8_t *)(&__MBAR[0x00873C])) +-#define MCF_PSC_SICR1 (*(vuint8_t *)(&__MBAR[0x008740])) +-#define MCF_PSC_IRCR11 (*(vuint8_t *)(&__MBAR[0x008744])) +-#define MCF_PSC_IRCR21 (*(vuint8_t *)(&__MBAR[0x008748])) +-#define MCF_PSC_IRSDR1 (*(vuint8_t *)(&__MBAR[0x00874C])) +-#define MCF_PSC_IRMDR1 (*(vuint8_t *)(&__MBAR[0x008750])) +-#define MCF_PSC_IRFDR1 (*(vuint8_t *)(&__MBAR[0x008754])) +-#define MCF_PSC_RFCNT1 (*(vuint16_t*)(&__MBAR[0x008758])) +-#define MCF_PSC_TFCNT1 (*(vuint16_t*)(&__MBAR[0x00875C])) +-#define MCF_PSC_RFSR1 (*(vuint16_t*)(&__MBAR[0x008764])) +-#define MCF_PSC_TFSR1 (*(vuint16_t*)(&__MBAR[0x008784])) +-#define MCF_PSC_RFCR1 (*(vuint32_t*)(&__MBAR[0x008768])) +-#define MCF_PSC_TFCR1 (*(vuint32_t*)(&__MBAR[0x008788])) +-#define MCF_PSC_RFAR1 (*(vuint16_t*)(&__MBAR[0x00876E])) +-#define MCF_PSC_TFAR1 (*(vuint16_t*)(&__MBAR[0x00878E])) +-#define MCF_PSC_RFRP1 (*(vuint16_t*)(&__MBAR[0x008772])) +-#define MCF_PSC_TFRP1 (*(vuint16_t*)(&__MBAR[0x008792])) +-#define MCF_PSC_RFWP1 (*(vuint16_t*)(&__MBAR[0x008776])) +-#define MCF_PSC_TFWP1 (*(vuint16_t*)(&__MBAR[0x008796])) +-#define MCF_PSC_RLRFP1 (*(vuint16_t*)(&__MBAR[0x00877A])) +-#define MCF_PSC_TLRFP1 (*(vuint16_t*)(&__MBAR[0x00879A])) +-#define MCF_PSC_RLWFP1 (*(vuint16_t*)(&__MBAR[0x00877E])) +-#define MCF_PSC_TLWFP1 (*(vuint16_t*)(&__MBAR[0x00879E])) +-#define MCF_PSC_MR2 (*(vuint8_t *)(&__MBAR[0x008800])) +-#define MCF_PSC_SR2 (*(vuint16_t*)(&__MBAR[0x008804])) +-#define MCF_PSC_CSR2 (*(vuint8_t *)(&__MBAR[0x008804])) +-#define MCF_PSC_CR2 (*(vuint8_t *)(&__MBAR[0x008808])) +-#define MCF_PSC_RB2 (*(vuint32_t*)(&__MBAR[0x00880C])) +-#define MCF_PSC_TB2 (*(vuint32_t*)(&__MBAR[0x00880C])) +-#define MCF_PSC_TB_8BIT2 (*(vuint32_t*)(&__MBAR[0x00880C])) +-#define MCF_PSC_TB_16BIT2 (*(vuint32_t*)(&__MBAR[0x00880C])) +-#define MCF_PSC_TB_AC972 (*(vuint32_t*)(&__MBAR[0x00880C])) +-#define MCF_PSC_IPCR2 (*(vuint8_t *)(&__MBAR[0x008810])) +-#define MCF_PSC_ACR2 (*(vuint8_t *)(&__MBAR[0x008810])) +-#define MCF_PSC_ISR2 (*(vuint16_t*)(&__MBAR[0x008814])) +-#define MCF_PSC_IMR2 (*(vuint16_t*)(&__MBAR[0x008814])) +-#define MCF_PSC_CTUR2 (*(vuint8_t *)(&__MBAR[0x008818])) +-#define MCF_PSC_CTLR2 (*(vuint8_t *)(&__MBAR[0x00881C])) +-#define MCF_PSC_IP2 (*(vuint8_t *)(&__MBAR[0x008834])) +-#define MCF_PSC_OPSET2 (*(vuint8_t *)(&__MBAR[0x008838])) +-#define MCF_PSC_OPRESET2 (*(vuint8_t *)(&__MBAR[0x00883C])) +-#define MCF_PSC_SICR2 (*(vuint8_t *)(&__MBAR[0x008840])) +-#define MCF_PSC_IRCR12 (*(vuint8_t *)(&__MBAR[0x008844])) +-#define MCF_PSC_IRCR22 (*(vuint8_t *)(&__MBAR[0x008848])) +-#define MCF_PSC_IRSDR2 (*(vuint8_t *)(&__MBAR[0x00884C])) +-#define MCF_PSC_IRMDR2 (*(vuint8_t *)(&__MBAR[0x008850])) +-#define MCF_PSC_IRFDR2 (*(vuint8_t *)(&__MBAR[0x008854])) +-#define MCF_PSC_RFCNT2 (*(vuint16_t*)(&__MBAR[0x008858])) +-#define MCF_PSC_TFCNT2 (*(vuint16_t*)(&__MBAR[0x00885C])) +-#define MCF_PSC_RFSR2 (*(vuint16_t*)(&__MBAR[0x008864])) +-#define MCF_PSC_TFSR2 (*(vuint16_t*)(&__MBAR[0x008884])) +-#define MCF_PSC_RFCR2 (*(vuint32_t*)(&__MBAR[0x008868])) +-#define MCF_PSC_TFCR2 (*(vuint32_t*)(&__MBAR[0x008888])) +-#define MCF_PSC_RFAR2 (*(vuint16_t*)(&__MBAR[0x00886E])) +-#define MCF_PSC_TFAR2 (*(vuint16_t*)(&__MBAR[0x00888E])) +-#define MCF_PSC_RFRP2 (*(vuint16_t*)(&__MBAR[0x008872])) +-#define MCF_PSC_TFRP2 (*(vuint16_t*)(&__MBAR[0x008892])) +-#define MCF_PSC_RFWP2 (*(vuint16_t*)(&__MBAR[0x008876])) +-#define MCF_PSC_TFWP2 (*(vuint16_t*)(&__MBAR[0x008896])) +-#define MCF_PSC_RLRFP2 (*(vuint16_t*)(&__MBAR[0x00887A])) +-#define MCF_PSC_TLRFP2 (*(vuint16_t*)(&__MBAR[0x00889A])) +-#define MCF_PSC_RLWFP2 (*(vuint16_t*)(&__MBAR[0x00887E])) +-#define MCF_PSC_TLWFP2 (*(vuint16_t*)(&__MBAR[0x00889E])) +-#define MCF_PSC_MR3 (*(vuint8_t *)(&__MBAR[0x008900])) +-#define MCF_PSC_SR3 (*(vuint16_t*)(&__MBAR[0x008904])) +-#define MCF_PSC_CSR3 (*(vuint8_t *)(&__MBAR[0x008904])) +-#define MCF_PSC_CR3 (*(vuint8_t *)(&__MBAR[0x008908])) +-#define MCF_PSC_RB3 (*(vuint32_t*)(&__MBAR[0x00890C])) +-#define MCF_PSC_TB3 (*(vuint32_t*)(&__MBAR[0x00890C])) +-#define MCF_PSC_TB_8BIT3 (*(vuint32_t*)(&__MBAR[0x00890C])) +-#define MCF_PSC_TB_16BIT3 (*(vuint32_t*)(&__MBAR[0x00890C])) +-#define MCF_PSC_TB_AC973 (*(vuint32_t*)(&__MBAR[0x00890C])) +-#define MCF_PSC_IPCR3 (*(vuint8_t *)(&__MBAR[0x008910])) +-#define MCF_PSC_ACR3 (*(vuint8_t *)(&__MBAR[0x008910])) +-#define MCF_PSC_ISR3 (*(vuint16_t*)(&__MBAR[0x008914])) +-#define MCF_PSC_IMR3 (*(vuint16_t*)(&__MBAR[0x008914])) +-#define MCF_PSC_CTUR3 (*(vuint8_t *)(&__MBAR[0x008918])) +-#define MCF_PSC_CTLR3 (*(vuint8_t *)(&__MBAR[0x00891C])) +-#define MCF_PSC_IP3 (*(vuint8_t *)(&__MBAR[0x008934])) +-#define MCF_PSC_OPSET3 (*(vuint8_t *)(&__MBAR[0x008938])) +-#define MCF_PSC_OPRESET3 (*(vuint8_t *)(&__MBAR[0x00893C])) +-#define MCF_PSC_SICR3 (*(vuint8_t *)(&__MBAR[0x008940])) +-#define MCF_PSC_IRCR13 (*(vuint8_t *)(&__MBAR[0x008944])) +-#define MCF_PSC_IRCR23 (*(vuint8_t *)(&__MBAR[0x008948])) +-#define MCF_PSC_IRSDR3 (*(vuint8_t *)(&__MBAR[0x00894C])) +-#define MCF_PSC_IRMDR3 (*(vuint8_t *)(&__MBAR[0x008950])) +-#define MCF_PSC_IRFDR3 (*(vuint8_t *)(&__MBAR[0x008954])) +-#define MCF_PSC_RFCNT3 (*(vuint16_t*)(&__MBAR[0x008958])) +-#define MCF_PSC_TFCNT3 (*(vuint16_t*)(&__MBAR[0x00895C])) +-#define MCF_PSC_RFSR3 (*(vuint16_t*)(&__MBAR[0x008964])) +-#define MCF_PSC_TFSR3 (*(vuint16_t*)(&__MBAR[0x008984])) +-#define MCF_PSC_RFCR3 (*(vuint32_t*)(&__MBAR[0x008968])) +-#define MCF_PSC_TFCR3 (*(vuint32_t*)(&__MBAR[0x008988])) +-#define MCF_PSC_RFAR3 (*(vuint16_t*)(&__MBAR[0x00896E])) +-#define MCF_PSC_TFAR3 (*(vuint16_t*)(&__MBAR[0x00898E])) +-#define MCF_PSC_RFRP3 (*(vuint16_t*)(&__MBAR[0x008972])) +-#define MCF_PSC_TFRP3 (*(vuint16_t*)(&__MBAR[0x008992])) +-#define MCF_PSC_RFWP3 (*(vuint16_t*)(&__MBAR[0x008976])) +-#define MCF_PSC_TFWP3 (*(vuint16_t*)(&__MBAR[0x008996])) +-#define MCF_PSC_RLRFP3 (*(vuint16_t*)(&__MBAR[0x00897A])) +-#define MCF_PSC_TLRFP3 (*(vuint16_t*)(&__MBAR[0x00899A])) +-#define MCF_PSC_RLWFP3 (*(vuint16_t*)(&__MBAR[0x00897E])) +-#define MCF_PSC_TLWFP3 (*(vuint16_t*)(&__MBAR[0x00899E])) +-#define MCF_PSC_MR(x) (*(vuint8_t *)(&__MBAR[0x008600+((x)*0x100)])) +-#define MCF_PSC_SR(x) (*(vuint16_t*)(&__MBAR[0x008604+((x)*0x100)])) +-#define MCF_PSC_CSR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) +-#define MCF_PSC_CR(x) (*(vuint8_t *)(&__MBAR[0x008608+((x)*0x100)])) +-#define MCF_PSC_RB(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) +-#define MCF_PSC_TB(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) +-#define MCF_PSC_TB_8BIT(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) +-#define MCF_PSC_TB_16BIT(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) +-#define MCF_PSC_TB_AC97(x) (*(vuint32_t*)(&__MBAR[0x00860C+((x)*0x100)])) +-#define MCF_PSC_IPCR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) +-#define MCF_PSC_ACR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) +-#define MCF_PSC_ISR(x) (*(vuint16_t*)(&__MBAR[0x008614+((x)*0x100)])) +-#define MCF_PSC_IMR(x) (*(vuint16_t*)(&__MBAR[0x008614+((x)*0x100)])) +-#define MCF_PSC_CTUR(x) (*(vuint8_t *)(&__MBAR[0x008618+((x)*0x100)])) +-#define MCF_PSC_CTLR(x) (*(vuint8_t *)(&__MBAR[0x00861C+((x)*0x100)])) +-#define MCF_PSC_IP(x) (*(vuint8_t *)(&__MBAR[0x008634+((x)*0x100)])) +-#define MCF_PSC_OPSET(x) (*(vuint8_t *)(&__MBAR[0x008638+((x)*0x100)])) +-#define MCF_PSC_OPRESET(x) (*(vuint8_t *)(&__MBAR[0x00863C+((x)*0x100)])) +-#define MCF_PSC_SICR(x) (*(vuint8_t *)(&__MBAR[0x008640+((x)*0x100)])) +-#define MCF_PSC_IRCR1(x) (*(vuint8_t *)(&__MBAR[0x008644+((x)*0x100)])) +-#define MCF_PSC_IRCR2(x) (*(vuint8_t *)(&__MBAR[0x008648+((x)*0x100)])) +-#define MCF_PSC_IRSDR(x) (*(vuint8_t *)(&__MBAR[0x00864C+((x)*0x100)])) +-#define MCF_PSC_IRMDR(x) (*(vuint8_t *)(&__MBAR[0x008650+((x)*0x100)])) +-#define MCF_PSC_IRFDR(x) (*(vuint8_t *)(&__MBAR[0x008654+((x)*0x100)])) +-#define MCF_PSC_RFCNT(x) (*(vuint16_t*)(&__MBAR[0x008658+((x)*0x100)])) +-#define MCF_PSC_TFCNT(x) (*(vuint16_t*)(&__MBAR[0x00865C+((x)*0x100)])) +-#define MCF_PSC_RFSR(x) (*(vuint16_t*)(&__MBAR[0x008664+((x)*0x100)])) +-#define MCF_PSC_TFSR(x) (*(vuint16_t*)(&__MBAR[0x008684+((x)*0x100)])) +-#define MCF_PSC_RFCR(x) (*(vuint32_t*)(&__MBAR[0x008668+((x)*0x100)])) +-#define MCF_PSC_TFCR(x) (*(vuint32_t*)(&__MBAR[0x008688+((x)*0x100)])) +-#define MCF_PSC_RFAR(x) (*(vuint16_t*)(&__MBAR[0x00866E+((x)*0x100)])) +-#define MCF_PSC_TFAR(x) (*(vuint16_t*)(&__MBAR[0x00868E+((x)*0x100)])) +-#define MCF_PSC_RFRP(x) (*(vuint16_t*)(&__MBAR[0x008672+((x)*0x100)])) +-#define MCF_PSC_TFRP(x) (*(vuint16_t*)(&__MBAR[0x008692+((x)*0x100)])) +-#define MCF_PSC_RFWP(x) (*(vuint16_t*)(&__MBAR[0x008676+((x)*0x100)])) +-#define MCF_PSC_TFWP(x) (*(vuint16_t*)(&__MBAR[0x008696+((x)*0x100)])) +-#define MCF_PSC_RLRFP(x) (*(vuint16_t*)(&__MBAR[0x00867A+((x)*0x100)])) +-#define MCF_PSC_TLRFP(x) (*(vuint16_t*)(&__MBAR[0x00869A+((x)*0x100)])) +-#define MCF_PSC_RLWFP(x) (*(vuint16_t*)(&__MBAR[0x00867E+((x)*0x100)])) +-#define MCF_PSC_TLWFP(x) (*(vuint16_t*)(&__MBAR[0x00869E+((x)*0x100)])) +- +-/* Bit definitions and macros for MCF_PSC_MR */ +-#define MCF_PSC_MR_BC(x) (((x)&0x03)<<0) +-#define MCF_PSC_MR_PT (0x04) +-#define MCF_PSC_MR_PM(x) (((x)&0x03)<<3) +-#define MCF_PSC_MR_ERR (0x20) +-#define MCF_PSC_MR_RXIRQ (0x40) +-#define MCF_PSC_MR_RXRTS (0x80) +-#define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0) +-#define MCF_PSC_MR_TXCTS (0x10) +-#define MCF_PSC_MR_TXRTS (0x20) +-#define MCF_PSC_MR_CM(x) (((x)&0x03)<<6) +-#define MCF_PSC_MR_PM_MULTI_ADDR (0x1C) +-#define MCF_PSC_MR_PM_MULTI_DATA (0x18) +-#define MCF_PSC_MR_PM_NONE (0x10) +-#define MCF_PSC_MR_PM_FORCE_HI (0x0C) +-#define MCF_PSC_MR_PM_FORCE_LO (0x08) +-#define MCF_PSC_MR_PM_ODD (0x04) +-#define MCF_PSC_MR_PM_EVEN (0x00) +-#define MCF_PSC_MR_BC_5 (0x00) +-#define MCF_PSC_MR_BC_6 (0x01) +-#define MCF_PSC_MR_BC_7 (0x02) +-#define MCF_PSC_MR_BC_8 (0x03) +-#define MCF_PSC_MR_CM_NORMAL (0x00) +-#define MCF_PSC_MR_CM_ECHO (0x40) +-#define MCF_PSC_MR_CM_LOCAL_LOOP (0x80) +-#define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0) +-#define MCF_PSC_MR_SB_STOP_BITS_1 (0x07) +-#define MCF_PSC_MR_SB_STOP_BITS_15 (0x08) +-#define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F) +- +-/* Bit definitions and macros for MCF_PSC_SR */ +-#define MCF_PSC_SR_ERR (0x0040) +-#define MCF_PSC_SR_CDE_DEOF (0x0080) +-#define MCF_PSC_SR_RXRDY (0x0100) +-#define MCF_PSC_SR_FU (0x0200) +-#define MCF_PSC_SR_TXRDY (0x0400) +-#define MCF_PSC_SR_TXEMP_URERR (0x0800) +-#define MCF_PSC_SR_OE (0x1000) +-#define MCF_PSC_SR_PE_CRCERR (0x2000) +-#define MCF_PSC_SR_FE_PHYERR (0x4000) +-#define MCF_PSC_SR_RB_NEOF (0x8000) +- +-/* Bit definitions and macros for MCF_PSC_CSR */ +-#define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0) +-#define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4) +-#define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0) +-#define MCF_PSC_CSR_RCSEL_CTM16 (0xE0) +-#define MCF_PSC_CSR_RCSEL_CTM (0xF0) +-#define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D) +-#define MCF_PSC_CSR_TCSEL_CTM16 (0x0E) +-#define MCF_PSC_CSR_TCSEL_CTM (0x0F) +- +-/* Bit definitions and macros for MCF_PSC_CR */ +-#define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0) +-#define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2) +-#define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4) +-#define MCF_PSC_CR_NONE (0x00) +-#define MCF_PSC_CR_STOP_BREAK (0x70) +-#define MCF_PSC_CR_START_BREAK (0x60) +-#define MCF_PSC_CR_BKCHGINT (0x50) +-#define MCF_PSC_CR_RESET_ERROR (0x40) +-#define MCF_PSC_CR_RESET_TX (0x30) +-#define MCF_PSC_CR_RESET_RX (0x20) +-#define MCF_PSC_CR_RESET_MR (0x10) +-#define MCF_PSC_CR_TX_DISABLED (0x08) +-#define MCF_PSC_CR_TX_ENABLED (0x04) +-#define MCF_PSC_CR_RX_DISABLED (0x02) +-#define MCF_PSC_CR_RX_ENABLED (0x01) +- +-/* Bit definitions and macros for MCF_PSC_TB_8BIT */ +-#define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0) +-#define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8) +-#define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16) +-#define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24) +- +-/* Bit definitions and macros for MCF_PSC_TB_16BIT */ +-#define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0) +-#define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16) +- +-/* Bit definitions and macros for MCF_PSC_TB_AC97 */ +-#define MCF_PSC_TB_AC97_SOF (0x00000800) +-#define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12) +- +-/* Bit definitions and macros for MCF_PSC_IPCR */ +-#define MCF_PSC_IPCR_RESERVED (0x0C) +-#define MCF_PSC_IPCR_CTS (0x0D) +-#define MCF_PSC_IPCR_D_CTS (0x1C) +-#define MCF_PSC_IPCR_SYNC (0x8C) +- +-/* Bit definitions and macros for MCF_PSC_ACR */ +-#define MCF_PSC_ACR_IEC0 (0x01) +-#define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4) +-#define MCF_PSC_ACR_BRG (0x80) +- +-/* Bit definitions and macros for MCF_PSC_ISR */ +-#define MCF_PSC_ISR_ERR (0x0040) +-#define MCF_PSC_ISR_DEOF (0x0080) +-#define MCF_PSC_ISR_TXRDY (0x0100) +-#define MCF_PSC_ISR_RXRDY_FU (0x0200) +-#define MCF_PSC_ISR_DB (0x0400) +-#define MCF_PSC_ISR_IPC (0x8000) +- +-/* Bit definitions and macros for MCF_PSC_IMR */ +-#define MCF_PSC_IMR_ERR (0x0040) +-#define MCF_PSC_IMR_DEOF (0x0080) +-#define MCF_PSC_IMR_TXRDY (0x0100) +-#define MCF_PSC_IMR_RXRDY_FU (0x0200) +-#define MCF_PSC_IMR_DB (0x0400) +-#define MCF_PSC_IMR_IPC (0x8000) +- +-/* Bit definitions and macros for MCF_PSC_IP */ +-#define MCF_PSC_IP_CTS (0x01) +-#define MCF_PSC_IP_TGL (0x40) +-#define MCF_PSC_IP_LWPR_B (0x80) +- +-/* Bit definitions and macros for MCF_PSC_OPSET */ +-#define MCF_PSC_OPSET_RTS (0x01) +- +-/* Bit definitions and macros for MCF_PSC_OPRESET */ +-#define MCF_PSC_OPRESET_RTS (0x01) +- +-/* Bit definitions and macros for MCF_PSC_SICR */ +-#define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0) +-#define MCF_PSC_SICR_SHDIR (0x10) +-#define MCF_PSC_SICR_DTS (0x20) +-#define MCF_PSC_SICR_AWR (0x40) +-#define MCF_PSC_SICR_ACRB (0x80) +-#define MCF_PSC_SICR_SIM_UART (0x00) +-#define MCF_PSC_SICR_SIM_MODEM8 (0x01) +-#define MCF_PSC_SICR_SIM_MODEM16 (0x02) +-#define MCF_PSC_SICR_SIM_AC97 (0x03) +-#define MCF_PSC_SICR_SIM_SIR (0x04) +-#define MCF_PSC_SICR_SIM_MIR (0x05) +-#define MCF_PSC_SICR_SIM_FIR (0x06) +- +-/* Bit definitions and macros for MCF_PSC_IRCR1 */ +-#define MCF_PSC_IRCR1_SPUL (0x01) +-#define MCF_PSC_IRCR1_SIPEN (0x02) +-#define MCF_PSC_IRCR1_FD (0x04) +- +-/* Bit definitions and macros for MCF_PSC_IRCR2 */ +-#define MCF_PSC_IRCR2_NXTEOF (0x01) +-#define MCF_PSC_IRCR2_ABORT (0x02) +-#define MCF_PSC_IRCR2_SIPREQ (0x04) +- +-/* Bit definitions and macros for MCF_PSC_IRMDR */ +-#define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0) +-#define MCF_PSC_IRMDR_FREQ (0x80) +- +-/* Bit definitions and macros for MCF_PSC_IRFDR */ +-#define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0) +- +-/* Bit definitions and macros for MCF_PSC_RFCNT */ +-#define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_TFCNT */ +-#define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_RFSR */ +-#define MCF_PSC_RFSR_EMT (0x0001) +-#define MCF_PSC_RFSR_ALARM (0x0002) +-#define MCF_PSC_RFSR_FU (0x0004) +-#define MCF_PSC_RFSR_FRMRY (0x0008) +-#define MCF_PSC_RFSR_OF (0x0010) +-#define MCF_PSC_RFSR_UF (0x0020) +-#define MCF_PSC_RFSR_RXW (0x0040) +-#define MCF_PSC_RFSR_FAE (0x0080) +-#define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8) +-#define MCF_PSC_RFSR_TAG (0x1000) +-#define MCF_PSC_RFSR_TXW (0x4000) +-#define MCF_PSC_RFSR_IP (0x8000) +-#define MCF_PSC_RFSR_FRM_BYTE0 (0x0800) +-#define MCF_PSC_RFSR_FRM_BYTE1 (0x0400) +-#define MCF_PSC_RFSR_FRM_BYTE2 (0x0200) +-#define MCF_PSC_RFSR_FRM_BYTE3 (0x0100) +- +-/* Bit definitions and macros for MCF_PSC_TFSR */ +-#define MCF_PSC_TFSR_EMT (0x0001) +-#define MCF_PSC_TFSR_ALARM (0x0002) +-#define MCF_PSC_TFSR_FU (0x0004) +-#define MCF_PSC_TFSR_FRMRY (0x0008) +-#define MCF_PSC_TFSR_OF (0x0010) +-#define MCF_PSC_TFSR_UF (0x0020) +-#define MCF_PSC_TFSR_RXW (0x0040) +-#define MCF_PSC_TFSR_FAE (0x0080) +-#define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8) +-#define MCF_PSC_TFSR_TAG (0x1000) +-#define MCF_PSC_TFSR_TXW (0x4000) +-#define MCF_PSC_TFSR_IP (0x8000) +-#define MCF_PSC_TFSR_FRM_BYTE0 (0x0800) +-#define MCF_PSC_TFSR_FRM_BYTE1 (0x0400) +-#define MCF_PSC_TFSR_FRM_BYTE2 (0x0200) +-#define MCF_PSC_TFSR_FRM_BYTE3 (0x0100) +- +-/* Bit definitions and macros for MCF_PSC_RFCR */ +-#define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0) +-#define MCF_PSC_RFCR_TXW_MSK (0x00040000) +-#define MCF_PSC_RFCR_OF_MSK (0x00080000) +-#define MCF_PSC_RFCR_UF_MSK (0x00100000) +-#define MCF_PSC_RFCR_RXW_MSK (0x00200000) +-#define MCF_PSC_RFCR_FAE_MSK (0x00400000) +-#define MCF_PSC_RFCR_IP_MSK (0x00800000) +-#define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24) +-#define MCF_PSC_RFCR_FRMEN (0x08000000) +-#define MCF_PSC_RFCR_TIMER (0x10000000) +-#define MCF_PSC_RFCR_WRITETAG (0x20000000) +-#define MCF_PSC_RFCR_SHADOW (0x80000000) +- +-/* Bit definitions and macros for MCF_PSC_TFCR */ +-#define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0) +-#define MCF_PSC_TFCR_TXW_MSK (0x00040000) +-#define MCF_PSC_TFCR_OF_MSK (0x00080000) +-#define MCF_PSC_TFCR_UF_MSK (0x00100000) +-#define MCF_PSC_TFCR_RXW_MSK (0x00200000) +-#define MCF_PSC_TFCR_FAE_MSK (0x00400000) +-#define MCF_PSC_TFCR_IP_MSK (0x00800000) +-#define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24) +-#define MCF_PSC_TFCR_FRMEN (0x08000000) +-#define MCF_PSC_TFCR_TIMER (0x10000000) +-#define MCF_PSC_TFCR_WRITETAG (0x20000000) +-#define MCF_PSC_TFCR_SHADOW (0x80000000) +- +-/* Bit definitions and macros for MCF_PSC_RFAR */ +-#define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_TFAR */ +-#define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_RFRP */ +-#define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_TFRP */ +-#define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_RFWP */ +-#define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_TFWP */ +-#define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_RLRFP */ +-#define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_TLRFP */ +-#define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_RLWFP */ +-#define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0) +- +-/* Bit definitions and macros for MCF_PSC_TLWFP */ +-#define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0) +- +-#endif /* __MCF548X_PSC_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sdramc.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sdramc.h +deleted file mode 100644 +index 452332d..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sdramc.h ++++ /dev/null +@@ -1,109 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * SDRAM Controller (SDRAMC) +- */ +-#ifndef __MCF548X_SDRAMC_H__ +-#define __MCF548X_SDRAMC_H__ +- +-/* +- * SDRAM Controller (SDRAMC) +- */ +- +-/* Register read/write macros */ +-#define MCF_SDRAMC_SDRAMDS (*(vuint32_t*)(&__MBAR[0x000004])) +-#define MCF_SDRAMC_CS0CFG (*(vuint32_t*)(&__MBAR[0x000020])) +-#define MCF_SDRAMC_CS1CFG (*(vuint32_t*)(&__MBAR[0x000024])) +-#define MCF_SDRAMC_CS2CFG (*(vuint32_t*)(&__MBAR[0x000028])) +-#define MCF_SDRAMC_CS3CFG (*(vuint32_t*)(&__MBAR[0x00002C])) +-#define MCF_SDRAMC_CSnCFG(x) (*(vuint32_t*)(&__MBAR[0x000020+((x)*0x004)])) +-#define MCF_SDRAMC_SDMR (*(vuint32_t*)(&__MBAR[0x000100])) +-#define MCF_SDRAMC_SDCR (*(vuint32_t*)(&__MBAR[0x000104])) +-#define MCF_SDRAMC_SDCFG1 (*(vuint32_t*)(&__MBAR[0x000108])) +-#define MCF_SDRAMC_SDCFG2 (*(vuint32_t*)(&__MBAR[0x00010C])) +- +-/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */ +-#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x00000003)<<0) +-#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x00000003)<<2) +-#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x00000003)<<4) +-#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x00000003)<<6) +-#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x00000003)<<8) +-#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x02) +-#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x01) +-#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0x00) +-#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x03) +- +-/* Bit definitions and macros for MCF_SDRAMC_CSnCFG */ +-#define MCF_SDRAMC_CSnCFG_CSSZ(x) (((x)&0x0000001F)<<0) +-#define MCF_SDRAMC_CSnCFG_CSBA(x) (((x)&0x00000FFF)<<20) +-#define MCF_SDRAMC_CSnCFG_CSSZ_DIABLE (0x00000000) +-#define MCF_SDRAMC_CSnCFG_CSSZ_1MBYTE (0x00000013) +-#define MCF_SDRAMC_CSnCFG_CSSZ_2MBYTE (0x00000014) +-#define MCF_SDRAMC_CSnCFG_CSSZ_4MBYTE (0x00000015) +-#define MCF_SDRAMC_CSnCFG_CSSZ_8MBYTE (0x00000016) +-#define MCF_SDRAMC_CSnCFG_CSSZ_16MBYTE (0x00000017) +-#define MCF_SDRAMC_CSnCFG_CSSZ_32MBYTE (0x00000018) +-#define MCF_SDRAMC_CSnCFG_CSSZ_64MBYTE (0x00000019) +-#define MCF_SDRAMC_CSnCFG_CSSZ_128MBYTE (0x0000001A) +-#define MCF_SDRAMC_CSnCFG_CSSZ_256MBYTE (0x0000001B) +-#define MCF_SDRAMC_CSnCFG_CSSZ_512MBYTE (0x0000001C) +-#define MCF_SDRAMC_CSnCFG_CSSZ_1GBYTE (0x0000001D) +-#define MCF_SDRAMC_CSnCFG_CSSZ_2GBYTE (0x0000001E) +-#define MCF_SDRAMC_CSnCFG_CSSZ_4GBYTE (0x0000001F) +- +-/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +-#define MCF_SDRAMC_SDMR_CMD (0x00010000) +-#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +-#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) +-#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) +-#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) +- +-/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +-#define MCF_SDRAMC_SDCR_IPALL (0x00000002) +-#define MCF_SDRAMC_SDCR_IREF (0x00000004) +-#define MCF_SDRAMC_SDCR_BUFF (0x00000010) +-#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +-#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +-#define MCF_SDRAMC_SDCR_DRIVE (0x00400000) +-#define MCF_SDRAMC_SDCR_AP (0x00800000) +-#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +-#define MCF_SDRAMC_SDCR_REF (0x10000000) +-#define MCF_SDRAMC_SDCR_DDR (0x20000000) +-#define MCF_SDRAMC_SDCR_CKE (0x40000000) +-#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) +- +-/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +-#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) +-#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +-#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +-#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +-#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +-#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +-#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) +- +-/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +-#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) +-#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +-#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +-#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) +- +-#endif /* __MCF548X_SDRAMC_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sec.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sec.h +deleted file mode 100644 +index 552527d..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sec.h ++++ /dev/null +@@ -1,389 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Integrated Security Engine (SEC) +- */ +-#ifndef __MCF548X_SEC_H__ +-#define __MCF548X_SEC_H__ +- +-/* +- * Integrated Security Engine (SEC) +- */ +- +-/* Register read/write macros */ +-#define MCF_SEC_EUACRH (*(vuint32_t*)(&__MBAR[0x021000])) +-#define MCF_SEC_EUACRL (*(vuint32_t*)(&__MBAR[0x021004])) +-#define MCF_SEC_EUASRH (*(vuint32_t*)(&__MBAR[0x021028])) +-#define MCF_SEC_EUASRL (*(vuint32_t*)(&__MBAR[0x02102C])) +-#define MCF_SEC_SIMRH (*(vuint32_t*)(&__MBAR[0x021008])) +-#define MCF_SEC_SIMRL (*(vuint32_t*)(&__MBAR[0x02100C])) +-#define MCF_SEC_SISRH (*(vuint32_t*)(&__MBAR[0x021010])) +-#define MCF_SEC_SISRL (*(vuint32_t*)(&__MBAR[0x021014])) +-#define MCF_SEC_SICRH (*(vuint32_t*)(&__MBAR[0x021018])) +-#define MCF_SEC_SICRL (*(vuint32_t*)(&__MBAR[0x02101C])) +-#define MCF_SEC_SIDR (*(vuint32_t*)(&__MBAR[0x021020])) +-#define MCF_SEC_SMCR (*(vuint32_t*)(&__MBAR[0x021030])) +-#define MCF_SEC_MEAR (*(vuint32_t*)(&__MBAR[0x021038])) +-#define MCF_SEC_CCCR0 (*(vuint32_t*)(&__MBAR[0x02200C])) +-#define MCF_SEC_CCCR1 (*(vuint32_t*)(&__MBAR[0x02300C])) +-#define MCF_SEC_CCPSRH0 (*(vuint32_t*)(&__MBAR[0x022010])) +-#define MCF_SEC_CCPSRH1 (*(vuint32_t*)(&__MBAR[0x023010])) +-#define MCF_SEC_CCPSRL0 (*(vuint32_t*)(&__MBAR[0x022014])) +-#define MCF_SEC_CCPSRL1 (*(vuint32_t*)(&__MBAR[0x023014])) +-#define MCF_SEC_CDPR0 (*(vuint32_t*)(&__MBAR[0x022044])) +-#define MCF_SEC_CDPR1 (*(vuint32_t*)(&__MBAR[0x023044])) +-#define MCF_SEC_FR0 (*(vuint32_t*)(&__MBAR[0x02204C])) +-#define MCF_SEC_FR1 (*(vuint32_t*)(&__MBAR[0x02304C])) +-#define MCF_SEC_AFRCR (*(vuint32_t*)(&__MBAR[0x028018])) +-#define MCF_SEC_AFSR (*(vuint32_t*)(&__MBAR[0x028028])) +-#define MCF_SEC_AFISR (*(vuint32_t*)(&__MBAR[0x028030])) +-#define MCF_SEC_AFIMR (*(vuint32_t*)(&__MBAR[0x028038])) +-#define MCF_SEC_DRCR (*(vuint32_t*)(&__MBAR[0x02A018])) +-#define MCF_SEC_DSR (*(vuint32_t*)(&__MBAR[0x02A028])) +-#define MCF_SEC_DISR (*(vuint32_t*)(&__MBAR[0x02A030])) +-#define MCF_SEC_DIMR (*(vuint32_t*)(&__MBAR[0x02A038])) +-#define MCF_SEC_MDRCR (*(vuint32_t*)(&__MBAR[0x02C018])) +-#define MCF_SEC_MDSR (*(vuint32_t*)(&__MBAR[0x02C028])) +-#define MCF_SEC_MDISR (*(vuint32_t*)(&__MBAR[0x02C030])) +-#define MCF_SEC_MDIMR (*(vuint32_t*)(&__MBAR[0x02C038])) +-#define MCF_SEC_RNGRCR (*(vuint32_t*)(&__MBAR[0x02E018])) +-#define MCF_SEC_RNGSR (*(vuint32_t*)(&__MBAR[0x02E028])) +-#define MCF_SEC_RNGISR (*(vuint32_t*)(&__MBAR[0x02E030])) +-#define MCF_SEC_RNGIMR (*(vuint32_t*)(&__MBAR[0x02E038])) +-#define MCF_SEC_AESRCR (*(vuint32_t*)(&__MBAR[0x032018])) +-#define MCF_SEC_AESSR (*(vuint32_t*)(&__MBAR[0x032028])) +-#define MCF_SEC_AESISR (*(vuint32_t*)(&__MBAR[0x032030])) +-#define MCF_SEC_AESIMR (*(vuint32_t*)(&__MBAR[0x032038])) +- +-/* Bit definitions and macros for MCF_SEC_EUACRH */ +-#define MCF_SEC_EUACRH_AFEU(x) (((x)&0x0000000F)<<0) +-#define MCF_SEC_EUACRH_MDEU(x) (((x)&0x0000000F)<<8) +-#define MCF_SEC_EUACRH_RNG(x) (((x)&0x0000000F)<<24) +-#define MCF_SEC_EUACRH_RNG_NOASSIGN (0x00000000) +-#define MCF_SEC_EUACRH_RNG_CHA0 (0x01000000) +-#define MCF_SEC_EUACRH_RNG_CHA1 (0x02000000) +-#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0x00000000) +-#define MCF_SEC_EUACRH_MDEU_CHA0 (0x00000100) +-#define MCF_SEC_EUACRH_MDEU_CHA1 (0x00000200) +-#define MCF_SEC_EUACRH_AFEU_NOASSIGN (0x00000000) +-#define MCF_SEC_EUACRH_AFEU_CHA0 (0x00000001) +-#define MCF_SEC_EUACRH_AFEU_CHA1 (0x00000002) +- +-/* Bit definitions and macros for MCF_SEC_EUACRL */ +-#define MCF_SEC_EUACRL_AESU(x) (((x)&0x0000000F)<<16) +-#define MCF_SEC_EUACRL_DEU(x) (((x)&0x0000000F)<<24) +-#define MCF_SEC_EUACRL_DEU_NOASSIGN (0x00000000) +-#define MCF_SEC_EUACRL_DEU_CHA0 (0x01000000) +-#define MCF_SEC_EUACRL_DEU_CHA1 (0x02000000) +-#define MCF_SEC_EUACRL_AESU_NOASSIGN (0x00000000) +-#define MCF_SEC_EUACRL_AESU_CHA0 (0x00010000) +-#define MCF_SEC_EUACRL_AESU_CHA1 (0x00020000) +- +-/* Bit definitions and macros for MCF_SEC_EUASRH */ +-#define MCF_SEC_EUASRH_AFEU(x) (((x)&0x0000000F)<<0) +-#define MCF_SEC_EUASRH_MDEU(x) (((x)&0x0000000F)<<8) +-#define MCF_SEC_EUASRH_RNG(x) (((x)&0x0000000F)<<24) +- +-/* Bit definitions and macros for MCF_SEC_EUASRL */ +-#define MCF_SEC_EUASRL_AESU(x) (((x)&0x0000000F)<<16) +-#define MCF_SEC_EUASRL_DEU(x) (((x)&0x0000000F)<<24) +- +-/* Bit definitions and macros for MCF_SEC_SIMRH */ +-#define MCF_SEC_SIMRH_AERR (0x08000000) +-#define MCF_SEC_SIMRH_CHA0DN (0x10000000) +-#define MCF_SEC_SIMRH_CHA0ERR (0x20000000) +-#define MCF_SEC_SIMRH_CHA1DN (0x40000000) +-#define MCF_SEC_SIMRH_CHA1ERR (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_SIMRL */ +-#define MCF_SEC_SIMRL_TEA (0x00000040) +-#define MCF_SEC_SIMRL_DEUDN (0x00000100) +-#define MCF_SEC_SIMRL_DEUERR (0x00000200) +-#define MCF_SEC_SIMRL_AESUDN (0x00001000) +-#define MCF_SEC_SIMRL_AESUERR (0x00002000) +-#define MCF_SEC_SIMRL_MDEUDN (0x00010000) +-#define MCF_SEC_SIMRL_MDEUERR (0x00020000) +-#define MCF_SEC_SIMRL_AFEUDN (0x00100000) +-#define MCF_SEC_SIMRL_AFEUERR (0x00200000) +-#define MCF_SEC_SIMRL_RNGDN (0x01000000) +-#define MCF_SEC_SIMRL_RNGERR (0x02000000) +- +-/* Bit definitions and macros for MCF_SEC_SISRH */ +-#define MCF_SEC_SISRH_AERR (0x08000000) +-#define MCF_SEC_SISRH_CHA0DN (0x10000000) +-#define MCF_SEC_SISRH_CHA0ERR (0x20000000) +-#define MCF_SEC_SISRH_CHA1DN (0x40000000) +-#define MCF_SEC_SISRH_CHA1ERR (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_SISRL */ +-#define MCF_SEC_SISRL_TEA (0x00000040) +-#define MCF_SEC_SISRL_DEUDN (0x00000100) +-#define MCF_SEC_SISRL_DEUERR (0x00000200) +-#define MCF_SEC_SISRL_AESUDN (0x00001000) +-#define MCF_SEC_SISRL_AESUERR (0x00002000) +-#define MCF_SEC_SISRL_MDEUDN (0x00010000) +-#define MCF_SEC_SISRL_MDEUERR (0x00020000) +-#define MCF_SEC_SISRL_AFEUDN (0x00100000) +-#define MCF_SEC_SISRL_AFEUERR (0x00200000) +-#define MCF_SEC_SISRL_RNGDN (0x01000000) +-#define MCF_SEC_SISRL_RNGERR (0x02000000) +- +-/* Bit definitions and macros for MCF_SEC_SICRH */ +-#define MCF_SEC_SICRH_AERR (0x08000000) +-#define MCF_SEC_SICRH_CHA0DN (0x10000000) +-#define MCF_SEC_SICRH_CHA0ERR (0x20000000) +-#define MCF_SEC_SICRH_CHA1DN (0x40000000) +-#define MCF_SEC_SICRH_CHA1ERR (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_SICRL */ +-#define MCF_SEC_SICRL_TEA (0x00000040) +-#define MCF_SEC_SICRL_DEUDN (0x00000100) +-#define MCF_SEC_SICRL_DEUERR (0x00000200) +-#define MCF_SEC_SICRL_AESUDN (0x00001000) +-#define MCF_SEC_SICRL_AESUERR (0x00002000) +-#define MCF_SEC_SICRL_MDEUDN (0x00010000) +-#define MCF_SEC_SICRL_MDEUERR (0x00020000) +-#define MCF_SEC_SICRL_AFEUDN (0x00100000) +-#define MCF_SEC_SICRL_AFEUERR (0x00200000) +-#define MCF_SEC_SICRL_RNGDN (0x01000000) +-#define MCF_SEC_SICRL_RNGERR (0x02000000) +- +-/* Bit definitions and macros for MCF_SEC_SMCR */ +-#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0x0000000F)<<4) +-#define MCF_SEC_SMCR_SWR (0x01000000) +-#define MCF_SEC_SMCR_CURR_CHAN_1 (0x00000010) +-#define MCF_SEC_SMCR_CURR_CHAN_2 (0x00000020) +- +-/* Bit definitions and macros for MCF_SEC_CCCRn */ +-#define MCF_SEC_CCCRn_RST (0x00000001) +-#define MCF_SEC_CCCRn_CDIE (0x00000002) +-#define MCF_SEC_CCCRn_NT (0x00000004) +-#define MCF_SEC_CCCRn_NE (0x00000008) +-#define MCF_SEC_CCCRn_WE (0x00000010) +-#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x00000007)<<8) +-#define MCF_SEC_CCCRn_BURST_SIZE_2 (0x00000000) +-#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x00000100) +-#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x00000200) +-#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x00000300) +-#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x00000400) +-#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x00000500) +-#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x00000600) +-#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x00000700) +- +-/* Bit definitions and macros for MCF_SEC_CCPSRHn */ +-#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0x000000FF)<<0) +- +-/* Bit definitions and macros for MCF_SEC_CCPSRLn */ +-#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0x000000FF)<<0) +-#define MCF_SEC_CCPSRLn_EUERR (0x00000100) +-#define MCF_SEC_CCPSRLn_SERR (0x00000200) +-#define MCF_SEC_CCPSRLn_DERR (0x00000400) +-#define MCF_SEC_CCPSRLn_PERR (0x00001000) +-#define MCF_SEC_CCPSRLn_TEA (0x00002000) +-#define MCF_SEC_CCPSRLn_SD (0x00010000) +-#define MCF_SEC_CCPSRLn_PD (0x00020000) +-#define MCF_SEC_CCPSRLn_SRD (0x00040000) +-#define MCF_SEC_CCPSRLn_PRD (0x00080000) +-#define MCF_SEC_CCPSRLn_SG (0x00100000) +-#define MCF_SEC_CCPSRLn_PG (0x00200000) +-#define MCF_SEC_CCPSRLn_SR (0x00400000) +-#define MCF_SEC_CCPSRLn_PR (0x00800000) +-#define MCF_SEC_CCPSRLn_MO (0x01000000) +-#define MCF_SEC_CCPSRLn_MI (0x02000000) +-#define MCF_SEC_CCPSRLn_STAT (0x04000000) +- +-/* Bit definitions and macros for MCF_SEC_AFRCR */ +-#define MCF_SEC_AFRCR_SR (0x01000000) +-#define MCF_SEC_AFRCR_MI (0x02000000) +-#define MCF_SEC_AFRCR_RI (0x04000000) +- +-/* Bit definitions and macros for MCF_SEC_AFSR */ +-#define MCF_SEC_AFSR_RD (0x01000000) +-#define MCF_SEC_AFSR_ID (0x02000000) +-#define MCF_SEC_AFSR_IE (0x04000000) +-#define MCF_SEC_AFSR_OFE (0x08000000) +-#define MCF_SEC_AFSR_IFW (0x10000000) +-#define MCF_SEC_AFSR_HALT (0x20000000) +- +-/* Bit definitions and macros for MCF_SEC_AFISR */ +-#define MCF_SEC_AFISR_DSE (0x00010000) +-#define MCF_SEC_AFISR_KSE (0x00020000) +-#define MCF_SEC_AFISR_CE (0x00040000) +-#define MCF_SEC_AFISR_ERE (0x00080000) +-#define MCF_SEC_AFISR_IE (0x00100000) +-#define MCF_SEC_AFISR_OFU (0x02000000) +-#define MCF_SEC_AFISR_IFO (0x04000000) +-#define MCF_SEC_AFISR_IFE (0x10000000) +-#define MCF_SEC_AFISR_OFE (0x20000000) +-#define MCF_SEC_AFISR_AE (0x40000000) +-#define MCF_SEC_AFISR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_AFIMR */ +-#define MCF_SEC_AFIMR_DSE (0x00010000) +-#define MCF_SEC_AFIMR_KSE (0x00020000) +-#define MCF_SEC_AFIMR_CE (0x00040000) +-#define MCF_SEC_AFIMR_ERE (0x00080000) +-#define MCF_SEC_AFIMR_IE (0x00100000) +-#define MCF_SEC_AFIMR_OFU (0x02000000) +-#define MCF_SEC_AFIMR_IFO (0x04000000) +-#define MCF_SEC_AFIMR_IFE (0x10000000) +-#define MCF_SEC_AFIMR_OFE (0x20000000) +-#define MCF_SEC_AFIMR_AE (0x40000000) +-#define MCF_SEC_AFIMR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_DRCR */ +-#define MCF_SEC_DRCR_SR (0x01000000) +-#define MCF_SEC_DRCR_MI (0x02000000) +-#define MCF_SEC_DRCR_RI (0x04000000) +- +-/* Bit definitions and macros for MCF_SEC_DSR */ +-#define MCF_SEC_DSR_RD (0x01000000) +-#define MCF_SEC_DSR_ID (0x02000000) +-#define MCF_SEC_DSR_IE (0x04000000) +-#define MCF_SEC_DSR_OFR (0x08000000) +-#define MCF_SEC_DSR_IFW (0x10000000) +-#define MCF_SEC_DSR_HALT (0x20000000) +- +-/* Bit definitions and macros for MCF_SEC_DISR */ +-#define MCF_SEC_DISR_DSE (0x00010000) +-#define MCF_SEC_DISR_KSE (0x00020000) +-#define MCF_SEC_DISR_CE (0x00040000) +-#define MCF_SEC_DISR_ERE (0x00080000) +-#define MCF_SEC_DISR_IE (0x00100000) +-#define MCF_SEC_DISR_KPE (0x00200000) +-#define MCF_SEC_DISR_OFU (0x02000000) +-#define MCF_SEC_DISR_IFO (0x04000000) +-#define MCF_SEC_DISR_IFE (0x10000000) +-#define MCF_SEC_DISR_OFE (0x20000000) +-#define MCF_SEC_DISR_AE (0x40000000) +-#define MCF_SEC_DISR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_DIMR */ +-#define MCF_SEC_DIMR_DSE (0x00010000) +-#define MCF_SEC_DIMR_KSE (0x00020000) +-#define MCF_SEC_DIMR_CE (0x00040000) +-#define MCF_SEC_DIMR_ERE (0x00080000) +-#define MCF_SEC_DIMR_IE (0x00100000) +-#define MCF_SEC_DIMR_KPE (0x00200000) +-#define MCF_SEC_DIMR_OFU (0x02000000) +-#define MCF_SEC_DIMR_IFO (0x04000000) +-#define MCF_SEC_DIMR_IFE (0x10000000) +-#define MCF_SEC_DIMR_OFE (0x20000000) +-#define MCF_SEC_DIMR_AE (0x40000000) +-#define MCF_SEC_DIMR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_MDRCR */ +-#define MCF_SEC_MDRCR_SR (0x01000000) +-#define MCF_SEC_MDRCR_MI (0x02000000) +-#define MCF_SEC_MDRCR_RI (0x04000000) +- +-/* Bit definitions and macros for MCF_SEC_MDSR */ +-#define MCF_SEC_MDSR_RD (0x01000000) +-#define MCF_SEC_MDSR_ID (0x02000000) +-#define MCF_SEC_MDSR_IE (0x04000000) +-#define MCF_SEC_MDSR_IFW (0x10000000) +-#define MCF_SEC_MDSR_HALT (0x20000000) +- +-/* Bit definitions and macros for MCF_SEC_MDISR */ +-#define MCF_SEC_MDISR_DSE (0x00010000) +-#define MCF_SEC_MDISR_KSE (0x00020000) +-#define MCF_SEC_MDISR_CE (0x00040000) +-#define MCF_SEC_MDISR_ERE (0x00080000) +-#define MCF_SEC_MDISR_IE (0x00100000) +-#define MCF_SEC_MDISR_IFO (0x04000000) +-#define MCF_SEC_MDISR_AE (0x40000000) +-#define MCF_SEC_MDISR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_MDIMR */ +-#define MCF_SEC_MDIMR_DSE (0x00010000) +-#define MCF_SEC_MDIMR_KSE (0x00020000) +-#define MCF_SEC_MDIMR_CE (0x00040000) +-#define MCF_SEC_MDIMR_ERE (0x00080000) +-#define MCF_SEC_MDIMR_IE (0x00100000) +-#define MCF_SEC_MDIMR_IFO (0x04000000) +-#define MCF_SEC_MDIMR_AE (0x40000000) +-#define MCF_SEC_MDIMR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_RNGRCR */ +-#define MCF_SEC_RNGRCR_SR (0x01000000) +-#define MCF_SEC_RNGRCR_MI (0x02000000) +-#define MCF_SEC_RNGRCR_RI (0x04000000) +- +-/* Bit definitions and macros for MCF_SEC_RNGSR */ +-#define MCF_SEC_RNGSR_RD (0x01000000) +-#define MCF_SEC_RNGSR_O (0x02000000) +-#define MCF_SEC_RNGSR_IE (0x04000000) +-#define MCF_SEC_RNGSR_OFR (0x08000000) +-#define MCF_SEC_RNGSR_HALT (0x20000000) +- +-/* Bit definitions and macros for MCF_SEC_RNGISR */ +-#define MCF_SEC_RNGISR_IE (0x00100000) +-#define MCF_SEC_RNGISR_OFU (0x02000000) +-#define MCF_SEC_RNGISR_AE (0x40000000) +-#define MCF_SEC_RNGISR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_RNGIMR */ +-#define MCF_SEC_RNGIMR_IE (0x00100000) +-#define MCF_SEC_RNGIMR_OFU (0x02000000) +-#define MCF_SEC_RNGIMR_AE (0x40000000) +-#define MCF_SEC_RNGIMR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_AESRCR */ +-#define MCF_SEC_AESRCR_SR (0x01000000) +-#define MCF_SEC_AESRCR_MI (0x02000000) +-#define MCF_SEC_AESRCR_RI (0x04000000) +- +-/* Bit definitions and macros for MCF_SEC_AESSR */ +-#define MCF_SEC_AESSR_RD (0x01000000) +-#define MCF_SEC_AESSR_ID (0x02000000) +-#define MCF_SEC_AESSR_IE (0x04000000) +-#define MCF_SEC_AESSR_OFR (0x08000000) +-#define MCF_SEC_AESSR_IFW (0x10000000) +-#define MCF_SEC_AESSR_HALT (0x20000000) +- +-/* Bit definitions and macros for MCF_SEC_AESISR */ +-#define MCF_SEC_AESISR_DSE (0x00010000) +-#define MCF_SEC_AESISR_KSE (0x00020000) +-#define MCF_SEC_AESISR_CE (0x00040000) +-#define MCF_SEC_AESISR_ERE (0x00080000) +-#define MCF_SEC_AESISR_IE (0x00100000) +-#define MCF_SEC_AESISR_OFU (0x02000000) +-#define MCF_SEC_AESISR_IFO (0x04000000) +-#define MCF_SEC_AESISR_IFE (0x10000000) +-#define MCF_SEC_AESISR_OFE (0x20000000) +-#define MCF_SEC_AESISR_AE (0x40000000) +-#define MCF_SEC_AESISR_ME (0x80000000) +- +-/* Bit definitions and macros for MCF_SEC_AESIMR */ +-#define MCF_SEC_AESIMR_DSE (0x00010000) +-#define MCF_SEC_AESIMR_KSE (0x00020000) +-#define MCF_SEC_AESIMR_CE (0x00040000) +-#define MCF_SEC_AESIMR_ERE (0x00080000) +-#define MCF_SEC_AESIMR_IE (0x00100000) +-#define MCF_SEC_AESIMR_OFU (0x02000000) +-#define MCF_SEC_AESIMR_IFO (0x04000000) +-#define MCF_SEC_AESIMR_IFE (0x10000000) +-#define MCF_SEC_AESIMR_OFE (0x20000000) +-#define MCF_SEC_AESIMR_AE (0x40000000) +-#define MCF_SEC_AESIMR_ME (0x80000000) +- +-#endif /* __MCF548X_SEC_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_siu.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_siu.h +deleted file mode 100644 +index 558530d..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_siu.h ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * DMA Serial Peripheral Interface (DSPI) +- */ +-#ifndef __MCF548X_SIU_H__ +-#define __MCF548X_SIU_H__ +- +-/* +- * System Integration Unit (SIU) +- */ +- +-/* Register read/write macros */ +-#define MCF_SIU_SBCR (*(vuint32_t*)(&__MBAR[0x000010])) +-#define MCF_SIU_SECSACR (*(vuint32_t*)(&__MBAR[0x000038])) +-#define MCF_SIU_RSR (*(vuint32_t*)(&__MBAR[0x000044])) +-#define MCF_SIU_JTAGID (*(vuint32_t*)(&__MBAR[0x000050])) +- +-/* Bit definitions and macros for MCF_SIU_SBCR */ +-#define MCF_SIU_SBCR_PIN2DSPI (0x08000000) +-#define MCF_SIU_SBCR_DMA2CPU (0x10000000) +-#define MCF_SIU_SBCR_CPU2DMA (0x20000000) +-#define MCF_SIU_SBCR_PIN2DMA (0x40000000) +-#define MCF_SIU_SBCR_PIN2CPU (0x80000000) +- +-/* Bit definitions and macros for MCF_SIU_SECSACR */ +-#define MCF_SIU_SECSACR_SEQEN (0x00000001) +- +-/* Bit definitions and macros for MCF_SIU_RSR */ +-#define MCF_SIU_RSR_RST (0x00000001) +-#define MCF_SIU_RSR_RSTWD (0x00000002) +-#define MCF_SIU_RSR_RSTJTG (0x00000008) +- +-/* Bit definitions and macros for MCF_SIU_JTAGID */ +-#define MCF_SIU_JTAGID_REV (0xF0000000) +-#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF) +-#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D) +-#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D) +-#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D) +-#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D) +-#define MCF_SIU_JTAGID_MCF5481 (0x0801001D) +-#define MCF_SIU_JTAGID_MCF5480 (0x0801101D) +-#define MCF_SIU_JTAGID_MCF5475 (0x0801201D) +-#define MCF_SIU_JTAGID_MCF5474 (0x0801301D) +-#define MCF_SIU_JTAGID_MCF5473 (0x0801401D) +-#define MCF_SIU_JTAGID_MCF5472 (0x0801501D) +-#define MCF_SIU_JTAGID_MCF5471 (0x0801601D) +-#define MCF_SIU_JTAGID_MCF5470 (0x0801701D) +- +-#endif /* __MCF548X_SIU_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_slt.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_slt.h +deleted file mode 100644 +index 10d94a4..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_slt.h ++++ /dev/null +@@ -1,71 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Slice Timers (SLT) +- */ +-#ifndef __MCF548X_SLT_H__ +-#define __MCF548X_SLT_H__ +- +-/* +- * Slice Timers (SLT) +- */ +- +-/* Register read/write macros */ +-#define MCF_SLT_SLTCNT0 (*(vuint32_t*)(&__MBAR[0x000900])) +-#define MCF_SLT_SCR0 (*(vuint32_t*)(&__MBAR[0x000904])) +-#define MCF_SLT_SCNT0 (*(vuint32_t*)(&__MBAR[0x000908])) +-#define MCF_SLT_SSR0 (*(vuint32_t*)(&__MBAR[0x00090C])) +- +-#define MCF_SLT_SLTCNT1 (*(vuint32_t*)(&__MBAR[0x000910])) +-#define MCF_SLT_SCR1 (*(vuint32_t*)(&__MBAR[0x000914])) +-#define MCF_SLT_SCNT1 (*(vuint32_t*)(&__MBAR[0x000918])) +-#define MCF_SLT_SSR1 (*(vuint32_t*)(&__MBAR[0x00091C])) +- +-#define MCF_SLT_SLTCNT(x) (*(vuint32_t*)(&__MBAR[0x000900+((x)*0x010)])) +-#define MCF_SLT_SCR(x) (*(vuint32_t*)(&__MBAR[0x000904+((x)*0x010)])) +-#define MCF_SLT_SCNT(x) (*(vuint32_t*)(&__MBAR[0x000908+((x)*0x010)])) +-#define MCF_SLT_SSR(x) (*(vuint32_t*)(&__MBAR[0x00090C+((x)*0x010)])) +- +-/* Bit definitions and macros for MCF_SLT_SCR */ +-#define MCF_SLT_SCR_TEN (0x01000000) +-#define MCF_SLT_SCR_IEN (0x02000000) +-#define MCF_SLT_SCR_RUN (0x04000000) +- +-/* Bit definitions and macros for MCF_SLT_SSR */ +-#define MCF_SLT_SSR_ST (0x01000000) +-#define MCF_SLT_SSR_BE (0x02000000) +- +- +-#ifndef __ASSEMBLY__ +- +-#define MCF_SLT_Address(x) ((struct mcf5xxx_slt*)(void*)(&__MBAR[0x000900+((x)*0x010)])) +- +-struct mcf5xxx_slt { +- vuint32_t STCNT; /* Slice Terminal Count */ +- vuint32_t SCR; /* Slice Timer Control Register */ +- vuint32_t SCNT; /* Slice Count Value */ +- vuint32_t SSR; /* Slice Timer Status Register */ +-}; +- +-#endif +- +-#endif /* __MCF548X_SLT_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sram.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sram.h +deleted file mode 100644 +index a706306..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_sram.h ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * 32KByte System SRAM (SRAM) +- */ +-#ifndef __MCF548X_SRAM_H__ +-#define __MCF548X_SRAM_H__ +- +-/* +- * 32KByte System SRAM (SRAM) +- */ +- +-/* Register read/write macros */ +-#define MCF_SRAM_SSCR (*(vuint32_t*)(&__MBAR[0x01FFC0])) +-#define MCF_SRAM_TCCR (*(vuint32_t*)(&__MBAR[0x01FFC4])) +-#define MCF_SRAM_TCCRDR (*(vuint32_t*)(&__MBAR[0x01FFC8])) +-#define MCF_SRAM_TCCRDW (*(vuint32_t*)(&__MBAR[0x01FFCC])) +-#define MCF_SRAM_TCCRSEC (*(vuint32_t*)(&__MBAR[0x01FFD0])) +- +-/* Bit definitions and macros for MCF_SRAM_SSCR */ +-#define MCF_SRAM_SSCR_INLV (0x00010000) +- +-/* Bit definitions and macros for MCF_SRAM_TCCR */ +-#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0x0000000F)<<0) +-#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0x0000000F)<<8) +-#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0x0000000F)<<16) +-#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0x0000000F)<<24) +- +-/* Bit definitions and macros for MCF_SRAM_TCCRDR */ +-#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0x0000000F)<<0) +-#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0x0000000F)<<8) +-#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0x0000000F)<<16) +-#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0x0000000F)<<24) +- +-/* Bit definitions and macros for MCF_SRAM_TCCRDW */ +-#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0x0000000F)<<0) +-#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0x0000000F)<<8) +-#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0x0000000F)<<16) +-#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0x0000000F)<<24) +- +-/* Bit definitions and macros for MCF_SRAM_TCCRSEC */ +-#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0x0000000F)<<0) +-#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0x0000000F)<<8) +-#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0x0000000F)<<16) +-#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0x0000000F)<<24) +- +-#endif /* __MCF548X_SRAM_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_uart.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_uart.h +deleted file mode 100644 +index 2fa25ce..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_uart.h ++++ /dev/null +@@ -1,233 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Programmable Serial Controller (UART Compatible Definitions) (UART) +- */ +-#ifndef __MCF548X_UART_H__ +-#define __MCF548X_UART_H__ +- +-/* +- * Programmable Serial Controller (UART Compatible Definitions) (UART) +- */ +- +-/* Register read/write macros */ +-#define MCF_UART_UMR0 (*(vuint8_t *)(&__MBAR[0x008600])) +-#define MCF_UART_USR0 (*(vuint8_t *)(&__MBAR[0x008604])) +-#define MCF_UART_UCSR0 (*(vuint8_t *)(&__MBAR[0x008604])) +-#define MCF_UART_UCR0 (*(vuint8_t *)(&__MBAR[0x008608])) +-#define MCF_UART_URB0 (*(vuint8_t *)(&__MBAR[0x00860C])) +-#define MCF_UART_UTB0 (*(vuint8_t *)(&__MBAR[0x00860C])) +-#define MCF_UART_UIPCR0 (*(vuint8_t *)(&__MBAR[0x008610])) +-#define MCF_UART_UACR0 (*(vuint8_t *)(&__MBAR[0x008610])) +-#define MCF_UART_UISR0 (*(vuint8_t *)(&__MBAR[0x008614])) +-#define MCF_UART_UIMR0 (*(vuint8_t *)(&__MBAR[0x008614])) +-#define MCF_UART_UBG10 (*(vuint8_t *)(&__MBAR[0x008618])) +-#define MCF_UART_UBG20 (*(vuint8_t *)(&__MBAR[0x00861C])) +-#define MCF_UART_UIP0 (*(vuint8_t *)(&__MBAR[0x008634])) +-#define MCF_UART_UOP10 (*(vuint8_t *)(&__MBAR[0x008638])) +-#define MCF_UART_UOP00 (*(vuint8_t *)(&__MBAR[0x00863C])) +- +-#define MCF_UART_UMR1 (*(vuint8_t *)(&__MBAR[0x008700])) +-#define MCF_UART_USR1 (*(vuint8_t *)(&__MBAR[0x008704])) +-#define MCF_UART_UCSR1 (*(vuint8_t *)(&__MBAR[0x008704])) +-#define MCF_UART_UCR1 (*(vuint8_t *)(&__MBAR[0x008708])) +-#define MCF_UART_URB1 (*(vuint8_t *)(&__MBAR[0x00870C])) +-#define MCF_UART_UTB1 (*(vuint8_t *)(&__MBAR[0x00870C])) +-#define MCF_UART_UIPCR1 (*(vuint8_t *)(&__MBAR[0x008710])) +-#define MCF_UART_UACR1 (*(vuint8_t *)(&__MBAR[0x008710])) +-#define MCF_UART_UISR1 (*(vuint8_t *)(&__MBAR[0x008714])) +-#define MCF_UART_UIMR1 (*(vuint8_t *)(&__MBAR[0x008714])) +-#define MCF_UART_UBG11 (*(vuint8_t *)(&__MBAR[0x008718])) +-#define MCF_UART_UBG21 (*(vuint8_t *)(&__MBAR[0x00871C])) +-#define MCF_UART_UIP1 (*(vuint8_t *)(&__MBAR[0x008734])) +-#define MCF_UART_UOP11 (*(vuint8_t *)(&__MBAR[0x008738])) +-#define MCF_UART_UOP01 (*(vuint8_t *)(&__MBAR[0x00873C])) +- +-#define MCF_UART_UMR2 (*(vuint8_t *)(&__MBAR[0x008800])) +-#define MCF_UART_USR2 (*(vuint8_t *)(&__MBAR[0x008804])) +-#define MCF_UART_UCSR2 (*(vuint8_t *)(&__MBAR[0x008804])) +-#define MCF_UART_UCR2 (*(vuint8_t *)(&__MBAR[0x008808])) +-#define MCF_UART_URB2 (*(vuint8_t *)(&__MBAR[0x00880C])) +-#define MCF_UART_UTB2 (*(vuint8_t *)(&__MBAR[0x00880C])) +-#define MCF_UART_UIPCR2 (*(vuint8_t *)(&__MBAR[0x008810])) +-#define MCF_UART_UACR2 (*(vuint8_t *)(&__MBAR[0x008810])) +-#define MCF_UART_UISR2 (*(vuint8_t *)(&__MBAR[0x008814])) +-#define MCF_UART_UIMR2 (*(vuint8_t *)(&__MBAR[0x008814])) +-#define MCF_UART_UBG12 (*(vuint8_t *)(&__MBAR[0x008818])) +-#define MCF_UART_UBG22 (*(vuint8_t *)(&__MBAR[0x00881C])) +-#define MCF_UART_UIP2 (*(vuint8_t *)(&__MBAR[0x008834])) +-#define MCF_UART_UOP12 (*(vuint8_t *)(&__MBAR[0x008838])) +-#define MCF_UART_UOP02 (*(vuint8_t *)(&__MBAR[0x00883C])) +- +-#define MCF_UART_UMR3 (*(vuint8_t *)(&__MBAR[0x008900])) +-#define MCF_UART_USR3 (*(vuint8_t *)(&__MBAR[0x008904])) +-#define MCF_UART_UCSR3 (*(vuint8_t *)(&__MBAR[0x008904])) +-#define MCF_UART_UCR3 (*(vuint8_t *)(&__MBAR[0x008908])) +-#define MCF_UART_URB3 (*(vuint8_t *)(&__MBAR[0x00890C])) +-#define MCF_UART_UTB3 (*(vuint8_t *)(&__MBAR[0x00890C])) +-#define MCF_UART_UIPCR3 (*(vuint8_t *)(&__MBAR[0x008910])) +-#define MCF_UART_UACR3 (*(vuint8_t *)(&__MBAR[0x008910])) +-#define MCF_UART_UISR3 (*(vuint8_t *)(&__MBAR[0x008914])) +-#define MCF_UART_UIMR3 (*(vuint8_t *)(&__MBAR[0x008914])) +-#define MCF_UART_UBG13 (*(vuint8_t *)(&__MBAR[0x008918])) +-#define MCF_UART_UBG23 (*(vuint8_t *)(&__MBAR[0x00891C])) +-#define MCF_UART_UIP3 (*(vuint8_t *)(&__MBAR[0x008934])) +-#define MCF_UART_UOP13 (*(vuint8_t *)(&__MBAR[0x008938])) +-#define MCF_UART_UOP03 (*(vuint8_t *)(&__MBAR[0x00893C])) +- +- +-#define MCF_UART_UMR(x) (*(vuint8_t *)(&__MBAR[0x008600+((x)*0x100)])) +-#define MCF_UART_USR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) +-#define MCF_UART_UCSR(x) (*(vuint8_t *)(&__MBAR[0x008604+((x)*0x100)])) +-#define MCF_UART_UCR(x) (*(vuint8_t *)(&__MBAR[0x008608+((x)*0x100)])) +-#define MCF_UART_URB(x) (*(vuint8_t *)(&__MBAR[0x00860C+((x)*0x100)])) +-#define MCF_UART_UTB(x) (*(vuint8_t *)(&__MBAR[0x00860C+((x)*0x100)])) +-#define MCF_UART_UIPCR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) +-#define MCF_UART_UACR(x) (*(vuint8_t *)(&__MBAR[0x008610+((x)*0x100)])) +-#define MCF_UART_UISR(x) (*(vuint8_t *)(&__MBAR[0x008614+((x)*0x100)])) +-#define MCF_UART_UIMR(x) (*(vuint8_t *)(&__MBAR[0x008614+((x)*0x100)])) +-#define MCF_UART_UBG1(x) (*(vuint8_t *)(&__MBAR[0x008618+((x)*0x100)])) +-#define MCF_UART_UBG2(x) (*(vuint8_t *)(&__MBAR[0x00861C+((x)*0x100)])) +-#define MCF_UART_UIP(x) (*(vuint8_t *)(&__MBAR[0x008634+((x)*0x100)])) +-#define MCF_UART_UOP1(x) (*(vuint8_t *)(&__MBAR[0x008638+((x)*0x100)])) +-#define MCF_UART_UOP0(x) (*(vuint8_t *)(&__MBAR[0x00863C+((x)*0x100)])) +- +-/* Bit definitions and macros for MCF_UART_UMR */ +-#define MCF_UART_UMR_BC(x) (((x)&0x03)<<0) +-#define MCF_UART_UMR_PT (0x04) +-#define MCF_UART_UMR_PM(x) (((x)&0x03)<<3) +-#define MCF_UART_UMR_ERR (0x20) +-#define MCF_UART_UMR_RXIRQ (0x40) +-#define MCF_UART_UMR_RXRTS (0x80) +-#define MCF_UART_UMR_SB(x) (((x)&0x0F)<<0) +-#define MCF_UART_UMR_TXCTS (0x10) +-#define MCF_UART_UMR_TXRTS (0x20) +-#define MCF_UART_UMR_CM(x) (((x)&0x03)<<6) +-#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C) +-#define MCF_UART_UMR_PM_MULTI_DATA (0x18) +-#define MCF_UART_UMR_PM_NONE (0x10) +-#define MCF_UART_UMR_PM_FORCE_HI (0x0C) +-#define MCF_UART_UMR_PM_FORCE_LO (0x08) +-#define MCF_UART_UMR_PM_ODD (0x04) +-#define MCF_UART_UMR_PM_EVEN (0x00) +-#define MCF_UART_UMR_BC_5 (0x00) +-#define MCF_UART_UMR_BC_6 (0x01) +-#define MCF_UART_UMR_BC_7 (0x02) +-#define MCF_UART_UMR_BC_8 (0x03) +-#define MCF_UART_UMR_CM_NORMAL (0x00) +-#define MCF_UART_UMR_CM_ECHO (0x40) +-#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80) +-#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0) +-#define MCF_UART_UMR_SB_STOP_BITS_1 (0x07) +-#define MCF_UART_UMR_SB_STOP_BITS_15 (0x08) +-#define MCF_UART_UMR_SB_STOP_BITS_2 (0x0F) +- +-/* Bit definitions and macros for MCF_UART_USR */ +-#define MCF_UART_USR_RXRDY (0x01) +-#define MCF_UART_USR_FFULL (0x02) +-#define MCF_UART_USR_TXRDY (0x04) +-#define MCF_UART_USR_TXEMP (0x08) +-#define MCF_UART_USR_OE (0x10) +-#define MCF_UART_USR_PE (0x20) +-#define MCF_UART_USR_FE (0x40) +-#define MCF_UART_USR_RB (0x80) +- +-/* Bit definitions and macros for MCF_UART_UCSR */ +-#define MCF_UART_UCSR_TCS(x) (((x)&0x0F)<<0) +-#define MCF_UART_UCSR_RCS(x) (((x)&0x0F)<<4) +-#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0) +-#define MCF_UART_UCSR_RCS_CTM16 (0xE0) +-#define MCF_UART_UCSR_RCS_CTM (0xF0) +-#define MCF_UART_UCSR_TCS_SYS_CLK (0x0D) +-#define MCF_UART_UCSR_TCS_CTM16 (0x0E) +-#define MCF_UART_UCSR_TCS_CTM (0x0F) +- +-/* Bit definitions and macros for MCF_UART_UCR */ +-#define MCF_UART_UCR_RXC(x) (((x)&0x03)<<0) +-#define MCF_UART_UCR_TXC(x) (((x)&0x03)<<2) +-#define MCF_UART_UCR_MISC(x) (((x)&0x07)<<4) +-#define MCF_UART_UCR_NONE (0x00) +-#define MCF_UART_UCR_STOP_BREAK (0x70) +-#define MCF_UART_UCR_START_BREAK (0x60) +-#define MCF_UART_UCR_BKCHGINT (0x50) +-#define MCF_UART_UCR_RESET_ERROR (0x40) +-#define MCF_UART_UCR_RESET_TX (0x30) +-#define MCF_UART_UCR_RESET_RX (0x20) +-#define MCF_UART_UCR_RESET_MR (0x10) +-#define MCF_UART_UCR_TX_DISABLED (0x08) +-#define MCF_UART_UCR_TX_ENABLED (0x04) +-#define MCF_UART_UCR_RX_DISABLED (0x02) +-#define MCF_UART_UCR_RX_ENABLED (0x01) +- +-/* Bit definitions and macros for MCF_UART_UIPCR */ +-#define MCF_UART_UIPCR_CTS (0x01) +-#define MCF_UART_UIPCR_COS (0x10) +- +-/* Bit definitions and macros for MCF_UART_UACR */ +-#define MCF_UART_UACR_IEC (0x01) +- +-/* Bit definitions and macros for MCF_UART_UISR */ +-#define MCF_UART_UISR_TXRDY (0x01) +-#define MCF_UART_UISR_RXRDY_FU (0x02) +-#define MCF_UART_UISR_DB (0x04) +-#define MCF_UART_UISR_RXFTO (0x08) +-#define MCF_UART_UISR_TXFIFO (0x10) +-#define MCF_UART_UISR_RXFIFO (0x20) +-#define MCF_UART_UISR_COS (0x80) +- +-/* Bit definitions and macros for MCF_UART_UIMR */ +-#define MCF_UART_UIMR_TXRDY (0x01) +-#define MCF_UART_UIMR_RXRDY_FU (0x02) +-#define MCF_UART_UIMR_DB (0x04) +-#define MCF_UART_UIMR_COS (0x80) +- +-/* Bit definitions and macros for MCF_UART_UIP */ +-#define MCF_UART_UIP_CTS (0x01) +- +-/* Bit definitions and macros for MCF_UART_UOP1 */ +-#define MCF_UART_UOP1_RTS (0x01) +- +-/* Bit definitions and macros for MCF_UART_UOP0 */ +-#define MCF_UART_UOP0_RTS (0x01) +- +-/* The UART registers for mem mapped access */ +-struct m5407uart +-{ +- vuint8_t umr; vuint24_t reserved0; +- vuint8_t usr; vuint24_t reserved1; /* ucsr */ +- vuint8_t ucr; vuint24_t reserved2; +- vuint8_t urb; vuint24_t reserved3; /* utb */ +- vuint8_t uipcr; vuint24_t reserved4; /* uacr */ +- vuint8_t uisr; vuint24_t reserved5; /* uimr */ +- vuint8_t udu; vuint24_t reserved6; +- vuint8_t ubg1; vuint24_t reserved7; +- vuint8_t ubg2; vuint24_t reserved8; +- const uint8_t uip; vuint24_t reserved9; +- vuint8_t uop1; vuint24_t reserved10; +- vuint8_t uop0; vuint24_t reserved11; +-} __attribute((packed)); +- +-#define MCF_UART(x) (*(struct m5407uart *)(&__MBAR[0x008600+((x)*0x100)])) +- +- +-#endif /* __MCF548X_UART_H__ */ +- +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_usb.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_usb.h +deleted file mode 100644 +index 0c256ef..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_usb.h ++++ /dev/null +@@ -1,509 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * Universal Serial Bus (USB) +- * +- * @note According to FreeScale errata sheet, the USB controller +- * isn't really usable on MCF54xx V4E CPUs. +- * Check V4M cores or wait for errata fixed +- * Last update: 25.02.2008 10:55:00 +- */ +-#ifndef __MCF548X_USB_H__ +-#define __MCF548X_USB_H__ +- +-/* +- * Universal Serial Bus (USB) +- */ +- +-/* Register read/write macros */ +-#define MCF_USB_USBAISR (*(vuint8_t *)(&__MBAR[0x00B000])) +-#define MCF_USB_USBAIMR (*(vuint8_t *)(&__MBAR[0x00B001])) +-#define MCF_USB_EPINFO (*(vuint8_t *)(&__MBAR[0x00B003])) +-#define MCF_USB_CFGR (*(vuint8_t *)(&__MBAR[0x00B004])) +-#define MCF_USB_CFGAR (*(vuint8_t *)(&__MBAR[0x00B005])) +-#define MCF_USB_SPEEDR (*(vuint8_t *)(&__MBAR[0x00B006])) +-#define MCF_USB_FRMNUMR (*(vuint16_t*)(&__MBAR[0x00B00E])) +-#define MCF_USB_EPTNR (*(vuint16_t*)(&__MBAR[0x00B010])) +-#define MCF_USB_IFUR (*(vuint16_t*)(&__MBAR[0x00B014])) +-#define MCF_USB_IFR0 (*(vuint16_t*)(&__MBAR[0x00B040])) +-#define MCF_USB_IFR1 (*(vuint16_t*)(&__MBAR[0x00B042])) +-#define MCF_USB_IFR2 (*(vuint16_t*)(&__MBAR[0x00B044])) +-#define MCF_USB_IFR3 (*(vuint16_t*)(&__MBAR[0x00B046])) +-#define MCF_USB_IFR4 (*(vuint16_t*)(&__MBAR[0x00B048])) +-#define MCF_USB_IFR5 (*(vuint16_t*)(&__MBAR[0x00B04A])) +-#define MCF_USB_IFR6 (*(vuint16_t*)(&__MBAR[0x00B04C])) +-#define MCF_USB_IFR7 (*(vuint16_t*)(&__MBAR[0x00B04E])) +-#define MCF_USB_IFR8 (*(vuint16_t*)(&__MBAR[0x00B050])) +-#define MCF_USB_IFR9 (*(vuint16_t*)(&__MBAR[0x00B052])) +-#define MCF_USB_IFR10 (*(vuint16_t*)(&__MBAR[0x00B054])) +-#define MCF_USB_IFR11 (*(vuint16_t*)(&__MBAR[0x00B056])) +-#define MCF_USB_IFR12 (*(vuint16_t*)(&__MBAR[0x00B058])) +-#define MCF_USB_IFR13 (*(vuint16_t*)(&__MBAR[0x00B05A])) +-#define MCF_USB_IFR14 (*(vuint16_t*)(&__MBAR[0x00B05C])) +-#define MCF_USB_IFR15 (*(vuint16_t*)(&__MBAR[0x00B05E])) +-#define MCF_USB_IFR16 (*(vuint16_t*)(&__MBAR[0x00B060])) +-#define MCF_USB_IFR17 (*(vuint16_t*)(&__MBAR[0x00B062])) +-#define MCF_USB_IFR18 (*(vuint16_t*)(&__MBAR[0x00B064])) +-#define MCF_USB_IFR19 (*(vuint16_t*)(&__MBAR[0x00B066])) +-#define MCF_USB_IFR20 (*(vuint16_t*)(&__MBAR[0x00B068])) +-#define MCF_USB_IFR21 (*(vuint16_t*)(&__MBAR[0x00B06A])) +-#define MCF_USB_IFR22 (*(vuint16_t*)(&__MBAR[0x00B06C])) +-#define MCF_USB_IFR23 (*(vuint16_t*)(&__MBAR[0x00B06E])) +-#define MCF_USB_IFR24 (*(vuint16_t*)(&__MBAR[0x00B070])) +-#define MCF_USB_IFR25 (*(vuint16_t*)(&__MBAR[0x00B072])) +-#define MCF_USB_IFR26 (*(vuint16_t*)(&__MBAR[0x00B074])) +-#define MCF_USB_IFR27 (*(vuint16_t*)(&__MBAR[0x00B076])) +-#define MCF_USB_IFR28 (*(vuint16_t*)(&__MBAR[0x00B078])) +-#define MCF_USB_IFR29 (*(vuint16_t*)(&__MBAR[0x00B07A])) +-#define MCF_USB_IFR30 (*(vuint16_t*)(&__MBAR[0x00B07C])) +-#define MCF_USB_IFR31 (*(vuint16_t*)(&__MBAR[0x00B07E])) +-#define MCF_USB_IFRn(x) (*(vuint16_t*)(&__MBAR[0x00B040+((x)*0x002)])) +-#define MCF_USB_PPCNT (*(vuint16_t*)(&__MBAR[0x00B080])) +-#define MCF_USB_DPCNT (*(vuint16_t*)(&__MBAR[0x00B082])) +-#define MCF_USB_CRCECNT (*(vuint16_t*)(&__MBAR[0x00B084])) +-#define MCF_USB_BSECNT (*(vuint16_t*)(&__MBAR[0x00B086])) +-#define MCF_USB_PIDECNT (*(vuint16_t*)(&__MBAR[0x00B088])) +-#define MCF_USB_FRMECNT (*(vuint16_t*)(&__MBAR[0x00B08A])) +-#define MCF_USB_TXPCNT (*(vuint16_t*)(&__MBAR[0x00B08C])) +-#define MCF_USB_CNTOVR (*(vuint8_t *)(&__MBAR[0x00B08E])) +-#define MCF_USB_EP0ACR (*(vuint8_t *)(&__MBAR[0x00B101])) +-#define MCF_USB_EP0MPSR (*(vuint16_t*)(&__MBAR[0x00B102])) +-#define MCF_USB_EP0IFR (*(vuint8_t *)(&__MBAR[0x00B104])) +-#define MCF_USB_EP0SR (*(vuint8_t *)(&__MBAR[0x00B105])) +-#define MCF_USB_BMRTR (*(vuint8_t *)(&__MBAR[0x00B106])) +-#define MCF_USB_BRTR (*(vuint8_t *)(&__MBAR[0x00B107])) +-#define MCF_USB_WVALUER (*(vuint16_t*)(&__MBAR[0x00B108])) +-#define MCF_USB_WINDEXR (*(vuint16_t*)(&__MBAR[0x00B10A])) +-#define MCF_USB_WLENGTH (*(vuint16_t*)(&__MBAR[0x00B10C])) +-#define MCF_USB_EP1OUTACR (*(vuint8_t *)(&__MBAR[0x00B131])) +-#define MCF_USB_EP2OUTACR (*(vuint8_t *)(&__MBAR[0x00B161])) +-#define MCF_USB_EP3OUTACR (*(vuint8_t *)(&__MBAR[0x00B191])) +-#define MCF_USB_EP4OUTACR (*(vuint8_t *)(&__MBAR[0x00B1C1])) +-#define MCF_USB_EP5OUTACR (*(vuint8_t *)(&__MBAR[0x00B1F1])) +-#define MCF_USB_EP6OUTACR (*(vuint8_t *)(&__MBAR[0x00B221])) +-#define MCF_USB_EPnOUTACR(x) (*(vuint8_t *)(&__MBAR[0x00B131+((x)*0x030)])) +-#define MCF_USB_EP1OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B132])) +-#define MCF_USB_EP2OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B162])) +-#define MCF_USB_EP3OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B192])) +-#define MCF_USB_EP4OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B1C2])) +-#define MCF_USB_EP5OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B1F2])) +-#define MCF_USB_EP6OUTMPSR (*(vuint16_t*)(&__MBAR[0x00B222])) +-#define MCF_USB_EPnOUTMPSR(x) (*(vuint16_t*)(&__MBAR[0x00B132+((x)*0x030)])) +-#define MCF_USB_EP1OUTIFR (*(vuint8_t *)(&__MBAR[0x00B134])) +-#define MCF_USB_EP2OUTIFR (*(vuint8_t *)(&__MBAR[0x00B164])) +-#define MCF_USB_EP3OUTIFR (*(vuint8_t *)(&__MBAR[0x00B194])) +-#define MCF_USB_EP4OUTIFR (*(vuint8_t *)(&__MBAR[0x00B1C4])) +-#define MCF_USB_EP5OUTIFR (*(vuint8_t *)(&__MBAR[0x00B1F4])) +-#define MCF_USB_EP6OUTIFR (*(vuint8_t *)(&__MBAR[0x00B224])) +-#define MCF_USB_EPnOUTIFR(x) (*(vuint8_t *)(&__MBAR[0x00B134+((x)*0x030)])) +-#define MCF_USB_EP1OUTSR (*(vuint8_t *)(&__MBAR[0x00B135])) +-#define MCF_USB_EP2OUTSR (*(vuint8_t *)(&__MBAR[0x00B165])) +-#define MCF_USB_EP3OUTSR (*(vuint8_t *)(&__MBAR[0x00B195])) +-#define MCF_USB_EP4OUTSR (*(vuint8_t *)(&__MBAR[0x00B1C5])) +-#define MCF_USB_EP5OUTSR (*(vuint8_t *)(&__MBAR[0x00B1F5])) +-#define MCF_USB_EP6OUTSR (*(vuint8_t *)(&__MBAR[0x00B225])) +-#define MCF_USB_EPnOUTSR(x) (*(vuint8_t *)(&__MBAR[0x00B135+((x)*0x030)])) +-#define MCF_USB_EP1OUTSFR (*(vuint16_t*)(&__MBAR[0x00B13E])) +-#define MCF_USB_EP2OUTSFR (*(vuint16_t*)(&__MBAR[0x00B16E])) +-#define MCF_USB_EP3OUTSFR (*(vuint16_t*)(&__MBAR[0x00B19E])) +-#define MCF_USB_EP4OUTSFR (*(vuint16_t*)(&__MBAR[0x00B1CE])) +-#define MCF_USB_EP5OUTSFR (*(vuint16_t*)(&__MBAR[0x00B1FE])) +-#define MCF_USB_EP6OUTSFR (*(vuint16_t*)(&__MBAR[0x00B22E])) +-#define MCF_USB_EPnOUTSFR(x) (*(vuint16_t*)(&__MBAR[0x00B13E+((x)*0x030)])) +-#define MCF_USB_EP1INACR (*(vuint8_t *)(&__MBAR[0x00B149])) +-#define MCF_USB_EP2INACR (*(vuint8_t *)(&__MBAR[0x00B179])) +-#define MCF_USB_EP3INACR (*(vuint8_t *)(&__MBAR[0x00B1A9])) +-#define MCF_USB_EP4INACR (*(vuint8_t *)(&__MBAR[0x00B1D9])) +-#define MCF_USB_EP5INACR (*(vuint8_t *)(&__MBAR[0x00B209])) +-#define MCF_USB_EP6INACR (*(vuint8_t *)(&__MBAR[0x00B239])) +-#define MCF_USB_EPnINACR(x) (*(vuint8_t *)(&__MBAR[0x00B149+((x)*0x030)])) +-#define MCF_USB_EP1INMPSR (*(vuint16_t*)(&__MBAR[0x00B14A])) +-#define MCF_USB_EP2INMPSR (*(vuint16_t*)(&__MBAR[0x00B17A])) +-#define MCF_USB_EP3INMPSR (*(vuint16_t*)(&__MBAR[0x00B1AA])) +-#define MCF_USB_EP4INMPSR (*(vuint16_t*)(&__MBAR[0x00B1DA])) +-#define MCF_USB_EP5INMPSR (*(vuint16_t*)(&__MBAR[0x00B20A])) +-#define MCF_USB_EP6INMPSR (*(vuint16_t*)(&__MBAR[0x00B23A])) +-#define MCF_USB_EPnINMPSR(x) (*(vuint16_t*)(&__MBAR[0x00B14A+((x)*0x030)])) +-#define MCF_USB_EP1INIFR (*(vuint8_t *)(&__MBAR[0x00B14C])) +-#define MCF_USB_EP2INIFR (*(vuint8_t *)(&__MBAR[0x00B17C])) +-#define MCF_USB_EP3INIFR (*(vuint8_t *)(&__MBAR[0x00B1AC])) +-#define MCF_USB_EP4INIFR (*(vuint8_t *)(&__MBAR[0x00B1DC])) +-#define MCF_USB_EP5INIFR (*(vuint8_t *)(&__MBAR[0x00B20C])) +-#define MCF_USB_EP6INIFR (*(vuint8_t *)(&__MBAR[0x00B23C])) +-#define MCF_USB_EPnINIFR(x) (*(vuint8_t *)(&__MBAR[0x00B14C+((x)*0x030)])) +-#define MCF_USB_EP1INSR (*(vuint8_t *)(&__MBAR[0x00B14D])) +-#define MCF_USB_EP2INSR (*(vuint8_t *)(&__MBAR[0x00B17D])) +-#define MCF_USB_EP3INSR (*(vuint8_t *)(&__MBAR[0x00B1AD])) +-#define MCF_USB_EP4INSR (*(vuint8_t *)(&__MBAR[0x00B1DD])) +-#define MCF_USB_EP5INSR (*(vuint8_t *)(&__MBAR[0x00B20D])) +-#define MCF_USB_EP6INSR (*(vuint8_t *)(&__MBAR[0x00B23D])) +-#define MCF_USB_EPnINSR(x) (*(vuint8_t *)(&__MBAR[0x00B14D+((x)*0x030)])) +-#define MCF_USB_EP1INSFR (*(vuint16_t*)(&__MBAR[0x00B15A])) +-#define MCF_USB_EP2INSFR (*(vuint16_t*)(&__MBAR[0x00B18A])) +-#define MCF_USB_EP3INSFR (*(vuint16_t*)(&__MBAR[0x00B1BA])) +-#define MCF_USB_EP4INSFR (*(vuint16_t*)(&__MBAR[0x00B1EA])) +-#define MCF_USB_EP5INSFR (*(vuint16_t*)(&__MBAR[0x00B21A])) +-#define MCF_USB_EP6INSFR (*(vuint16_t*)(&__MBAR[0x00B24A])) +-#define MCF_USB_EPnINSFR(x) (*(vuint16_t*)(&__MBAR[0x00B15A+((x)*0x030)])) +-#define MCF_USB_USBSR (*(vuint32_t*)(&__MBAR[0x00B400])) +-#define MCF_USB_USBCR (*(vuint32_t*)(&__MBAR[0x00B404])) +-#define MCF_USB_DRAMCR (*(vuint32_t*)(&__MBAR[0x00B408])) +-#define MCF_USB_DRAMDR (*(vuint32_t*)(&__MBAR[0x00B40C])) +-#define MCF_USB_USBISR (*(vuint32_t*)(&__MBAR[0x00B410])) +-#define MCF_USB_USBIMR (*(vuint32_t*)(&__MBAR[0x00B414])) +-#define MCF_USB_EP0STAT (*(vuint32_t*)(&__MBAR[0x00B440])) +-#define MCF_USB_EP1STAT (*(vuint32_t*)(&__MBAR[0x00B470])) +-#define MCF_USB_EP2STAT (*(vuint32_t*)(&__MBAR[0x00B4A0])) +-#define MCF_USB_EP3STAT (*(vuint32_t*)(&__MBAR[0x00B4D0])) +-#define MCF_USB_EP4STAT (*(vuint32_t*)(&__MBAR[0x00B500])) +-#define MCF_USB_EP5STAT (*(vuint32_t*)(&__MBAR[0x00B530])) +-#define MCF_USB_EP6STAT (*(vuint32_t*)(&__MBAR[0x00B560])) +-#define MCF_USB_EPnSTAT(x) (*(vuint32_t*)(&__MBAR[0x00B440+((x)*0x030)])) +-#define MCF_USB_EP0ISR (*(vuint32_t*)(&__MBAR[0x00B444])) +-#define MCF_USB_EP1ISR (*(vuint32_t*)(&__MBAR[0x00B474])) +-#define MCF_USB_EP2ISR (*(vuint32_t*)(&__MBAR[0x00B4A4])) +-#define MCF_USB_EP3ISR (*(vuint32_t*)(&__MBAR[0x00B4D4])) +-#define MCF_USB_EP4ISR (*(vuint32_t*)(&__MBAR[0x00B504])) +-#define MCF_USB_EP5ISR (*(vuint32_t*)(&__MBAR[0x00B534])) +-#define MCF_USB_EP6ISR (*(vuint32_t*)(&__MBAR[0x00B564])) +-#define MCF_USB_EPnISR(x) (*(vuint32_t*)(&__MBAR[0x00B444+((x)*0x030)])) +-#define MCF_USB_EP0IMR (*(vuint32_t*)(&__MBAR[0x00B448])) +-#define MCF_USB_EP1IMR (*(vuint32_t*)(&__MBAR[0x00B478])) +-#define MCF_USB_EP2IMR (*(vuint32_t*)(&__MBAR[0x00B4A8])) +-#define MCF_USB_EP3IMR (*(vuint32_t*)(&__MBAR[0x00B4D8])) +-#define MCF_USB_EP4IMR (*(vuint32_t*)(&__MBAR[0x00B508])) +-#define MCF_USB_EP5IMR (*(vuint32_t*)(&__MBAR[0x00B538])) +-#define MCF_USB_EP6IMR (*(vuint32_t*)(&__MBAR[0x00B568])) +-#define MCF_USB_EPnIMR(x) (*(vuint32_t*)(&__MBAR[0x00B448+((x)*0x030)])) +-#define MCF_USB_EP0FRCFGR (*(vuint32_t*)(&__MBAR[0x00B44C])) +-#define MCF_USB_EP1FRCFGR (*(vuint32_t*)(&__MBAR[0x00B47C])) +-#define MCF_USB_EP2FRCFGR (*(vuint32_t*)(&__MBAR[0x00B4AC])) +-#define MCF_USB_EP3FRCFGR (*(vuint32_t*)(&__MBAR[0x00B4DC])) +-#define MCF_USB_EP4FRCFGR (*(vuint32_t*)(&__MBAR[0x00B50C])) +-#define MCF_USB_EP5FRCFGR (*(vuint32_t*)(&__MBAR[0x00B53C])) +-#define MCF_USB_EP6FRCFGR (*(vuint32_t*)(&__MBAR[0x00B56C])) +-#define MCF_USB_EPnFRCFGR(x) (*(vuint32_t*)(&__MBAR[0x00B44C+((x)*0x030)])) +-#define MCF_USB_EP0FDR (*(vuint32_t*)(&__MBAR[0x00B450])) +-#define MCF_USB_EP1FDR (*(vuint32_t*)(&__MBAR[0x00B480])) +-#define MCF_USB_EP2FDR (*(vuint32_t*)(&__MBAR[0x00B4B0])) +-#define MCF_USB_EP3FDR (*(vuint32_t*)(&__MBAR[0x00B4E0])) +-#define MCF_USB_EP4FDR (*(vuint32_t*)(&__MBAR[0x00B510])) +-#define MCF_USB_EP5FDR (*(vuint32_t*)(&__MBAR[0x00B540])) +-#define MCF_USB_EP6FDR (*(vuint32_t*)(&__MBAR[0x00B570])) +-#define MCF_USB_EPnFDR(x) (*(vuint32_t*)(&__MBAR[0x00B450+((x)*0x030)])) +-#define MCF_USB_EP0FSR (*(vuint32_t*)(&__MBAR[0x00B454])) +-#define MCF_USB_EP1FSR (*(vuint32_t*)(&__MBAR[0x00B484])) +-#define MCF_USB_EP2FSR (*(vuint32_t*)(&__MBAR[0x00B4B4])) +-#define MCF_USB_EP3FSR (*(vuint32_t*)(&__MBAR[0x00B4E4])) +-#define MCF_USB_EP4FSR (*(vuint32_t*)(&__MBAR[0x00B514])) +-#define MCF_USB_EP5FSR (*(vuint32_t*)(&__MBAR[0x00B544])) +-#define MCF_USB_EP6FSR (*(vuint32_t*)(&__MBAR[0x00B574])) +-#define MCF_USB_EPnFSR(x) (*(vuint32_t*)(&__MBAR[0x00B454+((x)*0x030)])) +-#define MCF_USB_EP0FCR (*(vuint32_t*)(&__MBAR[0x00B458])) +-#define MCF_USB_EP1FCR (*(vuint32_t*)(&__MBAR[0x00B488])) +-#define MCF_USB_EP2FCR (*(vuint32_t*)(&__MBAR[0x00B4B8])) +-#define MCF_USB_EP3FCR (*(vuint32_t*)(&__MBAR[0x00B4E8])) +-#define MCF_USB_EP4FCR (*(vuint32_t*)(&__MBAR[0x00B518])) +-#define MCF_USB_EP5FCR (*(vuint32_t*)(&__MBAR[0x00B548])) +-#define MCF_USB_EP6FCR (*(vuint32_t*)(&__MBAR[0x00B578])) +-#define MCF_USB_EPnFCR(x) (*(vuint32_t*)(&__MBAR[0x00B458+((x)*0x030)])) +-#define MCF_USB_EP0FAR (*(vuint32_t*)(&__MBAR[0x00B45C])) +-#define MCF_USB_EP1FAR (*(vuint32_t*)(&__MBAR[0x00B48C])) +-#define MCF_USB_EP2FAR (*(vuint32_t*)(&__MBAR[0x00B4BC])) +-#define MCF_USB_EP3FAR (*(vuint32_t*)(&__MBAR[0x00B4EC])) +-#define MCF_USB_EP4FAR (*(vuint32_t*)(&__MBAR[0x00B51C])) +-#define MCF_USB_EP5FAR (*(vuint32_t*)(&__MBAR[0x00B54C])) +-#define MCF_USB_EP6FAR (*(vuint32_t*)(&__MBAR[0x00B57C])) +-#define MCF_USB_EPnFAR(x) (*(vuint32_t*)(&__MBAR[0x00B45C+((x)*0x030)])) +-#define MCF_USB_EP0FRP (*(vuint32_t*)(&__MBAR[0x00B460])) +-#define MCF_USB_EP1FRP (*(vuint32_t*)(&__MBAR[0x00B490])) +-#define MCF_USB_EP2FRP (*(vuint32_t*)(&__MBAR[0x00B4C0])) +-#define MCF_USB_EP3FRP (*(vuint32_t*)(&__MBAR[0x00B4F0])) +-#define MCF_USB_EP4FRP (*(vuint32_t*)(&__MBAR[0x00B520])) +-#define MCF_USB_EP5FRP (*(vuint32_t*)(&__MBAR[0x00B550])) +-#define MCF_USB_EP6FRP (*(vuint32_t*)(&__MBAR[0x00B580])) +-#define MCF_USB_EPnFRP(x) (*(vuint32_t*)(&__MBAR[0x00B460+((x)*0x030)])) +-#define MCF_USB_EP0FWP (*(vuint32_t*)(&__MBAR[0x00B464])) +-#define MCF_USB_EP1FWP (*(vuint32_t*)(&__MBAR[0x00B494])) +-#define MCF_USB_EP2FWP (*(vuint32_t*)(&__MBAR[0x00B4C4])) +-#define MCF_USB_EP3FWP (*(vuint32_t*)(&__MBAR[0x00B4F4])) +-#define MCF_USB_EP4FWP (*(vuint32_t*)(&__MBAR[0x00B524])) +-#define MCF_USB_EP5FWP (*(vuint32_t*)(&__MBAR[0x00B554])) +-#define MCF_USB_EP6FWP (*(vuint32_t*)(&__MBAR[0x00B584])) +-#define MCF_USB_EPnFWP(x) (*(vuint32_t*)(&__MBAR[0x00B464+((x)*0x030)])) +-#define MCF_USB_EP0LRFP (*(vuint32_t*)(&__MBAR[0x00B468])) +-#define MCF_USB_EP1LRFP (*(vuint32_t*)(&__MBAR[0x00B498])) +-#define MCF_USB_EP2LRFP (*(vuint32_t*)(&__MBAR[0x00B4C8])) +-#define MCF_USB_EP3LRFP (*(vuint32_t*)(&__MBAR[0x00B4F8])) +-#define MCF_USB_EP4LRFP (*(vuint32_t*)(&__MBAR[0x00B528])) +-#define MCF_USB_EP5LRFP (*(vuint32_t*)(&__MBAR[0x00B558])) +-#define MCF_USB_EP6LRFP (*(vuint32_t*)(&__MBAR[0x00B588])) +-#define MCF_USB_EPnLRFP(x) (*(vuint32_t*)(&__MBAR[0x00B468+((x)*0x030)])) +-#define MCF_USB_EP0LWFP (*(vuint32_t*)(&__MBAR[0x00B46C])) +-#define MCF_USB_EP1LWFP (*(vuint32_t*)(&__MBAR[0x00B49C])) +-#define MCF_USB_EP2LWFP (*(vuint32_t*)(&__MBAR[0x00B4CC])) +-#define MCF_USB_EP3LWFP (*(vuint32_t*)(&__MBAR[0x00B4FC])) +-#define MCF_USB_EP4LWFP (*(vuint32_t*)(&__MBAR[0x00B52C])) +-#define MCF_USB_EP5LWFP (*(vuint32_t*)(&__MBAR[0x00B55C])) +-#define MCF_USB_EP6LWFP (*(vuint32_t*)(&__MBAR[0x00B58C])) +-#define MCF_USB_EPnLWFP(x) (*(vuint32_t*)(&__MBAR[0x00B46C+((x)*0x030)])) +- +-/* Bit definitions and macros for MCF_USB_USBAISR */ +-#define MCF_USB_USBAISR_SETUP (0x01) +-#define MCF_USB_USBAISR_IN (0x02) +-#define MCF_USB_USBAISR_OUT (0x04) +-#define MCF_USB_USBAISR_EPHALT (0x08) +-#define MCF_USB_USBAISR_TRANSERR (0x10) +-#define MCF_USB_USBAISR_ACK (0x20) +-#define MCF_USB_USBAISR_CTROVFL (0x40) +-#define MCF_USB_USBAISR_EPSTALL (0x80) +- +-/* Bit definitions and macros for MCF_USB_USBAIMR */ +-#define MCF_USB_USBAIMR_SETUPEN (0x01) +-#define MCF_USB_USBAIMR_INEN (0x02) +-#define MCF_USB_USBAIMR_OUTEN (0x04) +-#define MCF_USB_USBAIMR_EPHALTEN (0x08) +-#define MCF_USB_USBAIMR_TRANSERREN (0x10) +-#define MCF_USB_USBAIMR_ACKEN (0x20) +-#define MCF_USB_USBAIMR_CTROVFLEN (0x40) +-#define MCF_USB_USBAIMR_EPSTALLEN (0x80) +- +-/* Bit definitions and macros for MCF_USB_EPINFO */ +-#define MCF_USB_EPINFO_EPDIR (0x01) +-#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x07)<<1) +- +-/* Bit definitions and macros for MCF_USB_CFGAR */ +-#define MCF_USB_CFGAR_RESERVED (0xA0) +-#define MCF_USB_CFGAR_RMTWKEUP (0xE0) +- +-/* Bit definitions and macros for MCF_USB_SPEEDR */ +-#define MCF_USB_SPEEDR_HS (0x01) +-#define MCF_USB_SPEEDR_FS (0x02) +- +-/* Bit definitions and macros for MCF_USB_FRMNUMR */ +-#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0x0FFF)<<0) +- +-/* Bit definitions and macros for MCF_USB_EPTNR */ +-#define MCF_USB_EPTNR_EP1T(x) (((x)&0x0003)<<0) +-#define MCF_USB_EPTNR_EP2T(x) (((x)&0x0003)<<2) +-#define MCF_USB_EPTNR_EP3T(x) (((x)&0x0003)<<4) +-#define MCF_USB_EPTNR_EP4T(x) (((x)&0x0003)<<6) +-#define MCF_USB_EPTNR_EP5T(x) (((x)&0x0003)<<8) +-#define MCF_USB_EPTNR_EP6T(x) (((x)&0x0003)<<10) +-#define MCF_USB_EPTNR_EPnT1 (0) +-#define MCF_USB_EPTNR_EPnT2 (1) +-#define MCF_USB_EPTNR_EPnT3 (2) +- +-/* Bit definitions and macros for MCF_USB_IFUR */ +-#define MCF_USB_IFUR_ALTSET(x) (((x)&0x00FF)<<0) +-#define MCF_USB_IFUR_IFNUM(x) (((x)&0x00FF)<<8) +- +-/* Bit definitions and macros for MCF_USB_IFRn */ +-#define MCF_USB_IFRn_ALTSET(x) (((x)&0x00FF)<<0) +-#define MCF_USB_IFRn_IFNUM(x) (((x)&0x00FF)<<8) +- +-/* Bit definitions and macros for MCF_USB_CNTOVR */ +-#define MCF_USB_CNTOVR_PPCNT (0x01) +-#define MCF_USB_CNTOVR_DPCNT (0x02) +-#define MCF_USB_CNTOVR_CRCECNT (0x04) +-#define MCF_USB_CNTOVR_BSECNT (0x08) +-#define MCF_USB_CNTOVR_PIDECNT (0x10) +-#define MCF_USB_CNTOVR_FRMECNT (0x20) +-#define MCF_USB_CNTOVR_TXPCNT (0x40) +- +-/* Bit definitions and macros for MCF_USB_EP0ACR */ +-#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x03)<<0) +-#define MCF_USB_EP0ACR_TTYPE_CTRL (0) +-#define MCF_USB_EP0ACR_TTYPE_ISOC (1) +-#define MCF_USB_EP0ACR_TTYPE_BULK (2) +-#define MCF_USB_EP0ACR_TTYPE_INT (3) +- +-/* Bit definitions and macros for MCF_USB_EP0MPSR */ +-#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +-#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x0003)<<11) +- +-/* Bit definitions and macros for MCF_USB_EP0SR */ +-#define MCF_USB_EP0SR_HALT (0x01) +-#define MCF_USB_EP0SR_ACTIVE (0x02) +-#define MCF_USB_EP0SR_PSTALL (0x04) +-#define MCF_USB_EP0SR_CCOMP (0x08) +-#define MCF_USB_EP0SR_TXZERO (0x20) +-#define MCF_USB_EP0SR_INT (0x80) +- +-/* Bit definitions and macros for MCF_USB_BMRTR */ +-#define MCF_USB_BMRTR_DIR (0x80) +-#define MCF_USB_BMRTR_TYPE_STANDARD (0x00) +-#define MCF_USB_BMRTR_TYPE_CLASS (0x20) +-#define MCF_USB_BMRTR_TYPE_VENDOR (0x40) +-#define MCF_USB_BMRTR_REC_DEVICE (0x00) +-#define MCF_USB_BMRTR_REC_INTERFACE (0x01) +-#define MCF_USB_BMRTR_REC_ENDPOINT (0x02) +-#define MCF_USB_BMRTR_REC_OTHER (0x03) +- +-/* Bit definitions and macros for MCF_USB_EPnOUTACR */ +-#define MCF_USB_EPnOUTACR_TTYPE(x) (((x)&0x03)<<0) +- +-/* Bit definitions and macros for MCF_USB_EPnOUTMPSR */ +-#define MCF_USB_EPnOUTMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +-#define MCF_USB_EPnOUTMPSR_ADDTRANS(x) (((x)&0x0003)<<11) +- +-/* Bit definitions and macros for MCF_USB_EPnOUTSR */ +-#define MCF_USB_EPnOUTSR_HALT (0x01) +-#define MCF_USB_EPnOUTSR_ACTIVE (0x02) +-#define MCF_USB_EPnOUTSR_PSTALL (0x04) +-#define MCF_USB_EPnOUTSR_CCOMP (0x08) +-#define MCF_USB_EPnOUTSR_TXZERO (0x20) +-#define MCF_USB_EPnOUTSR_INT (0x80) +- +-/* Bit definitions and macros for MCF_USB_EPnOUTSFR */ +-#define MCF_USB_EPnOUTSFR_FRMNUM(x) (((x)&0x07FF)<<0) +- +-/* Bit definitions and macros for MCF_USB_EPnINACR */ +-#define MCF_USB_EPnINACR_TTYPE(x) (((x)&0x03)<<0) +- +-/* Bit definitions and macros for MCF_USB_EPnINMPSR */ +-#define MCF_USB_EPnINMPSR_MAXPKTSZ(x) (((x)&0x07FF)<<0) +-#define MCF_USB_EPnINMPSR_ADDTRANS(x) (((x)&0x0003)<<11) +- +-/* Bit definitions and macros for MCF_USB_EPnINSR */ +-#define MCF_USB_EPnINSR_HALT (0x01) +-#define MCF_USB_EPnINSR_ACTIVE (0x02) +-#define MCF_USB_EPnINSR_PSTALL (0x04) +-#define MCF_USB_EPnINSR_CCOMP (0x08) +-#define MCF_USB_EPnINSR_TXZERO (0x20) +-#define MCF_USB_EPnINSR_INT (0x80) +- +-/* Bit definitions and macros for MCF_USB_EPnINSFR */ +-#define MCF_USB_EPnINSFR_FRMNUM(x) (((x)&0x07FF)<<0) +- +-/* Bit definitions and macros for MCF_USB_USBSR */ +-#define MCF_USB_USBSR_SUSP (0x00000080) +-#define MCF_USB_USBSR_ISOERREP (0x0000000F) +- +-/* Bit definitions and macros for MCF_USB_USBCR */ +-#define MCF_USB_USBCR_RESUME (0x00000001) +-#define MCF_USB_USBCR_APPLOCK (0x00000002) +-#define MCF_USB_USBCR_RST (0x00000004) +-#define MCF_USB_USBCR_RAMEN (0x00000008) +-#define MCF_USB_USBCR_RAMSPLIT (0x00000020) +- +-/* Bit definitions and macros for MCF_USB_DRAMCR */ +-#define MCF_USB_DRAMCR_DADR(x) (((x)&0x000003FF)<<0) +-#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x000007FF)<<16) +-#define MCF_USB_DRAMCR_BSY (0x40000000) +-#define MCF_USB_DRAMCR_START (0x80000000) +- +-/* Bit definitions and macros for MCF_USB_DRAMDR */ +-#define MCF_USB_DRAMDR_DDAT(x) (((x)&0x000000FF)<<0) +- +-/* Bit definitions and macros for MCF_USB_USBISR */ +-#define MCF_USB_USBISR_ISOERR (0x00000001) +-#define MCF_USB_USBISR_FTUNLCK (0x00000002) +-#define MCF_USB_USBISR_SUSP (0x00000004) +-#define MCF_USB_USBISR_RES (0x00000008) +-#define MCF_USB_USBISR_UPDSOF (0x00000010) +-#define MCF_USB_USBISR_RSTSTOP (0x00000020) +-#define MCF_USB_USBISR_SOF (0x00000040) +-#define MCF_USB_USBISR_MSOF (0x00000080) +- +-/* Bit definitions and macros for MCF_USB_USBIMR */ +-#define MCF_USB_USBIMR_ISOERR (0x00000001) +-#define MCF_USB_USBIMR_FTUNLCK (0x00000002) +-#define MCF_USB_USBIMR_SUSP (0x00000004) +-#define MCF_USB_USBIMR_RES (0x00000008) +-#define MCF_USB_USBIMR_UPDSOF (0x00000010) +-#define MCF_USB_USBIMR_RSTSTOP (0x00000020) +-#define MCF_USB_USBIMR_SOF (0x00000040) +-#define MCF_USB_USBIMR_MSOF (0x00000080) +- +-/* Bit definitions and macros for MCF_USB_EPnSTAT */ +-#define MCF_USB_EPnSTAT_RST (0x00000001) +-#define MCF_USB_EPnSTAT_FLUSH (0x00000002) +-#define MCF_USB_EPnSTAT_DIR (0x00000080) +-#define MCF_USB_EPnSTAT_BYTECNT(x) (((x)&0x00000FFF)<<16) +- +-/* Bit definitions and macros for MCF_USB_EPnISR */ +-#define MCF_USB_EPnISR_EOF (0x00000001) +-#define MCF_USB_EPnISR_EOT (0x00000004) +-#define MCF_USB_EPnISR_FIFOLO (0x00000010) +-#define MCF_USB_EPnISR_FIFOHI (0x00000020) +-#define MCF_USB_EPnISR_ERR (0x00000040) +-#define MCF_USB_EPnISR_EMT (0x00000080) +-#define MCF_USB_EPnISR_FU (0x00000100) +- +-/* Bit definitions and macros for MCF_USB_EPnIMR */ +-#define MCF_USB_EPnIMR_EOF (0x00000001) +-#define MCF_USB_EPnIMR_EOT (0x00000004) +-#define MCF_USB_EPnIMR_FIFOLO (0x00000010) +-#define MCF_USB_EPnIMR_FIFOHI (0x00000020) +-#define MCF_USB_EPnIMR_ERR (0x00000040) +-#define MCF_USB_EPnIMR_EMT (0x00000080) +-#define MCF_USB_EPnIMR_FU (0x00000100) +- +-/* Bit definitions and macros for MCF_USB_EPnFRCFGR */ +-#define MCF_USB_EPnFRCFGR_DEPTH(x) (((x)&0x00001FFF)<<0) +-#define MCF_USB_EPnFRCFGR_BASE(x) (((x)&0x00000FFF)<<16) +- +-/* Bit definitions and macros for MCF_USB_EPnFSR */ +-#define MCF_USB_EPnFSR_EMT (0x00010000) +-#define MCF_USB_EPnFSR_ALRM (0x00020000) +-#define MCF_USB_EPnFSR_FR (0x00040000) +-#define MCF_USB_EPnFSR_FU (0x00080000) +-#define MCF_USB_EPnFSR_OF (0x00100000) +-#define MCF_USB_EPnFSR_UF (0x00200000) +-#define MCF_USB_EPnFSR_RXW (0x00400000) +-#define MCF_USB_EPnFSR_FAE (0x00800000) +-#define MCF_USB_EPnFSR_FRM(x) (((x)&0x0000000F)<<24) +-#define MCF_USB_EPnFSR_TXW (0x40000000) +-#define MCF_USB_EPnFSR_IP (0x80000000) +- +-/* Bit definitions and macros for MCF_USB_EPnFCR */ +-#define MCF_USB_EPnFCR_COUNTER(x) (((x)&0x0000FFFF)<<0) +-#define MCF_USB_EPnFCR_TXWMSK (0x00040000) +-#define MCF_USB_EPnFCR_OFMSK (0x00080000) +-#define MCF_USB_EPnFCR_UFMSK (0x00100000) +-#define MCF_USB_EPnFCR_RXWMSK (0x00200000) +-#define MCF_USB_EPnFCR_FAEMSK (0x00400000) +-#define MCF_USB_EPnFCR_IPMSK (0x00800000) +-#define MCF_USB_EPnFCR_GR(x) (((x)&0x00000007)<<24) +-#define MCF_USB_EPnFCR_FRM (0x08000000) +-#define MCF_USB_EPnFCR_TMR (0x10000000) +-#define MCF_USB_EPnFCR_WFR (0x20000000) +-#define MCF_USB_EPnFCR_SHAD (0x80000000) +- +-/* Bit definitions and macros for MCF_USB_EPnFAR */ +-#define MCF_USB_EPnFAR_ALRMP(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_USB_EPnFRP */ +-#define MCF_USB_EPnFRP_RP(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_USB_EPnFWP */ +-#define MCF_USB_EPnFWP_WP(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_USB_EPnLRFP */ +-#define MCF_USB_EPnLRFP_LRFP(x) (((x)&0x00000FFF)<<0) +- +-/* Bit definitions and macros for MCF_USB_EPnLWFP */ +-#define MCF_USB_EPnLWFP_LWFP(x) (((x)&0x00000FFF)<<0) +- +- +-#endif /* __MCF548X_USB_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_xlbarb.h b/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_xlbarb.h +deleted file mode 100644 +index f4df976..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf548x/mcf548x_xlbarb.h ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Register and bit definitions for the MCF548X and MCF547x +- * XLB bus arbiter +- */ +-#ifndef __MCF548X_XLBARB_H__ +-#define __MCF548X_XLBARB_H__ +- +-/* +- * XLB arbiter register +- */ +-#define MCF_XLBARB_ACFG (*(vuint32*)(&__MBAR[0x000240])) +-#define MCF_XLBARB_VER (*(vuint32*)(&__MBAR[0x000244])) +-#define MCF_XLBARB_STA (*(vuint32*)(&__MBAR[0x000248])) +-#define MCF_XLBARB_INTEN (*(vuint32*)(&__MBAR[0x00024C])) +-#define MCF_XLBARB_ADRCAP (*(vuint32*)(&__MBAR[0x000250])) +-#define MCF_XLBARB_SIGCAP (*(vuint32*)(&__MBAR[0x000254])) +-#define MCF_XLBARB_ADRTO (*(vuint32*)(&__MBAR[0x000258])) +-#define MCF_XLBARB_DATTO (*(vuint32*)(&__MBAR[0x00025C])) +-#define MCF_XLBARB_BUSTO (*(vuint32*)(&__MBAR[0x000260])) +-#define MCF_XLBARB_PRIEN (*(vuint32*)(&__MBAR[0x000264])) +-#define MCF_XLBARB_PRI (*(vuint32*)(&__MBAR[0x000268])) +-#define MCF_XLBARB_BAR (*(vuint32*)(&__MBAR[0x00026C])) +- +- +-#endif /* __MCF548X_XLBARB_H__ */ +diff --git a/arch/m68k/include/asm/coldfire/mcf5xxx.h b/arch/m68k/include/asm/coldfire/mcf5xxx.h +deleted file mode 100644 +index 5edde1e..0000000 +--- a/arch/m68k/include/asm/coldfire/mcf5xxx.h ++++ /dev/null +@@ -1,258 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Definitions common across all ColdFire processors +- */ +-#ifndef __MCF5XXX__H +-#define __MCF5XXX__H +- +-/* +- * Common M68K & ColdFire definitions +- */ +-#define ADDRESS uint32_t +-#define INSTRUCTION uint16_t +-#define ILLEGAL 0x4AFC +-#define CPU_WORD_SIZE 16 +- +-/* +- * Definitions for CPU status register (SR) +- */ +-#define MCF5XXX_SR_T (0x8000) +-#define MCF5XXX_SR_S (0x2000) +-#define MCF5XXX_SR_M (0x1000) +-#define MCF5XXX_SR_IPL (0x0700) +-#define MCF5XXX_SR_IPL_0 (0x0000) +-#define MCF5XXX_SR_IPL_1 (0x0100) +-#define MCF5XXX_SR_IPL_2 (0x0200) +-#define MCF5XXX_SR_IPL_3 (0x0300) +-#define MCF5XXX_SR_IPL_4 (0x0400) +-#define MCF5XXX_SR_IPL_5 (0x0500) +-#define MCF5XXX_SR_IPL_6 (0x0600) +-#define MCF5XXX_SR_IPL_7 (0x0700) +-#define MCF5XXX_SR_X (0x0010) +-#define MCF5XXX_SR_N (0x0008) +-#define MCF5XXX_SR_Z (0x0004) +-#define MCF5XXX_SR_V (0x0002) +-#define MCF5XXX_SR_C (0x0001) +- +-/* +- * Definitions for CPU cache control register +- */ +-#define MCF5XXX_CACR_CENB (0x80000000) +-#define MCF5XXX_CACR_DEC (0x80000000) +-#define MCF5XXX_CACR_DW (0x40000000) +-#define MCF5XXX_CACR_DESB (0x20000000) +-#define MCF5XXX_CACR_CPDI (0x10000000) +-#define MCF5XXX_CACR_DDPI (0x10000000) +-#define MCF5XXX_CACR_CPD (0x10000000) +-#define MCF5XXX_CACR_CFRZ (0x08000000) +-#define MCF5XXX_CACR_DHLCK (0x08000000) +-#define MCF5XXX_CACR_DDCM_WT (0x00000000) +-#define MCF5XXX_CACR_DDCM_CB (0x02000000) +-#define MCF5XXX_CACR_DDCM_IP (0x04000000) +-#define MCF5XXX_CACR_DDCM_II (0x06000000) +-#define MCF5XXX_CACR_CINV (0x01000000) +-#define MCF5XXX_CACR_DCINVA (0x01000000) +-#define MCF5XXX_CACR_DIDI (0x00800000) +-#define MCF5XXX_CACR_DDSP (0x00800000) +-#define MCF5XXX_CACR_DISD (0x00400000) +-#define MCF5XXX_CACR_INVI (0x00200000) +-#define MCF5XXX_CACR_INVD (0x00100000) +-#define MCF5XXX_CACR_BEC (0x00080000) +-#define MCF5XXX_CACR_BCINVA (0x00040000) +-#define MCF5XXX_CACR_IEC (0x00008000) +-#define MCF5XXX_CACR_DNFB (0x00002000) +-#define MCF5XXX_CACR_IDPI (0x00001000) +-#define MCF5XXX_CACR_IHLCK (0x00000800) +-#define MCF5XXX_CACR_CEIB (0x00000400) +-#define MCF5XXX_CACR_IDCM (0x00000400) +-#define MCF5XXX_CACR_DCM_WR (0x00000000) +-#define MCF5XXX_CACR_DCM_CB (0x00000100) +-#define MCF5XXX_CACR_DCM_IP (0x00000200) +-#define MCF5XXX_CACR_DCM (0x00000200) +-#define MCF5XXX_CACR_DCM_II (0x00000300) +-#define MCF5XXX_CACR_DBWE (0x00000100) +-#define MCF5XXX_CACR_ICINVA (0x00000100) +-#define MCF5XXX_CACR_IDSP (0x00000080) +-#define MCF5XXX_CACR_DWP (0x00000020) +-#define MCF5XXX_CACR_EUSP (0x00000020) +-#define MCF5XXX_CACR_EUST (0x00000020) +-#define MCF5XXX_CACR_DF (0x00000010) +-#define MCF5XXX_CACR_CLNF_00 (0x00000000) +-#define MCF5XXX_CACR_CLNF_01 (0x00000002) +-#define MCF5XXX_CACR_CLNF_10 (0x00000004) +-#define MCF5XXX_CACR_CLNF_11 (0x00000006) +- +-/* +- * Definition for CPU access control register +- */ +-#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000) +-#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8) +-#define MCF5XXX_ACR_EN (0x00008000) +-#define MCF5XXX_ACR_SM_USER (0x00000000) +-#define MCF5XXX_ACR_SM_SUPER (0x00002000) +-#define MCF5XXX_ACR_SM_IGNORE (0x00006000) +-#define MCF5XXX_ACR_ENIB (0x00000080) +-#define MCF5XXX_ACR_CM (0x00000040) +-#define MCF5XXX_ACR_DCM_WR (0x00000000) +-#define MCF5XXX_ACR_DCM_CB (0x00000020) +-#define MCF5XXX_ACR_DCM_IP (0x00000040) +-#define MCF5XXX_ACR_DCM_II (0x00000060) +-#define MCF5XXX_ACR_CM (0x00000040) +-#define MCF5XXX_ACR_BWE (0x00000020) +-#define MCF5XXX_ACR_WP (0x00000004) +- +-/* +- * Definitions for CPU core sram control registers +- */ +-#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000) +-#define MCF5XXX_RAMBAR_PRI_00 (0x00000000) +-#define MCF5XXX_RAMBAR_PRI_01 (0x00004000) +-#define MCF5XXX_RAMBAR_PRI_10 (0x00008000) +-#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000) +-#define MCF5XXX_RAMBAR_WP (0x00000100) +-#define MCF5XXX_RAMBAR_CI (0x00000020) +-#define MCF5XXX_RAMBAR_SC (0x00000010) +-#define MCF5XXX_RAMBAR_SD (0x00000008) +-#define MCF5XXX_RAMBAR_UC (0x00000004) +-#define MCF5XXX_RAMBAR_UD (0x00000002) +-#define MCF5XXX_RAMBAR_V (0x00000001) +- +- +-#ifndef __ASSEMBLY__ +- +-extern char __MBAR[]; +- +- +-/* +- * Extention to thhe basic POSIX data types +- */ +-typedef volatile uint8_t vuint8_t; /* 8 bits */ +-typedef volatile uint16_t vuint16_t; /* 16 bits */ +-typedef volatile uint32_t vuint32_t; /* 32 bits */ +- +-/* +- * Routines and macros for accessing Input/Output devices +- */ +- +-#define mcf_iord_8(ADDR) *((vuint8_t *)(ADDR)) +-#define mcf_iord_16(ADDR) *((vuint16_t *)(ADDR)) +-#define mcf_iord_32(ADDR) *((vuint32_t *)(ADDR)) +- +-#define mcf_iowr_8(ADDR,DATA) *((vuint8_t *)(ADDR)) = (DATA) +-#define mcf_iowr_16(ADDR,DATA) *((vuint16_t *)(ADDR)) = (DATA) +-#define mcf_iowr_32(ADDR,DATA) *((vuint32_t *)(ADDR)) = (DATA) +- +-/* +- * The ColdFire family of processors has a simplified exception stack +- * frame that looks like the following: +- * +- * 3322222222221111 111111 +- * 1098765432109876 5432109876543210 +- * 8 +----------------+----------------+ +- * | Program Counter | +- * 4 +----------------+----------------+ +- * |FS/Fmt/Vector/FS| SR | +- * SP --> 0 +----------------+----------------+ +- * +- * The stack self-aligns to a 4-byte boundary at an exception, with +- * the FS/Fmt/Vector/FS field indicating the size of the adjustment +- * (SP += 0,1,2,3 bytes). +- */ +-#define MCF5XXX_RD_SF_FORMAT(PTR) \ +- ((*((uint16_t *)(PTR)) >> 12) & 0x00FF) +- +-#define MCF5XXX_RD_SF_VECTOR(PTR) \ +- ((*((uint16_t *)(PTR)) >> 2) & 0x00FF) +- +-#define MCF5XXX_RD_SF_FS(PTR) \ +- ( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) ) +- +-#define MCF5XXX_SF_SR(PTR) *((uint16_t *)(PTR)+1) +-#define MCF5XXX_SF_PC(PTR) *((uint32_t *)(PTR)+1) +- +-/* +- * Functions provided as inline code to access supervisor mode +- * registers from C. +- * +- * Note: Most registers are write-only. So you must use shadow registers in +- * RAM to track the state of each register! +- */ +-static __inline__ uint16_t mcf5xxx_rd_sr(void) { uint16_t rc; __asm__ __volatile__( "move.w %%sr,%0\n" : "=r" (rc) ); return rc; } +-static __inline__ void mcf5xxx_wr_sr(uint16_t value) { __asm__ __volatile__( "move.w %0,%%sr\n" : : "r" (value) ); } +- +-static __inline__ int asm_set_ipl(uint32_t value) +-{ +- uint32_t oldipl,newipl; +- value = (value & 0x7) << 8U; +- oldipl = mcf5xxx_rd_sr(); +- newipl = oldipl & ~0x0700U; +- newipl |= value; +- mcf5xxx_wr_sr(newipl); +- oldipl = (oldipl & 0x0700U) >> 8U; +- return oldipl; +-} +- +-static __inline__ void mcf5xxx_cpushl_bc(uint32_t* value) { __asm__ __volatile__( " move.l %0,%%a0 \n .word 0xF4E8\n nop\n" : : "a" (value) : "a0"); } +- // cpushl bc,%%a0@ ??? +- +-static __inline__ void mcf5xxx_wr_cacr(uint32_t value) { __asm__ __volatile__( "movec %0,%%cacr\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_asid(uint32_t value) { __asm__ __volatile__( "movec %0,%%asid\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_acr0(uint32_t value) { __asm__ __volatile__( "movec %0,#4\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_acr1(uint32_t value) { __asm__ __volatile__( "movec %0,#5\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_acr2(uint32_t value) { __asm__ __volatile__( "movec %0,#6\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_acr3(uint32_t value) { __asm__ __volatile__( "movec %0,#7\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_mmubar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mmubar\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_other_a7(uint32_t value) { __asm__ __volatile__( "movec %0,%%other_sp\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_vbr(uint32_t value) { __asm__ __volatile__( "movec %0,%%vbr\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_macsr(uint32_t value) { __asm__ __volatile__( "movec %0,%%macsr\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_mask(uint32_t value) { __asm__ __volatile__( "movec %0,%%mask\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_acc0(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc0\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_accext01(uint32_t value) { __asm__ __volatile__( "movec %0,%%accext01\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_accext23(uint32_t value) { __asm__ __volatile__( "movec %0,%%accext23\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_acc1(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc1\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_acc2(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc2\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_acc3(uint32_t value) { __asm__ __volatile__( "movec %0,%%acc3\n nop\n" : : "r" (value) ); } +-//static __inline__ void mcf5xxx_wr_sr(uint32_t value) { __asm__ __volatile__( "movec %0,%%sr\n nop\n" : : "r" (value) ); } +-//static __inline__ void mcf5xxx_wr_pc(uint32_t value) { __asm__ __volatile__( "movec %0,#0x080F\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_rombar0(uint32_t value) { __asm__ __volatile__( "movec %0,%%rombar0\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_rombar1(uint32_t value) { __asm__ __volatile__( "movec %0,%%rombar1\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_rambar0(uint32_t value) { __asm__ __volatile__( "movec %0,%%rambar0\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_rambar1(uint32_t value) { __asm__ __volatile__( "movec %0,%%rambar1\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_mpcr(uint32_t value) { __asm__ __volatile__( "movec %0,%%mpcr\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_secmbar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mbar1\n nop\n" : : "r" (value) ); } +-static __inline__ void mcf5xxx_wr_mbar(uint32_t value) { __asm__ __volatile__( "movec %0,%%mbar0\n nop\n" : : "r" (value) ); } +- +-#endif +- +-/* +- * Now do specific ColdFire processor +- */ +- +-#if (defined(CONFIG_ARCH_MCF54xx)) +-#include "asm/coldfire/mcf548x.h" +- +-#else +-#error "Error: Yet unsupported ColdFire processor." +-#endif +- +- +-#endif /* __MCF5XXX__H */ +diff --git a/arch/m68k/include/asm/common.h b/arch/m68k/include/asm/common.h +deleted file mode 100644 +index 202ccad..0000000 +--- a/arch/m68k/include/asm/common.h ++++ /dev/null +@@ -1,25 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Common include file wrapper for m68k architecture +- */ +- +-/* nothing */ +diff --git a/arch/m68k/include/asm/elf.h b/arch/m68k/include/asm/elf.h +deleted file mode 100644 +index 57fdcb2..0000000 +--- a/arch/m68k/include/asm/elf.h ++++ /dev/null +@@ -1,146 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Defines for M68k ELF Files +- */ +-#ifndef __ASMm68k_ELF_H +-#define __ASMm68k_ELF_H +- +-/* +- * ELF register definitions.. +- */ +- +-//#include <linux/config.h> +-#include <asm/ptrace.h> +-//#include <asm/user.h> +- +-/* +- * 68k ELF relocation types +- */ +-#define R_68K_NONE 0 +-#define R_68K_32 1 +-#define R_68K_16 2 +-#define R_68K_8 3 +-#define R_68K_PC32 4 +-#define R_68K_PC16 5 +-#define R_68K_PC8 6 +-#define R_68K_GOT32 7 +-#define R_68K_GOT16 8 +-#define R_68K_GOT8 9 +-#define R_68K_GOT32O 10 +-#define R_68K_GOT16O 11 +-#define R_68K_GOT8O 12 +-#define R_68K_PLT32 13 +-#define R_68K_PLT16 14 +-#define R_68K_PLT8 15 +-#define R_68K_PLT32O 16 +-#define R_68K_PLT16O 17 +-#define R_68K_PLT8O 18 +-#define R_68K_COPY 19 +-#define R_68K_GLOB_DAT 20 +-#define R_68K_JMP_SLOT 21 +-#define R_68K_RELATIVE 22 +- +-typedef unsigned long elf_greg_t; +- +-//#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) +-#define ELF_NGREG 20 +-typedef elf_greg_t elf_gregset_t[ELF_NGREG]; +- +-typedef struct user_m68kfp_struct elf_fpregset_t; +- +-/* +- * This is used to ensure we don't load something for the wrong architecture. +- */ +-#define elf_check_arch(x) ((x)->e_machine == EM_68K) +- +-/* +- * These are used to set parameters in the core dumps. +- */ +-#define ELF_CLASS ELFCLASS32 +-#define ELF_DATA ELFDATA2MSB +-#define ELF_ARCH EM_68K +- +-/* For SVR4/m68k the function pointer to be registered with `atexit' is +- passed in %a1. Although my copy of the ABI has no such statement, it +- is actually used on ASV. */ +-#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 +- +-#define USE_ELF_CORE_DUMP +-#if !defined(CONFIG_SUN3) && !defined(CONFIG_COLDFIRE) +-#define ELF_EXEC_PAGESIZE 4096 +-#else +-#define ELF_EXEC_PAGESIZE 8192 +-#endif +- +-/* This is the location that an ET_DYN program is loaded if exec'ed. Typical +- use of this is to invoke "./ld.so someprog" to test out a new version of +- the loader. We need to make sure that it is out of the way of the program +- that it will "exec", and that there is sufficient room for the brk. */ +- +-#ifndef CONFIG_SUN3 +-#define ELF_ET_DYN_BASE 0xD0000000UL +-#else +-#define ELF_ET_DYN_BASE 0x0D800000UL +-#endif +- +-#define ELF_CORE_COPY_REGS(pr_reg, regs) \ +- /* Bleech. */ \ +- pr_reg[0] = regs->d1; \ +- pr_reg[1] = regs->d2; \ +- pr_reg[2] = regs->d3; \ +- pr_reg[3] = regs->d4; \ +- pr_reg[4] = regs->d5; \ +- pr_reg[7] = regs->a0; \ +- pr_reg[8] = regs->a1; \ +- pr_reg[9] = regs->a2; \ +- pr_reg[14] = regs->d0; \ +- pr_reg[15] = rdusp(); \ +- pr_reg[16] = regs->orig_d0; \ +- pr_reg[17] = regs->sr; \ +- pr_reg[18] = regs->pc; \ +- pr_reg[19] = (regs->format << 12) | regs->vector; \ +- { \ +- struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \ +- pr_reg[5] = sw->d6; \ +- pr_reg[6] = sw->d7; \ +- pr_reg[10] = sw->a3; \ +- pr_reg[11] = sw->a4; \ +- pr_reg[12] = sw->a5; \ +- pr_reg[13] = sw->a6; \ +- } +- +-/* This yields a mask that user programs can use to figure out what +- instruction set this cpu supports. */ +- +-#define ELF_HWCAP (0) +- +-/* This yields a string that ld.so will use to load implementation +- specific libraries for optimization. This is more specific in +- intent than poking at uname or /proc/cpuinfo. */ +- +-#define ELF_PLATFORM (NULL) +- +-#ifdef __KERNEL__ +-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) +-#endif +- +-#endif +diff --git a/arch/m68k/include/asm/hardware.h b/arch/m68k/include/asm/hardware.h +deleted file mode 100644 +index eeca64e..0000000 +--- a/arch/m68k/include/asm/hardware.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Common hardware definitions +- */ +- +-#ifndef __M68K_HARDWARE_H +-#define __M68K_HARDWARE_H +- +-#include <mach/hardware.h> +- +-#endif +diff --git a/arch/m68k/include/asm/io.h b/arch/m68k/include/asm/io.h +deleted file mode 100644 +index b6b01cb..0000000 +--- a/arch/m68k/include/asm/io.h ++++ /dev/null +@@ -1,304 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Generic virtual read/write. Note that we don't support half-word +- * read/writes. We define __arch_*[bl] here, and leave __arch_*w +- * to the architecture specific code. +- */ +-#ifndef __ASM_M68K_IO_H +-#define __ASM_M68K_IO_H +- +-#ifdef __KERNEL__ +- +-#include <linux/types.h> +-#include <asm/byteorder.h> +-#include <asm/memory.h> +- +-/* +- */ +-#define __arch_getb(a) (*(volatile unsigned char *)(a)) +-#define __arch_getw(a) (*(volatile unsigned short *)(a)) +-#define __arch_getl(a) (*(volatile unsigned int *)(a)) +- +-#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +-#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +-#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) +- +-extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); +-extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); +-extern void __raw_writesl(unsigned int addr, const void *data, int longlen); +- +-extern void __raw_readsb(unsigned int addr, void *data, int bytelen); +-extern void __raw_readsw(unsigned int addr, void *data, int wordlen); +-extern void __raw_readsl(unsigned int addr, void *data, int longlen); +- +-#define __raw_writeb(v,a) __arch_putb(v,a) +-#define __raw_writew(v,a) __arch_putw(v,a) +-#define __raw_writel(v,a) __arch_putl(v,a) +- +-#define __raw_readb(a) __arch_getb(a) +-#define __raw_readw(a) __arch_getw(a) +-#define __raw_readl(a) __arch_getl(a) +- +-#define writeb(v,a) __arch_putb(v,a) +-#define writew(v,a) __arch_putw(v,a) +-#define writel(v,a) __arch_putl(v,a) +- +-#define readb(a) __arch_getb(a) +-#define readw(a) __arch_getw(a) +-#define readl(a) __arch_getl(a) +- +-/* +- * The compiler seems to be incapable of optimising constants +- * properly. Spell it out to the compiler in some cases. +- * These are only valid for small values of "off" (< 1<<12) +- */ +-#define __raw_base_writeb(val,base,off) __arch_base_putb(val,base,off) +-#define __raw_base_writew(val,base,off) __arch_base_putw(val,base,off) +-#define __raw_base_writel(val,base,off) __arch_base_putl(val,base,off) +- +-#define __raw_base_readb(base,off) __arch_base_getb(base,off) +-#define __raw_base_readw(base,off) __arch_base_getw(base,off) +-#define __raw_base_readl(base,off) __arch_base_getl(base,off) +- +-/* +- * Now, pick up the machine-defined IO definitions +- */ +- +-/* +- * IO port access primitives +- * ------------------------- +- * +- * The M68k doesn't have special IO access instructions; all IO is memory +- * mapped. Note that these are defined to perform little endian accesses +- * only. Their primary purpose is to access PCI and ISA peripherals. +- * +- * Note that for a big endian machine, this implies that the following +- * big endian mode connectivity is in place, as described by numerious +- * ARM documents: +- * +- * PCI: D0-D7 D8-D15 D16-D23 D24-D31 +- * ARM: D24-D31 D16-D23 D8-D15 D0-D7 +- * +- * The machine specific io.h include defines __io to translate an "IO" +- * address to a memory address. +- * +- * Note that we prevent GCC re-ordering or caching values in expressions +- * by introducing sequence points into the in*() definitions. Note that +- * __raw_* do not guarantee this behaviour. +- * +- * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. +- */ +-#ifdef __io +-#define outb(v,p) __raw_writeb(v,__io(p)) +-#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p)) +-#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) +- +-#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; }) +-#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; }) +-#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; }) +- +-#define outsb(p,d,l) __raw_writesb(__io(p),d,l) +-#define outsw(p,d,l) __raw_writesw(__io(p),d,l) +-#define outsl(p,d,l) __raw_writesl(__io(p),d,l) +- +-#define insb(p,d,l) __raw_readsb(__io(p),d,l) +-#define insw(p,d,l) __raw_readsw(__io(p),d,l) +-#define insl(p,d,l) __raw_readsl(__io(p),d,l) +-#endif +- +-#define outb_p(val,port) outb((val),(port)) +-#define outw_p(val,port) outw((val),(port)) +-#define outl_p(val,port) outl((val),(port)) +-#define inb_p(port) inb((port)) +-#define inw_p(port) inw((port)) +-#define inl_p(port) inl((port)) +- +-#define outsb_p(port,from,len) outsb(port,from,len) +-#define outsw_p(port,from,len) outsw(port,from,len) +-#define outsl_p(port,from,len) outsl(port,from,len) +-#define insb_p(port,to,len) insb(port,to,len) +-#define insw_p(port,to,len) insw(port,to,len) +-#define insl_p(port,to,len) insl(port,to,len) +- +-/* +- * ioremap and friends. +- * +- * ioremap takes a PCI memory address, as specified in +- * linux/Documentation/IO-mapping.txt. If you want a +- * physical address, use __ioremap instead. +- */ +-extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); +-extern void __iounmap(void *addr); +- +-/* +- * Generic ioremap support. +- * +- * Define: +- * iomem_valid_addr(off,size) +- * iomem_to_phys(off) +- */ +-#ifdef iomem_valid_addr +-#define __arch_ioremap(off,sz,nocache) \ +- ({ \ +- unsigned long _off = (off), _size = (sz); \ +- void *_ret = (void *)0; \ +- if (iomem_valid_addr(_off, _size)) \ +- _ret = __ioremap(iomem_to_phys(_off),_size,0); \ +- _ret; \ +- }) +- +-#define __arch_iounmap __iounmap +-#endif +- +-#define ioremap(off,sz) __arch_ioremap((off),(sz),0) +-#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) +-#define iounmap(_addr) __arch_iounmap(_addr) +- +-/* +- * DMA-consistent mapping functions. These allocate/free a region of +- * uncached, unwrite-buffered mapped memory space for use with DMA +- * devices. This is the "generic" version. The PCI specific version +- * is in pci.h +- */ +-extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +-extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); +-extern void consistent_sync(void *vaddr, size_t size, int rw); +- +-/* +- * String version of IO memory access ops: +- */ +-extern void _memcpy_fromio(void *, unsigned long, size_t); +-extern void _memcpy_toio(unsigned long, const void *, size_t); +-extern void _memset_io(unsigned long, int, size_t); +- +-extern void __readwrite_bug(const char *fn); +- +-/* +- * If this architecture has PCI memory IO, then define the read/write +- * macros. These should only be used with the cookie passed from +- * ioremap. +- */ +-#ifdef __mem_pci +- +-#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) +-#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) +-#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) +- +-#define writeb(v,c) __raw_writeb(v,__mem_pci(c)) +-#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c)) +-#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c)) +- +-#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l)) +-#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l)) +-#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l)) +- +-#define eth_io_copy_and_sum(s,c,l,b) \ +- eth_copy_and_sum((s),__mem_pci(c),(l),(b)) +- +-static inline int +-check_signature(unsigned long io_addr, const unsigned char *signature, +- int length) +-{ +- int retval = 0; +- do { +- if (readb(io_addr) != *signature) +- goto out; +- io_addr++; +- signature++; +- length--; +- } while (length); +- retval = 1; +-out: +- return retval; +-} +- +-#elif !defined(readb) +- +-#define readb(addr) (__readwrite_bug("readb"),0) +-#define readw(addr) (__readwrite_bug("readw"),0) +-#define readl(addr) (__readwrite_bug("readl"),0) +-#define writeb(v,addr) __readwrite_bug("writeb") +-#define writew(v,addr) __readwrite_bug("writew") +-#define writel(v,addr) __readwrite_bug("writel") +- +-#define eth_io_copy_and_sum(a,b,c,d) __readwrite_bug("eth_io_copy_and_sum") +- +-#define check_signature(io,sig,len) (0) +- +-#endif /* __mem_pci */ +- +-/* +- * If this architecture has ISA IO, then define the isa_read/isa_write +- * macros. +- */ +-#ifdef __mem_isa +- +-#define isa_readb(addr) __raw_readb(__mem_isa(addr)) +-#define isa_readw(addr) __raw_readw(__mem_isa(addr)) +-#define isa_readl(addr) __raw_readl(__mem_isa(addr)) +-#define isa_writeb(val,addr) __raw_writeb(val,__mem_isa(addr)) +-#define isa_writew(val,addr) __raw_writew(val,__mem_isa(addr)) +-#define isa_writel(val,addr) __raw_writel(val,__mem_isa(addr)) +-#define isa_memset_io(a,b,c) _memset_io(__mem_isa(a),(b),(c)) +-#define isa_memcpy_fromio(a,b,c) _memcpy_fromio((a),__mem_isa(b),(c)) +-#define isa_memcpy_toio(a,b,c) _memcpy_toio(__mem_isa((a)),(b),(c)) +- +-#define isa_eth_io_copy_and_sum(a,b,c,d) \ +- eth_copy_and_sum((a),__mem_isa(b),(c),(d)) +- +-static inline int +-isa_check_signature(unsigned long io_addr, const unsigned char *signature, +- int length) +-{ +- int retval = 0; +- do { +- if (isa_readb(io_addr) != *signature) +- goto out; +- io_addr++; +- signature++; +- length--; +- } while (length); +- retval = 1; +-out: +- return retval; +-} +- +-#else /* __mem_isa */ +- +-#define isa_readb(addr) (__readwrite_bug("isa_readb"),0) +-#define isa_readw(addr) (__readwrite_bug("isa_readw"),0) +-#define isa_readl(addr) (__readwrite_bug("isa_readl"),0) +-#define isa_writeb(val,addr) __readwrite_bug("isa_writeb") +-#define isa_writew(val,addr) __readwrite_bug("isa_writew") +-#define isa_writel(val,addr) __readwrite_bug("isa_writel") +-#define isa_memset_io(a,b,c) __readwrite_bug("isa_memset_io") +-#define isa_memcpy_fromio(a,b,c) __readwrite_bug("isa_memcpy_fromio") +-#define isa_memcpy_toio(a,b,c) __readwrite_bug("isa_memcpy_toio") +- +-#define isa_eth_io_copy_and_sum(a,b,c,d) \ +- __readwrite_bug("isa_eth_io_copy_and_sum") +- +-#define isa_check_signature(io,sig,len) (0) +- +-#endif /* __mem_isa */ +-#endif /* __KERNEL__ */ +-#endif /* __ASM_M68K_IO_H */ +diff --git a/arch/m68k/include/asm/mach-types.h b/arch/m68k/include/asm/mach-types.h +deleted file mode 100644 +index d221fcc..0000000 +--- a/arch/m68k/include/asm/mach-types.h ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * This was automagically generated from arch/m68k/tools/mach-types! +- * Do NOT edit +- */ +- +-#ifndef __ASM_M68K_MACH_TYPE_H +-#define __ASM_M68K_MACH_TYPE_H +- +-#ifndef __ASSEMBLY__ +-/* The type of machine we're running on */ +-extern unsigned int __machine_arch_type; +-#endif +- +-/* see arch/m68k/kernel/arch.c for a description of these */ +-#define MACH_TYPE_GENERIC 0 +-#define MACH_TYPE_MCF54xx 1 +-#define MACH_TYPE_MCF5445x 2 +- +-#ifdef CONFIG_ARCH_MCF54xx +-# ifdef machine_arch_type +-# undef machine_arch_type +-# define machine_arch_type __machine_arch_type +-# else +-# define machine_arch_type MACH_TYPE_MCF54xx +-# endif +-# define machine_is_mcf54xx() (machine_arch_type == MACH_TYPE_MCF54xx) +-#else +-# define machine_is_mcf54xx() (0) +-#endif +- +-#ifdef CONFIG_ARCH_MCF5445x +-# ifdef machine_arch_type +-# undef machine_arch_type +-# define machine_arch_type __machine_arch_type +-# else +-# define machine_arch_type MACH_TYPE_MCF5445x +-# endif +-# define machine_is_mcf5445x() (machine_arch_type == MACH_TYPE_MCF5445x) +-#else +-# define machine_is_mcf5445x() (0) +-#endif +- +- +-#ifndef machine_arch_type +-#define machine_arch_type __machine_arch_type +-#endif +- +-#endif +diff --git a/arch/m68k/include/asm/memory.h b/arch/m68k/include/asm/memory.h +deleted file mode 100644 +index 006ea3c..0000000 +--- a/arch/m68k/include/asm/memory.h ++++ /dev/null +@@ -1,28 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Note: this file should not be included by non-asm/.h files +- */ +-#ifndef __ASM_M68K_MEMORY_H +-#define __ASM_M68K_MEMORY_H +- +- +-#endif /* __ASM_M68K_MEMORY_H */ +diff --git a/arch/m68k/include/asm/module.h b/arch/m68k/include/asm/module.h +deleted file mode 100644 +index f04d794..0000000 +--- a/arch/m68k/include/asm/module.h ++++ /dev/null +@@ -1,36 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Defines for the ELF module loader +- */ +-#ifndef _ASM_M68K_MODULE_H +-#define _ASM_M68K_MODULE_H +- +-struct mod_arch_specific +-{ +- int foo; +-}; +- +-#define Elf_Shdr Elf32_Shdr +-#define Elf_Sym Elf32_Sym +-#define Elf_Ehdr Elf32_Ehdr +- +-#endif /* _ASM_M68K_MODULE_H */ +diff --git a/arch/m68k/include/asm/posix_types.h b/arch/m68k/include/asm/posix_types.h +deleted file mode 100644 +index d83afe9..0000000 +--- a/arch/m68k/include/asm/posix_types.h ++++ /dev/null +@@ -1,86 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * This file is generally used by user-level software, so you need to +- * be a little careful about namespace pollution etc. Also, we cannot +- * assume GCC is being used. +- */ +-#ifndef __ARCH_M68K_POSIX_TYPES_H +-#define __ARCH_M68K_POSIX_TYPES_H +- +- +-typedef unsigned long __kernel_ino_t; +-typedef unsigned short __kernel_mode_t; +-typedef unsigned short __kernel_nlink_t; +-typedef long __kernel_off_t; +-typedef int __kernel_pid_t; +-typedef unsigned short __kernel_ipc_pid_t; +-typedef unsigned short __kernel_uid_t; +-typedef unsigned short __kernel_gid_t; +-typedef unsigned int __kernel_size_t; +-typedef int __kernel_ssize_t; +-typedef int __kernel_ptrdiff_t; +-typedef long __kernel_time_t; +-typedef long __kernel_suseconds_t; +-typedef long __kernel_clock_t; +-typedef int __kernel_daddr_t; +-typedef char * __kernel_caddr_t; +-typedef unsigned short __kernel_uid16_t; +-typedef unsigned short __kernel_gid16_t; +-typedef unsigned int __kernel_uid32_t; +-typedef unsigned int __kernel_gid32_t; +- +-typedef unsigned short __kernel_old_uid_t; +-typedef unsigned short __kernel_old_gid_t; +- +-#ifdef __GNUC__ +-typedef long long __kernel_loff_t; +-#endif +- +-typedef struct { +-#if defined(__KERNEL__) || defined(__USE_ALL) +- int val[2]; +-#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +- int __val[2]; +-#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +-} __kernel_fsid_t; +- +-#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +- +-#undef __FD_SET +-#define __FD_SET(fd, fdsetp) \ +- (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) +- +-#undef __FD_CLR +-#define __FD_CLR(fd, fdsetp) \ +- (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) +- +-#undef __FD_ISSET +-#define __FD_ISSET(fd, fdsetp) \ +- ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) +- +-#undef __FD_ZERO +-#define __FD_ZERO(fdsetp) \ +- (memset (fdsetp, 0, sizeof (*(fd_set *)fdsetp))) +- +-#endif +- +-#endif +diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h +deleted file mode 100644 +index b0f82d0..0000000 +--- a/arch/m68k/include/asm/processor.h ++++ /dev/null +@@ -1,46 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * General processor specific definitions +- */ +-#ifndef __ASM_M68K_PROCESSOR_H +-#define __ASM_M68K_PROCESSOR_H +- +-/* +- * Default implementation of macro that returns current +- * instruction pointer ("program counter"). +- */ +-#define current_text_addr() ({ __label__ _l; _l: &&_l;}) +- +-static inline unsigned long rdusp(void) +-{ +- unsigned long usp; +- +- __asm__ __volatile__("movel %/usp,%0" : "=a" (usp)); +- return usp; +-} +- +-static inline void wrusp(unsigned long usp) +-{ +- __asm__ __volatile__("movel %0,%/usp" : : "a" (usp)); +-} +- +-#endif /* __ASM_M68K_PROCESSOR_H */ +diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h +deleted file mode 100644 +index 8f3d39a..0000000 +--- a/arch/m68k/include/asm/ptrace.h ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Remains of the pthread stuff... +- * @todo Rework these headers.... +- */ +-#ifndef __ASM_M68K_PTRACE_H +-#define __ASM_M68K_PTRACE_H +- +-#define PTRACE_GETREGS 12 +-#define PTRACE_SETREGS 13 +-#define PTRACE_GETFPREGS 14 +-#define PTRACE_SETFPREGS 15 +- +-#define PTRACE_SETOPTIONS 21 +- +- +-#include <proc/ptrace.h> +- +-#ifndef __ASSEMBLY__ +- +-#ifndef PS_S +-#define PS_S (0x2000) +-#define PS_M (0x1000) +-#endif +- +-//#define user_mode(regs) (!((regs)->sr & PS_S)) +-#define instruction_pointer(regs) ((regs)->M68K_pc) +-#define profile_pc(regs) instruction_pointer(regs) +- +-#ifdef __KERNEL__ +-extern void show_regs(struct pt_regs *); +-#endif +- +-#endif /* __ASSEMBLY__ */ +- +-#endif +diff --git a/arch/m68k/include/asm/setup.h b/arch/m68k/include/asm/setup.h +deleted file mode 100644 +index ee0bde8..0000000 +--- a/arch/m68k/include/asm/setup.h ++++ /dev/null +@@ -1,412 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Arch dependant barebox defines about linux mach types +- */ +-#ifndef _M68K_SETUP_H +-#define _M68K_SETUP_H +- +-#include <config.h> +- +- +-/* +- * Linux/m68k Architectures +- */ +- +-#define MACH_AMIGA 1 +-#define MACH_ATARI 2 +-#define MACH_MAC 3 +-#define MACH_APOLLO 4 +-#define MACH_SUN3 5 +-#define MACH_MVME147 6 +-#define MACH_MVME16x 7 +-#define MACH_BVME6000 8 +-#define MACH_HP300 9 +-#define MACH_Q40 10 +-#define MACH_SUN3X 11 +- /* ColdFire boards */ +-#define MACH_FIRE_ENGINE 12 +- +-#ifdef __KERNEL__ +- +-#ifndef __ASSEMBLY__ +-extern unsigned long m68k_machtype; +-#endif /* !__ASSEMBLY__ */ +- +-#if !defined(CONFIG_AMIGA) +-# define MACH_IS_AMIGA (0) +-#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ +- || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ +- || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) +-# define MACH_IS_AMIGA (m68k_machtype == MACH_AMIGA) +-#else +-# define MACH_AMIGA_ONLY +-# define MACH_IS_AMIGA (1) +-# define MACH_TYPE (MACH_AMIGA) +-#endif +- +-#if !defined(CONFIG_ATARI) +-# define MACH_IS_ATARI (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ +- || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ +- || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) +-# define MACH_IS_ATARI (m68k_machtype == MACH_ATARI) +-#else +-# define MACH_ATARI_ONLY +-# define MACH_IS_ATARI (1) +-# define MACH_TYPE (MACH_ATARI) +-#endif +- +-#if !defined(CONFIG_MAC) +-# define MACH_IS_MAC (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_ATARI) || defined(CONFIG_APOLLO) \ +- || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ +- || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) +-# define MACH_IS_MAC (m68k_machtype == MACH_MAC) +-#else +-# define MACH_MAC_ONLY +-# define MACH_IS_MAC (1) +-# define MACH_TYPE (MACH_MAC) +-#endif +- +-#if defined(CONFIG_SUN3) +-#define MACH_IS_SUN3 (1) +-#define MACH_SUN3_ONLY (1) +-#define MACH_TYPE (MACH_SUN3) +-#else +-#define MACH_IS_SUN3 (0) +-#endif +- +-#if !defined (CONFIG_APOLLO) +-# define MACH_IS_APOLLO (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ +- || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ +- || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) +-# define MACH_IS_APOLLO (m68k_machtype == MACH_APOLLO) +-#else +-# define MACH_APOLLO_ONLY +-# define MACH_IS_APOLLO (1) +-# define MACH_TYPE (MACH_APOLLO) +-#endif +- +-#if !defined (CONFIG_MVME147) +-# define MACH_IS_MVME147 (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ +- || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ +- || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME16x) +-# define MACH_IS_MVME147 (m68k_machtype == MACH_MVME147) +-#else +-# define MACH_MVME147_ONLY +-# define MACH_IS_MVME147 (1) +-# define MACH_TYPE (MACH_MVME147) +-#endif +- +-#if !defined (CONFIG_MVME16x) +-# define MACH_IS_MVME16x (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ +- || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ +- || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) +-# define MACH_IS_MVME16x (m68k_machtype == MACH_MVME16x) +-#else +-# define MACH_MVME16x_ONLY +-# define MACH_IS_MVME16x (1) +-# define MACH_TYPE (MACH_MVME16x) +-#endif +- +-#if !defined (CONFIG_BVME6000) +-# define MACH_IS_BVME6000 (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ +- || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ +- || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) +-# define MACH_IS_BVME6000 (m68k_machtype == MACH_BVME6000) +-#else +-# define MACH_BVME6000_ONLY +-# define MACH_IS_BVME6000 (1) +-# define MACH_TYPE (MACH_BVME6000) +-#endif +- +-#if !defined (CONFIG_HP300) +-# define MACH_IS_HP300 (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ +- || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ +- || defined(CONFIG_BVME6000) || defined(CONFIG_Q40) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) +-# define MACH_IS_HP300 (m68k_machtype == MACH_HP300) +-#else +-# define MACH_HP300_ONLY +-# define MACH_IS_HP300 (1) +-# define MACH_TYPE (MACH_HP300) +-#endif +- +-#if !defined (CONFIG_Q40) +-# define MACH_IS_Q40 (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ +- || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ +- || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ +- || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) +-# define MACH_IS_Q40 (m68k_machtype == MACH_Q40) +-#else +-# define MACH_Q40_ONLY +-# define MACH_IS_Q40 (1) +-# define MACH_TYPE (MACH_Q40) +-#endif +- +-#if !defined (CONFIG_SUN3X) +-# define MACH_IS_SUN3X (0) +-#elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ +- || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ +- || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ +- || defined(CONFIG_Q40) || defined(CONFIG_MVME147) +-# define MACH_IS_SUN3X (m68k_machtype == MACH_SUN3X) +-#else +-# define CONFIG_SUN3X_ONLY +-# define MACH_IS_SUN3X (1) +-# define MACH_TYPE (MACH_SUN3X) +-#endif +- +-/* +- * We only support one ColdFire board for the moment, so we don't do the +- * kind of complicated configuration this file does for the other 68k CPUs. --NL +- */ +-#if !defined (CONFIG_COLDFIRE) +-# define MACH_IS_COLDFIRE (0) +-#else +-# define CONFIG_COLDFIRE_ONLY +-# define MACH_IS_COLDFIRE (1) +-# define MACH_TYPE (MACH_COLDFIRE) +-#endif +- +-#ifndef MACH_TYPE +-# define MACH_TYPE (m68k_machtype) +-#endif +- +-#endif /* __KERNEL__ */ +- +- +- /* +- * CPU, FPU and MMU types +- * +- * Note: we may rely on the following equalities: +- * +- * CPU_68020 == MMU_68851 +- * CPU_68030 == MMU_68030 +- * CPU_68040 == FPU_68040 == MMU_68040 +- * CPU_68060 == FPU_68060 == MMU_68060 +- */ +- +-#define CPUB_68020 0 +-#define CPUB_68030 1 +-#define CPUB_68040 2 +-#define CPUB_68060 3 +-#define CPUB_CFV4E 4 +- +-#define CPU_68020 (1<<CPUB_68020) +-#define CPU_68030 (1<<CPUB_68030) +-#define CPU_68040 (1<<CPUB_68040) +-#define CPU_68060 (1<<CPUB_68060) +-#define CPU_CFV4E (1<<CPUB_CFV4E) +- +-#define FPUB_68881 0 +-#define FPUB_68882 1 +-#define FPUB_68040 2 /* Internal FPU */ +-#define FPUB_68060 3 /* Internal FPU */ +-#define FPUB_SUNFPA 4 /* Sun-3 FPA */ +-#define FPUB_CFV4E 5 +- +-#define FPU_68881 (1<<FPUB_68881) +-#define FPU_68882 (1<<FPUB_68882) +-#define FPU_68040 (1<<FPUB_68040) +-#define FPU_68060 (1<<FPUB_68060) +-#define FPU_SUNFPA (1<<FPUB_SUNFPA) +-#define FPU_CFV4E (1<<FPUB_CFV4E) +- +-#define MMUB_68851 0 +-#define MMUB_68030 1 /* Internal MMU */ +-#define MMUB_68040 2 /* Internal MMU */ +-#define MMUB_68060 3 /* Internal MMU */ +-#define MMUB_APOLLO 4 /* Custom Apollo */ +-#define MMUB_SUN3 5 /* Custom Sun-3 */ +-#define MMUB_CFV4E 6 +- +-#define MMU_68851 (1<<MMUB_68851) +-#define MMU_68030 (1<<MMUB_68030) +-#define MMU_68040 (1<<MMUB_68040) +-#define MMU_68060 (1<<MMUB_68060) +-#define MMU_SUN3 (1<<MMUB_SUN3) +-#define MMU_APOLLO (1<<MMUB_APOLLO) +-#define MMU_CFV4E (1<<MMUB_CFV4E) +- +-#ifdef __KERNEL__ +- +-#ifndef __ASSEMBLY__ +-extern unsigned long m68k_cputype; +-extern unsigned long m68k_fputype; +-extern unsigned long m68k_mmutype; /* Not really used yet */ +-#ifdef CONFIG_VME +-extern unsigned long vme_brdtype; +-#endif +- +- /* +- * m68k_is040or060 is != 0 for a '040 or higher; +- * used numbers are 4 for 68040 and 6 for 68060. +- */ +- +-extern int m68k_is040or060; +-#endif /* !__ASSEMBLY__ */ +- +-#if !defined(CONFIG_M68020) +-# define CPU_IS_020 (0) +-# define MMU_IS_851 (0) +-# define MMU_IS_SUN3 (0) +-#elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060) +-# define CPU_IS_020 (m68k_cputype & CPU_68020) +-# define MMU_IS_851 (m68k_mmutype & MMU_68851) +-# define MMU_IS_SUN3 (0) /* Sun3 not supported with other CPU enabled */ +-#else +-# define CPU_M68020_ONLY +-# define CPU_IS_020 (1) +-#ifdef MACH_SUN3_ONLY +-# define MMU_IS_SUN3 (1) +-# define MMU_IS_851 (0) +-#else +-# define MMU_IS_SUN3 (0) +-# define MMU_IS_851 (1) +-#endif +-#endif +- +-#if !defined(CONFIG_M68030) +-# define CPU_IS_030 (0) +-# define MMU_IS_030 (0) +-#elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060) +-# define CPU_IS_030 (m68k_cputype & CPU_68030) +-# define MMU_IS_030 (m68k_mmutype & MMU_68030) +-#else +-# define CPU_M68030_ONLY +-# define CPU_IS_030 (1) +-# define MMU_IS_030 (1) +-#endif +- +-#if !defined(CONFIG_M68040) +-# define CPU_IS_040 (0) +-# define MMU_IS_040 (0) +-#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060) +-# define CPU_IS_040 (m68k_cputype & CPU_68040) +-# define MMU_IS_040 (m68k_mmutype & MMU_68040) +-#else +-# define CPU_M68040_ONLY +-# define CPU_IS_040 (1) +-# define MMU_IS_040 (1) +-#endif +- +-#if !defined(CONFIG_M68060) +-# define CPU_IS_060 (0) +-# define MMU_IS_060 (0) +-#elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040) +-# define CPU_IS_060 (m68k_cputype & CPU_68060) +-# define MMU_IS_060 (m68k_mmutype & MMU_68060) +-#else +-# define CPU_M68060_ONLY +-# define CPU_IS_060 (1) +-# define MMU_IS_060 (1) +-#endif +- +-#if !defined(CONFIG_M68020) && !defined(CONFIG_M68030) +-# define CPU_IS_020_OR_030 (0) +-#else +-# define CPU_M68020_OR_M68030 +-# if defined(CONFIG_M68040) || defined(CONFIG_M68060) +-# define CPU_IS_020_OR_030 (!m68k_is040or060) +-# else +-# define CPU_M68020_OR_M68030_ONLY +-# define CPU_IS_020_OR_030 (1) +-# endif +-#endif +- +-#if !defined(CONFIG_M68040) && !defined(CONFIG_M68060) +-# define CPU_IS_040_OR_060 (0) +-#else +-# define CPU_M68040_OR_M68060 +-# if defined(CONFIG_M68020) || defined(CONFIG_M68030) +-# define CPU_IS_040_OR_060 (m68k_is040or060) +-# else +-# define CPU_M68040_OR_M68060_ONLY +-# define CPU_IS_040_OR_060 (1) +-# endif +-#endif +- +-#if !defined(CONFIG_CFV4E) +-# define CPU_IS_COLDFIRE (0) +-#else +-# define CPU_IS_COLDFIRE (1) +-# define CPU_IS_CFV4E (1) +-# define MMU_IS_CFV4E (1) +-#endif +- +-#define CPU_TYPE (m68k_cputype) +- +-#ifdef CONFIG_M68KFPU_EMU +-# ifdef CONFIG_M68KFPU_EMU_ONLY +-# define FPU_IS_EMU (1) +-# else +-# define FPU_IS_EMU (!m68k_fputype) +-# endif +-#else +-# define FPU_IS_EMU (0) +-#endif +- +- +-/* +- * Miscellaneous +- */ +- +-#define NUM_MEMINFO 4 +-#define CL_SIZE 256 +-#define COMMAND_LINE_SIZE CL_SIZE +- +-#ifndef __ASSEMBLY__ +-struct mem_info { +- unsigned long addr; /* physical address of memory chunk */ +- unsigned long size; /* length of memory chunk (in bytes) */ +-}; +-extern int m68k_num_memory; /* # of memory blocks found (and used) */ +-extern int m68k_realnum_memory; /* real # of memory blocks found */ +-extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ +- +-#endif +- +-#ifdef CONFIG_COLDFIRE +-#define QCHIP_RESTORE_DIRECTIVE ".chip 547x" +-#define CHIP_RESTORE_DIRECTIVE .chip 547x +-#else +-#define QCHIP_RESTORE_DIRECTIVE ".chip 68k" +-#define CHIP_RESTORE_DIRECTIVE .chip 68k +-#endif +- +-#endif /* __KERNEL__ */ +- +-#endif /* _M68K_SETUP_H */ +diff --git a/arch/m68k/include/asm/string.h b/arch/m68k/include/asm/string.h +deleted file mode 100644 +index 19e3de4..0000000 +--- a/arch/m68k/include/asm/string.h ++++ /dev/null +@@ -1,32 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Arch dependant configuration of std libc string and memory functions. +- */ +-#ifndef __ASM_M68K_STRING_H +-#define __ASM_M68K_STRING_H +- +-/* +- * We don't do inline string functions, since the +- * optimised inline asm versions are not small. +- */ +- +-#endif +diff --git a/arch/m68k/include/asm/types.h b/arch/m68k/include/asm/types.h +deleted file mode 100644 +index 90e8bd7..0000000 +--- a/arch/m68k/include/asm/types.h ++++ /dev/null +@@ -1,82 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Arch dependant types definitions +- */ +-#ifndef __ASM_M68K_TYPES_H +-#define __ASM_M68K_TYPES_H +- +-#ifndef __ASSEMBLY__ +- +-typedef unsigned short umode_t; +- +-/* +- * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the +- * header files exported to user space +- */ +- +-typedef __signed__ char __s8; +-typedef unsigned char __u8; +- +-typedef __signed__ short __s16; +-typedef unsigned short __u16; +- +-typedef __signed__ int __s32; +-typedef unsigned int __u32; +- +-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +-typedef __signed__ long long __s64; +-typedef unsigned long long __u64; +-#endif +- +-#endif /* __ASSEMBLY__ */ +- +-/* +- * These aren't exported outside the kernel to avoid name space clashes +- */ +-#ifdef __KERNEL__ +- +-#define BITS_PER_LONG 32 +- +-#ifndef __ASSEMBLY__ +- +-typedef signed char s8; +-typedef unsigned char u8; +- +-typedef signed short s16; +-typedef unsigned short u16; +- +-typedef signed int s32; +-typedef unsigned int u32; +- +-typedef signed long long s64; +-typedef unsigned long long u64; +- +-/* Dma addresses are 32-bits wide. */ +- +-typedef u32 dma_addr_t; +-typedef u32 dma64_addr_t; +- +-#endif /* __ASSEMBLY__ */ +- +-#endif /* __KERNEL__ */ +- +-#endif +diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile +deleted file mode 100644 +index 09cfb29..0000000 +--- a/arch/m68k/lib/Makefile ++++ /dev/null +@@ -1,31 +0,0 @@ +-# +-# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +-# See file CREDITS for list of people who contributed to this project. +-# +-# This file is part of barebox. +-# +-# barebox is free software: you can redistribute it and/or modify +-# it under the terms of the GNU General Public License as published by +-# the Free Software Foundation, either version 3 of the License, or +-# (at your option) any later version. +-# +-# barebox is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with barebox. If not, see <http://www.gnu.org/licenses/>. +-# +- +-# +-# Architecture dependant stubs and callbacks +-# +- +-obj-y += m68k-meminit.o +- +-obj-$(CONFIG_CMD_BOOTM) += m68k-linuxboot.o +- +-obj-$(CONFIG_MODULES) += m68k-module.o +- +-extra-$(CONFIG_GENERIC_LINKER_SCRIPT) += barebox.lds +diff --git a/arch/m68k/lib/barebox.lds.S b/arch/m68k/lib/barebox.lds.S +deleted file mode 100644 +index fb6673d..0000000 +--- a/arch/m68k/lib/barebox.lds.S ++++ /dev/null +@@ -1,92 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Generic Linker file for M68k targets +- */ +-#include <asm-generic/barebox.lds.h> +- +-OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", +- "elf32-m68k") +-OUTPUT_ARCH(m68k) +-ENTRY(_start) +-SECTIONS +-{ +- . = TEXT_BASE; +- . = ALIGN(4); +- +- /* Start of vector, text and rodata section */ +- _stext = .; +- _text = .; +- +- /* M68k/CF style vector table */ +- .vectors : +- { +- *(.vectors) +- } +- +- .text : +- { +- *(.text .stub .text.*) +- } =0x4e754e75 +- +- . = ALIGN(4); +- .rodata : +- { +- *(.rodata .rodata.*) +- } =0xdeadbeef +- +- . = ALIGN(4); +- __barebox_cmd_start = .; +- .barebox_cmd : { BAREBOX_CMDS } +- __barebox_cmd_end = .; +- +- __barebox_initcalls_start = .; +- .barebox_initcalls : { INITCALLS } +- __barebox_initcalls_end = .; +- +- __usymtab_start = .; +- __usymtab : { BAREBOX_SYMS } +- __usymtab_end = .; +- +- /* End of text and rodata section */ +- . = ALIGN(4); +- _etext = .; +- +- . = ALIGN(4); +- .got : { *(.got) } +- . = ALIGN(4); +- +- . = ALIGN(4); +- __early_init_data_begin = .; +- .early_init_data : { *(.early_init_data) } +- __early_init_data_end = .; +- +- .data : { *(.data .data.*) } +- +- . = ALIGN(4); +- __bss_start = .; +- .bss (NOLOAD) : { *(.bss .bass.*) } +- __bss_end =.; +- _end = .; +- +- . = ALIGN(4); +- _barebox_heap_start = .; +-} +diff --git a/arch/m68k/lib/m68k-linuxboot.c b/arch/m68k/lib/m68k-linuxboot.c +deleted file mode 100644 +index e5e90a8..0000000 +--- a/arch/m68k/lib/m68k-linuxboot.c ++++ /dev/null +@@ -1,177 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * @brief Linux boot preparation code. +- * +- * This file is responsible to start a linux kernel on +- * Coldfire targets. +- * +- * @note Only Colilo mode supported yet. +- */ +-#include <common.h> +-#include <command.h> +-#include <driver.h> +-#include <image.h> +-#include <zlib.h> +-#include <init.h> +- +-#include <asm/byteorder.h> +-#include <asm/setup.h> +-#include <environment.h> +-#include <boot.h> +-#include <asm/barebox-m68k.h> +-#include <asm/bootinfo.h> +- +- +-static int m68k_architecture = MACH_TYPE_GENERIC; +- +- +-/* +- * Setup M68k/Coldfire bootrecord info +- */ +-#if defined (CONFIG_SETUP_MEMORY_TAGS) || \ +- defined (CONFIG_CMDLINE_TAG) || \ +- defined (CONFIG_INITRD_TAG) +- +- +-static void setup_boot_record(char* start_boot_rec, const char* command_line) +-{ +- struct bi_record* record; +- +- *start_boot_rec++ = 'C'; +- *start_boot_rec++ = 'o'; +- *start_boot_rec++ = 'L'; +- *start_boot_rec++ = 'i'; +- *start_boot_rec++ = 'L'; +- *start_boot_rec++ = 'o'; +- +- record = (struct bi_record*) start_boot_rec; +- +- /* specify memory layout */ +-#ifdef CONFIG_SETUP_MEMORY_TAGS +- record->tag = BI_MEMCHUNK; +- record->data[0] = 0; +- record->data[1] = 64 * 1024 * 1024; // TODO: to be changed for different boards +- record->size = sizeof (record->tag) + sizeof (record->size) +- + sizeof (record->data[0]) + sizeof (record->data[0]); +- record = (struct bi_record *) ((void *) record + record->size); +-#endif +- +- /* add a kernel command line */ +-#ifdef CONFIG_CMDLINE_TAG +- record->tag = BI_COMMAND_LINE; +- strcpy ((char *) &record->data, command_line); +- record->size = sizeof (record->tag) + sizeof (record->size) +- + max (sizeof (record->data[0]), strlen (command_line)+1); +- record = (struct bi_record *) ((void *) record + record->size); +-#endif +- +- /* Add reference to initrd */ +-#ifdef CONFIG_INITRD_TAG +-#endif +- +- /* Mark end of tags */ +- record->tag = 0; +- record->data[0] = 0; +- record->data[1] = 0; +- record->size = sizeof(record->tag) + sizeof (record->size) +- + sizeof (record->data[0]) + sizeof (record->data[0]); +-} +- +-#else +-#define setup_boot_record(start_boot_rec,command_line) while (0) { } +- +-#endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ +- +- +-static int do_bootm_linux(struct image_data *data) +-{ +- image_header_t *os_header = &data->os->header; +- void (*theKernel)(int zero, int arch, uint params); +- const char *commandline = getenv ("bootargs"); +- uint32_t loadaddr,loadsize; +- +- if (image_check_type(os_header, IH_TYPE_MULTI)) { +- printf("Multifile images not handled at the moment\n"); +- return -1; +- } +- +- printf("commandline: %s\n", commandline); +- +- theKernel = (void (*)(int,int,uint))image_get_ep(os_header); +- +- debug ("## Transferring control to Linux (at address %08lx) ...\n", +- (ulong) theKernel); +- +- loadaddr = (uint32_t)image_get_load(os_header); +- loadsize = (uint32_t)image_get_size(os_header); +- setup_boot_record( (char*)(loadaddr+loadsize),(char*)commandline); +- +- if (relocate_image(data->os, (void *)loadaddr)) +- return -1; +- +- /* we assume that the kernel is in place */ +- printf ("\nStarting kernel image at 0x%08x size 0x%08x eentry 0x%08x\n\n", +- loadaddr, loadsize, (ulong) theKernel); +- +- /* Bring board into inactive post-reset state again */ +- cleanup_before_linux (); +- +- /* Jump to kernel entry point */ +- theKernel (0, m68k_architecture, 0xdeadbeaf); +- +- enable_interrupts(); +- printf("Error: Loaded kernel returned. Probably it couldn't\n" +- "find it's bootrecord.\n"); +- return -1; +-} +- +-/* +- * Register handler for m68k Kernel Images +- */ +-static int image_handle_cmdline_parse(struct image_data *data, int opt, char *optarg) +-{ +- switch (opt) +- { +- case 'a': +- m68k_architecture = simple_strtoul(optarg, NULL, 0); +- return 0; +- default: +- return 1; +- } +-} +- +-static struct image_handler handler = +-{ +- .cmdline_options = "a:", +- .cmdline_parse = image_handle_cmdline_parse, +- .help_string = " -a <arch> use architecture number <arch>", +- +- .bootm = do_bootm_linux, +- .image_type = IH_OS_LINUX, +-}; +- +-static int m68klinux_register_image_handler(void) +-{ +- return register_image_handler(&handler); +-} +- +-late_initcall(m68klinux_register_image_handler); +diff --git a/arch/m68k/lib/m68k-meminit.c b/arch/m68k/lib/m68k-meminit.c +deleted file mode 100644 +index 664ef50..0000000 +--- a/arch/m68k/lib/m68k-meminit.c ++++ /dev/null +@@ -1,43 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Init for memory allocator on m68k/Coldfire +- */ +-#include <common.h> +-#include <init.h> +-#include <mem_malloc.h> +-#include <asm/barebox-m68k.h> +-#include <reloc.h> +-#include <asm-generic/memory_layout.h> +- +-/** Initialize mem allocator on M68k/Coldfire +- */ +-int m68k_mem_malloc_init(void) +-{ +- /* Pass start and end address of managed memory */ +- +- mem_malloc_init((void *)MALLOC_BASE, +- (void *)(MALLOC_BASE + MALLOC_SIZE)); +- +- return 0; +-} +- +-core_initcall(m68k_mem_malloc_init); +diff --git a/arch/m68k/lib/m68k-module.c b/arch/m68k/lib/m68k-module.c +deleted file mode 100644 +index 6a4a2bc..0000000 +--- a/arch/m68k/lib/m68k-module.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Moduleloader Subsystem +- * +- * These relocation stubs are taken from Linux 2.6.10 They are used by the +- * higher level ELF loader code to place ELF files to arbitrary addresses. +- */ +-#include <common.h> +-#include <elf.h> +-#include <module.h> +-#include <errno.h> +- +-int apply_relocate(Elf32_Shdr *sechdrs, +- const char *strtab, +- unsigned int symindex, +- unsigned int relsec, +- struct module *me) +-{ +- unsigned int i; +- Elf32_Rel *rel = (void *)sechdrs[relsec].sh_addr; +- Elf32_Sym *sym; +- uint32_t *location; +- +- DEBUGP("Applying relocate section %u to %u\n", relsec, +- sechdrs[relsec].sh_info); +- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { +- /* This is where to make the change */ +- location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr +- + rel[i].r_offset; +- /* This is the symbol it is referring to. Note that all +- undefined symbols have been resolved. */ +- sym = (Elf32_Sym *)sechdrs[symindex].sh_addr +- + ELF32_R_SYM(rel[i].r_info); +- +- switch (ELF32_R_TYPE(rel[i].r_info)) { +- case R_68K_32: +- /* We add the value into the location given */ +- *location += sym->st_value; +- break; +- case R_68K_PC32: +- /* Add the value, subtract its postition */ +- *location += sym->st_value - (uint32_t)location; +- break; +- default: +- printk(KERN_ERR "module %s: Unknown relocation: %u\n", +- me->name, ELF32_R_TYPE(rel[i].r_info)); +- return -ENOEXEC; +- } +- } +- return 0; +-} +- +-int apply_relocate_add(Elf32_Shdr *sechdrs, +- const char *strtab, +- unsigned int symindex, +- unsigned int relsec, +- struct module *me) +-{ +- unsigned int i; +- Elf32_Rela *rel = (void *)sechdrs[relsec].sh_addr; +- Elf32_Sym *sym; +- uint32_t *location; +- +- DEBUGP("Applying relocate_add section %u to %u\n", relsec, +- sechdrs[relsec].sh_info); +- for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) { +- /* This is where to make the change */ +- location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr +- + rel[i].r_offset; +- /* This is the symbol it is referring to. Note that all +- undefined symbols have been resolved. */ +- sym = (Elf32_Sym *)sechdrs[symindex].sh_addr +- + ELF32_R_SYM(rel[i].r_info); +- +- switch (ELF32_R_TYPE(rel[i].r_info)) { +- case R_68K_32: +- /* We add the value into the location given */ +- *location = rel[i].r_addend + sym->st_value; +- break; +- case R_68K_PC32: +- /* Add the value, subtract its postition */ +- *location = rel[i].r_addend + sym->st_value - (uint32_t)location; +- break; +- default: +- printk(KERN_ERR "module %s: Unknown relocation: %u\n", +- me->name, ELF32_R_TYPE(rel[i].r_info)); +- return -ENOEXEC; +- } +- } +- return 0; +-} +diff --git a/arch/m68k/mach-mcfv4e.dox b/arch/m68k/mach-mcfv4e.dox +deleted file mode 100644 +index c6dc8f6..0000000 +--- a/arch/m68k/mach-mcfv4e.dox ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* This document is intended to provide the developer with information +- * how to integrate a new CPU (MACH) into this part of the barebox tree +- */ +- +-/** @page dev_m68k_mach M68k/Coldfire based CPU (MACH) into the tree +- +-FIXME - fill in further info about Coldfire and so on. Check code +- for compliance with the specs given below - move code otherwise. +- +-@par What's happens when the reset signal is gone +- +-@note Code running immediately after reset runs at an address it is not linked +- to: "runtime address != link address". You should only use branches and +- do not refer to fixed data. This implies the use of assembler code only. +- +-The M68k CPU starts at lable \<reset\> in one of the corresponding start-*.S +-files. After some basic hardware setup it can call a function +-\<arch_init_lowlevel\> if not disabled. This call is intended to give all +-developers a chance to use a standard reset vector file, but also do some +-special things required only on their specific CPU. +- +-After handling some MMU, Stack or similiar issues, \<board_init_lowlevel\> can +-be called (if not disabled). This is a board specific function for SDRAM setup +-for example. As its board specific, your can do whatever you need to bring +-your board up. As stack is already set to internal core RAM, this routine can +-be C. +- +-@note: You are not allowed to call other code here, because we are not running +- at link address. +- +-When \<board_init_lowlevel\> returns it will be assumed that there is now +-working RAM that can be used for all further steps. +- +-Next step is relocation of barebox itself. It gets copied to the end of +-available RAM and the last assembly instruction is a jump to \<start_barebox\>. +- +-At this point of time: "runtime address == link address". +- +-*/ +diff --git a/arch/m68k/mach-mcfv4e/Kconfig b/arch/m68k/mach-mcfv4e/Kconfig +deleted file mode 100644 +index aaba27e..0000000 +--- a/arch/m68k/mach-mcfv4e/Kconfig ++++ /dev/null +@@ -1,18 +0,0 @@ +- +-menu "M68k/Coldfire V4E specific settings" +- +-config COPY_LOWMEM_VECTORS +- bool "Copy vectors to SDRAM address 0" +- default y +- help +- This copies the vector table to SDRAM address 0 (default address) +- +-config USE_LOWMEM_VECTORS +- bool "Use vectors at SDRAM address 0" +- default n +- depends on COPY_LOWMEM_VECTORS +- help +- This copies the vector table to SDRAM address 0 (default address) and +- also uses this vector location +- +-endmenu +diff --git a/arch/m68k/mach-mcfv4e/Makefile b/arch/m68k/mach-mcfv4e/Makefile +deleted file mode 100644 +index f75834b..0000000 +--- a/arch/m68k/mach-mcfv4e/Makefile ++++ /dev/null +@@ -1,19 +0,0 @@ +-# +-# Generic code for Coldfire V4E targets (MCF547x/MCF548x) +-# +-obj-y += mcf_clocksource.o +-obj-y += mcf_reset_cpu.o +- +-# +-# FEC support +-# +-obj-y += multichannel_dma.o +-obj-y += dma_utils.o +-obj-y += fec.o +-obj-y += fecbd.o +- +-# +-# FreeScale MultiDMA Library +-# +-obj-y += mcdapi/ +-obj-y += net/ +diff --git a/arch/m68k/mach-mcfv4e/dma_utils.c b/arch/m68k/mach-mcfv4e/dma_utils.c +deleted file mode 100644 +index adeefea..0000000 +--- a/arch/m68k/mach-mcfv4e/dma_utils.c ++++ /dev/null +@@ -1,502 +0,0 @@ +-/* +- * File: dma_utils.c +- * Purpose: General purpose utilities for the multi-channel DMA +- * +- * Notes: The methodology used in these utilities assumes that +- * no single initiator will be tied to more than one +- * task/channel +- */ +- +-#include <common.h> +-#include <init.h> +-#include <linux/types.h> +-#include <mach/mcf54xx-regs.h> +-#include <proc/mcdapi/MCD_dma.h> +- +-#include <proc/dma_utils.h> +- +-/* +- * This global keeps track of which initiators have been +- * used of the available assignments. Initiators 0-15 are +- * hardwired. Initiators 16-31 are multiplexed and controlled +- * via the Initiatior Mux Control Registe (IMCR). The +- * assigned requestor is stored with the associated initiator +- * number. +- */ +-static int8_t used_reqs[32] = +-{ +- DMA_ALWAYS, DMA_DSPI_RX, DMA_DSPI_TX, DMA_DREQ0, +- DMA_PSC0_RX, DMA_PSC0_TX, DMA_USBEP0, DMA_USBEP1, +- DMA_USBEP2, DMA_USBEP3, DMA_PCI_TX, DMA_PCI_RX, +- DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX, +- 0, 0, 0, 0, +- 0, 0, 0, 0, +- 0, 0, 0, 0, +- 0, 0, 0, 0 +-}; +- +-/* +- * This global keeps track of which channels have been assigned +- * to tasks. This methology assumes that no single initiator +- * will be tied to more than one task/channel +- */ +-typedef struct +-{ +- int req; +- void (*handler)(void); +-} DMA_CHANNEL_STRUCT; +- +-static DMA_CHANNEL_STRUCT dma_channel[NCHANNELS] = +-{ +- {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, +- {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, +- {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL}, +- {-1,NULL}, {-1,NULL}, {-1,NULL}, {-1,NULL} +-}; +- +-/* +- * Enable all DMA interrupts +- * +- * Parameters: +- * pri Interrupt Priority +- * lvl Interrupt Level +- */ +-void +-dma_irq_enable(uint8_t lvl, uint8_t pri) +-{ +-//FIXME ASSERT(lvl > 0 && lvl < 8); +-//FIXME ASSERT(pri < 8); +- +- /* Setup the DMA ICR (#48) */ +- MCF_INTC_ICR48 = 0 +- | MCF_INTC_ICRn_IP(pri) +- | MCF_INTC_ICRn_IL(lvl); +- +- /* Unmask all task interrupts */ +- MCF_DMA_DIMR = 0; +- +- /* Clear the interrupt pending register */ +- MCF_DMA_DIPR = 0; +- +- /* Unmask the DMA interrupt in the interrupt controller */ +- MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK48; +-} +- +-/* +- * Disable all DMA interrupts +- */ +-void +-dma_irq_disable(void) +-{ +- /* Mask all task interrupts */ +- MCF_DMA_DIMR = (uint32_t)~0; +- +- /* Clear any pending task interrupts */ +- MCF_DMA_DIPR = (uint32_t)~0; +- +- /* Mask the DMA interrupt in the interrupt controller */ +- MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48; +-} +- +-/* +- * Attempt to enable the provided Initiator in the Initiator +- * Mux Control Register +- * +- * Parameters: +- * initiator Initiator identifier +- * +- * Return Value: +- * 1 if unable to make the assignment +- * 0 successful +- */ +-int +-dma_set_initiator(int initiator) +-{ +- switch (initiator) +- { +- /* These initiators are always active */ +- case DMA_ALWAYS: +- case DMA_DSPI_RX: +- case DMA_DSPI_TX: +- case DMA_DREQ0: +- case DMA_PSC0_RX: +- case DMA_PSC0_TX: +- case DMA_USBEP0: +- case DMA_USBEP1: +- case DMA_USBEP2: +- case DMA_USBEP3: +- case DMA_PCI_TX: +- case DMA_PCI_RX: +- case DMA_PSC1_RX: +- case DMA_PSC1_TX: +- case DMA_I2C_RX: +- case DMA_I2C_TX: +- break; +- case DMA_FEC0_RX: +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC16(3)) +- | MCF_DMA_IMCR_SRC16_FEC0RX; +- used_reqs[16] = DMA_FEC0_RX; +- break; +- case DMA_FEC0_TX: +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC17(3)) +- | MCF_DMA_IMCR_SRC17_FEC0TX; +- used_reqs[17] = DMA_FEC0_TX; +- break; +- case DMA_FEC1_RX: +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC20(3)) +- | MCF_DMA_IMCR_SRC20_FEC1RX; +- used_reqs[20] = DMA_FEC1_RX; +- break; +- case DMA_FEC1_TX: +- if (used_reqs[21] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3)) +- | MCF_DMA_IMCR_SRC21_FEC1TX; +- used_reqs[21] = DMA_FEC1_TX; +- } +- else if (used_reqs[25] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3)) +- | MCF_DMA_IMCR_SRC25_FEC1TX; +- used_reqs[25] = DMA_FEC1_TX; +- } +- else if (used_reqs[31] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) +- | MCF_DMA_IMCR_SRC31_FEC1TX; +- used_reqs[31] = DMA_FEC1_TX; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_DREQ1: +- if (used_reqs[29] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) +- | MCF_DMA_IMCR_SRC29_DREQ1; +- used_reqs[29] = DMA_DREQ1; +- } +- else if (used_reqs[21] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3)) +- | MCF_DMA_IMCR_SRC21_DREQ1; +- used_reqs[21] = DMA_DREQ1; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_CTM0: +- if (used_reqs[24] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC24(3)) +- | MCF_DMA_IMCR_SRC24_CTM0; +- used_reqs[24] = DMA_CTM0; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_CTM1: +- if (used_reqs[25] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3)) +- | MCF_DMA_IMCR_SRC25_CTM1; +- used_reqs[25] = DMA_CTM1; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_CTM2: +- if (used_reqs[26] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3)) +- | MCF_DMA_IMCR_SRC26_CTM2; +- used_reqs[26] = DMA_CTM2; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_CTM3: +- if (used_reqs[27] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3)) +- | MCF_DMA_IMCR_SRC27_CTM3; +- used_reqs[27] = DMA_CTM3; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_CTM4: +- if (used_reqs[28] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) +- | MCF_DMA_IMCR_SRC28_CTM4; +- used_reqs[28] = DMA_CTM4; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_CTM5: +- if (used_reqs[29] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) +- | MCF_DMA_IMCR_SRC29_CTM5; +- used_reqs[29] = DMA_CTM5; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_CTM6: +- if (used_reqs[30] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3)) +- | MCF_DMA_IMCR_SRC30_CTM6; +- used_reqs[30] = DMA_CTM6; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_CTM7: +- if (used_reqs[31] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) +- | MCF_DMA_IMCR_SRC31_CTM7; +- used_reqs[31] = DMA_CTM7; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_USBEP4: +- if (used_reqs[26] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3)) +- | MCF_DMA_IMCR_SRC26_USBEP4; +- used_reqs[26] = DMA_USBEP4; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_USBEP5: +- if (used_reqs[27] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3)) +- | MCF_DMA_IMCR_SRC27_USBEP5; +- used_reqs[27] = DMA_USBEP5; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_USBEP6: +- if (used_reqs[28] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) +- | MCF_DMA_IMCR_SRC28_USBEP6; +- used_reqs[28] = DMA_USBEP6; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_PSC2_RX: +- if (used_reqs[28] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3)) +- | MCF_DMA_IMCR_SRC28_PSC2RX; +- used_reqs[28] = DMA_PSC2_RX; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_PSC2_TX: +- if (used_reqs[29] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3)) +- | MCF_DMA_IMCR_SRC29_PSC2TX; +- used_reqs[29] = DMA_PSC2_TX; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_PSC3_RX: +- if (used_reqs[30] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3)) +- | MCF_DMA_IMCR_SRC30_PSC3RX; +- used_reqs[30] = DMA_PSC3_RX; +- } +- else /* No empty slots */ +- return 1; +- break; +- case DMA_PSC3_TX: +- if (used_reqs[31] == 0) +- { +- MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3)) +- | MCF_DMA_IMCR_SRC31_PSC3TX; +- used_reqs[31] = DMA_PSC3_TX; +- } +- else /* No empty slots */ +- return 1; +- break; +- default: +- return 1; +- } +- return 0; +-} +- +-/* +- * Return the initiator number for the given requestor +- * +- * Parameters: +- * requestor Initiator/Requestor identifier +- * +- * Return Value: +- * The initiator number (0-31) if initiator has been assigned +- * 0 (always initiator) otherwise +- */ +-uint32_t +-dma_get_initiator(int requestor) +-{ +- uint32_t i; +- +- for (i=0; i<sizeof(used_reqs); ++i) +- { +- if (used_reqs[i] == requestor) +- return i; +- } +- return 0; +-} +- +-/* +- * Remove the given initiator from the active list +- * +- * Parameters: +- * requestor Initiator/Requestor identifier +- */ +-void +-dma_free_initiator(int requestor) +-{ +- uint32_t i; +- +- for (i=16; i<sizeof(used_reqs); ++i) +- { +- if (used_reqs[i] == requestor) +- { +- used_reqs[i] = 0; +- break; +- } +- } +-} +- +-/* +- * Attempt to find an available channel and mark it as used +- * +- * Parameters: +- * requestor Initiator/Requestor identifier +- * +- * Return Value: +- * First available channel or -1 if they are all occupied +- */ +-int +-dma_set_channel(int requestor, void (*handler)(void)) +-{ +- int i; +- +- /* Check to see if this requestor is already assigned to a channel */ +- if ((i = dma_get_channel(requestor)) != -1) +- return i; +- +- for (i=0; i<NCHANNELS; ++i) +- { +- if (dma_channel[i].req == -1) +- { +- dma_channel[i].req = requestor; +- dma_channel[i].handler = handler; +- return i; +- } +- } +- +- /* All channels taken */ +- return -1; +-} +- +-/* +- * Return the channel being initiated by the given requestor +- * +- * Parameters: +- * requestor Initiator/Requestor identifier +- * +- * Return Value: +- * Channel that the requestor is controlling or -1 if hasn't been +- * activated +- */ +-int +-dma_get_channel(int requestor) +-{ +- uint32_t i; +- +- for (i=0; i<NCHANNELS; ++i) +- { +- if (dma_channel[i].req == requestor) +- return i; +- } +- return -1; +-} +- +-/* +- * Remove the channel being initiated by the given requestor from +- * the active list +- * +- * Parameters: +- * requestor Initiator/Requestor identifier +- */ +-void +-dma_free_channel(int requestor) +-{ +- uint32_t i; +- +- for (i=0; i<NCHANNELS; ++i) +- { +- if (dma_channel[i].req == requestor) +- { +- dma_channel[i].req = -1; +- dma_channel[i].handler = NULL; +- break; +- } +- } +-} +- +-/* +- * This is the catch-all interrupt handler for the mult-channel DMA +- */ +-int +-dma_interrupt_handler (void *arg1, void *arg2) +-{ +- uint32_t i, interrupts; +- (void)arg1; +- (void)arg2; +- +- disable_interrupts(); // was: board_irq_disable(); +- +- /* +- * Determine which interrupt(s) triggered by AND'ing the +- * pending interrupts with those that aren't masked. +- */ +- interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR; +- +- /* Make sure we are here for a reason */ +-// ASSERT(interrupts != 0); +- +- /* Clear the interrupt in the pending register */ +- MCF_DMA_DIPR = interrupts; +- +- for (i=0; i<16; ++i, interrupts>>=1) +- { +- if (interrupts & 0x1) +- { +- /* If there is a handler, call it */ +- if (dma_channel[i].handler != NULL) +- dma_channel[i].handler(); +- } +- } +- +- enable_interrupts(); // board_irq_enable(); +- return 1; +-} +diff --git a/arch/m68k/mach-mcfv4e/fec.c b/arch/m68k/mach-mcfv4e/fec.c +deleted file mode 100644 +index 7619283..0000000 +--- a/arch/m68k/mach-mcfv4e/fec.c ++++ /dev/null +@@ -1,1440 +0,0 @@ +-/* +- * File: fec.c +- * Purpose: Driver for the Fast Ethernet Controller (FEC) +- * +- * Notes: +- */ +-#include <common.h> +-#include <linux/types.h> +- +-#include <mach/mcf54xx-regs.h> +-#include <proc/mcdapi/MCD_dma.h> +-#include <proc/net/net.h> +-#include <proc/fecbd.h> +-#include <proc/fec.h> +-#include <proc/dma_utils.h> +- +- +-#define TRUE 1 +-#define FALSE 0 +-#define ASSERT(x) if (!(x)) hang(); +-#define nop() __asm__ __volatile__("nop\n") +- +- +-FEC_EVENT_LOG fec_log[2]; +- +-/* +- * Write a value to a PHY's MII register. +- * +- * Parameters: +- * ch FEC channel +- * phy_addr Address of the PHY. +- * reg_addr Address of the register in the PHY. +- * data Data to be written to the PHY register. +- * +- * Return Values: +- * 1 on failure +- * 0 on success. +- * +- * Please refer to your PHY manual for registers and their meanings. +- * mii_write() polls for the FEC's MII interrupt event (which should +- * be masked from the interrupt handler) and clears it. If after a +- * suitable amount of time the event isn't triggered, a value of 0 +- * is returned. +- */ +-int +-fec_mii_write(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t data) +-{ +- int timeout; +- uint32_t eimr; +- +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Clear the MII interrupt bit +- */ +- MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; +- +- /* +- * Write to the MII Management Frame Register to kick-off +- * the MII write +- */ +- MCF_FEC_MMFR(ch) = 0 +- | MCF_FEC_MMFR_ST_01 +- | MCF_FEC_MMFR_OP_WRITE +- | MCF_FEC_MMFR_PA(phy_addr) +- | MCF_FEC_MMFR_RA(reg_addr) +- | MCF_FEC_MMFR_TA_10 +- | MCF_FEC_MMFR_DATA(data); +- +- /* +- * Mask the MII interrupt +- */ +- eimr = MCF_FEC_EIMR(ch); +- MCF_FEC_EIMR(ch) &= ~MCF_FEC_EIMR_MII; +- +- /* +- * Poll for the MII interrupt (interrupt should be masked) +- */ +- for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) +- { +- if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII) +- break; +- } +- if(timeout == FEC_MII_TIMEOUT) +- return 1; +- +- /* +- * Clear the MII interrupt bit +- */ +- MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; +- +- /* +- * Restore the EIMR +- */ +- MCF_FEC_EIMR(ch) = eimr; +- +- return 0; +-} +- +-/* +- * Read a value from a PHY's MII register. +- * +- * Parameters: +- * ch FEC channel +- * phy_addr Address of the PHY. +- * reg_addr Address of the register in the PHY. +- * data Pointer to storage for the Data to be read +- * from the PHY register (passed by reference) +- * +- * Return Values: +- * 1 on failure +- * 0 on success. +- * +- * Please refer to your PHY manual for registers and their meanings. +- * mii_read() polls for the FEC's MII interrupt event (which should +- * be masked from the interrupt handler) and clears it. If after a +- * suitable amount of time the event isn't triggered, a value of 0 +- * is returned. +- */ +-int +-fec_mii_read(uint8_t ch, uint8_t phy_addr, uint8_t reg_addr, uint16_t *data) +-{ +- int timeout; +- +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Clear the MII interrupt bit +- */ +- MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; +- +- /* +- * Write to the MII Management Frame Register to kick-off +- * the MII read +- */ +- MCF_FEC_MMFR(ch) = 0 +- | MCF_FEC_MMFR_ST_01 +- | MCF_FEC_MMFR_OP_READ +- | MCF_FEC_MMFR_PA(phy_addr) +- | MCF_FEC_MMFR_RA(reg_addr) +- | MCF_FEC_MMFR_TA_10; +- +- /* +- * Poll for the MII interrupt (interrupt should be masked) +- */ +- for (timeout = 0; timeout < FEC_MII_TIMEOUT; timeout++) +- { +- if (MCF_FEC_EIR(ch) & MCF_FEC_EIR_MII) +- break; +- } +- +- if(timeout == FEC_MII_TIMEOUT) +- return 1; +- +- /* +- * Clear the MII interrupt bit +- */ +- MCF_FEC_EIR(ch) = MCF_FEC_EIR_MII; +- +- *data = (uint16_t)(MCF_FEC_MMFR(ch) & 0x0000FFFF); +- +- return 0; +-} +- +-/* +- * Initialize the MII interface controller +- * +- * Parameters: +- * ch FEC channel +- * sys_clk System Clock Frequency (in MHz) +- */ +-void +-fec_mii_init(uint8_t ch, uint32_t sys_clk) +-{ +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Initialize the MII clock (EMDC) frequency +- * +- * Desired MII clock is 2.5MHz +- * MII Speed Setting = System_Clock / (2.5MHz * 2) +- * (plus 1 to make sure we round up) +- */ +- MCF_FEC_MSCR(ch) = MCF_FEC_MSCR_MII_SPEED((sys_clk/5)+1); +-} +- +-/* Initialize the MIB counters +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_mib_init(uint8_t ch) +-{ +- ASSERT(ch == 0 || ch == 1); +-//To do +-} +- +-/* Display the MIB counters +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_mib_dump(uint8_t ch) +-{ +- ASSERT(ch == 0 || ch == 1); +-//To do +-} +- +-/* Initialize the FEC log +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_log_init(uint8_t ch) +-{ +- ASSERT(ch == 0 || ch == 1); +- memset(&fec_log[ch],0,sizeof(FEC_EVENT_LOG)); +-} +- +-/* Display the FEC log +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_log_dump(uint8_t ch) +-{ +- ASSERT(ch == 0 || ch == 1); +- printf("\n FEC%d Log\n---------------\n",ch); +- printf("Total: %4d\n",fec_log[ch].total); +- printf("hberr: %4d\n",fec_log[ch].hberr); +- printf("babr: %4d\n",fec_log[ch].babr); +- printf("babt: %4d\n",fec_log[ch].babt); +- printf("gra: %4d\n",fec_log[ch].gra); +- printf("txf: %4d\n",fec_log[ch].txf); +- printf("mii: %4d\n",fec_log[ch].mii); +- printf("lc: %4d\n",fec_log[ch].lc); +- printf("rl: %4d\n",fec_log[ch].rl); +- printf("xfun: %4d\n",fec_log[ch].xfun); +- printf("xferr: %4d\n",fec_log[ch].xferr); +- printf("rferr: %4d\n",fec_log[ch].rferr); +- printf("dtxf: %4d\n",fec_log[ch].dtxf); +- printf("drxf: %4d\n",fec_log[ch].drxf); +- printf("\nRFSW:\n"); +- printf("inv: %4d\n",fec_log[ch].rfsw_inv); +- printf("m: %4d\n",fec_log[ch].rfsw_m); +- printf("bc: %4d\n",fec_log[ch].rfsw_bc); +- printf("mc: %4d\n",fec_log[ch].rfsw_mc); +- printf("lg: %4d\n",fec_log[ch].rfsw_lg); +- printf("no: %4d\n",fec_log[ch].rfsw_no); +- printf("cr: %4d\n",fec_log[ch].rfsw_cr); +- printf("ov: %4d\n",fec_log[ch].rfsw_ov); +- printf("tr: %4d\n",fec_log[ch].rfsw_tr); +- printf("---------------\n\n"); +-} +- +-/* +- * Display some of the registers for debugging +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_debug_dump(uint8_t ch) +-{ +- printf("\n------------- FEC%d -------------\n",ch); +- printf("EIR %08x \n",MCF_FEC_EIR(ch)); +- printf("EIMR %08x \n",MCF_FEC_EIMR(ch)); +- printf("ECR %08x \n",MCF_FEC_ECR(ch)); +- printf("RCR %08x \n",MCF_FEC_RCR(ch)); +- printf("R_HASH %08x \n",MCF_FEC_R_HASH(ch)); +- printf("TCR %08x \n",MCF_FEC_TCR(ch)); +- printf("FECTFWR %08x \n",MCF_FEC_FECTFWR(ch)); +- printf("FECRFSR %08x \n",MCF_FEC_FECRFSR(ch)); +- printf("FECRFCR %08x \n",MCF_FEC_FECRFCR(ch)); +- printf("FECRLRFP %08x \n",MCF_FEC_FECRLRFP(ch)); +- printf("FECRLWFP %08x \n",MCF_FEC_FECRLWFP(ch)); +- printf("FECRFAR %08x \n",MCF_FEC_FECRFAR(ch)); +- printf("FECRFRP %08x \n",MCF_FEC_FECRFRP(ch)); +- printf("FECRFWP %08x \n",MCF_FEC_FECRFWP(ch)); +- printf("FECTFSR %08x \n",MCF_FEC_FECTFSR(ch)); +- printf("FECTFCR %08x \n",MCF_FEC_FECTFCR(ch)); +- printf("FECTLRFP %08x \n",MCF_FEC_FECTLRFP(ch)); +- printf("FECTLWFP %08x \n",MCF_FEC_FECTLWFP(ch)); +- printf("FECTFAR %08x \n",MCF_FEC_FECTFAR(ch)); +- printf("FECTFRP %08x \n",MCF_FEC_FECTFRP(ch)); +- printf("FECTFWP %08x \n",MCF_FEC_FECTFWP(ch)); +- printf("FRST %08x \n",MCF_FEC_FRST(ch)); +- printf("--------------------------------\n\n"); +-} +- +-/* +- * Set the duplex on the selected FEC controller +- * +- * Parameters: +- * ch FEC channel +- * duplex FEC_MII_FULL_DUPLEX or FEC_MII_HALF_DUPLEX +- */ +-void +-fec_duplex (uint8_t ch, uint8_t duplex) +-{ +- ASSERT(ch == 0 || ch == 1); +- +- switch (duplex) +- { +- case FEC_MII_HALF_DUPLEX: +- MCF_FEC_RCR(ch) |= MCF_FEC_RCR_DRT; +- MCF_FEC_TCR(ch) &= (uint32_t)~MCF_FEC_TCR_FDEN; +- break; +- case FEC_MII_FULL_DUPLEX: +- default: +- MCF_FEC_RCR(ch) &= (uint32_t)~MCF_FEC_RCR_DRT; +- MCF_FEC_TCR(ch) |= MCF_FEC_TCR_FDEN; +- break; +- } +-} +- +-/* +- * Generate the hash table settings for the given address +- * +- * Parameters: +- * addr 48-bit (6 byte) Address to generate the hash for +- * +- * Return Value: +- * The 6 most significant bits of the 32-bit CRC result +- */ +-uint8_t +-fec_hash_address(const uint8_t *addr) +-{ +- uint32_t crc; +- uint8_t byte; +- int i, j; +- +- crc = 0xFFFFFFFF; +- for(i=0; i<6; ++i) +- { +- byte = addr[i]; +- for(j=0; j<8; ++j) +- { +- if((byte & 0x01)^(crc & 0x01)) +- { +- crc >>= 1; +- crc = crc ^ 0xEDB88320; +- } +- else +- crc >>= 1; +- byte >>= 1; +- } +- } +- return (uint8_t)(crc >> 26); +-} +- +-/* +- * Set the Physical (Hardware) Address and the Individual Address +- * Hash in the selected FEC +- * +- * Parameters: +- * ch FEC channel +- * pa Physical (Hardware) Address for the selected FEC +- */ +-void +-fec_set_address (uint8_t ch, const uint8_t *pa) +-{ +- uint8_t crc; +- +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Set the Physical Address +- */ +- MCF_FEC_PALR(ch) = (uint32_t)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]); +- MCF_FEC_PAUR(ch) = (uint32_t)((pa[4]<<24) | (pa[5]<<16)); +- +- /* +- * Calculate and set the hash for given Physical Address +- * in the Individual Address Hash registers +- */ +- crc = fec_hash_address(pa); +- if(crc >= 32) +- MCF_FEC_IAUR(ch) |= (uint32_t)(1 << (crc - 32)); +- else +- MCF_FEC_IALR(ch) |= (uint32_t)(1 << crc); +-} +- +-/* +- * Reset the selected FEC controller +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_reset (uint8_t ch) +-{ +- int i; +- +- ASSERT(ch == 0 || ch == 1); +- +- /* Clear any events in the FIFO status registers */ +- MCF_FEC_FECRFSR(ch) = (0 +- | MCF_FEC_FECRFSR_OF +- | MCF_FEC_FECRFSR_UF +- | MCF_FEC_FECRFSR_RXW +- | MCF_FEC_FECRFSR_FAE +- | MCF_FEC_FECRFSR_IP); +- MCF_FEC_FECTFSR(ch) = (0 +- | MCF_FEC_FECRFSR_OF +- | MCF_FEC_FECRFSR_UF +- | MCF_FEC_FECRFSR_RXW +- | MCF_FEC_FECRFSR_FAE +- | MCF_FEC_FECRFSR_IP); +- +- /* Reset the FIFOs */ +- MCF_FEC_FRST(ch) |= MCF_FEC_FRST_SW_RST; +- MCF_FEC_FRST(ch) &= ~MCF_FEC_FRST_SW_RST; +- +- /* Set the Reset bit and clear the Enable bit */ +- MCF_FEC_ECR(ch) = MCF_FEC_ECR_RESET; +- +- /* Wait at least 8 clock cycles */ +- for (i=0; i<10; ++i) +- nop(); +-} +- +-/* +- * Initialize the selected FEC +- * +- * Parameters: +- * ch FEC channel +- * mode External interface mode (MII, 7-wire, or internal loopback) +- * pa Physical (Hardware) Address for the selected FEC +- */ +-void +-fec_init (uint8_t ch, uint8_t mode, const uint8_t *pa) +-{ +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Enable all the external interface signals +- */ +- if (mode == FEC_MODE_7WIRE) +- { +- if (ch == 1) +- MCF_GPIO_PAR_FECI2CIRQ |= MCF_GPIO_PAR_FECI2CIRQ_PAR_E17; +- else +- MCF_GPIO_PAR_FECI2CIRQ |= MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; +- } +- else if (mode == FEC_MODE_MII) +- { +- if (ch == 1) +- MCF_GPIO_PAR_FECI2CIRQ |= 0 +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E1MII +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E17; +- else +- MCF_GPIO_PAR_FECI2CIRQ |= 0 +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDC +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E0MII +- | MCF_GPIO_PAR_FECI2CIRQ_PAR_E07; +- } +- +- /* +- * Clear the Individual and Group Address Hash registers +- */ +- MCF_FEC_IALR(ch) = 0; +- MCF_FEC_IAUR(ch) = 0; +- MCF_FEC_GALR(ch) = 0; +- MCF_FEC_GAUR(ch) = 0; +- +- /* +- * Set the Physical Address for the selected FEC +- */ +- fec_set_address(ch, pa); +- +- /* +- * Mask all FEC interrupts +- */ +- MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL; +- +- /* +- * Clear all FEC interrupt events +- */ +- MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL; +- +- /* +- * Initialize the Receive Control Register +- */ +- MCF_FEC_RCR(ch) = 0 +- | MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) +- #ifdef FEC_PROMISCUOUS +- | MCF_FEC_RCR_PROM +- #endif +- | MCF_FEC_RCR_FCE; +- +- if (mode == FEC_MODE_MII) +- MCF_FEC_RCR(ch) |= MCF_FEC_RCR_MII_MODE; +- +- else if (mode == FEC_MODE_LOOPBACK) +- MCF_FEC_RCR(ch) |= MCF_FEC_RCR_LOOP; +- +- /* +- * Initialize the Transmit Control Register +- */ +- MCF_FEC_TCR(ch) = MCF_FEC_TCR_FDEN; +- +- /* +- * Set Rx FIFO alarm and granularity +- */ +- MCF_FEC_FECRFCR(ch) = 0 +- | MCF_FEC_FECRFCR_FRM +- | MCF_FEC_FECRFCR_RXW_MSK +- | MCF_FEC_FECRFCR_GR(7); +- MCF_FEC_FECRFAR(ch) = MCF_FEC_FECRFAR_ALARM(768); +- +- /* +- * Set Tx FIFO watermark, alarm and granularity +- */ +- MCF_FEC_FECTFCR(ch) = 0 +- | MCF_FEC_FECTFCR_FRM +- | MCF_FEC_FECTFCR_TXW_MSK +- | MCF_FEC_FECTFCR_GR(7); +- MCF_FEC_FECTFAR(ch) = MCF_FEC_FECTFAR_ALARM(256); +- MCF_FEC_FECTFWR(ch) = MCF_FEC_FECTFWR_X_WMRK_256; +- +- /* +- * Enable the transmitter to append the CRC +- */ +- MCF_FEC_CTCWR(ch) = 0 +- | MCF_FEC_CTCWR_TFCW +- | MCF_FEC_CTCWR_CRC; +-} +- +-/* +- * Start the FEC Rx DMA task +- * +- * Parameters: +- * ch FEC channel +- * rxbd First Rx buffer descriptor in the chain +- */ +-void +-fec_rx_start(uint8_t ch, int8_t *rxbd) +-{ +- uint32_t initiator; +- int channel, result; +- +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Make the initiator assignment +- */ +- result = dma_set_initiator(DMA_FEC_RX(ch)); +- ASSERT(result == 0); +- +- /* +- * Grab the initiator number +- */ +- initiator = dma_get_initiator(DMA_FEC_RX(ch)); +- +- /* +- * Determine the DMA channel running the task for the +- * selected FEC +- */ +- channel = dma_set_channel(DMA_FEC_RX(ch), +- (ch == 0) ? fec0_rx_frame : fec1_rx_frame); +- ASSERT(channel != -1); +- +- /* +- * Start the Rx DMA task +- */ +- /* +- * Start the Rx DMA task +- */ +- MCD_startDma(channel, +- (s8*)rxbd, +- 0, +- (s8*)MCF_FEC_FECRFDR_ADDR(ch), +- 0, +- RX_BUF_SZ, +- 0, +- initiator, +- FECRX_DMA_PRI(ch), +- 0 +- | MCD_FECRX_DMA +- | MCD_INTERRUPT +- | MCD_TT_FLAGS_CW +- | MCD_TT_FLAGS_RL +- | MCD_TT_FLAGS_SP +- , +- 0 +- | MCD_NO_CSUM +- | MCD_NO_BYTE_SWAP +- ); +-} +- +-/* +- * Continue the Rx DMA task +- * +- * This routine is called after the DMA task has halted after +- * encountering an Rx buffer descriptor that wasn't marked as +- * ready. There is no harm in calling the DMA continue routine +- * if the DMA is not halted. +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_rx_continue(uint8_t ch) +-{ +- int channel; +- +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Determine the DMA channel running the task for the +- * selected FEC +- */ +- channel = dma_get_channel(DMA_FEC_RX(ch)); +- ASSERT(channel != -1); +- +- /* +- * Continue/restart the DMA task +- */ +- MCD_continDma(channel); +-} +- +-/* +- * Stop all frame receptions on the selected FEC +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_rx_stop (uint8_t ch) +-{ +- uint32_t mask; +- int channel; +- +- ASSERT(ch == 0 || ch == 1); +- +- /* Save off the EIMR value */ +- mask = MCF_FEC_EIMR(ch); +- +- /* Mask all interrupts */ +- MCF_FEC_EIMR(ch) = 0; +- +- /* +- * Determine the DMA channel running the task for the +- * selected FEC +- */ +- channel = dma_get_channel(DMA_FEC_RX(ch)); +- ASSERT(channel != -1); +- +- /* Kill the FEC Rx DMA task */ +- MCD_killDma(channel); +- +- /* +- * Free up the FEC requestor from the software maintained +- * initiator list +- */ +- dma_free_initiator(DMA_FEC_RX(ch)); +- +- /* Free up the DMA channel */ +- dma_free_channel(DMA_FEC_RX(ch)); +- +- /* Restore the interrupt mask register value */ +- MCF_FEC_EIMR(ch) = mask; +-} +- +-/* +- * Receive Frame interrupt handler - this handler is called by the +- * DMA interrupt handler indicating that a packet was successfully +- * transferred out of the Rx FIFO. +- * +- * Parameters: +- * nif Pointer to Network Interface structure +- * ch FEC channel +- */ +-NBUF * +-fec_rx_frame(uint8_t ch, NIF *nif) +-{ +-// ETH_HDR *eth_hdr; +- FECBD *pRxBD; +- NBUF *cur_nbuf, *new_nbuf; +- int keep; +- +- while ((pRxBD = fecbd_rx_alloc(ch)) != NULL) +- { +- fec_log[ch].drxf++; +- keep = TRUE; +- +- /* +- * Check the Receive Frame Status Word for errors +- * - The L bit should always be set +- * - No undefined bits should be set +- * - The upper 5 bits of the length should be cleared +- */ +- if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608) +- || (pRxBD->length & 0xF800)) +- { +- keep = FALSE; +- fec_log[ch].rfsw_inv++; +- } +- else if (pRxBD->status & RX_BD_ERROR) +- { +- keep = FALSE; +- if (pRxBD->status & RX_BD_NO) +- fec_log[ch].rfsw_no++; +- if (pRxBD->status & RX_BD_CR) +- fec_log[ch].rfsw_cr++; +- if (pRxBD->status & RX_BD_OV) +- fec_log[ch].rfsw_ov++; +- if (pRxBD->status & RX_BD_TR) +- fec_log[ch].rfsw_tr++; +- } +- else +- { +- if (pRxBD->status & RX_BD_LG) +- fec_log[ch].rfsw_lg++; +- if (pRxBD->status & RX_BD_M) +- fec_log[ch].rfsw_m++; +- if (pRxBD->status & RX_BD_BC) +- fec_log[ch].rfsw_bc++; +- if (pRxBD->status & RX_BD_MC) +- fec_log[ch].rfsw_mc++; +- } +- +- if (keep) +- { +- /* +- * Pull the network buffer off the Rx ring queue +- */ +- cur_nbuf = nbuf_remove(NBUF_RX_RING); +- ASSERT(cur_nbuf); +- ASSERT(cur_nbuf->data == pRxBD->data); +- +- /* +- * Copy the buffer descriptor information to the network buffer +- */ +-// cur_nbuf->length = (pRxBD->length - (ETH_HDR_LEN + ETH_CRC_LEN)); +-// cur_nbuf->offset = ETH_HDR_LEN; +- cur_nbuf->length = (pRxBD->length - (ETH_CRC_LEN)); +- cur_nbuf->offset = 0; +- +- /* +- * Get a new buffer pointer for this buffer descriptor +- */ +- new_nbuf = nbuf_alloc(); +- if (new_nbuf == NULL) +- { +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("nbuf_alloc() failed\n"); +- #endif +- /* +- * Can't allocate a new network buffer, so we +- * have to trash the received data and reuse the buffer +- * hoping that some buffers will free up in the system +- * and this frame will be re-transmitted by the host +- */ +- pRxBD->length = RX_BUF_SZ; +- pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); +- pRxBD->status |= RX_BD_E; +- nbuf_add(NBUF_RX_RING, cur_nbuf); +- fec_rx_continue(ch); +- continue; +- } +- +- /* +- * Add the new network buffer to the Rx ring queue +- */ +- nbuf_add(NBUF_RX_RING, new_nbuf); +- +- /* +- * Re-initialize the buffer descriptor - pointing it +- * to the new data buffer. The previous data buffer +- * will be passed up the stack +- */ +- pRxBD->data = new_nbuf->data; +- pRxBD->length = RX_BUF_SZ; +- pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); +- pRxBD->status |= RX_BD_E; +- +- +- /* +- * Let the DMA know that there is a new Rx BD (in case the +- * ring was full and the DMA was waiting for an empty one) +- */ +- fec_rx_continue(ch); +- +- /* +- * Get pointer to the frame data inside the network buffer +- */ +-// eth_hdr = (ETH_HDR *)cur_nbuf->data; +- +- /* +- * Pass the received packet up the network stack if the +- * protocol is supported in our network interface (NIF) +- */ +-//FIXME if (nif_protocol_exist(nif,eth_hdr->type)) +-// { +-// nif_protocol_handler(nif, eth_hdr->type, cur_nbuf); +-// } +-// else +-// nbuf_free(cur_nbuf); +- return(cur_nbuf); +- } +- else +- { +- /* +- * This frame isn't a keeper +- * Reset the status and length, but don't need to get another +- * buffer since we are trashing the data in the current one +- */ +- pRxBD->length = RX_BUF_SZ; +- pRxBD->status &= (RX_BD_W | RX_BD_INTERRUPT); +- pRxBD->status |= RX_BD_E; +- +- /* +- * Move the current buffer from the beginning to the end of the +- * Rx ring queue +- */ +- cur_nbuf = nbuf_remove(NBUF_RX_RING); +- nbuf_add(NBUF_RX_RING, cur_nbuf); +- +- /* +- * Let the DMA know that there are new Rx BDs (in case +- * it is waiting for an empty one) +- */ +- fec_rx_continue(ch); +- } +- } +- return NULL; +-} +- +-void +-fec0_rx_frame(void) +-{ +-// extern NIF nif1; +-// fec_rx_frame(0, 0); +-} +- +-void +-fec1_rx_frame(void) +-{ +-// extern NIF nif1; +-// fec_rx_frame(1, 0); +-} +- +-/* +- * Start the FEC Tx DMA task +- * +- * Parameters: +- * ch FEC channel +- * txbd First Tx buffer descriptor in the chain +- */ +-void +-fec_tx_start(uint8_t ch, int8_t *txbd) +-{ +- uint32_t initiator; +- int channel, result; +- void fec0_tx_frame(void); +- void fec1_tx_frame(void); +- +- /* +- * Make the initiator assignment +- */ +- result = dma_set_initiator(DMA_FEC_TX(ch)); +- ASSERT(result == 0); +- +- /* +- * Grab the initiator number +- */ +- initiator = dma_get_initiator(DMA_FEC_TX(ch)); +- ASSERT(initiator != 0); +- +- /* +- * Determine the DMA channel running the task for the +- * selected FEC +- */ +- channel = dma_set_channel(DMA_FEC_TX(ch), +- (ch == 0) ? fec0_tx_frame : fec1_tx_frame); +- ASSERT(channel != -1); +- +- /* +- * Start the Tx DMA task +- */ +- MCD_startDma(channel, +- (s8*)txbd, +- 0, +- (s8*)MCF_FEC_FECTFDR_ADDR(ch), +- 0, +- ETH_MTU, +- 0, +- initiator, +- FECTX_DMA_PRI(ch), +- 0 +- | MCD_FECTX_DMA +- | MCD_INTERRUPT +- | MCD_TT_FLAGS_CW +- | MCD_TT_FLAGS_RL +- | MCD_TT_FLAGS_SP +- , +- 0 +- | MCD_NO_CSUM +- | MCD_NO_BYTE_SWAP +- ); +-} +- +-/* +- * Continue the Tx DMA task +- * +- * This routine is called after the DMA task has halted after +- * encountering an Tx buffer descriptor that wasn't marked as +- * ready. There is no harm in calling the continue DMA routine +- * if the DMA was not paused. +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_tx_continue(uint8_t ch) +-{ +- int channel; +- +- /* +- * Determine the DMA channel running the task for the +- * selected FEC +- */ +- channel = dma_get_channel(DMA_FEC_TX(ch)); +- ASSERT(channel > 0); +- +- /* +- * Continue/restart the DMA task +- */ +- MCD_continDma((int)channel); +-} +- +-/* +- * Stop all transmissions on the selected FEC and kill the DMA task +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_tx_stop (uint8_t ch) +-{ +- uint32_t mask; +- int channel; +- +- ASSERT(ch == 0 || ch == 1); +- +- /* Save off the EIMR value */ +- mask = MCF_FEC_EIMR(ch); +- +- /* Mask all interrupts */ +- MCF_FEC_EIMR(ch) = 0; +- +- /* If the Ethernet is still enabled... */ +- if (MCF_FEC_ECR(ch) & MCF_FEC_ECR_ETHER_EN) +- { +- /* Issue the Graceful Transmit Stop */ +- MCF_FEC_TCR(ch) |= MCF_FEC_TCR_GTS; +- +- /* Wait for the Graceful Stop Complete interrupt */ +- while(!(MCF_FEC_EIR(ch) & MCF_FEC_EIR_GRA)) +- { +- if (!(MCF_FEC_ECR(ch) & MCF_FEC_ECR_ETHER_EN)) +- break; +- } +- +- /* Clear the Graceful Stop Complete interrupt */ +- MCF_FEC_EIR(ch) = MCF_FEC_EIR_GRA; +- } +- +- /* +- * Determine the DMA channel running the task for the +- * selected FEC +- */ +- channel = dma_get_channel(DMA_FEC_TX(ch)); +- ASSERT(channel > 0); +- +- /* Kill the FEC Tx DMA task */ +- MCD_killDma(channel); +- +- /* +- * Free up the FEC requestor from the software maintained +- * initiator list +- */ +- dma_free_initiator(DMA_FEC_TX(ch)); +- +- /* Free up the DMA channel */ +- dma_free_channel(DMA_FEC_TX(ch)); +- +- /* Restore the interrupt mask register value */ +- MCF_FEC_EIMR(ch) = mask; +-} +- +-/* +- * Trasmit Frame interrupt handler - this handler is called by the +- * DMA interrupt handler indicating that a packet was successfully +- * transferred to the Tx FIFO. +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_tx_frame(uint8_t ch) +-{ +- FECBD *pTxBD; +- NBUF *pNbuf; +- +- while ((pTxBD = fecbd_tx_free(ch)) != NULL) +- { +- fec_log[ch].dtxf++; +- +- /* +- * Grab the network buffer associated with this buffer descriptor +- */ +- pNbuf = nbuf_remove(NBUF_TX_RING); +- ASSERT(pNbuf); +- ASSERT(pNbuf->data == pTxBD->data); +- +- /* +- * Free up the network buffer that was just transmitted +- */ +- nbuf_free(pNbuf); +- +- /* +- * Re-initialize the Tx BD +- */ +- pTxBD->data = NULL; +- pTxBD->length = 0; +- } +-} +- +-void +-fec0_tx_frame(void) +-{ +- fec_tx_frame(0); +-} +- +-void +-fec1_tx_frame(void) +-{ +- fec_tx_frame(1); +-} +- +-/* +- * Send a packet out the selected FEC +- * +- * Parameters: +- * ch FEC channel +- * nif Pointer to Network Interface (NIF) structure +- * dst Destination MAC Address +- * src Source MAC Address +- * type Ethernet Frame Type +- * length Number of bytes to be transmitted (doesn't include type, +- * src, or dest byte count) +- * pkt Pointer packet network buffer +- * +- * Return Value: +- * 1 success +- * 0 otherwise +- */ +-int +-fec_send (uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +-{ +- FECBD *pTxBD; +- ASSERT(ch == 0 || ch == 1); +- +- /* Check the length */ +- if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU) +- return 0; +- +- /* +- * Copy the destination address, source address, and Ethernet +- * type into the packet +- */ +-// memcpy(&nbuf->data[0], dst, 6); +-// memcpy(&nbuf->data[6], src, 6); +-// memcpy(&nbuf->data[12], &type, 2); +- +- /* +- * Grab the next available Tx Buffer Descriptor +- */ +- while ((pTxBD = fecbd_tx_alloc(ch)) == NULL) {}; +- +- /* +- * Put the network buffer into the Tx waiting queue +- */ +- nbuf_add(NBUF_TX_RING, nbuf); +- +- /* +- * Setup the buffer descriptor for transmission +- */ +- pTxBD->data = nbuf->data; +- pTxBD->length = nbuf->length; // + ETH_HDR_LEN; +- pTxBD->status |= (TX_BD_R | TX_BD_L); +- +- /* +- * Continue the Tx DMA task (in case it was waiting for a new +- * TxBD to be ready +- */ +- fec_tx_continue(ch); +- +- return 1; +-} +- +-int +-fec0_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +-{ +- return fec_send(0, nif, dst, src, type, nbuf); +-} +- +-int +-fec1_send(NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NBUF *nbuf) +-{ +- return fec_send(1, nif, dst, src, type, nbuf); +-} +- +-/* +- * Enable interrupts on the selected FEC +- * +- * Parameters: +- * ch FEC channel +- * pri Interrupt Priority +- * lvl Interrupt Level +- */ +-void +-fec_irq_enable(uint8_t ch, uint8_t lvl, uint8_t pri) +-{ +- ASSERT(ch == 0 || ch == 1); +- ASSERT(lvl > 0 && lvl < 8); +- ASSERT(pri < 8); +- +- /* +- * Setup the appropriate ICR +- */ +- MCF_INTC_ICRn((ch == 0) ? 39 : 38) = (uint8_t)(0 +- | MCF_INTC_ICRn_IP(pri) +- | MCF_INTC_ICRn_IL(lvl)); +- +- /* +- * Clear any pending FEC interrupt events +- */ +- MCF_FEC_EIR(ch) = MCF_FEC_EIR_CLEAR_ALL; +- +- /* +- * Unmask all FEC interrupts +- */ +- MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_UNMASK_ALL; +- +- /* +- * Unmask the FEC interrupt in the interrupt controller +- */ +- if (ch == 0) +- MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK39; +- else +- MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK38; +-} +- +-/* +- * Disable interrupts on the selected FEC +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_irq_disable(uint8_t ch) +-{ +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Mask all FEC interrupts +- */ +- MCF_FEC_EIMR(ch) = MCF_FEC_EIMR_MASK_ALL; +- +- /* +- * Mask the FEC interrupt in the interrupt controller +- */ +- if (ch == 0) +- MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK39; +- else +- MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK38; +-} +- +-/* +- * FEC interrupt handler +- * All interrupts are multiplexed into a single vector for each +- * FEC module. The lower level interrupt handler passes in the +- * channel to this handler. Note that the receive interrupt is +- * generated by the Multi-channel DMA FEC Rx task. +- * +- * Parameters: +- * ch FEC channel +- */ +-static void +-fec_irq_handler(uint8_t ch) +-{ +- uint32_t event, eir; +- +- /* +- * Determine which interrupt(s) asserted by AND'ing the +- * pending interrupts with those that aren't masked. +- */ +- eir = MCF_FEC_EIR(ch); +- event = eir & MCF_FEC_EIMR(ch); +- +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- if (event != eir) +- printf("Pending but not enabled: 0x%08X\n",(event ^ eir)); +- #endif +- +- /* +- * Clear the event(s) in the EIR immediately +- */ +- MCF_FEC_EIR(ch) = event; +- +- if (event & MCF_FEC_EIR_RFERR) +- { +- fec_log[ch].total++; +- fec_log[ch].rferr++; +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("RFERR\n"); +- printf("FECRFSR%d = 0x%08x\n",ch,MCF_FEC_FECRFSR(ch)); +- fec_eth_stop(ch); +- #endif +- } +- if (event & MCF_FEC_EIR_XFERR) +- { +- fec_log[ch].total++; +- fec_log[ch].xferr++; +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("XFERR\n"); +- #endif +- } +- if (event & MCF_FEC_EIR_XFUN) +- { +- fec_log[ch].total++; +- fec_log[ch].xfun++; +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("XFUN\n"); +- fec_eth_stop(ch); +- #endif +- } +- if (event & MCF_FEC_EIR_RL) +- { +- fec_log[ch].total++; +- fec_log[ch].rl++; +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("RL\n"); +- #endif +- } +- if (event & MCF_FEC_EIR_LC) +- { +- fec_log[ch].total++; +- fec_log[ch].lc++; +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("LC\n"); +- #endif +- } +- if (event & MCF_FEC_EIR_MII) +- { +- fec_log[ch].mii++; +- } +- if (event & MCF_FEC_EIR_TXF) +- { +- fec_log[ch].txf++; +- } +- if (event & MCF_FEC_EIR_GRA) +- { +- fec_log[ch].gra++; +- } +- if (event & MCF_FEC_EIR_BABT) +- { +- fec_log[ch].total++; +- fec_log[ch].babt++; +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("BABT\n"); +- #endif +- } +- if (event & MCF_FEC_EIR_BABR) +- { +- fec_log[ch].total++; +- fec_log[ch].babr++; +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("BABR\n"); +- #endif +- } +- if (event & MCF_FEC_EIR_HBERR) +- { +- fec_log[ch].total++; +- fec_log[ch].hberr++; +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("HBERR\n"); +- #endif +- } +-} +- +-int +-fec0_interrupt_handler(void* arg1, void* arg2) +-{ +- (void) arg1; +- (void) arg2; +- fec_irq_handler(0); +- return 1; +-} +- +-int +-fec1_interrupt_handler(void* arg1, void* arg2) +-{ +- (void) arg1; +- (void) arg2; +- fec_irq_handler(1); +- return 1; +-} +- +-/* +- * Configure the selected Ethernet port and enable all operations +- * +- * Parameters: +- * ch FEC channel +- * trcvr Transceiver mode (MII, 7-Wire or internal loopback) +- * speed Maximum operating speed (MII only) +- * duplex Full or Half-duplex (MII only) +- * mac Physical (MAC) Address +- */ +-void +-fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, const uint8_t *mac) +-{ +- ASSERT(ch == 0 || ch == 1); +- +- /* +- * Disable FEC interrupts +- */ +- fec_irq_disable(ch); +- +- /* +- * Initialize the event log +- */ +- fec_log_init(ch); +- +- /* +- * Initialize the network buffers and fec buffer descriptors +- */ +- nbuf_init(); +- fecbd_init(ch); +- +- /* +- * Initialize the FEC +- */ +- fec_reset(ch); +- fec_init(ch,trcvr,mac); +- +- if (trcvr == FEC_MODE_MII) +- { +- /* +- * Initialize the MII interface +- */ +- fec_mii_init(ch, CFG_SYSTEM_CORE_CLOCK); +- } +- +- /* +- * Initialize and enable FEC interrupts +- */ +- fec_irq_enable(ch, FEC_INTC_LVL(ch), FEC_INTC_PRI(ch)); +- +- /* +- * Enable the multi-channel DMA tasks +- */ +- fec_rx_start(ch, (int8_t*)fecbd_get_start(ch,Rx)); +- fec_tx_start(ch, (int8_t*)fecbd_get_start(ch,Tx)); +- +- /* +- * Enable the FEC channel +- */ +- MCF_FEC_ECR(ch) |= MCF_FEC_ECR_ETHER_EN; +-} +-/* +- * Reset the selected Ethernet port +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_eth_reset(uint8_t ch) +-{ +-// To do +-} +- +-/* +- * Stop the selected Ethernet port +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fec_eth_stop(uint8_t ch) +-{ +- int level; +- +- /* +- * Disable interrupts +- */ +- level = asm_set_ipl(7); +- +- /* +- * Gracefully disable the receiver and transmitter +- */ +- fec_tx_stop(ch); +- fec_rx_stop(ch); +- +- /* +- * Disable FEC interrupts +- */ +- fec_irq_disable(ch); +- +- /* +- * Disable the FEC channel +- */ +- MCF_FEC_ECR(ch) &= ~MCF_FEC_ECR_ETHER_EN; +- +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- nbuf_debug_dump(); +- fec_log_dump(ch); +- #endif +- +- /* +- * Flush the network buffers +- */ +- nbuf_flush(); +- +- /* +- * Restore interrupt level +- */ +- asm_set_ipl(level); +-} +diff --git a/arch/m68k/mach-mcfv4e/fecbd.c b/arch/m68k/mach-mcfv4e/fecbd.c +deleted file mode 100644 +index a8e732b..0000000 +--- a/arch/m68k/mach-mcfv4e/fecbd.c ++++ /dev/null +@@ -1,232 +0,0 @@ +-/* +- * File: fecbd.c +- * Purpose: Provide a simple buffer management driver +- * +- * Notes: +- */ +-#include <common.h> +-#include <linux/types.h> +- +-#include <mach/mcf54xx-regs.h> +-#include <proc/mcdapi/MCD_dma.h> +-#include <proc/net/net.h> +-#include <proc/fecbd.h> +-#include <proc/fec.h> +-#include <proc/dma_utils.h> +- +-#define ASSERT(x) if (!(x)) hang(); +- +-/* +- * This implements a simple static buffer descriptor +- * ring for each channel and each direction +- * +- * FEC Buffer Descriptors need to be aligned to a 4-byte boundary. +- * In order to accomplish this, data is over-allocated and manually +- * aligned at runtime +- * +- * Enough space is allocated for each of the two FEC channels to have +- * NRXBD Rx BDs and NTXBD Tx BDs +- * +- */ +-FECBD unaligned_bds[(2 * NRXBD) + (2 * NTXBD) + 1]; +- +-/* +- * These pointers are used to reference into the chunck of data set +- * aside for buffer descriptors +- */ +-FECBD *RxBD; +-FECBD *TxBD; +- +-/* +- * Macros to easier access to the BD ring +- */ +-#define RxBD(ch,i) RxBD[(ch * NRXBD) + i] +-#define TxBD(ch,i) TxBD[(ch * NTXBD) + i] +- +-/* +- * Buffer descriptor indexes +- */ +-static int iTxbd_new; +-static int iTxbd_old; +-static int iRxbd; +- +-/* +- * Initialize the FEC Buffer Descriptor ring +- * Buffer Descriptor format is defined by the MCDAPI +- * +- * Parameters: +- * ch FEC channel +- */ +-void +-fecbd_init(uint8_t ch) +-{ +- NBUF *nbuf; +- int i; +- +- /* +- * Align Buffer Descriptors to 4-byte boundary +- */ +- RxBD = (FECBD *)(((int)unaligned_bds + 3) & 0xFFFFFFFC); +- TxBD = (FECBD *)((int)RxBD + (sizeof(FECBD) * 2 * NRXBD)); +- +- /* +- * Initialize the Rx Buffer Descriptor ring +- */ +- for (i = 0; i < NRXBD; ++i) +- { +- /* Grab a network buffer from the free list */ +- nbuf = nbuf_alloc(); +- ASSERT(nbuf); +- +- /* Initialize the BD */ +- RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT; +- RxBD(ch,i).length = RX_BUF_SZ; +- RxBD(ch,i).data = nbuf->data; +- +- /* Add the network buffer to the Rx queue */ +- nbuf_add(NBUF_RX_RING, nbuf); +- } +- +- /* +- * Set the WRAP bit on the last one +- */ +- RxBD(ch,i-1).status |= RX_BD_W; +- +- /* +- * Initialize the Tx Buffer Descriptor ring +- */ +- for (i = 0; i < NTXBD; ++i) +- { +- TxBD(ch,i).status = TX_BD_INTERRUPT; +- TxBD(ch,i).length = 0; +- TxBD(ch,i).data = NULL; +- } +- +- /* +- * Set the WRAP bit on the last one +- */ +- TxBD(ch,i-1).status |= TX_BD_W; +- +- /* +- * Initialize the buffer descriptor indexes +- */ +- iTxbd_new = iTxbd_old = iRxbd = 0; +-} +- +-void +-fecbd_dump(uint8_t ch) +-{ +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- int i; +- +- printf("\n------------ FEC%d BDs -----------\n",ch); +- printf("RxBD Ring\n"); +- for (i=0; i<NRXBD; i++) +- { +- printf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n", +- i, &RxBD(ch,i), +- RxBD(ch,i).status, +- RxBD(ch,i).length, +- RxBD(ch,i).data); +- } +- printf("TxBD Ring\n"); +- for (i=0; i<NTXBD; i++) +- { +- printf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n", +- i, &TxBD(ch,i), +- TxBD(ch,i).status, +- TxBD(ch,i).length, +- TxBD(ch,i).data); +- } +- printf("--------------------------------\n\n"); +- #endif +-} +- +-/* +- * Return the address of the first buffer descriptor in the ring. +- * +- * Parameters: +- * ch FEC channel +- * direction Rx or Tx Macro +- * +- * Return Value: +- * The start address of the selected Buffer Descriptor ring +- */ +-uint32_t +-fecbd_get_start(uint8_t ch, uint8_t direction) +-{ +- switch (direction) +- { +- case Rx: +- return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD)); +- case Tx: +- default: +- return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD)); +- } +-} +- +-FECBD * +-fecbd_rx_alloc(uint8_t ch) +-{ +- int i = iRxbd; +- +- /* Check to see if the ring of BDs is full */ +- if (RxBD(ch,i).status & RX_BD_E) +- return NULL; +- +- /* Increment the circular index */ +- iRxbd = (uint8_t)((iRxbd + 1) % NRXBD); +- +- return &RxBD(ch,i); +-} +- +-/* +- * This function keeps track of the next available Tx BD in the ring +- * +- * Parameters: +- * ch FEC channel +- * +- * Return Value: +- * Pointer to next available buffer descriptor. +- * NULL if the BD ring is full +- */ +-FECBD * +-fecbd_tx_alloc(uint8_t ch) +-{ +- int i = iTxbd_new; +- +- /* Check to see if the ring of BDs is full */ +- if (TxBD(ch,i).status & TX_BD_R) +- return NULL; +- +- /* Increment the circular index */ +- iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD); +- +- return &TxBD(ch,i); +-} +- +-/* +- * This function keeps track of the Tx BDs that have already been +- * processed by the FEC +- * +- * Parameters: +- * ch FEC channel +- * +- * Return Value: +- * Pointer to the oldest buffer descriptor that has already been sent +- * by the FEC, NULL if the BD ring is empty +- */ +-FECBD * +-fecbd_tx_free(uint8_t ch) +-{ +- int i = iTxbd_old; +- +- /* Check to see if the ring of BDs is empty */ +- if ((TxBD(ch,i).data == NULL) || (TxBD(ch,i).status & TX_BD_R)) +- return NULL; +- +- /* Increment the circular index */ +- iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD); +- +- return &TxBD(ch,i); +-} +diff --git a/arch/m68k/mach-mcfv4e/include/mach/clocks.h b/arch/m68k/mach-mcfv4e/include/mach/clocks.h +deleted file mode 100644 +index daedb7a..0000000 +--- a/arch/m68k/mach-mcfv4e/include/mach/clocks.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * This File contains functions to query clock settings for the actual +- * board. +- */ +-#ifndef __ASM_ARCH_CLOCKS_H +-#define __ASM_ARCH_CLOCKS_H +- +-ulong mcfv4e_get_bus_clk(void); +- +-#endif /* __ASM_ARCH_CLOCKS_H */ +diff --git a/arch/m68k/mach-mcfv4e/include/mach/debug_ll.h b/arch/m68k/mach-mcfv4e/include/mach/debug_ll.h +deleted file mode 100644 +index c58be70..0000000 +--- a/arch/m68k/mach-mcfv4e/include/mach/debug_ll.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * This File contains declaration for early output support +- */ +-#ifndef __INCLUDE_ARCH_DEBUG_LL_H__ +-#define __INCLUDE_ARCH_DEBUG_LL_H__ +- +-extern __inline__ void putc( char ch ) +-{ +- //extern int early_console_putc( char ch); +- early_console_putc(NULL,ch); +-} +- +-#endif /* __INCLUDE_ARCH_DEBUG_LL_H__ */ +diff --git a/arch/m68k/mach-mcfv4e/include/mach/hardware.h b/arch/m68k/mach-mcfv4e/include/mach/hardware.h +deleted file mode 100644 +index 118afa6..0000000 +--- a/arch/m68k/mach-mcfv4e/include/mach/hardware.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * This File contains declaration for early output support +- */ +-#ifndef __ASM_ARCH_HARDWARE_H__ +-#define __ASM_ARCH_HARDWARE_H__ +- +-#include <sizes.h> +- +-#ifdef CONFIG_ARCH_MCF54xx +-#include "mcf54xx-regs.h" +-#endif +- +-#endif /* __ASM_ARCH_HARDWARE_H__ */ +diff --git a/arch/m68k/mach-mcfv4e/include/mach/mcf54xx-regs.h b/arch/m68k/mach-mcfv4e/include/mach/mcf54xx-regs.h +deleted file mode 100644 +index 8dd5ed2..0000000 +--- a/arch/m68k/mach-mcfv4e/include/mach/mcf54xx-regs.h ++++ /dev/null +@@ -1,30 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * This File contains declaration for early output support +- */ +-#ifndef __MCF54xx_REGS_H__ +-#define __MCF54xx_REGS_H__ +- +-/* System Registers for V4E cores (MCF547x and MCF548x) */ +-#include <asm/coldfire/mcf5xxx.h> +- +-#endif /* __MCF54xx_REGS_H__ */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/dma_utils.h b/arch/m68k/mach-mcfv4e/include/proc/dma_utils.h +deleted file mode 100644 +index 1cb2782..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/dma_utils.h ++++ /dev/null +@@ -1,80 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Declaration of support function used with the MultiChannel DMA +- */ +-#ifndef _DMA_UTILS_H_ +-#define _DMA_UTILS_H_ +- +- +-void dma_irq_enable(uint8_t, uint8_t); +-void dma_irq_disable(void); +-int dma_set_initiator(int); +-uint32_t dma_get_initiator(int); +-void dma_free_initiator(int); +-int dma_set_channel(int, void (*)(void)); +-int dma_get_channel(int); +-void dma_free_channel(int); +-int dma_interrupt_handler(void *, void *); +- +-/* +- * Create identifiers for each initiator/requestor +- */ +-#define DMA_ALWAYS (0) +-#define DMA_DSPI_RX (1) +-#define DMA_DSPI_TX (2) +-#define DMA_DREQ0 (3) +-#define DMA_PSC0_RX (4) +-#define DMA_PSC0_TX (5) +-#define DMA_USBEP0 (6) +-#define DMA_USBEP1 (7) +-#define DMA_USBEP2 (8) +-#define DMA_USBEP3 (9) +-#define DMA_PCI_TX (10) +-#define DMA_PCI_RX (11) +-#define DMA_PSC1_RX (12) +-#define DMA_PSC1_TX (13) +-#define DMA_I2C_RX (14) +-#define DMA_I2C_TX (15) +-#define DMA_FEC0_RX (16) +-#define DMA_FEC0_TX (17) +-#define DMA_FEC1_RX (18) +-#define DMA_FEC1_TX (19) +-#define DMA_DREQ1 (20) +-#define DMA_CTM0 (21) +-#define DMA_CTM1 (22) +-#define DMA_CTM2 (23) +-#define DMA_CTM3 (24) +-#define DMA_CTM4 (25) +-#define DMA_CTM5 (26) +-#define DMA_CTM6 (27) +-#define DMA_CTM7 (28) +-#define DMA_USBEP4 (29) +-#define DMA_USBEP5 (30) +-#define DMA_USBEP6 (31) +-#define DMA_PSC2_RX (32) +-#define DMA_PSC2_TX (33) +-#define DMA_PSC3_RX (34) +-#define DMA_PSC3_TX (35) +-#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX) +-#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX) +- +-#endif /* _DMA_UTILS_H_ */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/fec.h b/arch/m68k/mach-mcfv4e/include/proc/fec.h +deleted file mode 100644 +index 16bfaa6..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/fec.h ++++ /dev/null +@@ -1,130 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Declaration for the Fast Ethernet Controller (FEC) +- */ +-#ifndef _FEC_H_ +-#define _FEC_H_ +- +-// FIXME +-#define NIF void +- +-/********************************************************************/ +-/* MII Speed Settings */ +-#define FEC_MII_10BASE_T 0 +-#define FEC_MII_100BASE_TX 1 +- +-/* MII Duplex Settings */ +-#define FEC_MII_HALF_DUPLEX 0 +-#define FEC_MII_FULL_DUPLEX 1 +- +-/* Timeout for MII communications */ +-#define FEC_MII_TIMEOUT 0x10000 +- +-/* External Interface Modes */ +-#define FEC_MODE_7WIRE 0 +-#define FEC_MODE_MII 1 +-#define FEC_MODE_LOOPBACK 2 /* Internal Loopback */ +- +-/* +- * FEC Event Log +- */ +-typedef struct { +- int total; /* total count of errors */ +- int hberr; /* heartbeat error */ +- int babr; /* babbling receiver */ +- int babt; /* babbling transmitter */ +- int gra; /* graceful stop complete */ +- int txf; /* transmit frame */ +- int mii; /* MII */ +- int lc; /* late collision */ +- int rl; /* collision retry limit */ +- int xfun; /* transmit FIFO underrrun */ +- int xferr; /* transmit FIFO error */ +- int rferr; /* receive FIFO error */ +- int dtxf; /* DMA transmit frame */ +- int drxf; /* DMA receive frame */ +- int rfsw_inv; /* Invalid bit in RFSW */ +- int rfsw_l; /* RFSW Last in Frame */ +- int rfsw_m; /* RFSW Miss */ +- int rfsw_bc; /* RFSW Broadcast */ +- int rfsw_mc; /* RFSW Multicast */ +- int rfsw_lg; /* RFSW Length Violation */ +- int rfsw_no; /* RFSW Non-octet */ +- int rfsw_cr; /* RFSW Bad CRC */ +- int rfsw_ov; /* RFSW Overflow */ +- int rfsw_tr; /* RFSW Truncated */ +-} FEC_EVENT_LOG; +- +- +-int fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t ); +-int fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *x); +-void fec_mii_init(uint8_t, uint32_t); +- +-void fec_mib_init(uint8_t); +-void fec_mib_dump(uint8_t); +- +-void fec_log_init(uint8_t); +-void fec_log_dump(uint8_t); +- +-void fec_debug_dump(uint8_t); +-void fec_duplex (uint8_t, uint8_t); +- +-uint8_t fec_hash_address(const uint8_t *); +-void fec_set_address (uint8_t ch, const uint8_t *); +- +-void fec_reset (uint8_t); +-void fec_init (uint8_t, uint8_t, const uint8_t *); +- +-void fec_rx_start(uint8_t, int8_t *); +-void fec_rx_restart(uint8_t); +-void fec_rx_stop (uint8_t); +- +-NBUF * fec_rx_frame(uint8_t ch, NIF *nif); +- +-void fec0_rx_frame(void); +-void fec1_rx_frame(void); +- +-void fec_tx_start(uint8_t, int8_t *); +-void fec_tx_restart(uint8_t); +-void fec_tx_stop (uint8_t); +- +-void fec0_tx_frame(void); +-void fec1_tx_frame(void); +- +-int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); +-int fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); +-int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *); +- +-void fec_irq_enable(uint8_t, uint8_t, uint8_t); +-void fec_irq_disable(uint8_t); +- +-void fec_interrupt_handler(uint8_t); +-int fec0_interrupt_handler(void *, void *); +-int fec1_interrupt_handler(void *, void *); +- +-void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *); +- +-void fec_eth_reset(uint8_t); +- +-void fec_eth_stop(uint8_t); +- +-#endif /* _FEC_H_ */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/fecbd.h b/arch/m68k/mach-mcfv4e/include/proc/fecbd.h +deleted file mode 100644 +index d7551c6..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/fecbd.h ++++ /dev/null +@@ -1,115 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Provide a simple buffer management driver +- */ +- +-#ifndef _FECBD_H_ +-#define _FECBD_H_ +- +-/********************************************************************/ +- +-#define Rx 1 +-#define Tx 0 +- +-/* +- * Buffer sizes in bytes +- */ +-#ifndef RX_BUF_SZ +-#define RX_BUF_SZ NBUF_SZ +-#endif +-#ifndef TX_BUF_SZ +-#define TX_BUF_SZ NBUF_SZ +-#endif +- +-/* +- * Number of Rx and Tx Buffers and Buffer Descriptors +- */ +-#ifndef NRXBD +-#define NRXBD 10 +-#endif +-#ifndef NTXBD +-#define NTXBD 4 +-#endif +- +-/* +- * Buffer Descriptor Format +- */ +-typedef struct +-{ +- uint16_t status; /* control and status */ +- uint16_t length; /* transfer length */ +- uint8_t *data; /* buffer address */ +-} FECBD; +- +-/* +- * Bit level definitions for status field of buffer descriptors +- */ +-#define TX_BD_R 0x8000 +-#define TX_BD_TO1 0x4000 +-#define TX_BD_W 0x2000 +-#define TX_BD_TO2 0x1000 +-#define TX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */ +-#define TX_BD_L 0x0800 +-#define TX_BD_TC 0x0400 +-#define TX_BD_DEF 0x0200 /* MCF5272 Only */ +-#define TX_BD_ABC 0x0200 +-#define TX_BD_HB 0x0100 /* MCF5272 Only */ +-#define TX_BD_LC 0x0080 /* MCF5272 Only */ +-#define TX_BD_RL 0x0040 /* MCF5272 Only */ +-#define TX_BD_UN 0x0002 /* MCF5272 Only */ +-#define TX_BD_CSL 0x0001 /* MCF5272 Only */ +- +-#define RX_BD_E 0x8000 +-#define RX_BD_R01 0x4000 +-#define RX_BD_W 0x2000 +-#define RX_BD_R02 0x1000 +-#define RX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */ +-#define RX_BD_L 0x0800 +-#define RX_BD_M 0x0100 +-#define RX_BD_BC 0x0080 +-#define RX_BD_MC 0x0040 +-#define RX_BD_LG 0x0020 +-#define RX_BD_NO 0x0010 +-#define RX_BD_CR 0x0004 +-#define RX_BD_OV 0x0002 +-#define RX_BD_TR 0x0001 +-#define RX_BD_ERROR (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR) +- +-/* +- * Functions provided in fec_bd.c +- */ +-void +-fecbd_init(uint8_t); +- +-uint32_t +-fecbd_get_start(uint8_t, uint8_t); +- +-FECBD * +-fecbd_rx_alloc(uint8_t); +- +-FECBD * +-fecbd_tx_alloc(uint8_t); +- +-FECBD * +-fecbd_tx_free(uint8_t); +- +-#endif /* _FECBD_H_ */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_dma.h b/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_dma.h +deleted file mode 100644 +index ad7f139..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_dma.h ++++ /dev/null +@@ -1,379 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Main header file for multi-channel DMA API. +- */ +-#ifndef _MCD_API_H +-#define _MCD_API_H +- +-/* +- * Turn Execution Unit tasks ON (#define) or OFF (#undef) +- */ +-#undef MCD_INCLUDE_EU +- +-/* +- * Number of DMA channels +- */ +-#define NCHANNELS 16 +- +-/* +- * Total number of variants +- */ +-#ifdef MCD_INCLUDE_EU +-#define NUMOFVARIANTS 6 +-#else +-#define NUMOFVARIANTS 4 +-#endif +- +-/* +- * Define sizes of the various tables +- */ +-#define TASK_TABLE_SIZE (NCHANNELS*32) +-#define VAR_TAB_SIZE (128) +-#define CONTEXT_SAVE_SIZE (128) +-#define FUNCDESC_TAB_SIZE (256) +- +-#ifdef MCD_INCLUDE_EU +-#define FUNCDESC_TAB_NUM 16 +-#else +-#define FUNCDESC_TAB_NUM 1 +-#endif +- +- +-#ifndef DEFINESONLY +- +-/* +- * Portability typedefs +- */ +-//typedef signed int s32; +-//typedef unsigned int u32; +-//typedef signed short s16; +-//typedef unsigned short u16; +-//typedef signed char s8; +-//typedef unsigned char u8; +-// +-/* +- * These structures represent the internal registers of the +- * multi-channel DMA +- */ +-struct dmaRegs_s { +- u32 taskbar; /* task table base address register */ +- u32 currPtr; +- u32 endPtr; +- u32 varTablePtr; +- u16 dma_rsvd0; +- u16 ptdControl; /* ptd control */ +- u32 intPending; /* interrupt pending register */ +- u32 intMask; /* interrupt mask register */ +- u16 taskControl[16]; /* task control registers */ +- u8 priority[32]; /* priority registers */ +- u32 initiatorMux; /* initiator mux control */ +- u32 taskSize0; /* task size control register 0. */ +- u32 taskSize1; /* task size control register 1. */ +- u32 dma_rsvd1; /* reserved */ +- u32 dma_rsvd2; /* reserved */ +- u32 debugComp1; /* debug comparator 1 */ +- u32 debugComp2; /* debug comparator 2 */ +- u32 debugControl; /* debug control */ +- u32 debugStatus; /* debug status */ +- u32 ptdDebug; /* priority task decode debug */ +- u32 dma_rsvd3[31]; /* reserved */ +-}; +-typedef volatile struct dmaRegs_s dmaRegs; +- +-#endif +- +-/* +- * PTD contrl reg bits +- */ +-#define PTD_CTL_TSK_PRI 0x8000 +-#define PTD_CTL_COMM_PREFETCH 0x0001 +- +-/* +- * Task Control reg bits and field masks +- */ +-#define TASK_CTL_EN 0x8000 +-#define TASK_CTL_VALID 0x4000 +-#define TASK_CTL_ALWAYS 0x2000 +-#define TASK_CTL_INIT_MASK 0x1f00 +-#define TASK_CTL_ASTRT 0x0080 +-#define TASK_CTL_HIPRITSKEN 0x0040 +-#define TASK_CTL_HLDINITNUM 0x0020 +-#define TASK_CTL_ASTSKNUM_MASK 0x000f +- +-/* +- * Priority reg bits and field masks +- */ +-#define PRIORITY_HLD 0x80 +-#define PRIORITY_PRI_MASK 0x07 +- +-/* +- * Debug Control reg bits and field masks +- */ +-#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 +-#define DBG_CTL_AUTO_ARM 0x00008000 +-#define DBG_CTL_BREAK 0x00004000 +-#define DBG_CTL_COMP1_TYP_MASK 0x00003800 +-#define DBG_CTL_COMP2_TYP_MASK 0x00000070 +-#define DBG_CTL_EXT_BREAK 0x00000004 +-#define DBG_CTL_INT_BREAK 0x00000002 +- +-/* +- * PTD Debug reg selector addresses +- * This reg must be written with a value to show the contents of +- * one of the desired internal register. +- */ +-#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ +-#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and +- have initiators asserted */ +- +- +-/* +- * General return values +- */ +-#define MCD_OK 0 +-#define MCD_ERROR -1 +-#define MCD_TABLE_UNALIGNED -2 +-#define MCD_CHANNEL_INVALID -3 +- +-/* +- * MCD_initDma input flags +- */ +-#define MCD_RELOC_TASKS 0x00000001 +-#define MCD_NO_RELOC_TASKS 0x00000000 +-#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */ +- +-/* +- * MCD_dmaStatus Status Values for each channel +- */ +-#define MCD_NO_DMA 1 /* No DMA has been requested since reset */ +-#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */ +-#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */ +-#define MCD_PAUSED 4 /* DMA active but it is currently paused */ +-#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */ +-#define MCD_DONE 6 /* the most recent DMA has completed. */ +- +- +-/* +- * MCD_startDma parameter defines +- */ +- +-/* +- * Constants for the funcDesc parameter +- */ +-/* Byte swapping: */ +-#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */ +-#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */ +-#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of +- each 32-bit data value being DMAed.*/ +-#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each +- 16-bit half of each 32-bit data value DMAed */ +-#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */ +-#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */ +-/* CRCing: */ +-#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */ +-#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */ +-#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */ +-#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/ +-#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */ +- +-#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM) +-#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) +- +-/* +- * Constants for the flags parameter +- */ +-#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ +-#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ +-#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */ +-#define MCD_TT_FLAGS_MASK 0x000000ff +-#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) +- +-#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ +-#define MCD_CHAIN_DMA /* TBD */ +-#define MCD_EU_DMA /* TBD */ +-#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ +-#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ +- +- +-/* these flags are valid for MCD_startDma and the chained buffer descriptors */ +-#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */ +-#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */ +-#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */ +-#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring +- last byte of data in buffer */ +-#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum +- prior to performing the DMA. */ +- +-/* Defines for the FEC buffer descriptor control/status word*/ +-#define MCD_FEC_BUF_READY 0x8000 +-#define MCD_FEC_WRAP 0x2000 +-#define MCD_FEC_INTERRUPT 0x1000 +-#define MCD_FEC_END_FRAME 0x0800 +- +- +-/* +- * Defines for general intuitiveness +- */ +- +-#define MCD_TRUE 1 +-#define MCD_FALSE 0 +- +-/* +- * Three different cases for destination and source. +- */ +-#define MINUS1 -1 +-#define ZERO 0 +-#define PLUS1 1 +- +-#ifndef DEFINESONLY +- +-/* Task Table Entry struct*/ +-typedef struct { +- u32 TDTstart; /* task descriptor table start */ +- u32 TDTend; /* task descriptor table end */ +- u32 varTab; /* variable table start */ +- u32 FDTandFlags; /* function descriptor table start and flags */ +- volatile u32 descAddrAndStatus; +- volatile u32 modifiedVarTab; +- u32 contextSaveSpace; /* context save space start */ +- u32 literalBases; +-} TaskTableEntry; +- +- +-/* Chained buffer descriptor */ +-typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; +-struct MCD_bufDesc_struct { +- u32 flags; /* flags describing the DMA */ +- u32 csumResult; /* checksum from checksumming performed since last checksum reset */ +- s8 *srcAddr; /* the address to move data from */ +- s8 *destAddr; /* the address to move data to */ +- s8 *lastDestAddr; /* the last address written to */ +- u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */ +- MCD_bufDesc *next; /* next buffer descriptor in chain */ +- u32 info; /* private information about this descriptor; DMA does not affect it */ +-}; +- +-/* Progress Query struct */ +-typedef volatile struct MCD_XferProg_struct { +- s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */ +- s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */ +- u32 dmaSize; /* the amount of data transferred for the current buffer */ +- MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */ +-} MCD_XferProg; +- +- +-/* FEC buffer descriptor */ +-typedef volatile struct MCD_bufDescFec_struct { +- u16 statCtrl; +- u16 length; +- u32 dataPointer; +-} MCD_bufDescFec; +- +- +-/*************************************************************************/ +-/* +- * API function Prototypes - see MCD_dmaApi.c for further notes +- */ +- +-/* +- * MCD_startDma starts a particular kind of DMA . +- */ +-int MCD_startDma ( +- int channel, /* the channel on which to run the DMA */ +- s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */ +- s16 srcIncr, /* the amount to increment the source address per transfer */ +- s8 *destAddr, /* the address to move data to */ +- s16 destIncr, /* the amount to increment the destination address per transfer */ +- u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ +- u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ +- u32 initiator, /* what device initiates the DMA */ +- int priority, /* priority of the DMA */ +- u32 flags, /* flags describing the DMA */ +- u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ +-); +- +-/* +- * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA +- * registers, relocating and creating the appropriate task structures, and +- * setting up some global settings +- */ +-int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags); +- +-/* +- * MCD_dmaStatus() returns the status of the DMA on the requested channel. +- */ +-int MCD_dmaStatus (int channel); +- +-/* +- * MCD_XferProgrQuery() returns progress of DMA on requested channel +- */ +-int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep); +- +-/* +- * MCD_killDma() halts the DMA on the requested channel, without any +- * intention of resuming the DMA. +- */ +-int MCD_killDma (int channel); +- +-/* +- * MCD_continDma() continues a DMA which as stopped due to encountering an +- * unready buffer descriptor. +- */ +-int MCD_continDma (int channel); +- +-/* +- * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is +- * running on that channel). +- */ +-int MCD_pauseDma (int channel); +- +-/* +- * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is +- * running on that channel). +- */ +-int MCD_resumeDma (int channel); +- +-/* +- * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA +- */ +-int MCD_csumQuery (int channel, u32 *csum); +- +-/* +- * MCD_getCodeSize provides the packed size required by the microcoded task +- * and structures. +- */ +-int MCD_getCodeSize(void); +- +-/* +- * MCD_getVersion provides a pointer to a version string and returns a +- * version number. +- */ +-int MCD_getVersion(char **longVersion); +- +-/* macro for setting a location in the variable table */ +-#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value +- /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, +- so I'm avoiding surrounding it with "do {} while(0)" */ +- +-#endif /* DEFINESONLY */ +- +-#endif /* _MCD_API_H */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_progCheck.h b/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_progCheck.h +deleted file mode 100644 +index a536f14..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_progCheck.h ++++ /dev/null +@@ -1,27 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * This file is autogenerated. Do not change . +- */ +-#define CURRBD 4 +-#define DCOUNT 6 +-#define DESTPTR 5 +-#define SRCPTR 7 +diff --git a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_tasksInit.h b/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_tasksInit.h +deleted file mode 100644 +index 6b19d02..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/mcdapi/MCD_tasksInit.h ++++ /dev/null +@@ -1,66 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Declaration for the MCD tasks. Do not edit. +- */ +-#ifndef MCD_TSK_INIT_H +-#define MCD_TSK_INIT_H 1 +- +-/* +- * Do not edit! +- */ +- +-/* +- * Task 0 +- */ +-void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); +- +- +-/* +- * Task 1 +- */ +-void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); +- +- +-/* +- * Task 2 +- */ +-void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel); +- +- +-/* +- * Task 3 +- */ +-void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel); +- +- +-/* +- * Task 4 +- */ +-void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel); +- +- +-/* +- * Task 5 +- */ +-void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel); +- +-#endif /* MCD_TSK_INIT_H */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/net/eth.h b/arch/m68k/mach-mcfv4e/include/proc/net/eth.h +deleted file mode 100644 +index e86d064..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/net/eth.h ++++ /dev/null +@@ -1,70 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Declaration for for Ethernet Frames. +- */ +- +-#ifndef _ETH_H +-#define _ETH_H +- +- +-/* Ethernet standard lengths in bytes*/ +-#define ETH_ADDR_LEN (6) +-#define ETH_TYPE_LEN (2) +-#define ETH_CRC_LEN (4) +-#define ETH_MAX_DATA (1500) +-#define ETH_MIN_DATA (46) +-#define ETH_HDR_LEN (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN) +- +-/* Defined Ethernet Frame Types */ +-#define ETH_FRM_IP (0x0800) +-#define ETH_FRM_ARP (0x0806) +-#define ETH_FRM_RARP (0x8035) +-#define ETH_FRM_TEST (0xA5A5) +- +-/* Maximum and Minimum Ethernet Frame Sizes */ +-#define ETH_MAX_FRM (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN) +-#define ETH_MIN_FRM (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN) +-#define ETH_MTU (ETH_HDR_LEN + ETH_MAX_DATA) +- +-/* Ethernet Addresses */ +-typedef uint8_t ETH_ADDR[ETH_ADDR_LEN]; +- +-/* 16-bit Ethernet Frame Type, ie. Protocol */ +-typedef uint16_t ETH_FRM_TYPE; +- +-/* Ethernet Frame Header definition */ +-typedef struct +-{ +- ETH_ADDR dest; +- ETH_ADDR src; +- ETH_FRM_TYPE type; +-} ETH_HDR; +- +-/* Ethernet Frame definition */ +-typedef struct +-{ +- ETH_HDR head; +- uint8_t* data; +-} ETH_FRAME; +- +- +-#endif /* _ETH_H */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/net/nbuf.h b/arch/m68k/mach-mcfv4e/include/proc/net/nbuf.h +deleted file mode 100644 +index 8b6a89c..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/net/nbuf.h ++++ /dev/null +@@ -1,88 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Definitions for network buffer management +- */ +- +-#ifndef _MCFV4E_NBUF_H_ +-#define _MCFV4E_NBUF_H_ +- +-/* +- * Include the Queue structure definitions +- */ +-#include "queue.h" +- +-/* +- * Number of network buffers to use +- */ +-#define NBUF_MAX 30 +- +-/* +- * Size of each buffer in bytes +- */ +-#ifndef NBUF_SZ +-#define NBUF_SZ 1520 +-#endif +- +-/* +- * Defines to identify all the buffer queues +- * - FREE must always be defined as 0 +- */ +-#define NBUF_FREE 0 /* available buffers */ +-#define NBUF_TX_RING 1 /* buffers in the Tx BD ring */ +-#define NBUF_RX_RING 2 /* buffers in the Rx BD ring */ +-#define NBUF_SCRATCH 3 /* misc */ +-#define NBUF_MAXQ 4 /* total number of queueus */ +- +-/* +- * Buffer Descriptor Format +- * +- * Fields: +- * next Pointer to next node in the queue +- * data Pointer to the data buffer +- * offset Index into buffer +- * length Remaining bytes in buffer from (data + offset) +- */ +-typedef struct +-{ +- QNODE node; +- uint8_t *data; +- uint16_t offset; +- uint16_t length; +-} NBUF; +- +-/* +- * Functions to manipulate the network buffers. +- */ +-int nbuf_init(void); +-void nbuf_flush(void); +- +-NBUF * nbuf_alloc (void); +-void nbuf_free(NBUF *); +- +-NBUF *nbuf_remove(int); +-void nbuf_add(int, NBUF *); +- +-void nbuf_reset(void); +-void nbuf_debug_dump(void); +- +- +-#endif /* _MCFV4E_NBUF_H_ */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/net/net.h b/arch/m68k/mach-mcfv4e/include/proc/net/net.h +deleted file mode 100644 +index d687759..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/net/net.h ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Network definitions and prototypes for dBUG. +- */ +- +-#ifndef _MCFV4E_NET_H +-#define _MCFV4E_NET_H +- +-/* +- * Include information and prototypes for all protocols +- */ +-#include "eth.h" +-#include "nbuf.h" +- +-int netif_init(int channel); +-int netif_setup(int channel); +-int netif_done(int channel); +- +-#endif /* _MCFV4E_NET_H */ +- +diff --git a/arch/m68k/mach-mcfv4e/include/proc/net/queue.h b/arch/m68k/mach-mcfv4e/include/proc/net/queue.h +deleted file mode 100644 +index d5c13f8..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/net/queue.h ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Implement a first in, first out linked list +- */ +-#ifndef _QUEUE_H_ +-#define _QUEUE_H_ +- +-/* +- * Individual queue node +- */ +-typedef struct NODE +-{ +- struct NODE *next; +-} QNODE; +- +-/* +- * Queue Struture - linked list of qentry items +- */ +-typedef struct +-{ +- QNODE *head; +- QNODE *tail; +-} QUEUE; +- +-/* +- * Functions provided by queue.c +- */ +-void queue_init(QUEUE *); +-int queue_isempty(QUEUE *); +-void queue_add(QUEUE *, QNODE *); +-QNODE* queue_remove(QUEUE *); +-QNODE* queue_peek(QUEUE *); +-void queue_move(QUEUE *, QUEUE *); +- +-#endif /* _QUEUE_H_ */ +diff --git a/arch/m68k/mach-mcfv4e/include/proc/processor.h b/arch/m68k/mach-mcfv4e/include/proc/processor.h +deleted file mode 100644 +index 4f196bd..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/processor.h ++++ /dev/null +@@ -1,33 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Coldfire V4e processor specific defines +- */ +- +-/* Empty dummy FIXME */ +- +-/* interrupt management */ +- +-void mcf_interrupts_initialize (void); +-int mcf_interrupts_register_handler (int vector, int (*handler)(void *, void *), void *hdev, void *harg); +-void mcf_interrupts_remove_handler (int (*handler)(void *, void *)); +-int mcf_execute_irq_handler (struct pt_regs *pt_regs,int); +- +diff --git a/arch/m68k/mach-mcfv4e/include/proc/ptrace.h b/arch/m68k/mach-mcfv4e/include/proc/ptrace.h +deleted file mode 100644 +index 5e12059..0000000 +--- a/arch/m68k/mach-mcfv4e/include/proc/ptrace.h ++++ /dev/null +@@ -1,119 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Declaration and defines for M68k register frames +- */ +-#ifndef __ASM_PROC_PTRACE_H +-#define __ASM_PROC_PTRACE_H +- +-#define TRACE_FLAG 0x8000 +-#define SVR_MODE 0x2000 +-#define MODE_MASK 0x2000 +-#define MASTER_FLAG 0x1000 +-#define IRQ_MASK 0x0700 +-#define CC_MASK 0x00FF +- +-#define CC_X_BIT 0x0010 +-#define CC_N_BIT 0x0008 +-#define CC_Z_BIT 0x0004 +-#define CC_V_BIT 0x0002 +-#define CC_C_BIT 0x0001 +- +-#define PCMASK 0x0 +- +-#ifndef __ASSEMBLY__ +- +-/* this struct defines the way the registers are stored on the +- stack during a system call. */ +- +-struct pt_regs { +- long uregs[37]; +-}; +-#define M68K_sp uregs[37] +-#define M68K_sr uregs[36] +-#define M68K_pc uregs[35] +-#define M68K_fpiar uregs[34] +-#define M68K_fpsr uregs[33] +-#define M68K_fpcr uregs[32] +- +-#define M68K_fp7 uregs[30] +-#define M68K_fp6 uregs[28] +-#define M68K_fp5 uregs[26] +-#define M68K_fp4 uregs[24] +-#define M68K_fp3 uregs[22] +-#define M68K_fp2 uregs[20] +-#define M68K_fp1 uregs[18] +-#define M68K_fp0 uregs[16] +- +-#define M68K_a7 uregs[15] +-#define M68K_a6 uregs[14] +-#define M68K_a5 uregs[13] +-#define M68K_a4 uregs[12] +-#define M68K_a3 uregs[11] +-#define M68K_a2 uregs[10] +-#define M68K_a1 uregs[ 9] +-#define M68K_a0 uregs[ 8] +-#define M68K_d7 uregs[ 7] +-#define M68K_d6 uregs[ 6] +-#define M68K_d5 uregs[ 5] +-#define M68K_d4 uregs[ 4] +-#define M68K_d3 uregs[ 3] +-#define M68K_d2 uregs[ 2] +-#define M68K_d1 uregs[ 1] +-#define M68K_d0 uregs[ 0] +- +- +-#ifdef __KERNEL__ +- +-#define user_mode(regs) \ +- (((regs)->M68K_sr & SVR_MODE) == 0) +- +-#define processor_mode(regs) \ +- ((regs)->M68K_sr & SVR_MODE) +- +-#define interrupts_enabled(regs) \ +- (!((regs)->M68K_sr & IRQ_MASK)) +- +-#define condition_codes(regs) \ +- ((regs)->M68K_sr & CC_MASK) +- +-/* Are the current registers suitable for user mode? +- * (used to maintain security in signal handlers) +- */ +-static inline int valid_user_regs(struct pt_regs *regs) +-{ +- if ((regs->M68K_sr & SVR_MODE) == 0 && +- (regs->M68K_sr & IRQ_MASK) == 7) +- return 1; +- +- /* +- * Force SR to something logical... +- */ +- regs->M68K_sr &= ~(CC_MASK); +- +- return 0; +-} +- +-#endif /* __KERNEL__ */ +- +-#endif /* __ASSEMBLY__ */ +- +-#endif +diff --git a/arch/m68k/mach-mcfv4e/mcdapi/MCD_dmaApi.c b/arch/m68k/mach-mcfv4e/mcdapi/MCD_dmaApi.c +deleted file mode 100644 +index 60e2b6d..0000000 +--- a/arch/m68k/mach-mcfv4e/mcdapi/MCD_dmaApi.c ++++ /dev/null +@@ -1,907 +0,0 @@ +-/* +- * File: MCD_dmaApi.c +- * Purpose: Main C file for multi-channel DMA API. +- * +- * Notes: +- */ +- +-#include <asm/types.h> +-#include <proc/mcdapi/MCD_dma.h> +-#include <proc/mcdapi/MCD_tasksInit.h> +-#include <proc/mcdapi/MCD_progCheck.h> +- +-/* +- * This is an API-internal pointer to the DMA's registers +- */ +-dmaRegs *MCD_dmaBar; +- +-/* +- * These are the real and model task tables as generated by the +- * build process +- */ +-extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS]; +-extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS]; +- +-/* +- * However, this (usually) gets relocated to on-chip SRAM, at which +- * point we access them as these tables +- */ +-volatile TaskTableEntry *MCD_taskTable; +-TaskTableEntry *MCD_modelTaskTable; +- +- +-/* +- * MCD_chStatus[] is an array of status indicators for remembering +- * whether a DMA has ever been attempted on each channel, pausing +- * status, etc. +- */ +-static int MCD_chStatus[NCHANNELS] = +-{ +- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, +- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, +- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, +- MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA +-}; +- +-/* +- * Prototypes for local functions +- */ +-static void MCD_memcpy (int *dest, int *src, u32 size); +-static void MCD_resmActions (int channel); +- +-/* +- * Buffer descriptors used for storage of progress info for single Dmas +- * Also used as storage for the DMA for CRCs for single DMAs +- * Otherwise, the DMA does not parse these buffer descriptors +- */ +-#ifdef MCD_INCLUDE_EU +-extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; +-#else +-MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; +-#endif +-MCD_bufDesc *MCD_relocBuffDesc; +- +- +-/* +- * Defines for the debug control register's functions +- */ +-#define DBG_CTL_COMP1_TASK (0x00002000) /* have comparator 1 look for a task # */ +-#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \ +- DBG_CTL_BREAK | \ +- DBG_CTL_INT_BREAK | \ +- DBG_CTL_COMP1_TASK) +-#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \ +- DBG_CTL_INT_BREAK | \ +- DBG_CTL_COMP1_TASK) +-#define DBG_KILL_ALL_STAT (0xFFFFFFFF) +- +-/* +- * Offset to context save area where progress info is stored +- */ +-#define CSAVE_OFFSET 10 +- +-/* +- * Defines for Byte Swapping +- */ +-#define MCD_BYTE_SWAP_KILLER 0xFFF8888F +-#define MCD_NO_BYTE_SWAP_ATALL 0x00040000 +- +-/* +- * Execution Unit Identifiers +- */ +-#define MAC 0 /* legacy - not used */ +-#define LUAC 1 /* legacy - not used */ +-#define CRC 2 /* legacy - not used */ +-#define LURC 3 /* Logic Unit with CRC */ +- +-/* +- * Task Identifiers +- */ +-#define TASK_CHAINNOEU 0 +-#define TASK_SINGLENOEU 1 +-#ifdef MCD_INCLUDE_EU +-#define TASK_CHAINEU 2 +-#define TASK_SINGLEEU 3 +-#define TASK_FECRX 4 +-#define TASK_FECTX 5 +-#else +-#define TASK_CHAINEU 0 +-#define TASK_SINGLEEU 1 +-#define TASK_FECRX 2 +-#define TASK_FECTX 3 +-#endif +- +-/* +- * Structure to remember which variant is on which channel +- * TBD- need this? +- */ +-typedef struct MCD_remVariants_struct MCD_remVariant; +-struct MCD_remVariants_struct +-{ +- int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */ +- int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */ +- s16 remDestIncr[NCHANNELS]; /* DestIncr */ +- s16 remSrcIncr[NCHANNELS]; /* srcIncr */ +- u32 remXferSize[NCHANNELS]; /* xferSize */ +-}; +- +-/* +- * Structure to remember the startDma parameters for each channel +- */ +-MCD_remVariant MCD_remVariants; +- +-/* +- * Function: MCD_initDma +- * Purpose: Initializes the DMA API by setting up a pointer to the DMA +- * registers, relocating and creating the appropriate task +- * structures, and setting up some global settings +- * Arguments: +- * dmaBarAddr - pointer to the multichannel DMA registers +- * taskTableDest - location to move DMA task code and structs to +- * flags - operational parameters +- * Return Value: +- * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned +- * MCD_OK otherwise +- */ +-extern u32 MCD_funcDescTab0[]; +- +-int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags) +-{ +- int i; +- TaskTableEntry *entryPtr; +- +- /* setup the local pointer to register set */ +- MCD_dmaBar = dmaBarAddr; +- +- /* do we need to move/create a task table */ +- if ((flags & MCD_RELOC_TASKS) != 0) +- { +- int fixedSize; +- u32 *fixedPtr; +- /*int *tablePtr = taskTableDest;TBD*/ +- int varTabsOffset, funcDescTabsOffset, contextSavesOffset; +- int taskDescTabsOffset; +- int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize; +- int taskDescTabSize; +- +- int i; +- +- /* check if physical address is aligned on 512 byte boundary */ +- if (((u32)taskTableDest & 0x000001ff) != 0) +- return(MCD_TABLE_UNALIGNED); +- +- MCD_taskTable = taskTableDest; /* set up local pointer to task Table */ +- +- /* +- * Create a task table: +- * - compute aligned base offsets for variable tables and +- * function descriptor tables, then +- * - loop through the task table and setup the pointers +- * - copy over model task table with the the actual task descriptor +- * tables +- */ +- +- taskTableSize = NCHANNELS * sizeof(TaskTableEntry); +- /* align variable tables to size */ +- varTabsOffset = taskTableSize + (u32)taskTableDest; +- if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0) +- varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE); +- /* align function descriptor tables */ +- varTabsSize = NCHANNELS * VAR_TAB_SIZE; +- funcDescTabsOffset = varTabsOffset + varTabsSize; +- +- if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0) +- funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE) & +- (~FUNCDESC_TAB_SIZE); +- +- funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE; +- contextSavesOffset = funcDescTabsOffset + funcDescTabsSize; +- contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE); +- fixedSize = taskTableSize + varTabsSize + funcDescTabsSize + +- contextSavesSize; +- +- /* zero the thing out */ +- fixedPtr = (u32 *)taskTableDest; +- for (i = 0;i<(fixedSize/4);i++) +- fixedPtr[i] = 0; +- +- entryPtr = (TaskTableEntry*)MCD_taskTable; +- /* set up fixed pointers */ +- for (i = 0; i < NCHANNELS; i++) +- { +- entryPtr[i].varTab = (u32)varTabsOffset; /* update ptr to local value */ +- entryPtr[i].FDTandFlags = (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF; +- entryPtr[i].contextSaveSpace = (u32)contextSavesOffset; +- varTabsOffset += VAR_TAB_SIZE; +-#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */ +- funcDescTabsOffset += FUNCDESC_TAB_SIZE; +-#endif +- contextSavesOffset += CONTEXT_SAVE_SIZE; +- } +- /* copy over the function descriptor table */ +- for ( i = 0; i < FUNCDESC_TAB_NUM; i++) +- { +- MCD_memcpy((void*)(entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK), +- (void*)MCD_funcDescTab0, FUNCDESC_TAB_SIZE); +- } +- +- /* copy model task table to where the context saves stuff leaves off*/ +- MCD_modelTaskTable = (TaskTableEntry*)contextSavesOffset; +- +- MCD_memcpy ((void*)MCD_modelTaskTable, (void*)MCD_modelTaskTableSrc, +- NUMOFVARIANTS * sizeof(TaskTableEntry)); +- +- entryPtr = MCD_modelTaskTable; /* point to local version of +- model task table */ +- taskDescTabsOffset = (u32)MCD_modelTaskTable + +- (NUMOFVARIANTS * sizeof(TaskTableEntry)); +- +- /* copy actual task code and update TDT ptrs in local model task table */ +- for (i = 0; i < NUMOFVARIANTS; i++) +- { +- taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4; +- MCD_memcpy ((void*)taskDescTabsOffset, (void*)entryPtr[i].TDTstart, taskDescTabSize); +- entryPtr[i].TDTstart = (u32)taskDescTabsOffset; +- taskDescTabsOffset += taskDescTabSize; +- entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4; +- } +-#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls +- where they are since DMA might write to them */ +- MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4); +-#else /* DMA does not touch them so they can be wherever and we don't need to +- waste SRAM on them */ +- MCD_relocBuffDesc = MCD_singleBufDescs; +-#endif +- } +- else +- { +- /* point the would-be relocated task tables and the +- buffer descriptors to the ones the linker generated */ +- +- if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0) +- return(MCD_TABLE_UNALIGNED); +- +- /* need to add code to make sure that every thing else is aligned properly TBD*/ +- /* this is problematic if we init more than once or after running tasks, +- need to add variable to see if we have aleady init'd */ +- entryPtr = MCD_realTaskTableSrc; +- for (i = 0; i < NCHANNELS; i++) +- { +- if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) || +- ((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0)) +- return(MCD_TABLE_UNALIGNED); +- } +- +- MCD_taskTable = MCD_realTaskTableSrc; +- MCD_modelTaskTable = MCD_modelTaskTableSrc; +- MCD_relocBuffDesc = MCD_singleBufDescs; +- } +- +- +- /* Make all channels as totally inactive, and remember them as such: */ +- +- MCD_dmaBar->taskbar = (u32) MCD_taskTable; +- for (i = 0; i < NCHANNELS; i++) +- { +- MCD_dmaBar->taskControl[i] = 0x0; +- MCD_chStatus[i] = MCD_NO_DMA; +- } +- +- /* Set up pausing mechanism to inactive state: */ +- MCD_dmaBar->debugComp1 = 0; /* no particular values yet for either comparator registers */ +- MCD_dmaBar->debugComp2 = 0; +- MCD_dmaBar->debugControl = DBG_CTL_DISABLE; +- MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT; +- +- /* enable or disable commbus prefetch, really need an ifdef or +- something to keep from trying to set this in the 8220 */ +- if ((flags & MCD_COMM_PREFETCH_EN) != 0) +- MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH; +- else +- MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH; +- +- return(MCD_OK); +-} +- +-/* Function: MCD_dmaStatus +- * Purpose: Returns the status of the DMA on the requested channel +- * Arguments: channel - channel number +- * Returns: Predefined status indicators +- */ +-int MCD_dmaStatus (int channel) +-{ +- u16 tcrValue; +- +- if((channel < 0) || (channel >= NCHANNELS)) +- return(MCD_CHANNEL_INVALID); +- +- tcrValue = MCD_dmaBar->taskControl[channel]; +- if ((tcrValue & TASK_CTL_EN) == 0) +- { /* nothing running */ +- /* if last reported with task enabled */ +- if ( MCD_chStatus[channel] == MCD_RUNNING +- || MCD_chStatus[channel] == MCD_IDLE) +- MCD_chStatus[channel] = MCD_DONE; +- } +- else /* something is running */ +- { +- /* There are three possibilities: paused, running or idle. */ +- if ( MCD_chStatus[channel] == MCD_RUNNING +- || MCD_chStatus[channel] == MCD_IDLE) +- { +- MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; +- /* This register is selected to know which initiator is +- actually asserted. */ +- if ((MCD_dmaBar->ptdDebug >> channel ) & 0x1 ) +- MCD_chStatus[channel] = MCD_RUNNING; +- else +- MCD_chStatus[channel] = MCD_IDLE; +- /* do not change the status if it is already paused. */ +- } +- } +- return MCD_chStatus[channel]; +-} +- +-/* Function: MCD_startDma +- * Ppurpose: Starts a particular kind of DMA +- * Arguments: see below +- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK +- */ +- +-int MCD_startDma ( +- int channel, /* the channel on which to run the DMA */ +- s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */ +- s16 srcIncr, /* the amount to increment the source address per transfer */ +- s8 *destAddr, /* the address to move data to */ +- s16 destIncr, /* the amount to increment the destination address per transfer */ +- u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */ +- u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */ +- u32 initiator, /* what device initiates the DMA */ +- int priority, /* priority of the DMA */ +- u32 flags, /* flags describing the DMA */ +- u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */ +-#ifdef MCD_NEED_ADDR_TRANS +- s8 *srcAddrVirt /* virtual buffer descriptor address TBD*/ +-#endif +-) +-{ +- int srcRsdIncr, destRsdIncr; +- int *cSave; +- short xferSizeIncr; +- int tcrCount = 0; +-#ifdef MCD_INCLUDE_EU +- u32 *realFuncArray; +-#endif +- +- if((channel < 0) || (channel >= NCHANNELS)) +- return(MCD_CHANNEL_INVALID); +- +- /* tbd - need to determine the proper response to a bad funcDesc when not +- including EU functions, for now, assign a benign funcDesc, but maybe +- should return an error */ +-#ifndef MCD_INCLUDE_EU +- funcDesc = MCD_FUNC_NOEU1; +-#endif +- +-#ifdef MCD_DEBUG +-printf("startDma:Setting up params\n"); +-#endif +- /* Set us up for task-wise priority. We don't technically need to do this on every start, but +- since the register involved is in the same longword as other registers that users are in control +- of, setting it more than once is probably preferable. That since the documentation doesn't seem +- to be completely consistent about the nature of the PTD control register. */ +- MCD_dmaBar->ptdControl |= (u16) 0x8000; +-#if 1 /* Not sure what we need to keep here rtm TBD */ +- /* Calculate additional parameters to the regular DMA calls. */ +- srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0); +- destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0); +- +- xferSizeIncr = (xferSize & 0xffff) | 0x20000000; +- +- /* Remember for each channel which variant is running. */ +- MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr; +- MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr; +- MCD_remVariants.remDestIncr[channel] = destIncr; +- MCD_remVariants.remSrcIncr[channel] = srcIncr; +- MCD_remVariants.remXferSize[channel] = xferSize; +-#endif +- +- cSave = (int*)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + CURRBD; +- +-#ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */ +- realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00); +- /* Modify the LURC's normal and byte-residue-loop functions according to parameter. */ +- realFuncArray[(LURC*16)] = xferSize == 4 ? +- funcDesc : xferSize == 2 ? +- funcDesc & 0xfffff00f : funcDesc & 0xffff000f; +- realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL; +-#endif +- /* Write the initiator field in the TCR, and also set the initiator-hold +- bit. Note that,due to a hardware quirk, this could collide with an +- MDE access to the initiator-register file, so we have to verify that the write +- reads back correctly. */ +- +- MCD_dmaBar->taskControl[channel] = +- (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM; +- +- while(((MCD_dmaBar->taskControl[channel] & 0x1fff) != +- ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) && +- (tcrCount < 1000)) +- { +- tcrCount++; +- /*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020;*/ +- MCD_dmaBar->taskControl[channel] = +- (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM; +- } +- +- MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK; +- /* should be albe to handle this stuff with only one write to ts reg - tbd */ +- if (channel < 8 && channel >= 0) +- { +- MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4); +- MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel)*4) + 2); +- MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel)*4); +- } +- else +- { +- MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4); +- MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel)*4) + 2); +- MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel)*4); +- } +- +- /* setup task table flags/options which mostly control the line buffers */ +- MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK; +- MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags); +- +- if (flags & MCD_FECTX_DMA) +- { +- /* TDTStart and TDTEnd */ +- MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart; +- MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend; +- MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel); +- } +- else if (flags & MCD_FECRX_DMA) +- { +- /* TDTStart and TDTEnd */ +- MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECRX].TDTstart; +- MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend; +- MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel); +- } +- else if(flags & MCD_SINGLE_DMA) +- { +- /* this buffer descriptor is used for storing off initial parameters for later +- progress query calculation and for the DMA to write the resulting checksum +- The DMA does not use this to determine how to operate, that info is passed +- with the init routine*/ +- MCD_relocBuffDesc[channel].srcAddr = srcAddr; +- MCD_relocBuffDesc[channel].destAddr = destAddr; +- MCD_relocBuffDesc[channel].lastDestAddr = destAddr; /* definitely not its final value */ +- MCD_relocBuffDesc[channel].dmaSize = dmaSize; +- MCD_relocBuffDesc[channel].flags = 0; /* not used */ +- MCD_relocBuffDesc[channel].csumResult = 0; /* not used */ +- MCD_relocBuffDesc[channel].next = 0; /* not used */ +- +- /* Initialize the progress-querying stuff to show no progress:*/ +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr; +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr; +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = +- (u32) &(MCD_relocBuffDesc[channel]); +- /* tbd - need to keep the user from trying to call the EU routine +- when MCD_INCLUDE_EU is not defined */ +- if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) +- { +- /* TDTStart and TDTEnd */ +- MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart; +- MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLENOEU].TDTend; +- MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize, +- xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave, +- MCD_taskTable, channel); +- } +- else +- { +- /* TDTStart and TDTEnd */ +- MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLEEU].TDTstart; +- MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLEEU].TDTend; +- MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize, +- xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave, +- MCD_taskTable, channel); +- } +- } +- else +- { /* chained DMAS */ +- /* Initialize the progress-querying stuff to show no progress:*/ +-#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */ +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] +- = (int)((MCD_bufDesc*) srcAddr)->srcAddr; +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] +- = (int)((MCD_bufDesc*) srcAddr)->destAddr; +-#else /* if using address translation, need the virtual addr of the first buffdesc */ +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] +- = (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr; +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] +- = (int)((MCD_bufDesc*) srcAddrVirt)->destAddr; +-#endif +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; +- ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr; +- +- if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) +- { +- /*TDTStart and TDTEnd*/ +- MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart; +- MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINNOEU].TDTend; +- MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, destIncr, xferSize, +- xferSizeIncr, cSave, MCD_taskTable, channel); +- } +- else +- { +- /*TDTStart and TDTEnd*/ +- MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINEU].TDTstart; +- MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINEU].TDTend; +- MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, xferSize, +- xferSizeIncr, cSave, MCD_taskTable, channel); +- } +- } +- MCD_chStatus[channel] = MCD_IDLE; +- return(MCD_OK); +-} +- +-/* Function: MCD_XferProgrQuery +- * Purpose: Returns progress of DMA on requested channel +- * Arguments: channel - channel to retrieve progress for +- * progRep - pointer to user supplied MCD_XferProg struct +- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK +- * +- * Notes: +- * MCD_XferProgrQuery() upon completing or after aborting a DMA, or +- * while the DMA is in progress, this function returns the first +- * DMA-destination address not (or not yet) used in the DMA. When +- * encountering a non-ready buffer descriptor, the information for +- * the last completed descriptor is returned. +- * +- * MCD_XferProgQuery() has to avoid the possibility of getting +- * partially-updated information in the event that we should happen +- * to query DMA progress just as the DMA is updating it. It does that +- * by taking advantage of the fact context is not saved frequently for +- * the most part. We therefore read it at least twice until we get the +- * same information twice in a row. +- * +- * Because a small, but not insignificant, amount of time is required +- * to write out the progress-query information, especially upon +- * completion of the DMA, it would be wise to guarantee some time lag +- * between successive readings of the progress-query information. +- */ +- +-/* +- * How many iterations of the loop below to execute to stabilize values +- */ +-#define STABTIME 0 +- +-int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep) +-{ +- MCD_XferProg prevRep; +- int again; /* true if we are to try again to get consistent results */ +- int i; /* used as a time-waste counter */ +- int destDiffBytes; /* Total number of bytes that we think actually got xfered. */ +- int numIterations; /* number of iterations */ +- int bytesNotXfered; /* bytes that did not get xfered. */ +- s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr; +- int subModVal, addModVal; /* Mode values to added and subtracted from the +- final destAddr */ +- +- if((channel < 0) || (channel >= NCHANNELS)) +- return(MCD_CHANNEL_INVALID); +- +- /* Read a trial value for the progress-reporting values*/ +- prevRep.lastSrcAddr = +- (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; +- prevRep.lastDestAddr = +- (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; +- prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET]; +- prevRep.currBufDesc = +- (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]; +- /* Repeatedly reread those values until they match previous values: */ +- do { +- /* Waste a little bit of time to ensure stability: */ +- for (i = 0; i < STABTIME; i++) +- i += i >> 2; /* make sure this loop does something so that it doesn't get optimized out */ +- /* Check them again: */ +- progRep->lastSrcAddr = +- (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; +- progRep->lastDestAddr = +- (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; +- progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET]; +- progRep->currBufDesc = +- (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET]; +- /* See if they match: */ +- if ( prevRep.lastSrcAddr != progRep->lastSrcAddr +- || prevRep.lastDestAddr != progRep->lastDestAddr +- || prevRep.dmaSize != progRep->dmaSize +- || prevRep.currBufDesc != progRep->currBufDesc) +- { +- /* If they don't match, remember previous values and try again:*/ +- prevRep.lastSrcAddr = progRep->lastSrcAddr; +- prevRep.lastDestAddr = progRep->lastDestAddr; +- prevRep.dmaSize = progRep->dmaSize; +- prevRep.currBufDesc = progRep->currBufDesc; +- again = MCD_TRUE; +- } +- else +- again = MCD_FALSE; +- } while (again == MCD_TRUE); +- +- +- /* Update the dCount, srcAddr and destAddr */ +- /* To calculate dmaCount, we consider destination address. C +- overs M1,P1,Z for destination */ +- switch(MCD_remVariants.remDestRsdIncr[channel]) { +- case MINUS1: +- subModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); +- addModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); +- LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal; +- LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal; +- destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr; +- bytesNotXfered = (destDiffBytes/MCD_remVariants.remDestIncr[channel]) * +- ( MCD_remVariants.remDestIncr[channel] +- + MCD_remVariants.remXferSize[channel]); +- progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal - subModVal; +- break; +- case ZERO: +- progRep->lastDestAddr = progRep->currBufDesc->destAddr; +- break; +- case PLUS1: +- /* This value has to be subtracted from the final calculated dCount. */ +- subModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); +- /* These bytes are already in lastDestAddr. */ +- addModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); +- LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal; +- LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal; +- destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr); +- numIterations = ( LWAlignedCurrDestAddr - LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel]; +- bytesNotXfered = numIterations * +- ( MCD_remVariants.remDestIncr[channel] +- - MCD_remVariants.remXferSize[channel]); +- progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal; +- break; +- default: +- break; +- } +- +- /* This covers M1,P1,Z for source */ +- switch(MCD_remVariants.remSrcRsdIncr[channel]) { +- case MINUS1: +- progRep->lastSrcAddr = +- progRep->currBufDesc->srcAddr + +- ( MCD_remVariants.remSrcIncr[channel] * +- (progRep->dmaSize/MCD_remVariants.remXferSize[channel])); +- break; +- case ZERO: +- progRep->lastSrcAddr = progRep->currBufDesc->srcAddr; +- break; +- case PLUS1: +- progRep->lastSrcAddr = +- progRep->currBufDesc->srcAddr + +- ( MCD_remVariants.remSrcIncr[channel] * +- (progRep->dmaSize/MCD_remVariants.remXferSize[channel])); +- break; +- default: break; +- } +- +- return(MCD_OK); +-} +- +-/* MCD_resmActions() does the majority of the actions of a DMA resume. +- * It is called from MCD_killDma() and MCD_resumeDma(). It has to be +- * a separate function because the kill function has to negate the task +- * enable before resuming it, but the resume function has to do nothing +- * if there is no DMA on that channel (i.e., if the enable bit is 0). +- */ +-static void MCD_resmActions (int channel) +-{ +- MCD_dmaBar->debugControl = DBG_CTL_DISABLE; +- MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus; +- MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; /* This register is selected to know +- which initiator is actually asserted. */ +- if((MCD_dmaBar->ptdDebug >> channel ) & 0x1) +- MCD_chStatus[channel] = MCD_RUNNING; +- else +- MCD_chStatus[channel] = MCD_IDLE; +-} +- +-/* Function: MCD_killDma +- * Purpose: Halt the DMA on the requested channel, without any +- * intention of resuming the DMA. +- * Arguments: channel - requested channel +- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK +- * +- * Notes: +- * A DMA may be killed from any state, including paused state, and it +- * always goes to the MCD_HALTED state even if it is killed while in +- * the MCD_NO_DMA or MCD_IDLE states. +- */ +-int MCD_killDma (int channel) +-{ +- /* MCD_XferProg progRep; */ +- +- if((channel < 0) || (channel >= NCHANNELS)) +- return(MCD_CHANNEL_INVALID); +- +- MCD_dmaBar->taskControl[channel] = 0x0; +- MCD_resumeDma (channel); +- /* +- * This must be after the write to the TCR so that the task doesn't +- * start up again momentarily, and before the status assignment so +- * as to override whatever MCD_resumeDma() may do to the channel +- * status. +- */ +- MCD_chStatus[channel] = MCD_HALTED; +- +- /* +- * Update the current buffer descriptor's lastDestAddr field +- * +- * MCD_XferProgrQuery (channel, &progRep); +- * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr; +- */ +- return(MCD_OK); +-} +- +-/* Function: MCD_continDma +- * Purpose: Continue a DMA which as stopped due to encountering an +- * unready buffer descriptor. +- * Arguments: channel - channel to continue the DMA on +- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK +- * +- * Notes: +- * This routine does not check to see if there is a task which can +- * be continued. Also this routine should not be used with single DMAs. +- */ +-int MCD_continDma (int channel) +-{ +- if((channel < 0) || (channel >= NCHANNELS)) +- return(MCD_CHANNEL_INVALID); +- +- MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN; +- MCD_chStatus[channel] = MCD_RUNNING; +- +- return(MCD_OK); +-} +- +-/* +- * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit +- * to freeze a task and resume it. We freeze a task by breakpointing +- * on the stated task. That is, not any specific place in the task, +- * but any time that task executes. In particular, when that task +- * executes, we want to freeze that task and only that task. +- * +- * The bits of the debug control register influence interrupts vs. +- * breakpoints as follows: +- * - Bits 14 and 0 enable or disable debug functions. If enabled, you +- * will get the interrupt but you may or may not get a breakpoint. +- * - Bits 2 and 1 decide whether you also get a breakpoint in addition +- * to an interrupt. +- * +- * The debug unit can do these actions in response to either internally +- * detected breakpoint conditions from the comparators, or in response +- * to the external breakpoint pin, or both. +- * - Bits 14 and 1 perform the above-described functions for +- * internally-generated conditions, i.e., the debug comparators. +- * - Bits 0 and 2 perform the above-described functions for external +- * conditions, i.e., the breakpoint external pin. +- * +- * Note that, although you "always" get the interrupt when you turn +- * the debug functions, the interrupt can nevertheless, if desired, be +- * masked by the corresponding bit in the PTD's IMR. Note also that +- * this means that bits 14 and 0 must enable debug functions before +- * bits 1 and 2, respectively, have any effect. +- * +- * NOTE: It's extremely important to not pause more than one DMA channel +- * at a time. +- ********************************************************************/ +- +-/* Function: MCD_pauseDma +- * Purpose: Pauses the DMA on a given channel (if any DMA is running +- * on that channel). +- * Arguments: channel +- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK +- */ +-int MCD_pauseDma (int channel) +-{ +- /* MCD_XferProg progRep; */ +- +- if((channel < 0) || (channel >= NCHANNELS)) +- return(MCD_CHANNEL_INVALID); +- +- if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) +- { +- MCD_dmaBar->debugComp1 = channel; +- MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16)); +- MCD_chStatus[channel] = MCD_PAUSED; +- +- /* +- * Update the current buffer descriptor's lastDestAddr field +- * +- * MCD_XferProgrQuery (channel, &progRep); +- * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr; +- */ +- } +- return(MCD_OK); +-} +- +-/* Function: MCD_resumeDma +- * Purpose: Resumes the DMA on a given channel (if any DMA is +- * running on that channel). +- * Arguments: channel - channel on which to resume DMA +- * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK +- */ +-int MCD_resumeDma (int channel) +-{ +- if((channel < 0) || (channel >= NCHANNELS)) +- return(MCD_CHANNEL_INVALID); +- +- if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) +- MCD_resmActions (channel); +- +- return(MCD_OK); +-} +- +-/* Function: MCD_csumQuery +- * Purpose: Provide the checksum after performing a non-chained DMA +- * Arguments: channel - channel to report on +- * csum - pointer to where to write the checksum/CRC +- * Returns: MCD_ERROR if the channel is invalid, else MCD_OK +- * +- * Notes: +- * +- */ +-int MCD_csumQuery (int channel, u32 *csum) +-{ +-#ifdef MCD_INCLUDE_EU +- if((channel < 0) || (channel >= NCHANNELS)) +- return(MCD_CHANNEL_INVALID); +- +- *csum = MCD_relocBuffDesc[channel].csumResult; +- return(MCD_OK); +-#else +- return(MCD_ERROR); +-#endif +-} +- +-/* Function: MCD_getCodeSize +- * Purpose: Provide the size requirements of the microcoded tasks +- * Returns: Size in bytes +- */ +-int MCD_getCodeSize(void) +-{ +-#ifdef MCD_INCLUDE_EU +- return(0x2b5c); +-#else +- return(0x173c); +-#endif +-} +- +-/* Function: MCD_getVersion +- * Purpose: Provide the version string and number +- * Arguments: longVersion - user supplied pointer to a pointer to a char +- * which points to the version string +- * Returns: Version number and version string (by reference) +- */ +-char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)"; +-#define MCD_REV_MAJOR 0x00 +-#define MCD_REV_MINOR 0x03 +- +-int MCD_getVersion(char **longVersion) +-{ +- *longVersion = MCD_versionString; +- return((MCD_REV_MAJOR << 8) | MCD_REV_MINOR); +-} +- +-/* Private version of memcpy() +- * Note that everything this is used for is longword-aligned. +- */ +-static void MCD_memcpy (int *dest, int *src, u32 size) +-{ +- u32 i; +- +- for (i = 0; i < size; i += sizeof(int), dest++, src++) +- *dest = *src; +-} +diff --git a/arch/m68k/mach-mcfv4e/mcdapi/MCD_library.dox b/arch/m68k/mach-mcfv4e/mcdapi/MCD_library.dox +deleted file mode 100644 +index ec3a730..0000000 +--- a/arch/m68k/mach-mcfv4e/mcdapi/MCD_library.dox ++++ /dev/null +@@ -1,10 +0,0 @@ +-/** @page mcfv4e_MCDlib MultiChannelDMA library for Coldfire V4e +- * +- * The MCD library is taken as is from sources publically available from +- * FreeScale Semiconductors az http://www.freescale.com +- * +- * It is slight reformatted and cleaned up, but otherwise unchanged to support +- * later merged with updated MCD library releases. +- * +- * See the PDF document supplied with the library for API documentation +- */ +diff --git a/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasks.c b/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasks.c +deleted file mode 100644 +index 812120d..0000000 +--- a/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasks.c ++++ /dev/null +@@ -1,2449 +0,0 @@ +-/* +- * File: MCD_tasks.c +- * Purpose: Contains task code and structures for Multi-channel DMA +- * +- * Notes: +- */ +-#include <asm/types.h> +-#include <proc/mcdapi/MCD_dma.h> +- +-u32 MCD_varTab0[]; +-u32 MCD_varTab1[]; +-u32 MCD_varTab2[]; +-u32 MCD_varTab3[]; +-u32 MCD_varTab4[]; +-u32 MCD_varTab5[]; +-u32 MCD_varTab6[]; +-u32 MCD_varTab7[]; +-u32 MCD_varTab8[]; +-u32 MCD_varTab9[]; +-u32 MCD_varTab10[]; +-u32 MCD_varTab11[]; +-u32 MCD_varTab12[]; +-u32 MCD_varTab13[]; +-u32 MCD_varTab14[]; +-u32 MCD_varTab15[]; +- +-u32 MCD_funcDescTab0[]; +-#ifdef MCD_INCLUDE_EU +-u32 MCD_funcDescTab1[]; +-u32 MCD_funcDescTab2[]; +-u32 MCD_funcDescTab3[]; +-u32 MCD_funcDescTab4[]; +-u32 MCD_funcDescTab5[]; +-u32 MCD_funcDescTab6[]; +-u32 MCD_funcDescTab7[]; +-u32 MCD_funcDescTab8[]; +-u32 MCD_funcDescTab9[]; +-u32 MCD_funcDescTab10[]; +-u32 MCD_funcDescTab11[]; +-u32 MCD_funcDescTab12[]; +-u32 MCD_funcDescTab13[]; +-u32 MCD_funcDescTab14[]; +-u32 MCD_funcDescTab15[]; +-#endif +- +-u32 MCD_contextSave0[]; +-u32 MCD_contextSave1[]; +-u32 MCD_contextSave2[]; +-u32 MCD_contextSave3[]; +-u32 MCD_contextSave4[]; +-u32 MCD_contextSave5[]; +-u32 MCD_contextSave6[]; +-u32 MCD_contextSave7[]; +-u32 MCD_contextSave8[]; +-u32 MCD_contextSave9[]; +-u32 MCD_contextSave10[]; +-u32 MCD_contextSave11[]; +-u32 MCD_contextSave12[]; +-u32 MCD_contextSave13[]; +-u32 MCD_contextSave14[]; +-u32 MCD_contextSave15[]; +- +-u32 MCD_realTaskTableSrc[] = +-{ +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab0, /* Task 0 Variable Table */ +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave0, /* Task 0 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab1, /* Task 1 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave1, /* Task 1 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab2, /* Task 2 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave2, /* Task 2 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab3, /* Task 3 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave3, /* Task 3 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab4, /* Task 4 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave4, /* Task 4 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab5, /* Task 5 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave5, /* Task 5 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab6, /* Task 6 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave6, /* Task 6 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab7, /* Task 7 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave7, /* Task 7 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab8, /* Task 8 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave8, /* Task 8 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab9, /* Task 9 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave9, /* Task 9 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab10, /* Task 10 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave10, /* Task 10 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab11, /* Task 11 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave11, /* Task 11 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab12, /* Task 12 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave12, /* Task 12 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab13, /* Task 13 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave13, /* Task 13 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab14, /* Task 14 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave14, /* Task 14 context save space */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_varTab15, /* Task 15 Variable Table */ +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */ +-#else +- (u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */ +-#endif +- 0x00000000, +- 0x00000000, +- (u32)MCD_contextSave15, /* Task 15 context save space */ +- 0x00000000, +-}; +- +- +-u32 MCD_varTab0[] = +-{ /* Task 0 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +- +-u32 MCD_varTab1[] = +-{ /* Task 1 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab2[]= +-{ /* Task 2 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab3[]= +-{ /* Task 3 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab4[]= +-{ /* Task 4 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab5[]= +-{ /* Task 5 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab6[]= +-{ /* Task 6 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab7[]= +-{ /* Task 7 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab8[]= +-{ /* Task 8 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab9[]= +-{ /* Task 9 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab10[]= +-{ /* Task 10 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab11[]= +-{ /* Task 11 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab12[]= +-{ /* Task 12 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab13[]= +-{ /* Task 13 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab14[]= +-{ /* Task 14 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_varTab15[]= +-{ /* Task 15 Variable Table */ +- 0x00000000, /* var[0] */ +- 0x00000000, /* var[1] */ +- 0x00000000, /* var[2] */ +- 0x00000000, /* var[3] */ +- 0x00000000, /* var[4] */ +- 0x00000000, /* var[5] */ +- 0x00000000, /* var[6] */ +- 0x00000000, /* var[7] */ +- 0x00000000, /* var[8] */ +- 0x00000000, /* var[9] */ +- 0x00000000, /* var[10] */ +- 0x00000000, /* var[11] */ +- 0x00000000, /* var[12] */ +- 0x00000000, /* var[13] */ +- 0x00000000, /* var[14] */ +- 0x00000000, /* var[15] */ +- 0x00000000, /* var[16] */ +- 0x00000000, /* var[17] */ +- 0x00000000, /* var[18] */ +- 0x00000000, /* var[19] */ +- 0x00000000, /* var[20] */ +- 0x00000000, /* var[21] */ +- 0x00000000, /* var[22] */ +- 0x00000000, /* var[23] */ +- 0xe0000000, /* inc[0] */ +- 0x20000000, /* inc[1] */ +- 0x2000ffff, /* inc[2] */ +- 0x00000000, /* inc[3] */ +- 0x00000000, /* inc[4] */ +- 0x00000000, /* inc[5] */ +- 0x00000000, /* inc[6] */ +- 0x00000000, /* inc[7] */ +-}; +- +-u32 MCD_funcDescTab0[]= +-{ /* Task 0 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-#ifdef MCD_INCLUDE_EU +-u32 MCD_funcDescTab1[]= +-{ /* Task 1 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab2[]= +-{ /* Task 2 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab3[]= +-{ /* Task 3 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab4[]= +-{ /* Task 4 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab5[]= +-{ /* Task 5 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab6[]= +-{ /* Task 6 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab7[]= +-{ /* Task 7 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab8[]= +-{ /* Task 8 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab9[]= +-{ /* Task 9 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab10[]= +-{ /* Task 10 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab11[]= +-{ /* Task 11 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab12[]= +-{ /* Task 12 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab13[]= +-{ /* Task 13 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab14[]= +-{ /* Task 14 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +- +-u32 MCD_funcDescTab15[]= +-{ /* Task 15 Function Descriptor Table */ +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0xa0045670, /* mainFunc(), EU# 3 */ +- 0xa0000000, /* rsduFunc(), EU# 3 */ +- 0xa0000000, /* crcAccumVal(), EU# 3 */ +- 0x20000000, /* setCrcAccum(), EU# 3 */ +- 0x21800000, /* and(), EU# 3 */ +- 0x21e00000, /* or(), EU# 3 */ +- 0x20400000, /* add(), EU# 3 */ +- 0x20500000, /* sub(), EU# 3 */ +- 0x205a0000, /* andNot(), EU# 3 */ +- 0x20a00000, /* shiftR(), EU# 3 */ +- 0x202fa000, /* andReadyBit(), EU# 3 */ +- 0x202f9000, /* andNotReadyBit(), EU# 3 */ +- 0x202ea000, /* andWrapBit(), EU# 3 */ +- 0x202da000, /* andLastBit(), EU# 3 */ +- 0x202e2000, /* andInterruptBit(), EU# 3 */ +- 0x202f2000, /* andCrcRestartBit(), EU# 3 */ +-}; +-#endif /*MCD_INCLUDE_EU*/ +- +-u32 MCD_contextSave0[128]; /* Task 0 context save space */ +-u32 MCD_contextSave1[128]; /* Task 1 context save space */ +-u32 MCD_contextSave2[128]; /* Task 2 context save space */ +-u32 MCD_contextSave3[128]; /* Task 3 context save space */ +-u32 MCD_contextSave4[128]; /* Task 4 context save space */ +-u32 MCD_contextSave5[128]; /* Task 5 context save space */ +-u32 MCD_contextSave6[128]; /* Task 6 context save space */ +-u32 MCD_contextSave7[128]; /* Task 7 context save space */ +-u32 MCD_contextSave8[128]; /* Task 8 context save space */ +-u32 MCD_contextSave9[128]; /* Task 9 context save space */ +-u32 MCD_contextSave10[128]; /* Task 10 context save space */ +-u32 MCD_contextSave11[128]; /* Task 11 context save space */ +-u32 MCD_contextSave12[128]; /* Task 12 context save space */ +-u32 MCD_contextSave13[128]; /* Task 13 context save space */ +-u32 MCD_contextSave14[128]; /* Task 14 context save space */ +-u32 MCD_contextSave15[128]; /* Task 15 context save space */ +- +- +-u32 MCD_ChainNoEu_TDT[]; +-u32 MCD_SingleNoEu_TDT[]; +-#ifdef MCD_INCLUDE_EU +-u32 MCD_ChainEu_TDT[]; +-u32 MCD_SingleEu_TDT[]; +-#endif +-u32 MCD_ENetRcv_TDT[]; +-u32 MCD_ENetXmit_TDT[]; +- +-u32 MCD_modelTaskTableSrc[]= +-{ +- (u32)MCD_ChainNoEu_TDT, +- (u32)&((u8*)MCD_ChainNoEu_TDT)[0x0000016c], +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_SingleNoEu_TDT, +- (u32)&((u8*)MCD_SingleNoEu_TDT)[0x000000d4], +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-#ifdef MCD_INCLUDE_EU +- (u32)MCD_ChainEu_TDT, +- (u32)&((u8*)MCD_ChainEu_TDT)[0x000001b4], +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_SingleEu_TDT, +- (u32)&((u8*)MCD_SingleEu_TDT)[0x00000124], +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-#endif +- (u32)MCD_ENetRcv_TDT, +- (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c], +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- (u32)MCD_ENetXmit_TDT, +- (u32)&((u8*)MCD_ENetXmit_TDT)[0x000000d0], +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +- 0x00000000, +-}; +-u32 MCD_ChainNoEu_TDT[]= +-{ +- 0x80004000, /* 0000(:370): LCDEXT: idx0 = 0x00000000; ; */ +- 0x8118801b, /* 0004(:370): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */ +- 0xb8c60018, /* 0008(:371): LCD: idx2 = *(idx1 + var12); idx2 once var0; idx2 += inc3 */ +- 0x10002b10, /* 000C(:372): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x7000000d, /* 0010(:373): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ +- 0x018cf89f, /* 0014(:373): DRD2B1: var6 = EU3(); EU3(idx2) */ +- 0x6000000a, /* 0018(:374): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ +- 0x080cf89f, /* 001C(:374): DRD2B1: idx0 = EU3(); EU3(idx2) */ +- 0x000001f8, /* 0020(:0): NOP */ +- 0x98180364, /* 0024(:378): LCD: idx0 = idx0; idx0 == var13; idx0 += inc4 */ +- 0x8118801b, /* 0028(:380): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */ +- 0xf8c6001a, /* 002C(:381): LCDEXT: idx2 = *(idx1 + var12 + 8); idx2 once var0; idx2 += inc3 */ +- 0xb8c6601b, /* 0030(:382): LCD: idx3 = *(idx1 + var12 + 12); ; idx3 += inc3 */ +- 0x10002710, /* 0034(:384): DRD1A: var9 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x00000f18, /* 0038(:385): DRD1A: var3 = idx3; FN=0 init=0 WS=0 RS=0 */ +- 0xb8c6001d, /* 003C(:387): LCD: idx2 = *(idx1 + var12 + 20); idx2 once var0; idx2 += inc3 */ +- 0x10001310, /* 0040(:388): DRD1A: var4 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x60000007, /* 0044(:389): DRD2A: EU0=0 EU1=0 EU2=0 EU3=7 EXT init=0 WS=0 RS=0 */ +- 0x014cf88b, /* 0048(:389): DRD2B1: var5 = EU3(); EU3(idx2,var11) */ +- 0x98c6001c, /* 004C(:391): LCD: idx2 = idx1 + var12 + 4; idx2 once var0; idx2 += inc3 */ +- 0x00000710, /* 0050(:392): DRD1A: var1 = idx2; FN=0 init=0 WS=0 RS=0 */ +- 0x98c70018, /* 0054(:393): LCD: idx2 = idx1 + var14; idx2 once var0; idx2 += inc3 */ +- 0x10001f10, /* 0058(:394): DRD1A: var7 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x0000c818, /* 005C(:395): DRD1A: *idx2 = var3; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 0060(:0): NOP */ +- 0xc1476018, /* 0064(:399): LCDEXT: idx1 = var2 + var14; ; idx1 += inc3 */ +- 0xc003231d, /* 0068(:399): LCDEXT: idx2 = var0, idx3 = var6; idx3 == var12; idx2 += inc3, idx3 += inc5 */ +- 0x811a601b, /* 006C(:400): LCD: idx4 = var2; ; idx4 += inc3 */ +- 0xc1862102, /* 0070(:403): LCDEXT: idx5 = var3, idx6 = var12; idx6 < var4; idx5 += inc0, idx6 += inc2 */ +- 0x849be009, /* 0074(:403): LCD: idx7 = var9; ; idx7 += inc1 */ +- 0x03fed7b8, /* 0078(:406): DRD1A: *idx7; FN=0 init=31 WS=3 RS=3 */ +- 0xda9b001b, /* 007C(:408): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 0080(:408): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x1000cb20, /* 0084(:409): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 0088(:410): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88f, /* 008C(:410): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ +- 0x1000cb28, /* 0090(:411): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 0094(:412): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88f, /* 0098(:412): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ +- 0x1000cb30, /* 009C(:413): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00A0(:414): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88f, /* 00A4(:414): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ +- 0x1000cb38, /* 00A8(:415): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x0000c728, /* 00AC(:416): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 00B0(:0): NOP */ +- 0xc1476018, /* 00B4(:420): LCDEXT: idx1 = var2 + var14; ; idx1 += inc3 */ +- 0xc003241d, /* 00B8(:420): LCDEXT: idx2 = var0, idx3 = var6; idx3 == var16; idx2 += inc3, idx3 += inc5 */ +- 0x811a601b, /* 00BC(:421): LCD: idx4 = var2; ; idx4 += inc3 */ +- 0xda9b001b, /* 00C0(:424): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 00C4(:424): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x0000d3a0, /* 00C8(:425): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */ +- 0xc1862102, /* 00CC(:427): LCDEXT: idx5 = var3, idx6 = var12; idx6 < var4; idx5 += inc0, idx6 += inc2 */ +- 0x849be009, /* 00D0(:427): LCD: idx7 = var9; ; idx7 += inc1 */ +- 0x0bfed7b8, /* 00D4(:430): DRD1A: *idx7; FN=0 TFD init=31 WS=3 RS=3 */ +- 0xda9b001b, /* 00D8(:432): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 00DC(:432): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x1000cb20, /* 00E0(:433): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00E4(:434): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88f, /* 00E8(:434): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ +- 0x1000cb28, /* 00EC(:435): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00F0(:436): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88f, /* 00F4(:436): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ +- 0x1000cb30, /* 00F8(:437): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00FC(:438): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88f, /* 0100(:438): DRD2B1: idx2 = EU3(); EU3(idx2,var15) */ +- 0x1000cb38, /* 0104(:439): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x0000c728, /* 0108(:440): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 010C(:0): NOP */ +- 0x8118801b, /* 0110(:444): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */ +- 0xd8c60018, /* 0114(:446): LCDEXT: idx2 = idx1 + var12; idx2 once var0; idx2 += inc3 */ +- 0x98c6601c, /* 0118(:446): LCD: idx3 = idx1 + var12 + 4; ; idx3 += inc3 */ +- 0x6000000b, /* 011C(:447): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */ +- 0x0c8cfc9f, /* 0120(:447): DRD2B1: *idx2 = EU3(); EU3(*idx2) */ +- 0x000001f8, /* 0124(:0): NOP */ +- 0xa146001e, /* 0128(:450): LCD: idx1 = *(var2 + var12 + 24); idx1 once var0; idx1 += inc3 */ +- 0x10000b08, /* 012C(:451): DRD1A: var2 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x10002050, /* 0130(:452): DRD1A: var8 = var10; FN=0 MORE init=0 WS=0 RS=0 */ +- 0xb8c60018, /* 0134(:453): LCD: idx2 = *(idx1 + var12); idx2 once var0; idx2 += inc3 */ +- 0x10002b10, /* 0138(:454): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x7000000a, /* 013C(:455): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT MORE init=0 WS=0 RS=0 */ +- 0x080cf89f, /* 0140(:455): DRD2B1: idx0 = EU3(); EU3(idx2) */ +- 0x6000000d, /* 0144(:456): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */ +- 0x018cf89f, /* 0148(:456): DRD2B1: var6 = EU3(); EU3(idx2) */ +- 0x000001f8, /* 014C(:0): NOP */ +- 0x8618801b, /* 0150(:462): LCD: idx1 = var12; idx1 once var0; idx1 += inc3 */ +- 0x7000000e, /* 0154(:463): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */ +- 0x084cf21f, /* 0158(:463): DRD2B1: idx1 = EU3(); EU3(var8) */ +- 0xd8990336, /* 015C(:464): LCDEXT: idx2 = idx1; idx2 > var12; idx2 += inc6 */ +- 0x8019801b, /* 0160(:464): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */ +- 0x040001f8, /* 0164(:465): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ +- 0x000001f8, /* 0168(:0): NOP */ +- 0x000001f8, /* 016C(:0): NOP */ +-}; +-u32 MCD_SingleNoEu_TDT[]= +-{ +- 0x8198001b, /* 0000(:657): LCD: idx0 = var3; idx0 once var0; idx0 += inc3 */ +- 0x7000000d, /* 0004(:658): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ +- 0x080cf81f, /* 0008(:658): DRD2B1: idx0 = EU3(); EU3(idx0) */ +- 0x8198801b, /* 000C(:659): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ +- 0x6000000e, /* 0010(:660): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */ +- 0x084cf85f, /* 0014(:660): DRD2B1: idx1 = EU3(); EU3(idx1) */ +- 0x000001f8, /* 0018(:0): NOP */ +- 0x8298001b, /* 001C(:664): LCD: idx0 = var5; idx0 once var0; idx0 += inc3 */ +- 0x7000000d, /* 0020(:665): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ +- 0x010cf81f, /* 0024(:665): DRD2B1: var4 = EU3(); EU3(idx0) */ +- 0x6000000e, /* 0028(:666): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */ +- 0x018cf81f, /* 002C(:666): DRD2B1: var6 = EU3(); EU3(idx0) */ +- 0xc202601b, /* 0030(:669): LCDEXT: idx0 = var4, idx1 = var4; ; idx0 += inc3, idx1 += inc3 */ +- 0xc002221c, /* 0034(:669): LCDEXT: idx2 = var0, idx3 = var4; idx3 == var8; idx2 += inc3, idx3 += inc4 */ +- 0x809a601b, /* 0038(:670): LCD: idx4 = var1; ; idx4 += inc3 */ +- 0xc10420c2, /* 003C(:673): LCDEXT: idx5 = var2, idx6 = var8; idx6 < var3; idx5 += inc0, idx6 += inc2 */ +- 0x839be009, /* 0040(:673): LCD: idx7 = var7; ; idx7 += inc1 */ +- 0x03fed7b8, /* 0044(:676): DRD1A: *idx7; FN=0 init=31 WS=3 RS=3 */ +- 0xda9b001b, /* 0048(:678): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 004C(:678): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x70000006, /* 0050(:680): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf889, /* 0054(:680): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ +- 0x1000cb28, /* 0058(:681): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 005C(:682): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf889, /* 0060(:682): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ +- 0x1000cb30, /* 0064(:683): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 0068(:684): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf889, /* 006C(:684): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ +- 0x0000cb38, /* 0070(:685): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 0074(:0): NOP */ +- 0xc202601b, /* 0078(:689): LCDEXT: idx0 = var4, idx1 = var4; ; idx0 += inc3, idx1 += inc3 */ +- 0xc002229c, /* 007C(:689): LCDEXT: idx2 = var0, idx3 = var4; idx3 == var10; idx2 += inc3, idx3 += inc4 */ +- 0x809a601b, /* 0080(:690): LCD: idx4 = var1; ; idx4 += inc3 */ +- 0xda9b001b, /* 0084(:693): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 0088(:693): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x0000d3a0, /* 008C(:694): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */ +- 0xc10420c2, /* 0090(:696): LCDEXT: idx5 = var2, idx6 = var8; idx6 < var3; idx5 += inc0, idx6 += inc2 */ +- 0x839be009, /* 0094(:696): LCD: idx7 = var7; ; idx7 += inc1 */ +- 0x0bfed7b8, /* 0098(:699): DRD1A: *idx7; FN=0 TFD init=31 WS=3 RS=3 */ +- 0xda9b001b, /* 009C(:701): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 00A0(:701): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x70000006, /* 00A4(:703): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf889, /* 00A8(:703): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ +- 0x1000cb28, /* 00AC(:704): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00B0(:705): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf889, /* 00B4(:705): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ +- 0x1000cb30, /* 00B8(:706): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00BC(:707): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf889, /* 00C0(:707): DRD2B1: idx2 = EU3(); EU3(idx2,var9) */ +- 0x0000cb38, /* 00C4(:708): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 00C8(:0): NOP */ +- 0xc318022d, /* 00CC(:712): LCDEXT: idx0 = var6; idx0 > var8; idx0 += inc5 */ +- 0x8018801b, /* 00D0(:712): LCD: idx1 = var0; idx1 once var0; idx1 += inc3 */ +- 0x040001f8, /* 00D4(:713): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ +-}; +-#ifdef MCD_INCLUDE_EU +-u32 MCD_ChainEu_TDT[]= +-{ +- 0x80004000, /* 0000(:947): LCDEXT: idx0 = 0x00000000; ; */ +- 0x8198801b, /* 0004(:947): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ +- 0xb8c68018, /* 0008(:948): LCD: idx2 = *(idx1 + var13); idx2 once var0; idx2 += inc3 */ +- 0x10002f10, /* 000C(:949): DRD1A: var11 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x7000000d, /* 0010(:950): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ +- 0x01ccf89f, /* 0014(:950): DRD2B1: var7 = EU3(); EU3(idx2) */ +- 0x6000000a, /* 0018(:951): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ +- 0x080cf89f, /* 001C(:951): DRD2B1: idx0 = EU3(); EU3(idx2) */ +- 0x000001f8, /* 0020(:0): NOP */ +- 0x981803a4, /* 0024(:955): LCD: idx0 = idx0; idx0 == var14; idx0 += inc4 */ +- 0x8198801b, /* 0028(:957): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ +- 0xf8c6801a, /* 002C(:958): LCDEXT: idx2 = *(idx1 + var13 + 8); idx2 once var0; idx2 += inc3 */ +- 0xb8c6e01b, /* 0030(:959): LCD: idx3 = *(idx1 + var13 + 12); ; idx3 += inc3 */ +- 0x10002b10, /* 0034(:961): DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x00001318, /* 0038(:962): DRD1A: var4 = idx3; FN=0 init=0 WS=0 RS=0 */ +- 0xb8c6801d, /* 003C(:964): LCD: idx2 = *(idx1 + var13 + 20); idx2 once var0; idx2 += inc3 */ +- 0x10001710, /* 0040(:965): DRD1A: var5 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x60000007, /* 0044(:966): DRD2A: EU0=0 EU1=0 EU2=0 EU3=7 EXT init=0 WS=0 RS=0 */ +- 0x018cf88c, /* 0048(:966): DRD2B1: var6 = EU3(); EU3(idx2,var12) */ +- 0x98c6801c, /* 004C(:968): LCD: idx2 = idx1 + var13 + 4; idx2 once var0; idx2 += inc3 */ +- 0x00000b10, /* 0050(:969): DRD1A: var2 = idx2; FN=0 init=0 WS=0 RS=0 */ +- 0x98c78018, /* 0054(:970): LCD: idx2 = idx1 + var15; idx2 once var0; idx2 += inc3 */ +- 0x10002310, /* 0058(:971): DRD1A: var8 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x0000c820, /* 005C(:972): DRD1A: *idx2 = var4; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 0060(:0): NOP */ +- 0x8698801b, /* 0064(:976): LCD: idx1 = var13; idx1 once var0; idx1 += inc3 */ +- 0x7000000f, /* 0068(:977): DRD2A: EU0=0 EU1=0 EU2=0 EU3=15 EXT MORE init=0 WS=0 RS=0 */ +- 0x084cf2df, /* 006C(:977): DRD2B1: idx1 = EU3(); EU3(var11) */ +- 0xd899042d, /* 0070(:978): LCDEXT: idx2 = idx1; idx2 >= var16; idx2 += inc5 */ +- 0x8019801b, /* 0074(:978): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */ +- 0x60000003, /* 0078(:979): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */ +- 0x2cd7c7df, /* 007C(:979): DRD2B2: EU3(var13) */ +- 0xd8990364, /* 0080(:980): LCDEXT: idx2 = idx1; idx2 == var13; idx2 += inc4 */ +- 0x8019801b, /* 0084(:980): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */ +- 0x60000003, /* 0088(:981): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */ +- 0x2c17c7df, /* 008C(:981): DRD2B2: EU3(var1) */ +- 0x000001f8, /* 0090(:0): NOP */ +- 0xc1c7e018, /* 0094(:984): LCDEXT: idx1 = var3 + var15; ; idx1 += inc3 */ +- 0xc003a35e, /* 0098(:984): LCDEXT: idx2 = var0, idx3 = var7; idx3 == var13; idx2 += inc3, idx3 += inc6 */ +- 0x819a601b, /* 009C(:985): LCD: idx4 = var3; ; idx4 += inc3 */ +- 0xc206a142, /* 00A0(:988): LCDEXT: idx5 = var4, idx6 = var13; idx6 < var5; idx5 += inc0, idx6 += inc2 */ +- 0x851be009, /* 00A4(:988): LCD: idx7 = var10; ; idx7 += inc1 */ +- 0x63fe0000, /* 00A8(:991): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=31 WS=3 RS=3 */ +- 0x0d4cfddf, /* 00AC(:991): DRD2B1: *idx5 = EU3(); EU3(*idx7) */ +- 0xda9b001b, /* 00B0(:993): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 00B4(:993): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x70000002, /* 00B8(:994): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */ +- 0x004cf81f, /* 00BC(:994): DRD2B1: var1 = EU3(); EU3(idx0) */ +- 0x1000cb20, /* 00C0(:995): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00C4(:996): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf891, /* 00C8(:996): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ +- 0x1000cb28, /* 00CC(:997): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00D0(:998): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf891, /* 00D4(:998): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ +- 0x1000cb30, /* 00D8(:999): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00DC(:1000): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf891, /* 00E0(:1000): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ +- 0x1000cb38, /* 00E4(:1001): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x0000c728, /* 00E8(:1002): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 00EC(:0): NOP */ +- 0xc1c7e018, /* 00F0(:1006): LCDEXT: idx1 = var3 + var15; ; idx1 += inc3 */ +- 0xc003a49e, /* 00F4(:1006): LCDEXT: idx2 = var0, idx3 = var7; idx3 == var18; idx2 += inc3, idx3 += inc6 */ +- 0x819a601b, /* 00F8(:1007): LCD: idx4 = var3; ; idx4 += inc3 */ +- 0xda9b001b, /* 00FC(:1010): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 0100(:1010): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x0000d3a0, /* 0104(:1011): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */ +- 0xc206a142, /* 0108(:1013): LCDEXT: idx5 = var4, idx6 = var13; idx6 < var5; idx5 += inc0, idx6 += inc2 */ +- 0x851be009, /* 010C(:1013): LCD: idx7 = var10; ; idx7 += inc1 */ +- 0x6bfe0000, /* 0110(:1016): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 TFD EXT init=31 WS=3 RS=3 */ +- 0x0d4cfddf, /* 0114(:1016): DRD2B1: *idx5 = EU3(); EU3(*idx7) */ +- 0xda9b001b, /* 0118(:1018): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 011C(:1018): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x70000002, /* 0120(:1019): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */ +- 0x004cf81f, /* 0124(:1019): DRD2B1: var1 = EU3(); EU3(idx0) */ +- 0x1000cb20, /* 0128(:1020): DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 012C(:1021): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf891, /* 0130(:1021): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ +- 0x1000cb28, /* 0134(:1022): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 0138(:1023): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf891, /* 013C(:1023): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ +- 0x1000cb30, /* 0140(:1024): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 0144(:1025): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf891, /* 0148(:1025): DRD2B1: idx2 = EU3(); EU3(idx2,var17) */ +- 0x1000cb38, /* 014C(:1026): DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x0000c728, /* 0150(:1027): DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 0154(:0): NOP */ +- 0x8198801b, /* 0158(:1031): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */ +- 0xd8c68018, /* 015C(:1033): LCDEXT: idx2 = idx1 + var13; idx2 once var0; idx2 += inc3 */ +- 0x98c6e01c, /* 0160(:1033): LCD: idx3 = idx1 + var13 + 4; ; idx3 += inc3 */ +- 0x6000000b, /* 0164(:1034): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */ +- 0x0c8cfc9f, /* 0168(:1034): DRD2B1: *idx2 = EU3(); EU3(*idx2) */ +- 0x0000cc08, /* 016C(:1035): DRD1A: *idx3 = var1; FN=0 init=0 WS=0 RS=0 */ +- 0xa1c6801e, /* 0170(:1038): LCD: idx1 = *(var3 + var13 + 24); idx1 once var0; idx1 += inc3 */ +- 0x10000f08, /* 0174(:1039): DRD1A: var3 = idx1; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x10002458, /* 0178(:1040): DRD1A: var9 = var11; FN=0 MORE init=0 WS=0 RS=0 */ +- 0xb8c68018, /* 017C(:1041): LCD: idx2 = *(idx1 + var13); idx2 once var0; idx2 += inc3 */ +- 0x10002f10, /* 0180(:1042): DRD1A: var11 = idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x7000000a, /* 0184(:1043): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT MORE init=0 WS=0 RS=0 */ +- 0x080cf89f, /* 0188(:1043): DRD2B1: idx0 = EU3(); EU3(idx2) */ +- 0x6000000d, /* 018C(:1044): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */ +- 0x01ccf89f, /* 0190(:1044): DRD2B1: var7 = EU3(); EU3(idx2) */ +- 0x000001f8, /* 0194(:0): NOP */ +- 0x8698801b, /* 0198(:1050): LCD: idx1 = var13; idx1 once var0; idx1 += inc3 */ +- 0x7000000e, /* 019C(:1051): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */ +- 0x084cf25f, /* 01A0(:1051): DRD2B1: idx1 = EU3(); EU3(var9) */ +- 0xd899037f, /* 01A4(:1052): LCDEXT: idx2 = idx1; idx2 > var13; idx2 += inc7 */ +- 0x8019801b, /* 01A8(:1052): LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */ +- 0x040001f8, /* 01AC(:1053): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ +- 0x000001f8, /* 01B0(:0): NOP */ +- 0x000001f8, /* 01B4(:0): NOP */ +-}; +-u32 MCD_SingleEu_TDT[]= +-{ +- 0x8218001b, /* 0000(:1248): LCD: idx0 = var4; idx0 once var0; idx0 += inc3 */ +- 0x7000000d, /* 0004(:1249): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ +- 0x080cf81f, /* 0008(:1249): DRD2B1: idx0 = EU3(); EU3(idx0) */ +- 0x8218801b, /* 000C(:1250): LCD: idx1 = var4; idx1 once var0; idx1 += inc3 */ +- 0x6000000e, /* 0010(:1251): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */ +- 0x084cf85f, /* 0014(:1251): DRD2B1: idx1 = EU3(); EU3(idx1) */ +- 0x000001f8, /* 0018(:0): NOP */ +- 0x8318001b, /* 001C(:1255): LCD: idx0 = var6; idx0 once var0; idx0 += inc3 */ +- 0x7000000d, /* 0020(:1256): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ +- 0x014cf81f, /* 0024(:1256): DRD2B1: var5 = EU3(); EU3(idx0) */ +- 0x6000000e, /* 0028(:1257): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */ +- 0x01ccf81f, /* 002C(:1257): DRD2B1: var7 = EU3(); EU3(idx0) */ +- 0x8498001b, /* 0030(:1260): LCD: idx0 = var9; idx0 once var0; idx0 += inc3 */ +- 0x7000000f, /* 0034(:1261): DRD2A: EU0=0 EU1=0 EU2=0 EU3=15 EXT MORE init=0 WS=0 RS=0 */ +- 0x080cf19f, /* 0038(:1261): DRD2B1: idx0 = EU3(); EU3(var6) */ +- 0xd81882a4, /* 003C(:1262): LCDEXT: idx1 = idx0; idx1 >= var10; idx1 += inc4 */ +- 0x8019001b, /* 0040(:1262): LCD: idx2 = var0; idx2 once var0; idx2 += inc3 */ +- 0x60000003, /* 0044(:1263): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */ +- 0x2c97c7df, /* 0048(:1263): DRD2B2: EU3(var9) */ +- 0xd818826d, /* 004C(:1264): LCDEXT: idx1 = idx0; idx1 == var9; idx1 += inc5 */ +- 0x8019001b, /* 0050(:1264): LCD: idx2 = var0; idx2 once var0; idx2 += inc3 */ +- 0x60000003, /* 0054(:1265): DRD2A: EU0=0 EU1=0 EU2=0 EU3=3 EXT init=0 WS=0 RS=0 */ +- 0x2c17c7df, /* 0058(:1265): DRD2B2: EU3(var1) */ +- 0x000001f8, /* 005C(:0): NOP */ +- 0xc282e01b, /* 0060(:1268): LCDEXT: idx0 = var5, idx1 = var5; ; idx0 += inc3, idx1 += inc3 */ +- 0xc002a25e, /* 0064(:1268): LCDEXT: idx2 = var0, idx3 = var5; idx3 == var9; idx2 += inc3, idx3 += inc6 */ +- 0x811a601b, /* 0068(:1269): LCD: idx4 = var2; ; idx4 += inc3 */ +- 0xc184a102, /* 006C(:1272): LCDEXT: idx5 = var3, idx6 = var9; idx6 < var4; idx5 += inc0, idx6 += inc2 */ +- 0x841be009, /* 0070(:1272): LCD: idx7 = var8; ; idx7 += inc1 */ +- 0x63fe0000, /* 0074(:1275): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=31 WS=3 RS=3 */ +- 0x0d4cfddf, /* 0078(:1275): DRD2B1: *idx5 = EU3(); EU3(*idx7) */ +- 0xda9b001b, /* 007C(:1277): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 0080(:1277): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x70000002, /* 0084(:1279): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */ +- 0x004cf99f, /* 0088(:1279): DRD2B1: var1 = EU3(); EU3(idx6) */ +- 0x70000006, /* 008C(:1280): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88b, /* 0090(:1280): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ +- 0x1000cb28, /* 0094(:1281): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 0098(:1282): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88b, /* 009C(:1282): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ +- 0x1000cb30, /* 00A0(:1283): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00A4(:1284): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88b, /* 00A8(:1284): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ +- 0x0000cb38, /* 00AC(:1285): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 00B0(:0): NOP */ +- 0xc282e01b, /* 00B4(:1289): LCDEXT: idx0 = var5, idx1 = var5; ; idx0 += inc3, idx1 += inc3 */ +- 0xc002a31e, /* 00B8(:1289): LCDEXT: idx2 = var0, idx3 = var5; idx3 == var12; idx2 += inc3, idx3 += inc6 */ +- 0x811a601b, /* 00BC(:1290): LCD: idx4 = var2; ; idx4 += inc3 */ +- 0xda9b001b, /* 00C0(:1293): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 00C4(:1293): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x0000d3a0, /* 00C8(:1294): DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */ +- 0xc184a102, /* 00CC(:1296): LCDEXT: idx5 = var3, idx6 = var9; idx6 < var4; idx5 += inc0, idx6 += inc2 */ +- 0x841be009, /* 00D0(:1296): LCD: idx7 = var8; ; idx7 += inc1 */ +- 0x6bfe0000, /* 00D4(:1299): DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 TFD EXT init=31 WS=3 RS=3 */ +- 0x0d4cfddf, /* 00D8(:1299): DRD2B1: *idx5 = EU3(); EU3(*idx7) */ +- 0xda9b001b, /* 00DC(:1301): LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */ +- 0x9b9be01b, /* 00E0(:1301): LCD: idx7 = idx7; ; idx7 += inc3 */ +- 0x70000002, /* 00E4(:1303): DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT MORE init=0 WS=0 RS=0 */ +- 0x004cf99f, /* 00E8(:1303): DRD2B1: var1 = EU3(); EU3(idx6) */ +- 0x70000006, /* 00EC(:1304): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88b, /* 00F0(:1304): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ +- 0x1000cb28, /* 00F4(:1305): DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 00F8(:1306): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88b, /* 00FC(:1306): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ +- 0x1000cb30, /* 0100(:1307): DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x70000006, /* 0104(:1308): DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */ +- 0x088cf88b, /* 0108(:1308): DRD2B1: idx2 = EU3(); EU3(idx2,var11) */ +- 0x0000cb38, /* 010C(:1309): DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */ +- 0x000001f8, /* 0110(:0): NOP */ +- 0x8144801c, /* 0114(:1312): LCD: idx0 = var2 + var9 + 4; idx0 once var0; idx0 += inc3 */ +- 0x0000c008, /* 0118(:1313): DRD1A: *idx0 = var1; FN=0 init=0 WS=0 RS=0 */ +- 0xc398027f, /* 011C(:1315): LCDEXT: idx0 = var7; idx0 > var9; idx0 += inc7 */ +- 0x8018801b, /* 0120(:1315): LCD: idx1 = var0; idx1 once var0; idx1 += inc3 */ +- 0x040001f8, /* 0124(:1316): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ +-}; +-#endif +-u32 MCD_ENetRcv_TDT[]= +-{ +- 0x80004000, /* 0000(:1389): LCDEXT: idx0 = 0x00000000; ; */ +- 0x81988000, /* 0004(:1389): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +- 0x10000788, /* 0008(:1390): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x6000000a, /* 000C(:1391): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ +- 0x080cf05f, /* 0010(:1391): DRD2B1: idx0 = EU3(); EU3(var1) */ +- 0x98180209, /* 0014(:1394): LCD: idx0 = idx0; idx0 != var8; idx0 += inc1 */ +- 0x81c40004, /* 0018(:1396): LCD: idx1 = var3 + var8 + 4; idx1 once var0; idx1 += inc0 */ +- 0x7000000e, /* 001C(:1397): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */ +- 0x010cf05f, /* 0020(:1397): DRD2B1: var4 = EU3(); EU3(var1) */ +- 0x7000000c, /* 0024(:1398): DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */ +- 0x01ccf05f, /* 0028(:1398): DRD2B1: var7 = EU3(); EU3(var1) */ +- 0x70000004, /* 002C(:1399): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */ +- 0x014cf049, /* 0030(:1399): DRD2B1: var5 = EU3(); EU3(var1,var9) */ +- 0x70000004, /* 0034(:1400): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */ +- 0x004cf04a, /* 0038(:1400): DRD2B1: var1 = EU3(); EU3(var1,var10) */ +- 0x00000b88, /* 003C(:1403): DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */ +- 0xc4030150, /* 0040(:1406): LCDEXT: idx1 = var8, idx2 = var6; idx1 < var5; idx1 += inc2, idx2 += inc0 */ +- 0x8119e012, /* 0044(:1406): LCD: idx3 = var2; ; idx3 += inc2 */ +- 0x03e0cf90, /* 0048(:1409): DRD1A: *idx3 = *idx2; FN=0 init=31 WS=0 RS=0 */ +- 0x81188000, /* 004C(:1412): LCD: idx1 = var2; idx1 once var0; idx1 += inc0 */ +- 0x000ac788, /* 0050(:1413): DRD1A: *idx1 = *idx1; FN=0 init=0 WS=1 RS=1 */ +- 0xc4030000, /* 0054(:1415): LCDEXT: idx1 = var8, idx2 = var6; idx1 once var0; idx1 += inc0, idx2 += inc0 */ +- 0x8199e000, /* 0058(:1415): LCD: idx3 = var3; ; idx3 += inc0 */ +- 0x70000004, /* 005C(:1421): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */ +- 0x084cfc8b, /* 0060(:1421): DRD2B1: idx1 = EU3(); EU3(*idx2,var11) */ +- 0x60000005, /* 0064(:1422): DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */ +- 0x0cccf841, /* 0068(:1422): DRD2B1: *idx3 = EU3(); EU3(idx1,var1) */ +- 0x81c60000, /* 006C(:1428): LCD: idx1 = var3 + var12; idx1 once var0; idx1 += inc0 */ +- 0xc399021b, /* 0070(:1430): LCDEXT: idx2 = var7; idx2 > var8; idx2 += inc3 */ +- 0x80198000, /* 0074(:1430): LCD: idx3 = var0; idx3 once var0; idx3 += inc0 */ +- 0x00008400, /* 0078(:1431): DRD1A: idx1 = var0; FN=0 init=0 WS=0 RS=0 */ +- 0x00000f08, /* 007C(:1432): DRD1A: var3 = idx1; FN=0 init=0 WS=0 RS=0 */ +- 0x81988000, /* 0080(:1435): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +- 0x10000788, /* 0084(:1436): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x6000000a, /* 0088(:1437): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ +- 0x080cf05f, /* 008C(:1437): DRD2B1: idx0 = EU3(); EU3(var1) */ +- 0xc2188209, /* 0090(:1440): LCDEXT: idx1 = var4; idx1 != var8; idx1 += inc1 */ +- 0x80190000, /* 0094(:1440): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +- 0x040001f8, /* 0098(:1441): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ +- 0x000001f8, /* 009C(:0): NOP */ +-}; +-u32 MCD_ENetXmit_TDT[]= +-{ +- 0x80004000, /* 0000(:1516): LCDEXT: idx0 = 0x00000000; ; */ +- 0x81988000, /* 0004(:1516): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +- 0x10000788, /* 0008(:1517): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x6000000a, /* 000C(:1518): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ +- 0x080cf05f, /* 0010(:1518): DRD2B1: idx0 = EU3(); EU3(var1) */ +- 0x98180309, /* 0014(:1521): LCD: idx0 = idx0; idx0 != var12; idx0 += inc1 */ +- 0x80004003, /* 0018(:1523): LCDEXT: idx1 = 0x00000003; ; */ +- 0x81c60004, /* 001C(:1523): LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */ +- 0x7000000e, /* 0020(:1524): DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT MORE init=0 WS=0 RS=0 */ +- 0x014cf05f, /* 0024(:1524): DRD2B1: var5 = EU3(); EU3(var1) */ +- 0x7000000c, /* 0028(:1525): DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */ +- 0x028cf05f, /* 002C(:1525): DRD2B1: var10 = EU3(); EU3(var1) */ +- 0x7000000d, /* 0030(:1526): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */ +- 0x018cf05f, /* 0034(:1526): DRD2B1: var6 = EU3(); EU3(var1) */ +- 0x70000004, /* 0038(:1527): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */ +- 0x01ccf04d, /* 003C(:1527): DRD2B1: var7 = EU3(); EU3(var1,var13) */ +- 0x10000b90, /* 0040(:1528): DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x60000004, /* 0044(:1529): DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT init=0 WS=0 RS=0 */ +- 0x020cf0a1, /* 0048(:1529): DRD2B1: var8 = EU3(); EU3(var2,idx1) */ +- 0xc3188312, /* 004C(:1532): LCDEXT: idx1 = var6; idx1 > var12; idx1 += inc2 */ +- 0x83c70000, /* 0050(:1532): LCD: idx2 = var7 + var14; idx2 once var0; idx2 += inc0 */ +- 0x00001f10, /* 0054(:1533): DRD1A: var7 = idx2; FN=0 init=0 WS=0 RS=0 */ +- 0xc583a3c3, /* 0058(:1535): LCDEXT: idx1 = var11, idx2 = var7; idx2 >= var15; idx1 += inc0, idx2 += inc3 */ +- 0x81042325, /* 005C(:1535): LCD: idx3 = var2, idx4 = var8; idx4 == var12; idx3 += inc4, idx4 += inc5 */ +- 0x03e0c798, /* 0060(:1540): DRD1A: *idx1 = *idx3; FN=0 init=31 WS=0 RS=0 */ +- 0xd8990000, /* 0064(:1543): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */ +- 0x9999e000, /* 0068(:1543): LCD: idx3 = idx3; ; idx3 += inc0 */ +- 0x000acf98, /* 006C(:1544): DRD1A: *idx3 = *idx3; FN=0 init=0 WS=1 RS=1 */ +- 0xd8992306, /* 0070(:1546): LCDEXT: idx1 = idx1, idx2 = idx2; idx2 > var12; idx1 += inc0, idx2 += inc6 */ +- 0x9999e03f, /* 0074(:1546): LCD: idx3 = idx3; ; idx3 += inc7 */ +- 0x03eac798, /* 0078(:1549): DRD1A: *idx1 = *idx3; FN=0 init=31 WS=1 RS=1 */ +- 0xd8990000, /* 007C(:1552): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */ +- 0x9999e000, /* 0080(:1552): LCD: idx3 = idx3; ; idx3 += inc0 */ +- 0x000acf98, /* 0084(:1553): DRD1A: *idx3 = *idx3; FN=0 init=0 WS=1 RS=1 */ +- 0xd8990000, /* 0088(:1555): LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */ +- 0x99832302, /* 008C(:1555): LCD: idx3 = idx3, idx4 = var6; idx4 > var12; idx3 += inc0, idx4 += inc2 */ +- 0x0beac798, /* 0090(:1558): DRD1A: *idx1 = *idx3; FN=0 TFD init=31 WS=1 RS=1 */ +- 0x81988000, /* 0094(:1560): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +- 0x6000000b, /* 0098(:1561): DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT init=0 WS=0 RS=0 */ +- 0x0c4cfc5f, /* 009C(:1561): DRD2B1: *idx1 = EU3(); EU3(*idx1) */ +- 0x81c80000, /* 00A0(:1563): LCD: idx1 = var3 + var16; idx1 once var0; idx1 += inc0 */ +- 0xc5190312, /* 00A4(:1565): LCDEXT: idx2 = var10; idx2 > var12; idx2 += inc2 */ +- 0x80198000, /* 00A8(:1565): LCD: idx3 = var0; idx3 once var0; idx3 += inc0 */ +- 0x00008400, /* 00AC(:1566): DRD1A: idx1 = var0; FN=0 init=0 WS=0 RS=0 */ +- 0x00000f08, /* 00B0(:1567): DRD1A: var3 = idx1; FN=0 init=0 WS=0 RS=0 */ +- 0x81988000, /* 00B4(:1570): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */ +- 0x10000788, /* 00B8(:1571): DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */ +- 0x6000000a, /* 00BC(:1572): DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */ +- 0x080cf05f, /* 00C0(:1572): DRD2B1: idx0 = EU3(); EU3(var1) */ +- 0xc2988309, /* 00C4(:1575): LCDEXT: idx1 = var5; idx1 != var12; idx1 += inc1 */ +- 0x80190000, /* 00C8(:1575): LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */ +- 0x040001f8, /* 00CC(:1576): DRD1A: FN=0 INT init=0 WS=0 RS=0 */ +- 0x000001f8, /* 00D0(:0): NOP */ +-}; +- +-#ifdef MCD_INCLUDE_EU +-MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; +-#endif +diff --git a/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasksInit.c b/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasksInit.c +deleted file mode 100644 +index 8d82b47..0000000 +--- a/arch/m68k/mach-mcfv4e/mcdapi/MCD_tasksInit.c ++++ /dev/null +@@ -1,225 +0,0 @@ +-/* +- * File: MCD_tasksInit.c +- * Purpose: Functions for initializing variable tables of different +- * types of tasks. +- * +- * Notes: +- */ +- +-/* +- * Do not edit! +- */ +- +-#include <asm/types.h> +-#include <proc/mcdapi/MCD_dma.h> +- +-extern dmaRegs *MCD_dmaBar; +- +- +-/* +- * Task 0 +- */ +- +-void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) +-{ +- +- MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ +- MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ +- MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ +- MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */ +- MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ +- MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ +- MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ +- MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */ +- MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ +- MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ +- MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ +- MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ +- MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ +- MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ +- MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ +- MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ +- MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */ +- MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */ +- MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ +- MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */ +- MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ +- MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ +- MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */ +- MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */ +- +- /* Set the task's Enable bit in its Task Control Register */ +- MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +-} +- +- +-/* +- * Task 1 +- */ +- +-void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) +-{ +- +- MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */ +- MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ +- MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */ +- MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ +- MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */ +- MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ +- MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */ +- MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */ +- MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ +- MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ +- MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ +- MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ +- MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */ +- MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */ +- MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ +- MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */ +- MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */ +- +- /* Set the task's Enable bit in its Task Control Register */ +- MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +-} +- +- +-/* +- * Task 2 +- */ +- +-void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel) +-{ +- +- MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ +- MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ +- MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ +- MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */ +- MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ +- MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ +- MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ +- MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ +- MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ +- MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ +- MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ +- MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ +- MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ +- MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ +- MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ +- MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */ +- MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */ +- MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */ +- MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */ +- MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */ +- MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */ +- MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */ +- MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ +- MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */ +- MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */ +- MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ +- MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ +- +- /* Set the task's Enable bit in its Task Control Register */ +- MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +-} +- +- +-/* +- * Task 3 +- */ +- +-void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel) +-{ +- +- MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */ +- MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ +- MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */ +- MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ +- MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */ +- MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ +- MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */ +- MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */ +- MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */ +- MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ +- MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ +- MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ +- MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ +- MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */ +- MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */ +- MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */ +- MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */ +- MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */ +- MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ +- MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */ +- MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */ +- +- /* Set the task's Enable bit in its Task Control Register */ +- MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +-} +- +- +-/* +- * Task 4 +- */ +- +-void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel) +-{ +- +- MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ +- MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ +- MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */ +- MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ +- MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ +- MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ +- MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ +- MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ +- MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ +- MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */ +- MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */ +- MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */ +- MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */ +- MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ +- MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ +- MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */ +- MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */ +- +- /* Set the task's Enable bit in its Task Control Register */ +- MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +-} +- +- +-/* +- * Task 5 +- */ +- +-void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel) +-{ +- +- MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */ +- MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */ +- MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */ +- MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */ +- MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */ +- MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */ +- MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */ +- MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */ +- MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */ +- MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */ +- MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */ +- MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */ +- MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */ +- MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */ +- MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */ +- MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */ +- MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */ +- MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */ +- MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */ +- MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */ +- MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */ +- MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */ +- MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */ +- MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */ +- MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */ +- +- /* Set the task's Enable bit in its Task Control Register */ +- MCD_dmaBar->taskControl[channel] |= (u16)0x8000; +-} +diff --git a/arch/m68k/mach-mcfv4e/mcdapi/Makefile b/arch/m68k/mach-mcfv4e/mcdapi/Makefile +deleted file mode 100644 +index 52ddaf8..0000000 +--- a/arch/m68k/mach-mcfv4e/mcdapi/Makefile ++++ /dev/null +@@ -1,26 +0,0 @@ +-# +-# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +-# See file CREDITS for list of people who contributed to this project. +-# +-# This file is part of barebox. +-# +-# barebox is free software: you can redistribute it and/or modify +-# it under the terms of the GNU General Public License as published by +-# the Free Software Foundation, either version 3 of the License, or +-# (at your option) any later version. +-# +-# barebox is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with barebox. If not, see <http://www.gnu.org/licenses/>. +-# +- +-# +-# FreeScale MultiDMA Library +-# +-obj-y += MCD_dmaApi.o MCD_tasks.o MCD_tasksInit.o +- +- +diff --git a/arch/m68k/mach-mcfv4e/mcdapi/ReleaseNotes.txt b/arch/m68k/mach-mcfv4e/mcdapi/ReleaseNotes.txt +deleted file mode 100644 +index bc10e71..0000000 +--- a/arch/m68k/mach-mcfv4e/mcdapi/ReleaseNotes.txt ++++ /dev/null +@@ -1,27 +0,0 @@ +- +-Multi-channel DMA API Release Notes +- +-Version 0.3 +- +-* MCD_INCLUDE_EU functionality supported(microcode changes for all tasks +-except ethernet). +-* Fixed bug when using MCD_END_FRAME which would cause the DMA to transfer +-zero bytes and then complete. +-* Code cleanup. +- +- +-Version 0.2 (Slight Update) +- +-* Modified casts and task table implementations that were causing +-warnings (and even errors on certain compilers) +-* Cosmetic changes to clean up MCD_dmaApi.c and MCD_dma.h +-* Fixed table declarations so that MCD_tasks.c will compile if +- MCD_INCLUDE_EU is defined (Note: EU functionality still not supported) +- +-Version 0.1 (Initial release) +- +-Alpha version +-MCD_INCLUDE_EU functionality not supported. +-MCD_INCLUDE_JBIG not supported. +- +- +diff --git a/arch/m68k/mach-mcfv4e/mcf_clocksource.c b/arch/m68k/mach-mcfv4e/mcf_clocksource.c +deleted file mode 100644 +index 8fb2fba..0000000 +--- a/arch/m68k/mach-mcfv4e/mcf_clocksource.c ++++ /dev/null +@@ -1,138 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Implements the clocksource for Coldfire V4E +- */ +-#include <common.h> +-#include <init.h> +-#include <clock.h> +-#include <mach/mcf54xx-regs.h> +-#include <mach/clocks.h> +-#include <proc/processor.h> //FIXME - move to other file +- +-#ifdef CONFIG_USE_IRQ +- +-static uint32_t mcf_sltirq_hits; // FIXME: test code +- +-static int slt_timer_default_isr(void *not_used, void *t) +-{ +- struct mcf5xxx_slt *slt = MCF_SLT_Address(0); +- if ( MCF_INTC_IPRH | MCF_INTC_IPRH_INT54 ) +- { +- if (slt->SSR & MCF_SLT_SSR_ST) +- { +- slt->SSR = 0UL +- | MCF_SLT_SSR_ST; +- } +- mcf_sltirq_hits++; +- return 1; +- } +- return 0; +-} +-#endif +- +- +-static uint64_t mcf_clocksource_read(void) +-{ +- struct mcf5xxx_slt *slt = MCF_SLT_Address(0); +- uint32_t sltcnt; +- uint64_t rc = 0; +- +- if (slt->SSR & MCF_SLT_SSR_ST) +- { +-#ifndef CONFIG_USE_IRQ +- slt->SSR = 0UL +- | MCF_SLT_SSR_ST; +-#endif +- +- rc = 0xffffffffULL + 1; +- } +- +- sltcnt = 0xffffffffUL - slt->SCNT; +- +- rc += sltcnt; +- +- return rc; +-} +- +- +-static struct clocksource cs = { +- .read = mcf_clocksource_read, +- .mask = 0xffffffff, +- .mult = 1, +- .shift = 0, +-}; +- +-static int clocksource_init (void) +-{ +- struct mcf5xxx_slt *slt = MCF_SLT_Address(0); +- uint32_t sltclk = mcfv4e_get_bus_clk() * 1000000; +- +- /* Setup a slice timer terminal count */ +- slt->STCNT = 0xffffffff; +- +- /* Reset status bits */ +- slt->SSR = 0UL +- | MCF_SLT_SSR_ST +- | MCF_SLT_SSR_BE; +- +- /* Start timer to run continously */ +- slt->SCR = 0UL +- | MCF_SLT_SCR_TEN +- | MCF_SLT_SCR_RUN +- | MCF_SLT_SCR_IEN; // FIXME - add irq handler +- +- /* Setup up multiplier */ +- cs.mult = clocksource_hz2mult(sltclk, cs.shift); +- +- /* +- * Register the timer interrupt handler +- */ +- init_clock(&cs); +- +- return 0; +-} +- +-core_initcall(clocksource_init); +- +-#ifdef CONFIG_USE_IRQ +- +-static int clocksource_irq_init(void) +-{ +- if (!mcf_interrupts_register_handler( +- 118, // FIXME! +- (int (*)(void*,void*))slt_timer_default_isr, +- NULL, +- NULL) +- ) +- { +- return 1; +- } +- // Setup ICR +- MCF_INTC_ICR54 = MCF_INTC_ICRn_IL(1) | MCF_INTC_ICRn_IP(0); +- // Enable IRQ source +- MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK54; +- return 0; +-} +- +-postcore_initcall(clocksource_irq_init); +- +-#endif +diff --git a/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c b/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c +deleted file mode 100644 +index 3b1a25b..0000000 +--- a/arch/m68k/mach-mcfv4e/mcf_reset_cpu.c ++++ /dev/null +@@ -1,45 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Implements a watchdog triggered reset for V4e Coldfire cores +- */ +-#include <common.h> +-#include <mach/mcf54xx-regs.h> +- +-/** +- * Reset the cpu by setting up the watchdog timer and let it time out +- */ +-void __noreturn reset_cpu (unsigned long ignored) +-{ +- while ( ignored ) { ; }; +- +- /* Disable watchdog and set Time-Out field to minimum timeout value */ +- MCF_GPT_GMS0 = 0; +- MCF_GPT_GCIR0 = MCF_GPT_GCIR_PRE(1) | MCF_GPT_GCIR_CNT(0xffff); +- +- /* Enable watchdog */ +- MCF_GPT_GMS0 = MCF_GPT_GMS_OCPW(0xA5) | MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS_GPIO; +- +- while (1); +- /*NOTREACHED*/ +-} +-EXPORT_SYMBOL(reset_cpu); +- +diff --git a/arch/m68k/mach-mcfv4e/multichannel_dma.c b/arch/m68k/mach-mcfv4e/multichannel_dma.c +deleted file mode 100644 +index acc104e..0000000 +--- a/arch/m68k/mach-mcfv4e/multichannel_dma.c ++++ /dev/null +@@ -1,51 +0,0 @@ +-/* +- * barebox Header File +- * +- * Generic Clocksource for V4E +- * +- * Copyright (c) 2007 Carsten Schlote <c.schlote\@konzeptpark.de> +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +-#include <common.h> +-#include <init.h> +-#include <mach/mcf54xx-regs.h> +-#include <proc/mcdapi/MCD_dma.h> +-#include <proc/dma_utils.h> +- +- +-static int mcdapi_init(void) +-{ +- /* +- * Initialize the Multi-channel DMA +- */ +- MCD_initDma ((dmaRegs*)(__MBAR+0x8000), +- (void *)CFG_SYS_SRAM_ADDRESS, +- MCD_COMM_PREFETCH_EN | MCD_RELOC_TASKS); +- +- /* +- * Enable interrupts in DMA and INTC +- */ +- dma_irq_enable(DMA_INTC_LVL, DMA_INTC_PRI); +- +- return 0; +-} +- +-postcore_initcall(mcdapi_init); +- +diff --git a/arch/m68k/mach-mcfv4e/net/Makefile b/arch/m68k/mach-mcfv4e/net/Makefile +deleted file mode 100644 +index 78c528f..0000000 +--- a/arch/m68k/mach-mcfv4e/net/Makefile ++++ /dev/null +@@ -1,26 +0,0 @@ +-# +-# (C) Copyright 2007 Carsten Schlote <schlote@vahanus.net> +-# See file CREDITS for list of people who contributed to this project. +-# +-# This file is part of barebox. +-# +-# barebox is free software: you can redistribute it and/or modify +-# it under the terms of the GNU General Public License as published by +-# the Free Software Foundation, either version 3 of the License, or +-# (at your option) any later version. +-# +-# barebox is distributed in the hope that it will be useful, +-# but WITHOUT ANY WARRANTY; without even the implied warranty of +-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-# GNU General Public License for more details. +-# +-# You should have received a copy of the GNU General Public License +-# along with barebox. If not, see <http://www.gnu.org/licenses/>. +-# +- +-# +-# Support code for current FEC driver code - must be eliminated later... +-# +-obj-y += nbuf.o queue.o net.o +- +- +diff --git a/arch/m68k/mach-mcfv4e/net/nbuf.c b/arch/m68k/mach-mcfv4e/net/nbuf.c +deleted file mode 100644 +index 234e758..0000000 +--- a/arch/m68k/mach-mcfv4e/net/nbuf.c ++++ /dev/null +@@ -1,239 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Implementation of network buffer scheme. +- * @todo Obsolete this file +- */ +-#include <common.h> +-#include <malloc.h> +-#include <linux/types.h> +- +-#include <proc/net/queue.h> +-#include <proc/net/net.h> +- +-#include <mach/mcf54xx-regs.h> +- +- +-#define ASSERT(x) +- +-/** +- * Queues used for network buffer storage +- */ +-QUEUE nbuf_queue[NBUF_MAXQ]; +- +-/* +- * Some devices require line-aligned buffers. In order to accomplish +- * this, the nbuf data is over-allocated and adjusted. The following +- * array keeps track of the original data pointer returned by malloc +- */ +-ADDRESS unaligned_buffers[NBUF_MAX]; +- +-/** +- * Initialize all the network buffer queues +- * +- * Return Value: +- * 0 success +- * 1 failure +- */ +-int +-nbuf_init(void) +-{ +- int i; +- NBUF *nbuf; +- +- for (i=0; i<NBUF_MAXQ; ++i) +- { +- /* Initialize all the queues */ +- queue_init(&nbuf_queue[i]); +- } +- +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("Creating %d net buffers of %d bytes\n",NBUF_MAX,NBUF_SZ); +- #endif +- +- for (i=0; i<NBUF_MAX; ++i) +- { +- /* Allocate memory for the network buffer structure */ +- nbuf = (NBUF *)malloc(sizeof(NBUF)); +- if (!nbuf) +- { +- ASSERT(nbuf); +- return 1; +- } +- +- /* Allocate memory for the actual data */ +- unaligned_buffers[i] = (ADDRESS)malloc(NBUF_SZ + 16); +- nbuf->data = (uint8_t *)((uint32_t)(unaligned_buffers[i] + 15) & 0xFFFFFFF0); +- if (!nbuf->data) +- { +- ASSERT(nbuf->data); +- return 1; +- } +- +- /* Initialize the network buffer */ +- nbuf->offset = 0; +- nbuf->length = 0; +- +- /* Add the network buffer to the free list */ +- queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf); +- } +- +- #ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- printf("NBUF allocation complete\n"); +- nbuf_debug_dump(); +- #endif +- +- return 0; +-} +-/** +- * Return all the allocated memory to the heap +- */ +-void +-nbuf_flush(void) +-{ +- NBUF *nbuf; +- int i, level = asm_set_ipl(7); +- int n = 0; +- +- for (i=0; i<NBUF_MAX; ++i) +- free((uint8_t*)unaligned_buffers[i]); +- +- for (i=0; i<NBUF_MAXQ; ++i) +- { +- while ((nbuf = (NBUF *)queue_remove(&nbuf_queue[i])) != NULL) +- { +- free(nbuf); +- ++n; +- } +- } +- ASSERT(n == NBUF_MAX); +- asm_set_ipl(level); +-} +-/** +- * Allocate a network buffer from the free list +- * +- * Return Value: +- * Pointer to a free network buffer +- * NULL if none are available +- */ +-NBUF * +-nbuf_alloc(void) +-{ +- NBUF *nbuf; +- int level = asm_set_ipl(7); +- +- nbuf = (NBUF *)queue_remove(&nbuf_queue[NBUF_FREE]); +- asm_set_ipl(level); +- return nbuf; +-} +-/** +- * Add the specified network buffer back to the free list +- * +- * Parameters: +- * nbuf Buffer to add back to the free list +- */ +-void +-nbuf_free(NBUF *nbuf) +-{ +- int level = asm_set_ipl(7); +- +- nbuf->offset = 0; +- nbuf->length = NBUF_SZ; +- queue_add(&nbuf_queue[NBUF_FREE],(QNODE *)nbuf); +- +- asm_set_ipl(level); +-} +-/** +- * Remove a network buffer from the specified queue +- * +- * Parameters: +- * q The index that identifies the queue to pull the buffer from +- */ +-NBUF * +-nbuf_remove(int q) +-{ +- NBUF *nbuf; +- int level = asm_set_ipl(7); +- +- nbuf = (NBUF *)queue_remove(&nbuf_queue[q]); +- asm_set_ipl(level); +- return nbuf; +-} +-/** +- * Add a network buffer to the specified queue +- * +- * Parameters: +- * q The index that identifies the queue to add the buffer to +- */ +-void +-nbuf_add(int q, NBUF *nbuf) +-{ +- int level = asm_set_ipl(7); +- queue_add(&nbuf_queue[q],(QNODE *)nbuf); +- asm_set_ipl(level); +-} +-/** +- * Put all the network buffers back into the free list +- */ +-void +-nbuf_reset(void) +-{ +- NBUF *nbuf; +- int i, level = asm_set_ipl(7); +- +- for (i=1; i<NBUF_MAXQ; ++i) +- { +- while ((nbuf = nbuf_remove(i)) != NULL) +- nbuf_free(nbuf); +- } +- asm_set_ipl(level); +-} +-/** +- * Display all the nbuf queues +- */ +-void +-nbuf_debug_dump(void) +-{ +-#ifdef CONFIG_DRIVER_NET_MCF54XX_DEBUG +- NBUF *nbuf; +- int i, j, level; +- +- level = asm_set_ipl(7); +- +- for (i=0; i<NBUF_MAXQ; ++i) +- { +- printf("\n\nQueue #%d\n\n",i); +- printf("\tBuffer Location\tOffset\tLength\n"); +- printf("--------------------------------------\n"); +- j = 0; +- nbuf = (NBUF *)queue_peek(&nbuf_queue[i]); +- while (nbuf != NULL) +- { +- printf("%d\t 0x%08x\t0x%04x\t0x%04x\n",j++,nbuf->data, +- nbuf->offset, +- nbuf->length); +- nbuf = (NBUF *)nbuf->node.next; +- } +- } +- +- asm_set_ipl(level); +-#endif +-} +diff --git a/arch/m68k/mach-mcfv4e/net/net.c b/arch/m68k/mach-mcfv4e/net/net.c +deleted file mode 100644 +index febabfe..0000000 +--- a/arch/m68k/mach-mcfv4e/net/net.c ++++ /dev/null +@@ -1,156 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Network initialization for MCF V4E FEC support code +- * @todo Obsolete this file +- */ +-#include <common.h> +-#include <malloc.h> +-#include <linux/types.h> +- +-#include <mach/mcf54xx-regs.h> +-#include <proc/mcdapi/MCD_dma.h> +-#include <proc/net/net.h> +-#include <proc/fecbd.h> +-#include <proc/fec.h> +-#include <proc/dma_utils.h> +- +-#include <proc/processor.h> //FIXME - move to other file +- +-int netif_init(int channel) +-{ +- uint8_t* board_get_ethaddr(uint8_t*); +- +-#ifdef CONFIG_USE_IRQ +- int vector; +- int (*handler)(void *, void *); +- +- disable_interrupts(); +- +- /* +- * Register the FEC0 interrupt handler +- */ +- handler = (channel == 0) ? fec0_interrupt_handler +- : fec1_interrupt_handler; +- vector = (channel == 0) ? 103 : 102; +- +- if (!mcf_interrupts_register_handler( +- vector,handler, NULL,(void *)0xdeadbeef)) +- { +- printf("Error: Unable to register handler\n"); +- return 0; +- } +- +- /* +- * Register the DMA interrupt handler +- */ +- handler = dma_interrupt_handler; +- vector = 112; +- +- if (!mcf_interrupts_register_handler( +- vector,handler, NULL,NULL)) +- { +- printf("Error: Unable to register handler\n"); +- return 0; +- } +-#endif +- /* +- * Enable interrupts +- */ +- enable_interrupts(); +- +- return 1; +-} +- +-int netif_setup(int channel) +-{ +- uint8_t mac[6]; +- /* +- * Get user programmed MAC address +- */ +-// board_get_ethaddr(mac); +- +- +- /* +- * Initialize the network interface structure +- */ +-// nif_init(&nif1); +-// nif1.mtu = ETH_MTU; +-// nif1.send = (DBUG_ETHERNET_PORT == 0) ? fec0_send : fec1_send; +- +- /* +- * Initialize the dBUG Ethernet port +- */ +- fec_eth_setup(channel, /* Which FEC to use */ +- FEC_MODE_MII, /* Use MII mode */ +- FEC_MII_100BASE_TX, /* Allow 10 and 100Mbps */ +- FEC_MII_FULL_DUPLEX, /* Allow Full and Half Duplex */ +- mac); +- +- /* +- * Copy the Ethernet address to the NIF structure +- */ +-// memcpy(nif1.hwa, mac, 6); +- +- #ifdef DEBUG +- printf("Ethernet Address is %02X:%02X:%02X:%02X:%02X:%02X\n",\ +- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); +- #endif +- +- return 1; +-} +- +-int netif_done(int channel) +-{ +- /* +- * Download complete, clean up +- */ +-#ifdef CONFIG_USE_IRQ +- int (*handler)(void *, void *); +-#endif +- /* +- * Disable interrupts +- */ +- disable_interrupts(); +- +- /* +- * Disable the Instruction Cache +- */ +- mcf5xxx_wr_cacr(MCF5XXX_CACR_ICINVA); +- +- /* +- * Disable the dBUG Ethernet port +- */ +- fec_eth_stop(channel); +- +- /* +- * Remove the interrupt handlers +- */ +-#ifdef CONFIG_USE_IRQ +- handler = (channel == 0) ? fec0_interrupt_handler +- : fec1_interrupt_handler; +- mcf_interrupts_remove_handler(handler); +- mcf_interrupts_remove_handler(dma_interrupt_handler); +-#endif +- return 1; +-} +- +- +diff --git a/arch/m68k/mach-mcfv4e/net/queue.c b/arch/m68k/mach-mcfv4e/net/queue.c +deleted file mode 100644 +index 9f77947..0000000 +--- a/arch/m68k/mach-mcfv4e/net/queue.c ++++ /dev/null +@@ -1,128 +0,0 @@ +-/* +- * Copyright (c) 2008 Carsten Schlote <c.schlote@konzeptpark.de> +- * See file CREDITS for list of people who contributed to this project. +- * +- * This file is part of barebox. +- * +- * barebox is free software: you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation, either version 3 of the License, or +- * (at your option) any later version. +- * +- * barebox is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with barebox. If not, see <http://www.gnu.org/licenses/>. +- */ +- +-/** @file +- * Implements a first in, first out linked list +- * +- * @note Simple selfcontaining basic code +- * @todo Replace by barebox standard list functions +- */ +-#include <linux/types.h> +-#include <proc/net/queue.h> +- +-/** Initialize the specified queue to an empty state +- * +- * @param[in] +- * q Pointer to queue structure +- */ +-void queue_init(QUEUE *q) +-{ +- q->head = NULL; +-} +- +-/** +- * Check for an empty queue +- * +- * @param[in] q Pointer to queue structure +- * @return +- * 1 if Queue is empty +- * 0 otherwise +- */ +-int +-queue_isempty(QUEUE *q) +-{ +- return (q->head == NULL); +-} +- +-/** +- * Add an item to the end of the queue +- * +- * @param[in] q Pointer to queue structure +- * @param[in] node New node to add to the queue +- */ +-void queue_add(QUEUE *q, QNODE *node) +-{ +- if (queue_isempty(q)) +- { +- q->head = q->tail = node; +- } +- else +- { +- q->tail->next = node; +- q->tail = node; +- } +- +- node->next = NULL; +-} +- +-/** Remove and return first (oldest) entry from the specified queue +- * +- * @param[in] q Pointer to queue structure +- * @return +- * Node at head of queue - NULL if queue is empty +- */ +-QNODE* +-queue_remove(QUEUE *q) +-{ +- QNODE *oldest; +- +- if (queue_isempty(q)) +- return NULL; +- +- oldest = q->head; +- q->head = oldest->next; +- return oldest; +-} +- +-/** Peek into the queue and return pointer to first (oldest) entry. +- * +- * The queue is not modified +- * +- * @param[in] q Pointer to queue structure +- * @return +- * Node at head of queue - NULL if queue is empty +- */ +-QNODE* +-queue_peek(QUEUE *q) +-{ +- return q->head; +-} +- +-/** Move entire contents of one queue to the other +- * +- * @param[in] src Pointer to source queue +- * @param[in] dst Pointer to destination queue +- */ +-void +-queue_move(QUEUE *dst, QUEUE *src) +-{ +- if (queue_isempty(src)) +- return; +- +- if (queue_isempty(dst)) +- dst->head = src->head; +- else +- dst->tail->next = src->head; +- +- dst->tail = src->tail; +- src->head = NULL; +- return; +-} +- +diff --git a/arch/ppc/lib/Makefile b/arch/ppc/lib/Makefile +index 400b1e1..0844d56 100644 +--- a/arch/ppc/lib/Makefile ++++ b/arch/ppc/lib/Makefile +@@ -1,6 +1,5 @@ + obj-y += bat_rw.o + obj-y += board.o +-obj-y += cache.o + obj-y += extable.o + obj-$(CONFIG_USE_IRQ) += interrupts.o + obj-y += kgdb.o +diff --git a/arch/ppc/lib/cache.c b/arch/ppc/lib/cache.c +deleted file mode 100644 +index 3d863b3..0000000 +--- a/arch/ppc/lib/cache.c ++++ /dev/null +@@ -1,50 +0,0 @@ +-/* +- * (C) Copyright 2002 +- * Wolfgang Denk, DENX Software Engineering, wd@denx.de. +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +- +-#include <common.h> +- +- +-void flush_cache (ulong start_addr, ulong size) +-{ +-#ifndef CONFIG_5xx +- ulong addr, end_addr = start_addr + size; +- +- if (CONFIG_CACHELINE_SIZE) { +- addr = start_addr & (CONFIG_CACHELINE_SIZE - 1); +- for (addr = start_addr; +- addr < end_addr; +- addr += CONFIG_CACHELINE_SIZE) { +- asm ("dcbst 0,%0": :"r" (addr)); +- } +- asm ("sync"); /* Wait for all dcbst to complete on bus */ +- +- for (addr = start_addr; +- addr < end_addr; +- addr += CONFIG_CACHELINE_SIZE) { +- asm ("icbi 0,%0": :"r" (addr)); +- } +- } +- asm ("sync"); /* Always flush prefetch queue in any case */ +- asm ("isync"); +-#endif +-} +diff --git a/arch/ppc/lib/ppclinux.c b/arch/ppc/lib/ppclinux.c +index 5ee908d..fc22a87 100644 +--- a/arch/ppc/lib/ppclinux.c ++++ b/arch/ppc/lib/ppclinux.c +@@ -45,7 +45,7 @@ static int do_bootm_linux(struct image_data *idata) + printf("entering %s: os_header: %p initrd_header: %p oftree: %s\n", + __FUNCTION__, os_header, initrd_header, idata->oftree); + +- if (image_check_type(os_header, IH_TYPE_MULTI)) { ++ if (image_get_type(os_header) == IH_TYPE_MULTI) { + unsigned long *data = (unsigned long *)(idata->os->data); + unsigned long len1 = 0, len2 = 0; + +diff --git a/arch/ppc/mach-mpc5xxx/cpu.c b/arch/ppc/mach-mpc5xxx/cpu.c +index 7ee1954..4d08c55 100644 +--- a/arch/ppc/mach-mpc5xxx/cpu.c ++++ b/arch/ppc/mach-mpc5xxx/cpu.c +@@ -71,7 +71,7 @@ int checkcpu (void) + + /* ------------------------------------------------------------------------- */ + +-void __noreturn reset_cpu (unsigned long unused) ++void __noreturn reset_cpu (unsigned long addr) + { + ulong msr; + /* Interrupts and MMU off */ +diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c +index ad625d7..38a52a8 100644 +--- a/arch/sandbox/board/hostfile.c ++++ b/arch/sandbox/board/hostfile.c +@@ -79,7 +79,9 @@ static int hf_probe(struct device_d *dev) + priv->cdev.size = hf->size; + priv->cdev.ops = &hf_fops; + priv->cdev.priv = hf; ++#ifdef CONFIG_FS_DEVFS + devfs_create(&priv->cdev); ++#endif + + return 0; + } +diff --git a/arch/sandbox/os/common.c b/arch/sandbox/os/common.c +index c73aa79..287be0d 100644 +--- a/arch/sandbox/os/common.c ++++ b/arch/sandbox/os/common.c +@@ -138,7 +138,7 @@ uint64_t linux_get_time(void) + return now; + } + +-void __attribute__((noreturn)) reset_cpu(int unused) ++void __attribute__((noreturn)) reset_cpu(unsigned long addr) + { + cookmode(); + exit(0); +@@ -213,11 +213,6 @@ off_t linux_lseek(int fd, off_t offset) + return lseek(fd, offset, SEEK_SET); + } + +-void flush_cache(unsigned long dummy1, unsigned long dummy2) +-{ +- /* why should we? */ +-} +- + extern void start_barebox(void); + extern void mem_malloc_init(void *start, void *end); + +diff --git a/arch/x86/Makefile b/arch/x86/Makefile +index 57c5dbc..8ab40b6 100644 +--- a/arch/x86/Makefile ++++ b/arch/x86/Makefile +@@ -5,7 +5,8 @@ machine-y := i386 + + TEXT_BASE = $(CONFIG_TEXT_BASE) + +-CPPFLAGS += -march=i386 -DTEXT_BASE=$(TEXT_BASE) -P ++CPPFLAGS += -march=i386 -m32 -DTEXT_BASE=$(TEXT_BASE) -P ++LDFLAGS += -m elf_i386 + + ifndef CONFIG_MODULES + # Add cleanup flags +diff --git a/arch/x86/boards/x86_generic/generic_pc.c b/arch/x86/boards/x86_generic/generic_pc.c +index a6cd7e0..b9c31aa 100644 +--- a/arch/x86/boards/x86_generic/generic_pc.c ++++ b/arch/x86/boards/x86_generic/generic_pc.c +@@ -46,7 +46,7 @@ static struct device_d sdram_dev = { + static struct device_d bios_disk_dev = { + .id = -1, + .name = "biosdrive", +- .size = 1, ++ .size = 0, /* auto guess */ + }; + + /* +diff --git a/arch/x86/boot/boot_hdisk.S b/arch/x86/boot/boot_hdisk.S +index 40388e9..fc4c4d5 100644 +--- a/arch/x86/boot/boot_hdisk.S ++++ b/arch/x86/boot/boot_hdisk.S +@@ -31,7 +31,6 @@ + * from the boot media. + */ + +-#ifndef DOXYGEN_SHOULD_SKIP_THIS + + .file "boot_hdisk.S" + .code16 +@@ -173,4 +172,3 @@ notification_string: .asciz "UBOOT2 " + chs_string: .asciz "CHS " + jmp_string: .asciz "JMP " + +-#endif +diff --git a/arch/x86/boot/boot_main.S b/arch/x86/boot/boot_main.S +index f3d248a..94fe434 100644 +--- a/arch/x86/boot/boot_main.S ++++ b/arch/x86/boot/boot_main.S +@@ -30,7 +30,6 @@ + * @brief Fix segment:offset settings of some buggy BIOSs + */ + +-#ifndef DOXYGEN_SHOULD_SKIP_THIS + + .file "boot_main.S" + .code16 +@@ -55,4 +54,3 @@ _start: + + .size _start, .-_start + +-#endif +diff --git a/arch/x86/boot/pmjump.S b/arch/x86/boot/pmjump.S +index d48e198..0e4cd38 100644 +--- a/arch/x86/boot/pmjump.S ++++ b/arch/x86/boot/pmjump.S +@@ -20,7 +20,6 @@ + * @fn void protected_mode_jump(void) + * @brief Switches the first time from real mode to flat mode + */ +-#ifndef DOXYGEN_SHOULD_SKIP_THIS + + #include <asm/modes.h> + #include "boot.h" +@@ -86,4 +85,3 @@ in_pm32: + + .size protected_mode_jump, .-protected_mode_jump + +-#endif +diff --git a/arch/x86/lib/memory16.S b/arch/x86/lib/memory16.S +index 01450fa..cb2f833 100644 +--- a/arch/x86/lib/memory16.S ++++ b/arch/x86/lib/memory16.S +@@ -38,7 +38,6 @@ + * + */ + +-#ifndef DOXYGEN_SHOULD_SKIP_THIS + + .section .boot.text.bios_get_memsize, "ax" + .code32 +@@ -70,4 +69,3 @@ bios_get_memsize: + + .size bios_get_memsize, .-bios_get_memsize + +-#endif +diff --git a/arch/x86/lib/traveler.S b/arch/x86/lib/traveler.S +index 2b6dc85..0614195 100644 +--- a/arch/x86/lib/traveler.S ++++ b/arch/x86/lib/traveler.S +@@ -41,8 +41,6 @@ + * Called from a 16 bit real mode segment and returns into a 32 bit segment + */ + +-#ifndef DOXYGEN_SHOULD_SKIP_THIS +- + #include <asm/modes.h> + + .file "walkyrie.S" +@@ -180,4 +178,3 @@ enter_realmode: + + .size prot_to_real, .-prot_to_real + +-#endif +diff --git a/arch/x86/mach-x86.dox b/arch/x86/mach-x86.dox +index fc5b85a..661e905 100644 +--- a/arch/x86/mach-x86.dox ++++ b/arch/x86/mach-x86.dox +@@ -2,7 +2,7 @@ + * how to integrate a new CPU (MACH) into this part of the barebox tree + */ + +-/** @page x86_runtime barebox on x86 at runtime ++/** @page dev_x86_mach barebox on x86 at runtime + + @section mach_x86_memory_layout barebox's memory layout (BIOS based) + +diff --git a/commands/Kconfig b/commands/Kconfig +index 0fc80aa..5416073 100644 +--- a/commands/Kconfig ++++ b/commands/Kconfig +@@ -202,6 +202,11 @@ config CMD_CRC + select CRC32 + prompt "crc" + ++config CMD_CRC_CMP ++ tristate ++ depends on CMD_CRC ++ prompt "compare 2 files crc" ++ + config CMD_MTEST + tristate + prompt "mtest" +diff --git a/commands/bmp.c b/commands/bmp.c +index 6e17200..5bac031 100644 +--- a/commands/bmp.c ++++ b/commands/bmp.c +@@ -193,17 +193,28 @@ failed_memmap: + return 1; + } + +-static const __maybe_unused char cmd_bmp_help[] = +-"Usage: bmp [OPTION]... FILE\n" +-"show bmp image FILE.\n" +-" -f <fb> framebuffer device (/dev/fb0)\n" +-" -x <xofs> x offset (default center)\n" +-" -y <yofs> y offset (default center)\n" +-" -o render offscreen\n"; ++BAREBOX_CMD_HELP_START(bmp) ++BAREBOX_CMD_HELP_USAGE("bmp [OPTIONS] FILE\n") ++BAREBOX_CMD_HELP_SHORT("Show the bitmap FILE on the framebuffer.\n") ++BAREBOX_CMD_HELP_OPT ("-f <fb>", "framebuffer device (/dev/fb0)\n") ++BAREBOX_CMD_HELP_OPT ("-x <xofs>", "x offset (default center)\n") ++BAREBOX_CMD_HELP_OPT ("-y <yofs>", "y offset (default center)\n") ++BAREBOX_CMD_HELP_OPT ("-o", "render offscreen\n") ++BAREBOX_CMD_HELP_END ++ ++/** ++ * @page bmp_command ++ ++This command displays a graphics in the bitmap (.bmp) format on the ++framebuffer. Currently the bmp command supports images with 8 and 24 bit ++color depth. ++ ++\todo What does the -o (offscreen) option do? ++ ++ */ + + BAREBOX_CMD_START(bmp) + .cmd = do_bmp, + .usage = "show a bmp image", + BAREBOX_CMD_HELP(cmd_bmp_help) + BAREBOX_CMD_END +- +diff --git a/commands/bootm.c b/commands/bootm.c +index 83d36d3..34164bc 100644 +--- a/commands/bootm.c ++++ b/commands/bootm.c +@@ -167,7 +167,7 @@ struct image_handle *map_image(const char *filename, int verify) + goto err_out; + } + +- if (image_check_magic(header)) { ++ if (image_get_magic(header) != IH_MAGIC) { + puts ("Bad Magic Number\n"); + goto err_out; + } +@@ -225,7 +225,7 @@ void unmap_image(struct image_handle *handle) + } + EXPORT_SYMBOL(unmap_image); + +-LIST_HEAD(handler_list); ++static LIST_HEAD(handler_list); + + int register_image_handler(struct image_handler *handler) + { +@@ -332,7 +332,7 @@ static int do_bootm(struct command *cmdtp, int argc, char *argv[]) + + os_header = &os_handle->header; + +- if (image_check_arch(os_header, IH_ARCH)) { ++ if (image_get_arch(os_header) != IH_ARCH) { + printf("Unsupported Architecture 0x%x\n", + image_get_arch(os_header)); + goto err_out; +@@ -350,7 +350,7 @@ static int do_bootm(struct command *cmdtp, int argc, char *argv[]) + + /* loop through the registered handlers */ + list_for_each_entry(handler, &handler_list, list) { +- if (image_check_os(os_header, handler->image_type)) { ++ if (image_get_os(os_header) == handler->image_type) { + handler->bootm(&data); + printf("handler returned!\n"); + goto err_out; +@@ -368,19 +368,25 @@ err_out: + return 1; + } + +-static const __maybe_unused char cmd_bootm_help[] = +-"Usage: bootm [OPTION] image\n" +-"Boot application image\n" +-" -n do not verify the images (speeds up boot process)\n" +-" -h show advanced options\n"; +- ++BAREBOX_CMD_HELP_START(bootm) ++BAREBOX_CMD_HELP_USAGE("bootm [-n] image\n") ++BAREBOX_CMD_HELP_SHORT("Boot an application image.\n") ++BAREBOX_CMD_HELP_OPT ("-n", "Do not verify the image (speeds up boot process)\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(bootm) + .cmd = do_bootm, +- .usage = "boot application image", ++ .usage = "boot an application image", + BAREBOX_CMD_HELP(cmd_bootm_help) + BAREBOX_CMD_END + ++/** ++ * @page bootm_command ++ ++\todo What does bootm do, what kind of image does it boot? ++ ++ */ ++ + #ifdef CONFIG_CMD_IMI + static int do_iminfo(struct command *cmdtp, int argc, char *argv[]) + { +@@ -409,7 +415,7 @@ static int image_info (ulong addr) + /* Copy header so we can blank CRC field for re-calculation */ + memmove (&header, (char *)addr, image_get_header_size()); + +- if (image_check_magic(hdr)) { ++ if (image_get_magic(hdr) != IH_MAGIC) { + puts (" Bad Magic Number\n"); + return 1; + } +@@ -440,14 +446,16 @@ static int image_info (ulong addr) + return 0; + } + +-BAREBOX_CMD( +- iminfo, 1, do_iminfo, +- "iminfo - print header information for application image\n", +- "addr [addr ...]\n" +- " - print header information for application image starting at\n" +- " address 'addr' in memory; this includes verification of the\n" +- " image contents (magic number, header and payload checksums)\n" +-); ++BAREBOX_CMD_HELP_START(iminfo) ++BAREBOX_CMD_HELP_USAGE("iminfo\n") ++BAREBOX_CMD_HELP_SHORT("Print header information for an application image.\n") ++BAREBOX_CMD_HELP_END ++ ++BAREBOX_CMD_START(iminfo) ++ .cmd = do_iminfo, ++ .usage = "print header information for an application image", ++ BAREBOX_CMD_HELP(cmd_iminfo_help) ++BAREBOX_CMD_END + + #endif /* CONFIG_CMD_IMI */ + +@@ -473,5 +481,4 @@ void bz_internal_error(int errcode) + * - @subpage arm_boot_preparation + * - @subpage ppc_boot_preparation + * - @subpage x86_boot_preparation +- * - @subpage m68k_boot_preparation + */ +diff --git a/commands/cat.c b/commands/cat.c +index 41b3324..37e6505 100644 +--- a/commands/cat.c ++++ b/commands/cat.c +@@ -85,22 +85,15 @@ out: + return err; + } + +-static const __maybe_unused char cmd_cat_help[] = +-"Usage: cat [FILES]\n" +-"Concatenate files on stdout. Currently only printable characters\n" +-"and \\n and \\t are printed, but this should be optional\n"; ++BAREBOX_CMD_HELP_START(cat) ++BAREBOX_CMD_HELP_USAGE("cat [FILES]\n") ++BAREBOX_CMD_HELP_SHORT("Concatenate files on stdout.\n") ++BAREBOX_CMD_HELP_TEXT ("Currently only printable characters and \\ n and \\ t are printed,\n") ++BAREBOX_CMD_HELP_TEXT ("but this should be optional.\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(cat) + .cmd = do_cat, + .usage = "concatenate file(s)", + BAREBOX_CMD_HELP(cmd_cat_help) + BAREBOX_CMD_END +- +-/** +- * @page cat_command cat (concatenate) +- * +- * Usage is: cat \<file\> [\<file\> ...] +- * +- * Concatenate files to stdout. Currently only printable characters +- * and \\n and \\t are printed, but this should be optional +- */ +diff --git a/commands/cd.c b/commands/cd.c +index a842f4d..d73be32 100644 +--- a/commands/cd.c ++++ b/commands/cd.c +@@ -47,21 +47,14 @@ static int do_cd(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_cd_help[] = +-"Usage: cd [directory]\n" +-"change to directory. If called without argument, change to /\n"; ++BAREBOX_CMD_HELP_START(cd) ++BAREBOX_CMD_HELP_USAGE("cd [directory]\n") ++BAREBOX_CMD_HELP_SHORT("Change to directory.\n") ++BAREBOX_CMD_HELP_TEXT ("If called without an argument, change to the root directory /.\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(cd) + .cmd = do_cd, + .usage = "change working directory", + BAREBOX_CMD_HELP(cmd_cd_help) + BAREBOX_CMD_END +- +-/** +- * @page cd_command cd (change working directory) +- * +- * Usage is: cd [\<directory name>] +- * +- * Change to \<directory name>. If called without argument, change to \b / +- * (root) +- */ +diff --git a/commands/clear.c b/commands/clear.c +index 7589a0c..6a6b6c5 100644 +--- a/commands/clear.c ++++ b/commands/clear.c +@@ -31,6 +31,11 @@ static int do_clear(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + ++BAREBOX_CMD_HELP_START(clear) ++BAREBOX_CMD_HELP_USAGE("clear\n") ++BAREBOX_CMD_HELP_SHORT("Clear the screen.\n") ++BAREBOX_CMD_HELP_END ++ + BAREBOX_CMD_START(clear) + .cmd = do_clear, + .usage = "clear screen", +diff --git a/commands/cp.c b/commands/cp.c +index 2c35ba1..ae8719b 100644 +--- a/commands/cp.c ++++ b/commands/cp.c +@@ -51,7 +51,7 @@ static int do_cp(struct command *cmdtp, int argc, char *argv[]) + if (S_ISDIR(statbuf.st_mode)) + last_is_dir = 1; + } +- ++ + if (argc > 3 && !last_is_dir) { + printf("cp: target `%s' is not a directory\n", argv[argc - 1]); + return 1; +@@ -77,10 +77,19 @@ out: + return ret; + } + +-static const __maybe_unused char cmd_cp_help[] = +-"Usage: cp <source> <destination>\n" +-"cp copies file <source> to <destination>.\n" +-"This command is file based only. See memcpy for memory copy\n"; ++BAREBOX_CMD_HELP_START(cp) ++BAREBOX_CMD_HELP_USAGE("cp <source> <destination>\n") ++BAREBOX_CMD_HELP_SHORT("copy file from <source> to <destination>.\n") ++BAREBOX_CMD_HELP_END ++ ++/** ++ * @page cp_command ++This command operates on files. ++ ++If you want to copy between memory blocks, use 'memcpy'. ++ ++\todo What does this mean? Add examples. ++ */ + + BAREBOX_CMD_START(cp) + .cmd = do_cp, +@@ -88,14 +97,3 @@ BAREBOX_CMD_START(cp) + BAREBOX_CMD_HELP(cmd_cp_help) + BAREBOX_CMD_END + +-/** +- * @page cp_command cp: Copy file +- * +- * Usage: cp \<source> [\<source>] \<destination> +- * +- * \c cp copies file \<source> to \<destination> +- * +- * Currently only this form is supported and you have to specify the exact +- * target filename (not a target directory).\n +- * This command is file based only. See memcpy for generic memory copy +- */ +diff --git a/commands/crc.c b/commands/crc.c +index 4842cdc..0873a1c 100644 +--- a/commands/crc.c ++++ b/commands/crc.c +@@ -30,20 +30,80 @@ + #include <malloc.h> + #include <linux/ctype.h> + ++static int file_crc(char* filename, ulong start, ulong size, ulong *crc, ++ ulong *total) ++{ ++ int fd, now; ++ int ret = 0; ++ char *buf; ++ ++ *total = 0; ++ *crc = 0; ++ ++ fd = open(filename, O_RDONLY); ++ if (fd < 0) { ++ printf("open %s: %s\n", filename, errno_str()); ++ return fd; ++ } ++ ++ if (start > 0) { ++ ret = lseek(fd, start, SEEK_SET); ++ if (ret == -1) { ++ perror("lseek"); ++ goto out; ++ } ++ } ++ ++ buf = xmalloc(4096); ++ ++ while (size) { ++ now = min((ulong)4096, size); ++ now = read(fd, buf, now); ++ if (now < 0) { ++ ret = now; ++ perror("read"); ++ goto out_free; ++ } ++ if (!now) ++ break; ++ *crc = crc32(*crc, buf, now); ++ size -= now; ++ *total += now; ++ } ++ ++ printf ("CRC32 for %s 0x%08lx ... 0x%08lx ==> 0x%08lx", ++ filename, start, start + *total - 1, *crc); ++ ++out_free: ++ free(buf); ++out: ++ close(fd); ++ ++ return ret; ++} ++ + static int do_crc(struct command *cmdtp, int argc, char *argv[]) + { + ulong start = 0, size = ~0, total = 0; + ulong crc = 0, vcrc = 0; + char *filename = "/dev/mem"; +- char *buf; +- int fd, opt, err = 0, filegiven = 0, verify = 0, now; ++#ifdef CONFIG_CMD_CRC_CMP ++ char *vfilename = NULL; ++#endif ++ int opt, err = 0, filegiven = 0, verify = 0; + +- while((opt = getopt(argc, argv, "f:v:")) > 0) { ++ while((opt = getopt(argc, argv, "f:F:v:")) > 0) { + switch(opt) { + case 'f': + filename = optarg; + filegiven = 1; + break; ++#ifdef CONFIG_CMD_CRC_CMP ++ case 'F': ++ verify = 1; ++ vfilename = optarg; ++ break; ++#endif + case 'v': + verify = 1; + vcrc = simple_strtoul(optarg, NULL, 0); +@@ -61,38 +121,17 @@ static int do_crc(struct command *cmdtp, int argc, char *argv[]) + } + } + +- fd = open(filename, O_RDONLY); +- if (fd < 0) { +- printf("open %s: %s\n", filename, errno_str()); ++ if (file_crc(filename, start, size, &crc, &total) < 0) + return 1; +- } + +- if (start > 0) { +- if (lseek(fd, start, SEEK_SET) == -1) { +- perror("lseek"); +- err = 1; +- goto out; +- } +- } +- +- buf = xmalloc(4096); +- +- while (size) { +- now = min((ulong)4096, size); +- now = read(fd, buf, now); +- if (now < 0) { +- perror("read"); +- goto out_free; +- } +- if (!now) +- break; +- crc = crc32(crc, buf, now); +- size -= now; +- total += now; ++#ifdef CONFIG_CMD_CRC_CMP ++ if (vfilename) { ++ size = total; ++ puts("\n"); ++ if (file_crc(vfilename, start, size, &vcrc, &total) < 0) ++ return 1; + } +- +- printf ("CRC32 for %s 0x%08lx ... 0x%08lx ==> 0x%08lx", +- filename, start, start + total - 1, crc); ++#endif + + if (verify && crc != vcrc) { + printf(" != 0x%08x ** ERROR **", vcrc); +@@ -101,24 +140,21 @@ static int do_crc(struct command *cmdtp, int argc, char *argv[]) + + printf("\n"); + +-out_free: +- free(buf); +-out: +- close(fd); +- + return err; + } + +-static const __maybe_unused char cmd_crc_help[] = +-"Usage: crc32 [OPTION] [AREA]\n" +-"Calculate a crc32 checksum of a memory area\n" +-"Options:\n" +-" -f <file> Use file instead of memory\n" +-" -v <crc> Verfify\n"; ++BAREBOX_CMD_HELP_START(crc) ++BAREBOX_CMD_HELP_USAGE("crc32 [OPTION] [AREA]\n") ++BAREBOX_CMD_HELP_SHORT("Calculate a crc32 checksum of a memory area.\n") ++BAREBOX_CMD_HELP_OPT ("-f <file>", "Use file instead of memory.\n") ++#ifdef CONFIG_CMD_CRC_CMP ++BAREBOX_CMD_HELP_OPT ("-F <file>", "Use file to compare.\n") ++#endif ++BAREBOX_CMD_HELP_OPT ("-v <crc>", "Verfify\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(crc32) + .cmd = do_crc, + .usage = "crc32 checksum calculation", + BAREBOX_CMD_HELP(cmd_crc_help) + BAREBOX_CMD_END +- +diff --git a/commands/dfu.c b/commands/dfu.c +index 66fd6ea..385fd89 100644 +--- a/commands/dfu.c ++++ b/commands/dfu.c +@@ -162,16 +162,24 @@ out: + return 1; + } + +-static const __maybe_unused char cmd_dfu_help[] = +-"Usage: dfu [OPTION]... description\n" +-"start dfu firmware update\n" +-" -m <str> Manufacturer string (barebox)\n" +-" -p <str> product string (" CONFIG_BOARDINFO ")\n" +-" -V <id> vendor id\n" +-" -P <id> product id\n" +-"description has the form\n" +-"device1(name1)[sr],device2(name2)[sr]\n" +-"where s is for save mode and r for read back of firmware\n"; ++BAREBOX_CMD_HELP_START(dfu) ++BAREBOX_CMD_HELP_USAGE("dfu [OPTIONS] <description>\n") ++BAREBOX_CMD_HELP_SHORT("Start firmware update with the Device Firmware Update (DFU) protocol.\n") ++BAREBOX_CMD_HELP_OPT ("-m <str>", "Manufacturer string (barebox)\n") ++BAREBOX_CMD_HELP_OPT ("-p <str>", "product string (" CONFIG_BOARDINFO ")\n") ++BAREBOX_CMD_HELP_OPT ("-V <id>", "vendor id\n") ++BAREBOX_CMD_HELP_OPT ("-P <id>", "product id\n") ++BAREBOX_CMD_HELP_END ++ ++/** ++ * @page dfu_command ++\<description> has the following form: ++device1(name1)[sr],device2(name2)[sr] ++'s' means 'safe mode' (download the complete image before flashing) and ++'r' that readback of the firmware is allowed. ++ ++\todo Add example, how to use dfu from a Linux or Windows host. ++ */ + + BAREBOX_CMD_START(dfu) + .cmd = do_dfu, +diff --git a/commands/echo.c b/commands/echo.c +index dfa14d6..3e098df 100644 +--- a/commands/echo.c ++++ b/commands/echo.c +@@ -111,8 +111,25 @@ no_optarg_out: + return 1; + } + ++BAREBOX_CMD_HELP_START(echo) ++BAREBOX_CMD_HELP_USAGE("echo [OPTIONS] [STRING]\n") ++BAREBOX_CMD_HELP_SHORT("Display a line of text.\n") ++BAREBOX_CMD_HELP_OPT ("-n", "do not output the trailing newline\n") ++BAREBOX_CMD_HELP_OPT ("-a", "FIXME\n") ++BAREBOX_CMD_HELP_OPT ("-o", "FIXME\n") ++BAREBOX_CMD_HELP_OPT ("-e", "FIXME\n") ++BAREBOX_CMD_HELP_END ++ ++/** ++ * @page echo_command ++ ++\todo Add documentation for -a, -o and -e. ++ ++ */ ++ + BAREBOX_CMD_START(echo) + .cmd = do_echo, + .usage = "echo args to console", ++ BAREBOX_CMD_HELP(cmd_echo_help) + BAREBOX_CMD_END + +diff --git a/commands/edit.c b/commands/edit.c +index a65b08a..ca40d59 100644 +--- a/commands/edit.c ++++ b/commands/edit.c +@@ -58,7 +58,7 @@ static int textx = 0; /* position in text */ + static struct line *curline; /* line where the cursor is */ + + static struct line *scrline; /* the first line on screen */ +-int scrcol = 0; /* the first column on screen */ ++static int scrcol = 0; /* the first column on screen */ + + static void pos(int x, int y) + { +@@ -231,7 +231,7 @@ static int edit_read_file(const char *path) + line->prev = lastline; + if (lastline) + lastline->next = line; +- line->next = 0; ++ line->next = NULL; + lastline = line; + + if (!lineend) +@@ -550,35 +550,25 @@ out: + + static const char *edit_aliases[] = { "sedit", NULL}; + +-static const __maybe_unused char cmd_edit_help[] = +-"Usage: (s)edit <file>\n" +-"This is a very small editor. Its only features are moving the cursor with\n" +-"the usual keys and typing characters.\n" +-"<ctrl-c> quits the editor without saving,\n" +-"<ctrl-d> quits the editor with saving the current file.\n" +-"\n" +-"If called as sedit the editor uses ansi codes to scroll the screen.\n"; ++BAREBOX_CMD_HELP_START(edit) ++BAREBOX_CMD_HELP_USAGE("(s)edit <file>\n") ++BAREBOX_CMD_HELP_SHORT("A small editor. <ctrl-c> is exit, <ctrl-d> exit-with-save.\n") ++BAREBOX_CMD_HELP_END + +-static const __maybe_unused char cmd_edit_usage[] = "edit a file"; ++/** ++ * @page edit_command ++ ++<p> Barebox contains a small text editor which can be used to edit ++config files in /env. You can move the cursor around with the arrow keys ++and type characters. </p> ++ ++If called as sedit, the editor uses ansi codes to scroll the screen. ++ */ + + BAREBOX_CMD_START(edit) + .cmd = do_edit, + .aliases = edit_aliases, +- .usage = cmd_edit_usage, ++ .usage = "Usage: (s)edit <file>", + BAREBOX_CMD_HELP(cmd_edit_help) + BAREBOX_CMD_END + +- +-/** +- * @page edit_command edit (editor) +- * +- * Usage is: [s]edit \<file\> +- * +- * This is a very small editor. It's only features are moving the cursor with +- * the usual keys and typing characters. +- * +- * \b \<ctrl-c\> quits the editor without saving,\n +- * \b \<ctrl-d\> quits the editor with saving the current file. +- * +- * If called as \c sedit the editor uses ansi codes to scroll the screen. +- */ +diff --git a/commands/export.c b/commands/export.c +index 31259cc..98b1e1a 100644 +--- a/commands/export.c ++++ b/commands/export.c +@@ -51,9 +51,10 @@ static int do_export(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_export_help[] = +-"Usage: export <var>[=value]...\n" +-"export an environment variable to subsequently executed scripts\n"; ++BAREBOX_CMD_HELP_START(export) ++BAREBOX_CMD_HELP_USAGE("export <var>[=value]\n") ++BAREBOX_CMD_HELP_SHORT("export an environment variable to subsequently executed scripts\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(export) + .cmd = do_export, +@@ -61,10 +62,3 @@ BAREBOX_CMD_START(export) + BAREBOX_CMD_HELP(cmd_export_help) + BAREBOX_CMD_END + +-/** +- * @page export_command export: Export an environment variable +- * +- * Usage: export \<var>[=value]... +- * +- * Export an environment variable to subsequently executed scripts. +- */ +diff --git a/commands/flash.c b/commands/flash.c +index 20f5cfc..9a0eb50 100644 +--- a/commands/flash.c ++++ b/commands/flash.c +@@ -83,10 +83,10 @@ out: + return ret; + } + +-static const __maybe_unused char cmd_erase_help[] = +-"Usage: erase <device> [area]\n" +-"Erase a flash device or parts of a device if an area specification\n" +-"is given\n"; ++BAREBOX_CMD_HELP_START(erase) ++BAREBOX_CMD_HELP_USAGE("erase <device> [area]\n") ++BAREBOX_CMD_HELP_SHORT("Erase a flash device or parts of a device if an area specification is given.\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(erase) + .cmd = do_flerase, +@@ -94,16 +94,18 @@ BAREBOX_CMD_START(erase) + BAREBOX_CMD_HELP(cmd_erase_help) + BAREBOX_CMD_END + +-/** @page erase_command erase Erase flash memory +- * +- * Usage is: erase \<devicee> +- * +- * Erase the flash memory behind the device. It depends on the device given, +- * what area will be erased. If the device represents the whole flash memory +- * the whole memory will be erased. If the device represents a partition on +- * a main flash memory, only this partition part will be erased. +- * +- * Refer \b addpart, \b delpart and \b devinfo for partition handling. ++/** ++ * @page erase_command ++ ++<p> Erase the flash memory handled by this device. Which area will be ++erased depends on the device: If the device represents the whole flash ++memory, the whole memory will be erased. If the device represents a ++partition on a main flash memory, only this partition part will be ++erased. </p> ++ ++Refer to \ref addpart_command, \ref delpart_command and \ref ++devinfo_command for partition handling. ++ + */ + + static int do_protect(struct command *cmdtp, int argc, char *argv[]) +@@ -160,43 +162,57 @@ out: + return ret; + } + +-static const __maybe_unused char cmd_protect_help[] = +-"Usage: (un)protect <device> [area]\n" +-"(un)protect a flash device or parts of a device if an area specification\n" +-"is given\n"; ++BAREBOX_CMD_HELP_START(protect) ++BAREBOX_CMD_HELP_USAGE("protect <device> [area]\n") ++BAREBOX_CMD_HELP_SHORT("protect a flash device (or parts of a device, if an area is specified)\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(protect) + .cmd = do_protect, +- .usage = "enable FLASH write protection", ++ .usage = "enable flash write protection", + BAREBOX_CMD_HELP(cmd_protect_help) + BAREBOX_CMD_END + ++/** ++ * @page protect_command ++ ++Protect the flash memory behind the device. It depends on the device ++given, what area will be protected. If the device represents the whole ++flash memory the whole memory will be protected. If the device ++represents a partition on a main flash memory, only this partition part ++will be protected. ++ ++Refer addpart_command, delpart_command and devinfo_command for partition ++handling. ++ ++\todo Rework this documentation, what is an 'area'? Explain more about ++flashes here. ++ ++ */ ++ ++BAREBOX_CMD_HELP_START(unprotect) ++BAREBOX_CMD_HELP_USAGE("unprotect <device> [area]\n") ++BAREBOX_CMD_HELP_SHORT("unprotect a flash device (or parts of a device, if an area is specified)\n") ++BAREBOX_CMD_HELP_END ++ + BAREBOX_CMD_START(unprotect) + .cmd = do_protect, +- .usage = "disable FLASH write protection", +- BAREBOX_CMD_HELP(cmd_protect_help) ++ .usage = "disable flash write protection", ++ BAREBOX_CMD_HELP(cmd_unprotect_help) + BAREBOX_CMD_END + +-/** @page protect_command protect Protect a flash memory +- * +- * Usage is: protect \<devicee> +- * +- * Protect the flash memory behind the device. It depends on the device given, +- * what area will be protected. If the device represents the whole flash memory +- * the whole memory will be protected. If the device represents a partition on +- * a main flash memory, only this partition part will be protected. +- * +- * Refer \b addpart, \b delpart and \b devinfo for partition handling. +- */ ++/** ++ * @page unprotect_command ++ ++Unprotect the flash memory behind the device. It depends on the device given, ++what area will be unprotected. If the device represents the whole flash memory ++the whole memory will be unprotected. If the device represents a partition ++on a main flash memory, only this partition part will be unprotected. ++ ++Refer addpart_command, delpart_command and devinfo_command for partition ++handling. ++ ++\todo Rework this documentation, what does it mean? + +-/** @page unprotect_command unprotect Unprotect a flash memory +- * +- * Usage is: unprotect \<devicee> +- * +- * Unprotect the flash memory behind the device. It depends on the device given, +- * what area will be unprotected. If the device represents the whole flash memory +- * the whole memory will be unprotected. If the device represents a partition +- * on a main flash memory, only this partition part will be unprotected. +- * +- * Refer \b addpart, \b delpart and \b devinfo for partition handling. + */ ++ +diff --git a/commands/gpio.c b/commands/gpio.c +index 2575c1e..0cf19fe 100644 +--- a/commands/gpio.c ++++ b/commands/gpio.c +@@ -36,12 +36,14 @@ static int do_gpio_get_value(struct command *cmdtp, int argc, char *argv[]) + return value; + } + +-static const __maybe_unused char cmd_gpio_get_value_help[] = +-"Usage: gpio_set_value <gpio>\n"; ++BAREBOX_CMD_HELP_START(gpio_get_value) ++BAREBOX_CMD_HELP_USAGE("gpio_get_value <gpio>\n") ++BAREBOX_CMD_HELP_SHORT("get the value of an gpio input pin\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(gpio_get_value) + .cmd = do_gpio_get_value, +- .usage = "return a gpio's value", ++ .usage = "return value of a gpio pin", + BAREBOX_CMD_HELP(cmd_gpio_get_value_help) + BAREBOX_CMD_END + +@@ -60,8 +62,10 @@ static int do_gpio_set_value(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_gpio_set_value_help[] = +-"Usage: gpio_set_value <gpio> <value>\n"; ++BAREBOX_CMD_HELP_START(gpio_set_value) ++BAREBOX_CMD_HELP_USAGE("gpio_set_value <gpio> <value>\n") ++BAREBOX_CMD_HELP_SHORT("set the value of an gpio output pin\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(gpio_set_value) + .cmd = do_gpio_set_value, +@@ -85,13 +89,15 @@ static int do_gpio_direction_input(struct command *cmdtp, int argc, char *argv[] + return 0; + } + +-static const __maybe_unused char cmd_do_gpio_direction_input_help[] = +-"Usage: gpio_direction_input <gpio>\n"; ++BAREBOX_CMD_HELP_START(gpio_direction_input) ++BAREBOX_CMD_HELP_USAGE("gpio_direction_input <gpio>\n") ++BAREBOX_CMD_HELP_SHORT("set direction of a gpio pin to input\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(gpio_direction_input) + .cmd = do_gpio_direction_input, +- .usage = "set a gpio as output", +- BAREBOX_CMD_HELP(cmd_do_gpio_direction_input_help) ++ .usage = "set direction of a gpio pin to input", ++ BAREBOX_CMD_HELP(cmd_gpio_direction_input_help) + BAREBOX_CMD_END + + static int do_gpio_direction_output(struct command *cmdtp, int argc, char *argv[]) +@@ -111,12 +117,75 @@ static int do_gpio_direction_output(struct command *cmdtp, int argc, char *argv[ + return 0; + } + +-static const __maybe_unused char cmd_gpio_direction_output_help[] = +-"Usage: gpio_direction_output <gpio> <value>\n"; ++BAREBOX_CMD_HELP_START(gpio_direction_output) ++BAREBOX_CMD_HELP_USAGE("gpio_direction_output <gpio> <value>\n") ++BAREBOX_CMD_HELP_SHORT("set direction of a gpio pin to output\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(gpio_direction_output) + .cmd = do_gpio_direction_output, +- .usage = "set a gpio as output", ++ .usage = "set direction of a gpio pin to output", + BAREBOX_CMD_HELP(cmd_gpio_direction_output_help) + BAREBOX_CMD_END + ++/** ++ * @page gpio_for_users GPIO Handling ++ ++@section regular_gpio General usage information ++ ++These commands are available if the symbol @b CONFIG_GENERIC_GPIO and @b ++CONFIG_CMD_GPIO are enabled in Kconfig. ++ ++@note All gpio related commands take a number to identify the pad. This ++number is architecture dependent and may not directly correlate with the ++pad numbers. Due to this, it is also possible that the numbers changes ++between @b barebox releases. ++ ++@section gpio_dir_out Use Pad as GPIO Output ++@verbatim ++# gpio_direction_output <gpio_no> <initial_value> ++@endverbatim ++- gpio_no: Architecture dependend GPIO number ++- initial_value: Output value ++ ++<p> To avoid glitches on the pad the routines will first sett up the ++pad's value and afterwards switch the pad to output (if the silicon is ++able to do so). If the pad is already configured in non-GPIO mode (if ++available), this command may silently fail. </p> ++ ++@section gpio_dir_in Use Pad as GPIO Input ++@verbatim ++# gpio_direction_input <gpio_no> ++@endverbatim ++- gpio_no: Architecture dependent GPIO number ++ ++<p> If the pad is already configured in non-GPIO mode (if available), ++this command may silently fail. </p> ++ ++@section gpio_get_value Read Input Value from GPIO Pin ++@verbatim ++# gpio_get_value <gpio_no> ++@endverbatim ++ ++<p> Reads the current value of a GPIO pin and return the value as a ++shell return code. There is no visible output on stdout. You can check ++the return value by using "echo $?". </p> ++ ++<p> A return code other than '0' or '1' specifies an error code. </p> ++ ++<p> If the pad is not configured in GPIO mode, this command may silently ++fail and return garbage. </p> ++ ++@section gpio_set_value Set Output Value on GPIO Pin ++@verbatim ++# gpio_set_value <gpio_no> <value> ++@endverbatim ++- gpio_no: Architecture dependent GPIO number ++- value: Output value ++ ++<p> Set a new output value on pad with GPIO number \<gpio_no>. </p> ++ ++<p> If the pad is not configured in GPIO-mode, this command may silently ++fail. </p> ++ ++*/ +diff --git a/commands/linux16.c b/commands/linux16.c +index b15812f..5f412e2 100644 +--- a/commands/linux16.c ++++ b/commands/linux16.c +@@ -150,7 +150,7 @@ struct linux_kernel_header { + * (setup = 'real mode code' and kernel = 'protected mode code') to their + * default locations, switches back to real mode and runs the setup code. + */ +-static int do_linux16(cmd_tbl_t *cmdtp, int argc, char *argv[]) ++static int do_linux16(struct command *cmdtp, int argc, char *argv[]) + { + struct linux_kernel_header *lh = NULL; + int rc; +@@ -288,14 +288,22 @@ on_error: + return rc; + } + +-static const __maybe_unused char cmd_linux16_help[] = +-"Usage: linux16 <file>\n" +-"Boot a linux kernel via real mode code\n"; ++BAREBOX_CMD_HELP_START(linux16) ++BAREBOX_CMD_HELP_USAGE("linux16 <file>\n") ++BAREBOX_CMD_HELP_SHORT("Boot a kernel on x86 via real mode code.\n") ++BAREBOX_CMD_HELP_END + ++/** ++ * @page linux16_command ++ ++<p> Only kernel images in bzImage format are supported by now. See \ref ++x86_boot_preparation for more info about how to use this command.</p> ++ ++ */ + + BAREBOX_CMD_START(linux16) + .cmd = do_linux16, +- .usage = "boot linux kernel", ++ .usage = "boot a linux kernel", + BAREBOX_CMD_HELP(cmd_linux16_help) + BAREBOX_CMD_END + +@@ -305,15 +313,6 @@ BAREBOX_CMD_END + */ + + /** +- * @page linux16_command linux16: Boot a bzImage kernel on x86 +- * +- * Usage is: linux16 \<file\> +- * +- * Boot a linux kernel via real mode code. Only kernel images in the +- * @p bzImage format are supported. +- */ +- +-/** + * @page x86_boot_preparation Linux Preparation on x86 + * + * Due to some real mode constraints, starting Linux is somehow tricky. +diff --git a/commands/loadb.c b/commands/loadb.c +index acfb94f..faf4a97 100644 +--- a/commands/loadb.c ++++ b/commands/loadb.c +@@ -636,7 +636,6 @@ static ulong load_serial_ymodem(void) + 0) { + size += res; + addr += res; +- flush_cache((ulong) yModemBuf, res); + wr = write(ofd, ymodemBuf, res); + if (res != wr) { + perror("ymodem"); +diff --git a/commands/loadenv.c b/commands/loadenv.c +index 14fbf1e..c33c34f 100644 +--- a/commands/loadenv.c ++++ b/commands/loadenv.c +@@ -43,28 +43,22 @@ static int do_loadenv(struct command *cmdtp, int argc, char *argv[]) + return envfs_load(filename, dirname); + } + +-static const __maybe_unused char cmd_loadenv_help[] = +-"Usage: loadenv [ENVFS] [DIRECTORY]\n" +-"Load the persistent storage contained in <envfs> to the directory\n" +-"<directory>.\n" +-"If ommitted <directory> defaults to /env and <envfs> defaults to /dev/env0.\n" +-"Note that envfs can only handle files. Directories are skipped silently.\n"; ++BAREBOX_CMD_HELP_START(loadenv) ++BAREBOX_CMD_HELP_USAGE("loadenv [ENVFS] [DIRECTORY]\n") ++BAREBOX_CMD_HELP_SHORT("Load environment from ENVFS into DIRECTORY (default: /dev/env0 -> /env).\n") ++BAREBOX_CMD_HELP_END ++ ++/** ++ * @page loadenv_command ++ ++ENVFS can only handle files, directories are skipped silently. ++ ++\todo This needs proper documentation. What is ENVFS, why is it FS etc. Explain the concepts. ++ ++ */ + + BAREBOX_CMD_START(loadenv) + .cmd = do_loadenv, +- .usage = "load environment from persistent storage", ++ .usage = "Load environment from ENVFS into DIRECTORY (default: /dev/env0 -> /env).", + BAREBOX_CMD_HELP(cmd_loadenv_help) + BAREBOX_CMD_END +- +-/** +- * @page loadenv_command loadenv +- * +- * Usage: loadenv [\<directory>] [\<envfs>] +- * +- * Load the persistent storage contained in \<envfs> to the directory \<directory>. +- * +- * If ommitted \<directory> defaults to \c /env and \<envfs> defaults to +- * \c /dev/env0. +- * +- * @note envfs can only handle files. Directories are skipped silently. +- */ +diff --git a/commands/loads.c b/commands/loads.c +index 8269af1..6e0dc7f 100644 +--- a/commands/loads.c ++++ b/commands/loads.c +@@ -175,7 +175,6 @@ load_serial (ulong offset) + "## Total Size = 0x%08lX = %ld Bytes\n", + start_addr, end_addr, size, size + ); +- flush_cache (start_addr, size); + sprintf(buf, "%lX", size); + setenv("filesize", buf); + return (addr); +diff --git a/commands/ls.c b/commands/ls.c +index a02ccfe..4f9c408 100644 +--- a/commands/ls.c ++++ b/commands/ls.c +@@ -194,10 +194,11 @@ static int do_ls(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_ls_help[] = +-"Usage: ls [OPTION]... [FILE]...\n" +-"List information about the FILEs (the current directory by default).\n" +-" -R list subdirectories recursively\n"; ++BAREBOX_CMD_HELP_START(ls) ++BAREBOX_CMD_HELP_USAGE("ls [OPTIONS] [FILES]\n") ++BAREBOX_CMD_HELP_SHORT("List information about the FILEs (the current directory by default).\n") ++BAREBOX_CMD_HELP_OPT ("-R", "list subdirectories recursively\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(ls) + .cmd = do_ls, +diff --git a/commands/mem.c b/commands/mem.c +index bc84f6d..73bf915 100644 +--- a/commands/mem.c ++++ b/commands/mem.c +@@ -110,7 +110,7 @@ int memory_display(char *addr, ulong offs, ulong nbytes, int size) + return 0; + } + +-int open_and_lseek(const char *filename, int mode, off_t pos) ++static int open_and_lseek(const char *filename, int mode, off_t pos) + { + int fd, ret; + +diff --git a/commands/mount.c b/commands/mount.c +index 8e4388e..52d1700 100644 +--- a/commands/mount.c ++++ b/commands/mount.c +@@ -58,49 +58,45 @@ static int do_mount(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_mount_help[] = +-"Usage: mount: list mounted filesystems\n" +-"or: mount <device> <fstype> <mountpoint>\n" +-"\n" +-"Mount a filesystem of a given type to a mountpoint.\n" +-"<device> can be one of /dev/* or some arbitrary string if no\n" +-"device is needed for this driver (for example ramfs).\n" +-"<fstype> is the filesystem driver to use. Try the 'devinfo' command\n" +-"for a list of available drivers.\n" +-"<mountpoint> must be an empty directory descending directly from the\n" +-"root directory.\n"; ++BAREBOX_CMD_HELP_START(mount) ++BAREBOX_CMD_HELP_USAGE("mount [<device> <fstype> <mountpoint>]\n") ++BAREBOX_CMD_HELP_SHORT("Mount a filesystem of a given type to a mountpoint.\n") ++BAREBOX_CMD_HELP_SHORT("If no argument is given, list mounted filesystems.\n") ++BAREBOX_CMD_HELP_END + +-BAREBOX_CMD_START(mount) +- .cmd = do_mount, +- .usage = "mount a filesystem to a device", +- BAREBOX_CMD_HELP(cmd_mount_help) +-BAREBOX_CMD_END ++/** ++ * @page mount_command ++ ++<ul> ++<li>\<device> can be a device in /dev or some arbitrary string if no ++ device is needed for this driver, i.e. on ramfs. </li> ++<li>\<fstype> is the filesystem driver. A list of available drivers can ++ be shown with the \ref devinfo_command command.</li> ++<li>\<mountpoint> must be an empty directory, one level below the / ++ directory.</li> ++</ul> + +-/** @page mount_command mount +- * Usage: mount [\<device> \<fstype> \<mountpoint>] +- * +- * Mounts a filesystem of a given \<fstype> on a \<device> to a \<mountpoint>. +- * \<device> can be one of /dev/ * or some arbitrary string if no +- * device is needed for this driver (for example ramfs). +- * +- * \<fstype> is the filesystem driver to use. Try the 'devinfo' command +- * for a list of available drivers. +- * +- * \<mountpoint> must be an empty directory descending directly from the +- * root directory. + */ + +-/** @page how_mount_works How mount works in barebox +- * +- * Mounting a filesystem ontop of a device is working like devices and drivers +- * are finding together. +- * +- * The mount command creates a new device with the filesystem name as the +- * driver for this "device". So the framework is able to merge both parts +- * together. +- * +- * By the way: With this feature its impossible to accidentely remove +- * partitions in use. A partition is internally also a device. If its mounted +- * it will be marked as busy, so an delpart command fails, until the filesystem +- * has been unmounted. ++/** ++ * @page how_mount_works How mount works in barebox ++ ++Mounting a filesystem ontop of a device is working like devices and ++drivers are finding together. ++ ++The mount command creates a new device with the filesystem name as the ++driver for this "device". So the framework is able to merge both parts ++together. ++ ++By the way: With this feature its impossible to accidentely remove ++partitions in use. A partition is internally also a device. If its ++mounted it will be marked as busy, so an delpart command fails, until ++the filesystem has been unmounted. ++ + */ ++ ++BAREBOX_CMD_START(mount) ++ .cmd = do_mount, ++ .usage = "Mount a filesystem of a given type to a mountpoint or list mounted filesystems.", ++ BAREBOX_CMD_HELP(cmd_mount_help) ++BAREBOX_CMD_END +diff --git a/commands/partition.c b/commands/partition.c +index 7794925..db9b9fb 100644 +--- a/commands/partition.c ++++ b/commands/partition.c +@@ -149,19 +149,24 @@ static int do_addpart(struct command * cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_addpart_help[] = +-"Usage: addpart <device> <partition description>\n" +-"\n" +-"addpart adds a partition description to a device. The partition description\n" +-"has the form\n" +-"size1[@offset1](name1)[ro],size2[@offset2](name2)[ro],...\n" +-"<device> is the device name under. Size and offset can be given in decimal\n" +-"or - if prefixed with 0x in hex. Both can have an optional suffix K,M,G.\n" +-"The size of the last partition can be specified as '-' for the remaining\n" +-"space of the device.\n" +-"This format is the same as used in the Linux kernel for cmdline mtd partitions.\n" +-"\n" +-"Note: That this command has to be reworked and will probably change it's API."; ++BAREBOX_CMD_HELP_START(addpart) ++BAREBOX_CMD_HELP_USAGE("addpart <device> <part_desc>\n") ++BAREBOX_CMD_HELP_SHORT("Add a partition description to a device.\n") ++BAREBOX_CMD_HELP_OPT ("<device>", "device being worked on\n") ++BAREBOX_CMD_HELP_OPT ("<part_desc>", "size1[@offset1](name1)[ro],size2[@offset2](name2)[ro],...\n") ++BAREBOX_CMD_HELP_END ++ ++/** ++ * @page addpart_command ++ ++The size and the offset can be given in decimal (without any prefix) and ++in hex (prefixed with 0x). Both can have an optional suffix K, M or G. ++The size of the last partition can be specified as '-' for the remaining ++space on the device. This format is the same as used by the Linux ++kernel or cmdline mtd partitions. ++ ++\todo This command has to be reworked and will probably change it's API. ++*/ + + BAREBOX_CMD_START(addpart) + .cmd = do_addpart, +@@ -169,26 +174,6 @@ BAREBOX_CMD_START(addpart) + BAREBOX_CMD_HELP(cmd_addpart_help) + BAREBOX_CMD_END + +-/** @page addpart_command addpart Add a partition to a device +- * +- * Usage is: addpart \<device> \<partition description> +- * +- * Adds a partition description to a device. The partition description has the +- * form +- * +- * size1[@offset1](name1)[ro],size2[@offset2](name2)[ro],... +- * +- * \<device> is the device name under. Size and offset can be given in decimal +- * or - if prefixed with 0x - in hex. Both can have an optional suffix K,M,G. +- * The size of the last partition can be specified as '-' for the remaining +- * space of the device. +- * +- * @note The format is the same as used in the Linux kernel for cmdline mtd +- * partitions. +- * +- * @note This command has to be reworked and will probably change it's API. +- */ +- + static int do_delpart(struct command * cmdtp, int argc, char *argv[]) + { + int i, err; +@@ -204,9 +189,21 @@ static int do_delpart(struct command * cmdtp, int argc, char *argv[]) + return 1; + } + +-static const __maybe_unused char cmd_delpart_help[] = +-"Usage: delpart FILE...\n" +-"Delete partitions previously added to a device with addpart.\n"; ++BAREBOX_CMD_HELP_START(delpart) ++BAREBOX_CMD_HELP_USAGE("delpart <part 1> [<part n>] \n") ++BAREBOX_CMD_HELP_SHORT("Delete partitions previously added to a device with addpart.\n") ++BAREBOX_CMD_HELP_END ++ ++/** ++ * @page delpart_command ++ ++Partitions are created by adding their description with the addpart ++command. If you want to get rid of a partition again, use delpart. The ++argument list is taken as a list of partitions to be deleted. ++ ++\todo Add an example ++ ++ */ + + BAREBOX_CMD_START(delpart) + .cmd = do_delpart, +@@ -214,9 +211,3 @@ BAREBOX_CMD_START(delpart) + BAREBOX_CMD_HELP(cmd_delpart_help) + BAREBOX_CMD_END + +-/** @page delpart_command delpart Delete a partition +- * +- * Usage is: delpart \<partions> +- * +- * Delete a partition previously added to a device with addpart. +- */ +diff --git a/commands/printenv.c b/commands/printenv.c +index e6fc0e4..4078bbc 100644 +--- a/commands/printenv.c ++++ b/commands/printenv.c +@@ -65,26 +65,22 @@ static int do_printenv(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_printenv_help[] = +-"\n - print values of all environment variables\n" +-"printenv name ...\n" +-" - print value of environment variable 'name'\n"; ++BAREBOX_CMD_HELP_START(printenv) ++BAREBOX_CMD_HELP_USAGE("printenv [variable]\n") ++BAREBOX_CMD_HELP_SHORT("Print value of one or all environment variables.\n") ++BAREBOX_CMD_HELP_END + ++/** ++ * @page printenv_command ++ ++<p>If an argument is given, printenv prints the content of an environment ++variable to the terminal. If no argument is specified, all variables are ++printed.</p> ++ ++ */ + + BAREBOX_CMD_START(printenv) + .cmd = do_printenv, +- .usage = "print environment variables", ++ .usage = "Print value of one or all environment variables.", + BAREBOX_CMD_HELP(cmd_printenv_help) + BAREBOX_CMD_END +- +-/** +- * @page printenv_command printenv +- * +- * Usage: printenv [\<name>] +- * +- * Print environment variables. +- * If \<name> was given, it prints out its content if the environment variable +- * \<name> exists. +- * +- * Without the \<name> argument all current environment variables are printed. +- */ +diff --git a/commands/saveenv.c b/commands/saveenv.c +index 42ea58f..2f969fe 100644 +--- a/commands/saveenv.c ++++ b/commands/saveenv.c +@@ -94,12 +94,10 @@ out: + return ret; + } + +-static const __maybe_unused char cmd_saveenv_help[] = +-"Usage: saveenv [<envfs>] [<directory>]\n" +-"Save the files in <directory> to the persistent storage device <envfs>.\n" +-"<envfs> is normally a block in flash, but could be any other file.\n" +-"If ommitted <directory> defaults to /env and <envfs> defaults to /dev/env0.\n" +-"Note that envfs can only handle files. Directories are skipped silently.\n"; ++BAREBOX_CMD_HELP_START(saveenv) ++BAREBOX_CMD_HELP_USAGE("saveenv [envfs] [directory]\n") ++BAREBOX_CMD_HELP_SHORT("Save the files in <directory> to the persistent storage device <envfs>.\n") ++BAREBOX_CMD_HELP_END + + BAREBOX_CMD_START(saveenv) + .cmd = do_saveenv, +@@ -108,15 +106,14 @@ BAREBOX_CMD_START(saveenv) + BAREBOX_CMD_END + + /** +- * @page saveenv_command saveenv +- * +- * Usage: saveenv [\<envfs>] [\<directory>] +- * +- * Save the files in \<directory> to the persistent storage device \<envfs>. +- * \<envfs> is normally a block in flash, but could be any other file. +- * +- * If ommitted \<directory> defaults to \c /env and \<envfs> defaults to +- * \c /dev/env0. +- * +- * @note envfs can only handle files. Directories are skipped silently. ++ * @page saveenv_command ++ ++<p>\<envfs> is usually a block in flash but can be any other file. If ++ommitted, \<directory> defaults to /env and \<envfs> defaults to ++/dev/env0. Note that envfs can only handle files, directories are being ++skipped silently.</p> ++ ++\todo What does 'block in flash' mean? Add example. ++ + */ ++ +diff --git a/commands/setenv.c b/commands/setenv.c +index 257348f..e39db20 100644 +--- a/commands/setenv.c ++++ b/commands/setenv.c +@@ -38,27 +38,23 @@ static int do_setenv(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_setenv_help[] = +-"name value ...\n" +-" - set environment variable 'name' to 'value ...'\n" +-"setenv name\n" +-" - delete environment variable 'name'\n"; ++BAREBOX_CMD_HELP_START(setenv) ++BAREBOX_CMD_HELP_USAGE("setenv <name> [<value>]\n") ++BAREBOX_CMD_HELP_SHORT("Set environment variable to a value or delete if value is avoided.\n") ++BAREBOX_CMD_HELP_END + ++/** ++ * @page setenv_command ++ ++<p> This command is only available if the simple command line parser is ++in use. Within the hush shell, \c setenv is not required.</p> ++ ++\todo Check if kconfig does this correctly. ++ ++ */ + + BAREBOX_CMD_START(setenv) + .cmd = do_setenv, + .usage = "set environment variables", + BAREBOX_CMD_HELP(cmd_setenv_help) + BAREBOX_CMD_END +- +-/** +- * @page setenv_command setenv: set an environment variable +- * +- * Usage: setenv \<name> [\<value>] +- * +- * Set environment variable \<name> to \<value>. Without a given value, the +- * environment variable will be deleted. +- * +- * @note This command is only available if the simple command line parser is +- * in use. Within the hush shell \c setenv is not required. +- */ +diff --git a/commands/version.c b/commands/version.c +index 6c683d9..2b3ac05 100644 +--- a/commands/version.c ++++ b/commands/version.c +@@ -26,7 +26,6 @@ + + static int do_version(struct command *cmdtp, int argc, char *argv[]) + { +- extern char version_string[]; + printf ("\n%s\n", version_string); + return 0; + } +diff --git a/common/Kconfig b/common/Kconfig +index ad70cde..617f640 100644 +--- a/common/Kconfig ++++ b/common/Kconfig +@@ -248,6 +248,13 @@ config HUSH_FANCY_PROMPT + Allow to set PS1 from the command line. PS1 can have several escaped commands + like \h for CONFIG_BOARDINFO or \w for the current working directory. + ++config HUSH_GETOPT ++ bool ++ depends on SHELL_HUSH ++ prompt "enable builtin getopt" ++ help ++ This enables a getopt function builtin to hush. ++ + config CMDLINE_EDITING + bool + prompt "Enable command line editing" +@@ -382,6 +389,22 @@ config DEFAULT_ENVIRONMENT + Enabling this option will give you a default environment when + the environment found in the environment sector is invalid + ++config DEFAULT_ENVIRONMENT_GENERIC ++ bool ++ depends on DEFAULT_ENVIRONMENT ++ select SHELL_HUSH ++ select HUSH_GETOPT ++ select CMD_CRC ++ select CMD_CRC_CMP ++ prompt "Default environment generic" ++ help ++ With this option barebox will use the generic default ++ environment found under defaultenv/ in the src tree. ++ The Directory given with DEFAULT_ENVIRONMENT_PATH ++ will be added to the default environment. This should ++ at least contain a /env/config file. ++ This will be able to overwrite the files from defaultenv. ++ + config DEFAULT_ENVIRONMENT_PATH + string + depends on DEFAULT_ENVIRONMENT +diff --git a/common/Makefile b/common/Makefile +index e56dbc2..753455b 100644 +--- a/common/Makefile ++++ b/common/Makefile +@@ -26,12 +26,18 @@ ifdef CONFIG_DEFAULT_ENVIRONMENT + $(obj)/startup.o: include/generated/barebox_default_env.h + $(obj)/env.o: include/generated/barebox_default_env.h + +-ENV_FILES := $(shell cd $(srctree); for i in $(CONFIG_DEFAULT_ENVIRONMENT_PATH); do find $${i} -type f -exec readlink -f {} \;; done) ++ifeq ($(CONFIG_DEFAULT_ENVIRONMENT_GENERIC),y) ++DEFAULT_ENVIRONMENT_PATH = "defaultenv" ++endif ++ ++DEFAULT_ENVIRONMENT_PATH += $(CONFIG_DEFAULT_ENVIRONMENT_PATH) ++ ++ENV_FILES := $(shell cd $(srctree); for i in $(DEFAULT_ENVIRONMENT_PATH); do find $${i} -type f -exec readlink -f {} \;; done) + + endif # ifdef CONFIG_DEFAULT_ENVIRONMENT + + barebox_default_env: $(ENV_FILES) +- $(Q)$(srctree)/scripts/genenv $(srctree) $(objtree) $(CONFIG_DEFAULT_ENVIRONMENT_PATH) ++ $(Q)$(srctree)/scripts/genenv $(srctree) $(objtree) $(DEFAULT_ENVIRONMENT_PATH) + + include/generated/barebox_default_env.h: barebox_default_env + $(Q)cat $< | $(objtree)/scripts/bin2c default_environment > $@ +diff --git a/common/console.c b/common/console.c +index 204a08c..82786f2 100644 +--- a/common/console.c ++++ b/common/console.c +@@ -43,8 +43,6 @@ EXPORT_SYMBOL(console_list); + #define CONSOLE_INIT_EARLY 1 + #define CONSOLE_INIT_FULL 2 + +-extern char version_string[]; +- + static void display_banner (void) + { + printf (RELOC("\n\n%s\n\n"), RELOC_VAR(version_string)); +@@ -120,7 +118,7 @@ static int console_baudrate_set(struct device_d *dev, struct param_d *param, + static struct kfifo *console_input_buffer; + static struct kfifo *console_output_buffer; + +-int getc_buffer_flush(void) ++static int getc_buffer_flush(void) + { + console_input_buffer = kfifo_alloc(1024); + console_output_buffer = kfifo_alloc(1024); +@@ -247,7 +245,9 @@ int tstc(void) + } + EXPORT_SYMBOL(tstc); + +-void __early_initdata *early_console_base; ++#ifdef CONFIG_HAS_EARLY_INIT ++static void __early_initdata *early_console_base; ++#endif + + void console_putc(unsigned int ch, char c) + { +diff --git a/common/dlmalloc.c b/common/dlmalloc.c +index 83b1e18..ff63fbe 100644 +--- a/common/dlmalloc.c ++++ b/common/dlmalloc.c +@@ -792,7 +792,7 @@ typedef struct malloc_chunk *mbinptr; + #define IAV(i) bin_at(i), bin_at(i) + + static mbinptr av_[NAV * 2 + 2] = { +- 0, 0, ++ NULL, NULL, + IAV (0), IAV (1), IAV (2), IAV (3), IAV (4), IAV (5), IAV (6), IAV (7), + IAV (8), IAV (9), IAV (10), IAV (11), IAV (12), IAV (13), IAV (14), + IAV (15), +@@ -1209,7 +1209,7 @@ void *malloc(size_t bytes) + INTERNAL_SIZE_T nb; + + if ((long) bytes < 0) +- return 0; ++ return NULL; + + nb = request2size(bytes); /* padded request size; */ + +@@ -1364,7 +1364,7 @@ void *malloc(size_t bytes) + /* Try to extend */ + malloc_extend_top(nb); + if ((remainder_size = chunksize(top) - nb) < (long) MINSIZE) +- return 0; /* propagate failure */ ++ return NULL; /* propagate failure */ + } + + victim = top; +@@ -1405,7 +1405,7 @@ void free(void *mem) + mchunkptr fwd; /* misc temp for linking */ + int islr; /* track whether merging with last_remainder */ + +- if (mem == 0) /* free(0) has no effect */ ++ if (!mem) /* free(0) has no effect */ + return; + + p = mem2chunk(mem); +@@ -1524,15 +1524,15 @@ void *realloc(void *oldmem, size_t bytes) + #ifdef REALLOC_ZERO_BYTES_FREES + if (bytes == 0) { + free(oldmem); +- return 0; ++ return NULL; + } + #endif + + if ((long)bytes < 0) +- return 0; ++ return NULL; + + /* realloc of null is supposed to be same as malloc */ +- if (oldmem == 0) ++ if (!oldmem) + return malloc(bytes); + + newp = oldp = mem2chunk(oldmem); +@@ -1570,7 +1570,7 @@ void *realloc(void *oldmem, size_t bytes) + goto split; + } + } else { +- next = 0; ++ next = NULL; + nextsize = 0; + } + +@@ -1582,7 +1582,7 @@ void *realloc(void *oldmem, size_t bytes) + + /* try forward + backward first to save a later consolidation */ + +- if (next != 0) { ++ if (next) { + /* into top */ + if (next == top) { + if ((long) +@@ -1618,8 +1618,7 @@ void *realloc(void *oldmem, size_t bytes) + } + + /* backward only */ +- if (prev != 0 +- && (long)(prevsize + newsize) >= (long)nb) { ++ if (prev && (long)(prevsize + newsize) >= (long)nb) { + unlink(prev, bck, fwd); + newp = prev; + newsize += prevsize; +@@ -1633,8 +1632,8 @@ void *realloc(void *oldmem, size_t bytes) + + newmem = malloc(bytes); + +- if (newmem == 0) /* propagate failure */ +- return 0; ++ if (!newmem) /* propagate failure */ ++ return NULL; + + /* Avoid copy if newp is next chunk after oldp. */ + /* (This can only happen when new chunk is sbrk'ed.) */ +@@ -1697,7 +1696,7 @@ void *memalign(size_t alignment, size_t bytes) + long remainder_size; /* its size */ + + if ((long) bytes < 0) +- return 0; ++ return NULL; + + /* If need less alignment than we give anyway, just relay to malloc */ + +@@ -1714,8 +1713,8 @@ void *memalign(size_t alignment, size_t bytes) + nb = request2size(bytes); + m = (char*)(malloc (nb + alignment + MINSIZE)); + +- if (m == 0) +- return 0; /* propagate failure */ ++ if (!m) ++ return NULL; /* propagate failure */ + + p = mem2chunk(m); + +@@ -1763,6 +1762,7 @@ void *memalign(size_t alignment, size_t bytes) + return chunk2mem(p); + } + ++#if 0 + /* + * valloc just invokes memalign with alignment argument equal + * to the page size of the system (or as near to this as can +@@ -1772,6 +1772,7 @@ void *valloc(size_t bytes) + { + return memalign(malloc_getpagesize, bytes); + } ++#endif + + /* + * pvalloc just invokes valloc for the nearest pagesize +@@ -1802,10 +1803,10 @@ void *calloc(size_t n, size_t elem_size) + void *mem = malloc(sz); + + if ((long)n < 0) +- return 0; ++ return NULL; + +- if (mem == 0) +- return 0; ++ if (!mem) ++ return NULL; + else { + p = mem2chunk(mem); + +@@ -1915,7 +1916,7 @@ size_t malloc_usable_size(void *mem) + { + mchunkptr p; + +- if (mem == 0) ++ if (!mem) + return 0; + else { + p = mem2chunk(mem); +diff --git a/common/env.c b/common/env.c +index edaf388..f81bd46 100644 +--- a/common/env.c ++++ b/common/env.c +@@ -137,7 +137,7 @@ const char *getenv (const char *name) + const char *val; + + if (strchr(name, '.')) { +- const char *ret = 0; ++ const char *ret = NULL; + char *devstr = strdup(name); + char *par = strchr(devstr, '.'); + struct device_d *dev; +diff --git a/common/environment.c b/common/environment.c +index 0eb7e6b..e5f24ec 100644 +--- a/common/environment.c ++++ b/common/environment.c +@@ -109,7 +109,7 @@ int envfs_save(char *filename, char *dirname) + struct action_data data; + void *buf = NULL; + +- data.writep = 0; ++ data.writep = NULL; + data.base = dirname; + + /* first pass: calculate size */ +diff --git a/common/hush.c b/common/hush.c +index 19e35f5..77610bb 100644 +--- a/common/hush.c ++++ b/common/hush.c +@@ -120,6 +120,8 @@ + #include <fs.h> + #include <libbb.h> + #include <glob.h> ++#include <getopt.h> ++#include <linux/list.h> + + /*cmd_boot.c*/ + extern int do_bootd(struct command *cmdtp, int flag, int argc, char *argv[]); /* do_bootd */ +@@ -174,6 +176,12 @@ typedef enum { + #define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */ + #define FLAG_REPARSING (1 << 2) /* >=2nd pass */ + ++struct option { ++ struct list_head list; ++ char opt; ++ char *optarg; ++}; ++ + /* This holds pointers to the various results of parsing */ + struct p_context { + struct child_prog *child; +@@ -187,6 +195,9 @@ struct p_context { + + char **global_argv; + unsigned int global_argc; ++ ++ int options_parsed; ++ struct list_head options; + }; + + +@@ -267,13 +278,14 @@ static void setup_string_in_str(struct in_str *i, const char *s); + static int free_pipe_list(struct pipe *head, int indent); + static int free_pipe(struct pipe *pi, int indent); + /* really run the final data structures: */ +-static int run_list_real(struct pipe *pi); +-static int run_pipe_real(struct pipe *pi); ++static int run_list_real(struct p_context *ctx, struct pipe *pi); ++static int run_pipe_real(struct p_context *ctx, struct pipe *pi); + /* extended glob support: */ + /* variable assignment: */ + static int is_assignment(const char *s); + /* data structure manipulation: */ + static void initialize_context(struct p_context *ctx); ++static void release_context(struct p_context *ctx); + static int done_word(o_string *dest, struct p_context *ctx); + static int done_command(struct p_context *ctx); + static int done_pipe(struct p_context *ctx, pipe_style type); +@@ -350,7 +362,7 @@ static int b_addqchr(o_string *o, int ch, int quote) + } + + /* belongs in utility.c */ +-char *simple_itoa(unsigned int i) ++static char *simple_itoa(unsigned int i) + { + /* 21 digits plus null terminator, good for 64-bit or smaller ints */ + static char local[22]; +@@ -498,6 +510,50 @@ static void setup_string_in_str(struct in_str *i, const char *s) + i->p = s; + } + ++#ifdef CONFIG_HUSH_GETOPT ++static int builtin_getopt(struct p_context *ctx, struct child_prog *child) ++{ ++ char *optstring, *var; ++ int opt; ++ char opta[2]; ++ struct option *o; ++ ++ if (child->argc != 3) ++ return -2 - 1; ++ ++ optstring = child->argv[1]; ++ var = child->argv[2]; ++ ++ getopt_reset(); ++ ++ if (!ctx->options_parsed) { ++ while((opt = getopt(ctx->global_argc, ctx->global_argv, optstring)) > 0) { ++ o = xzalloc(sizeof(*o)); ++ o->opt = opt; ++ o->optarg = xstrdup(optarg); ++ list_add_tail(&o->list, &ctx->options); ++ } ++ } ++ ++ ctx->options_parsed = 1; ++ ++ if (list_empty(&ctx->options)) ++ return -1; ++ ++ o = list_first_entry(&ctx->options, struct option, list); ++ ++ opta[0] = o->opt; ++ opta[1] = 0; ++ setenv(var, opta); ++ setenv("OPTARG", o->optarg); ++ ++ free(o->optarg); ++ list_del(&o->list); ++ free(o); ++ ++ return 0; ++} ++#endif + + /* run_pipe_real() starts all the jobs, but doesn't wait for anything + * to finish. See checkjobs(). +@@ -515,7 +571,7 @@ static void setup_string_in_str(struct in_str *i, const char *s) + * now has its stdout directed to the input of the appropriate pipe, + * so this routine is noticeably simpler. + */ +-static int run_pipe_real(struct pipe *pi) ++static int run_pipe_real(struct p_context *ctx, struct pipe *pi) + { + int i; + int nextin; +@@ -541,7 +597,7 @@ static int run_pipe_real(struct pipe *pi) + if (pi->num_progs == 1 && child->group) { + int rcode; + debug("non-subshell grouping\n"); +- rcode = run_list_real(child->group); ++ rcode = run_list_real(ctx, child->group); + return rcode; + } else if (pi->num_progs == 1 && pi->progs[0].argv != NULL) { + for (i=0; is_assignment(child->argv[i]); i++) { /* nothing */ } +@@ -580,13 +636,17 @@ static int run_pipe_real(struct pipe *pi) + } + if (child->sp) { + char * str = NULL; +- struct p_context ctx; ++ struct p_context ctx1; + str = make_string((child->argv + i)); +- parse_string_outer(&ctx, str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING); ++ parse_string_outer(&ctx1, str, FLAG_EXIT_FROM_LOOP | FLAG_REPARSING); ++ release_context(&ctx1); + free(str); + return last_return_code; + } +- ++#ifdef CONFIG_HUSH_GETOPT ++ if (!strcmp(child->argv[i], "getopt")) ++ return builtin_getopt(ctx, child); ++#endif + if (strchr(child->argv[i], '/')) { + return execute_script(child->argv[i], child->argc-i, &child->argv[i]); + } +@@ -601,7 +661,7 @@ static int run_pipe_real(struct pipe *pi) + return -1; + } + +-static int run_list_real(struct pipe *pi) ++static int run_list_real(struct p_context *ctx, struct pipe *pi) + { + char *save_name = NULL; + char **list = NULL; +@@ -699,7 +759,7 @@ static int run_list_real(struct pipe *pi) + } + if (pi->num_progs == 0) + continue; +- rcode = run_pipe_real(pi); ++ rcode = run_pipe_real(ctx, pi); + debug("run_pipe_real returned %d\n",rcode); + if (rcode < -1) { + last_return_code = -rcode - 2; +@@ -790,6 +850,7 @@ static int globhack(const char *src, int flags, glob_t *pglob) + } + dest = xmalloc(cnt); + if (!(flags & GLOB_APPEND)) { ++ globfree(pglob); + pglob->gl_pathv = NULL; + pglob->gl_pathc = 0; + pglob->gl_offs = 0; +@@ -853,11 +914,11 @@ static int xglob(o_string *dest, int flags, glob_t *pglob) + } + + /* Select which version we will use */ +-static int run_list(struct pipe *pi) ++static int run_list(struct p_context *ctx, struct pipe *pi) + { + int rcode = 0; + +- rcode = run_list_real(pi); ++ rcode = run_list_real(ctx, pi); + + /* free_pipe_list has the side effect of clearing memory + * In the long run that function can be merged with run_list_real, +@@ -887,7 +948,7 @@ static int set_local_var(const char *s, int flg_export) + * NAME=VALUE format. So the first order of business is to + * split 's' on the '=' into 'name' and 'value' */ + value = strchr(name, '='); +- if (value==0 && ++value==0) { ++ if (!value) { + free(name); + return -1; + } +@@ -928,9 +989,23 @@ static void initialize_context(struct p_context *ctx) + ctx->w=RES_NONE; + ctx->stack=NULL; + ctx->old_flag=0; ++ ctx->options_parsed = 0; ++ INIT_LIST_HEAD(&ctx->options); + done_command(ctx); /* creates the memory for working child */ + } + ++static void release_context(struct p_context *ctx) ++{ ++#ifdef CONFIG_HUSH_GETOPT ++ struct option *opt, *tmp; ++ ++ list_for_each_entry_safe(opt, tmp, &ctx->options, list) { ++ free(opt->optarg); ++ free(opt); ++ } ++#endif ++} ++ + /* normal return is 0 + * if a reserved word is found, and processed, return 1 + * should handle if, then, elif, else, fi, for, while, until, do, done. +@@ -1371,7 +1446,7 @@ static int parse_stream_outer(struct p_context *ctx, struct in_str *inp, int fla + done_word(&temp, ctx); + done_pipe(ctx,PIPE_SEQ); + if (ctx->list_head->num_progs) { +- code = run_list(ctx->list_head); ++ code = run_list(ctx, ctx->list_head); + } else { + free_pipe_list(ctx->list_head, 0); + continue; +@@ -1533,7 +1608,12 @@ static char * make_string(char ** inp) + int run_command (const char *cmd, int flag) + { + struct p_context ctx; +- return parse_string_outer(&ctx, cmd, FLAG_PARSE_SEMICOLON); ++ int ret; ++ ++ ret = parse_string_outer(&ctx, cmd, FLAG_PARSE_SEMICOLON); ++ release_context(&ctx); ++ ++ return ret; + } + + static int execute_script(const char *path, int argc, char *argv[]) +@@ -1564,6 +1644,7 @@ static int source_script(const char *path, int argc, char *argv[]) + + ret = parse_string_outer(&ctx, script, FLAG_PARSE_SEMICOLON); + ++ release_context(&ctx); + free(script); + + return ret; +@@ -1577,6 +1658,7 @@ int run_shell(void) + + setup_file_in_str(&input); + rcode = parse_stream_outer(&ctx, &input, FLAG_PARSE_SEMICOLON); ++ release_context(&ctx); + return rcode; + } + +@@ -1627,6 +1709,31 @@ BAREBOX_CMD_START(source) + BAREBOX_CMD_HELP(cmd_source_help) + BAREBOX_CMD_END + ++#ifdef CONFIG_HUSH_GETOPT ++static int do_getopt(struct command *cmdtp, int argc, char *argv[]) ++{ ++ /* ++ * This function is never reached. The 'getopt' command is ++ * only here to provide a help text for the getopt builtin. ++ */ ++ return 0; ++} ++ ++static const __maybe_unused char cmd_getopt_help[] = ++"Usage: getopt <optstring> <var>\n" ++"\n" ++"hush option parser. <optstring> is a string with valid options. Add\n" ++"a colon to an options if this option has a required argument or two\n" ++"colons for an optional argument. The current option is saved in <var>,\n" ++"arguments are saved in OPTARG.\n"; ++ ++BAREBOX_CMD_START(getopt) ++ .cmd = do_getopt, ++ .usage = "getopt <optstring> <var>", ++ BAREBOX_CMD_HELP(cmd_getopt_help) ++BAREBOX_CMD_END ++#endif ++ + /** + * @file + * @brief A prototype Bourne shell grammar parser +diff --git a/common/image.c b/common/image.c +index 104446a..a4c8b95 100644 +--- a/common/image.c ++++ b/common/image.c +@@ -266,6 +266,7 @@ void image_print_contents(const void *ptr) + { + const image_header_t *hdr = (const image_header_t *)ptr; + const char *p; ++ int type; + + #ifdef __BAREBOX__ + p = " "; +@@ -285,8 +286,8 @@ void image_print_contents(const void *ptr) + printf ("%sLoad Address: %08x\n", p, image_get_load(hdr)); + printf ("%sEntry Point: %08x\n", p, image_get_ep(hdr)); + +- if (image_check_type(hdr, IH_TYPE_MULTI) || +- image_check_type(hdr, IH_TYPE_SCRIPT)) { ++ type = image_get_type(hdr); ++ if (type == IH_TYPE_MULTI || type == IH_TYPE_SCRIPT) { + int i; + ulong data, len; + ulong count = image_multi_count(hdr); +@@ -298,7 +299,7 @@ void image_print_contents(const void *ptr) + printf("%s Image %d: ", p, i); + image_print_size(len); + +- if (image_check_type(hdr, IH_TYPE_SCRIPT) && i > 0) { ++ if (image_get_type(hdr) != IH_TYPE_SCRIPT && i > 0) { + /* + * the user may need to know offsets + * if planning to do something with +diff --git a/common/kallsyms.c b/common/kallsyms.c +index 4069f4b..490adb9 100644 +--- a/common/kallsyms.c ++++ b/common/kallsyms.c +@@ -2,6 +2,8 @@ + #include <init.h> + #include <kallsyms.h> + ++#ifndef DOXYGEN_SHOULD_SKIP_THIS ++ + /* These will be re-linked against their real values during the second link stage */ + extern const unsigned long kallsyms_addresses[] __attribute__((weak)); + extern const unsigned long kallsyms_num_syms __attribute__((weak)); +@@ -12,6 +14,8 @@ extern const u16 kallsyms_token_index[] __attribute__((weak)); + + extern const unsigned long kallsyms_markers[] __attribute__((weak)); + ++#endif /* DOXYGEN_SHOULD_SKIP_THIS */ ++ + /* expand a compressed symbol data into the resulting uncompressed string, + given the offset to where the symbol is in the compressed stream */ + static unsigned int kallsyms_expand_symbol(unsigned int off, char *result) +diff --git a/common/memsize.c b/common/memsize.c +index 505e43f..e3bc56c 100644 +--- a/common/memsize.c ++++ b/common/memsize.c +@@ -21,6 +21,7 @@ + * MA 02111-1307 USA + */ + ++#include <common.h> + #include <config.h> + #if defined (__PPC__) && !defined (__SANDBOX__) + /* +diff --git a/common/parser.c b/common/parser.c +index 97e354b..fd578c7 100644 +--- a/common/parser.c ++++ b/common/parser.c +@@ -6,9 +6,8 @@ static int parse_line (char *line, char *argv[]) + { + int nargs = 0; + +-#ifdef DEBUG_PARSER +- printf ("parse_line: \"%s\"\n", line); +-#endif ++ pr_debug("parse_line: \"%s\"\n", line); ++ + while (nargs < CONFIG_MAXARGS) { + + /* skip any white space */ +@@ -18,9 +17,9 @@ static int parse_line (char *line, char *argv[]) + + if (*line == '\0') { /* end of line, no more args */ + argv[nargs] = NULL; +-#ifdef DEBUG_PARSER +- printf ("parse_line: nargs=%d\n", nargs); +-#endif ++ ++ pr_debug("parse_line: nargs=%d\n", nargs); ++ + return (nargs); + } + +@@ -33,9 +32,9 @@ static int parse_line (char *line, char *argv[]) + + if (*line == '\0') { /* end of line, no more args */ + argv[nargs] = NULL; +-#ifdef DEBUG_PARSER +- printf ("parse_line: nargs=%d\n", nargs); +-#endif ++ ++ pr_debug("parse_line: nargs=%d\n", nargs); ++ + return (nargs); + } + +@@ -43,10 +42,8 @@ static int parse_line (char *line, char *argv[]) + } + + printf ("** Too many args (max. %d) **\n", CONFIG_MAXARGS); ++ pr_debug("parse_line: nargs=%d\n", nargs); + +-#ifdef DEBUG_PARSER +- printf ("parse_line: nargs=%d\n", nargs); +-#endif + return (nargs); + } + +@@ -61,12 +58,12 @@ static void process_macros (const char *input, char *output) + /* 1 = waiting for '(' or '{' */ + /* 2 = waiting for ')' or '}' */ + /* 3 = waiting for ''' */ +-#ifdef DEBUG_PARSER ++#ifdef DEBUG + char *output_start = output; ++#endif + +- printf ("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen (input), ++ pr_debug("[PROCESS_MACROS] INPUT len %d: \"%s\"\n", strlen (input), + input); +-#endif + + prev = '\0'; /* previous character */ + +@@ -153,10 +150,8 @@ static void process_macros (const char *input, char *output) + if (outputcnt) + *output = 0; + +-#ifdef DEBUG_PARSER +- printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", ++ pr_debug("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n", + strlen (output_start), output_start); +-#endif + } + + /**************************************************************************** +@@ -185,8 +180,8 @@ int run_command (const char *cmd, int flag) + int argc, inquotes; + int rc = 0; + +-#ifdef DEBUG_PARSER +- printf ("[RUN_COMMAND] cmd[%p]=\"", cmd); ++#ifdef DEBUG ++ pr_debug("[RUN_COMMAND] cmd[%p]=\"", cmd); + puts (cmd ? cmd : "NULL"); /* use puts - string may be loooong */ + puts ("\"\n"); + #endif +@@ -202,13 +197,13 @@ int run_command (const char *cmd, int flag) + + strcpy (cmdbuf, cmd); + +- /* Process separators and check for invalid ++ /* ++ * Process separators and check for invalid + * repeatable commands + */ + +-#ifdef DEBUG_PARSER +- printf ("[PROCESS_SEPARATORS] %s\n", cmd); +-#endif ++ pr_debug("[PROCESS_SEPARATORS] %s\n", cmd); ++ + while (*str) { + + /* +@@ -235,11 +230,11 @@ int run_command (const char *cmd, int flag) + str = sep + 1; /* start of command for next pass */ + *sep = '\0'; + } +- else ++ else { + str = sep; /* no more commands for next pass */ +-#ifdef DEBUG_PARSER +- printf ("token: \"%s\"\n", token); +-#endif ++ } ++ ++ pr_debug("token: \"%s\"\n", token); + + /* find macros in this token and replace them */ + process_macros (token, finaltoken); +diff --git a/defaultenv/bin/_update b/defaultenv/bin/_update +index ddd6b84..87e6922 100644 +--- a/defaultenv/bin/_update ++++ b/defaultenv/bin/_update +@@ -10,18 +10,16 @@ if [ ! -e "$part" ]; then + exit 1 + fi + +-if [ $# = 1 ]; then +- image=$1 +-fi +- +-if [ x$ip = xdhcp ]; then +- dhcp +-fi +- +-ping $eth0.serverip +-if [ $? -ne 0 ] ; then +- echo "Server did not reply! Update aborted." +- exit 1 ++if [ x$mode = xtftp ]; then ++ if [ x$ip = xdhcp ]; then ++ dhcp ++ fi ++ ++ ping $eth0.serverip ++ if [ $? -ne 0 ] ; then ++ echo "Server did not reply! Update aborted." ++ exit 1 ++ fi + fi + + unprotect $part +@@ -34,6 +32,12 @@ erase $part + echo + echo "flashing $image to $part" + echo +-tftp $image $part ++ ++if [ x$mode = xtftp ]; then ++ tftp $image $part ++else ++ loadb -f $image -c ++ cp $image $part ++fi + + protect $part +diff --git a/defaultenv/bin/_update_help b/defaultenv/bin/_update_help +new file mode 100644 +index 0000000..22d940e +--- /dev/null ++++ b/defaultenv/bin/_update_help +@@ -0,0 +1,12 @@ ++#!/bin/sh ++ ++echo "usage: $0 -t <kernel|rootfs|barebox> -d <nor|nand> [-m tftp|xmodem] [-f imagename] -c" ++echo "update tools." ++echo "" ++echo "options" ++echo " -c to check the crc32 for the image and flashed one" ++echo "" ++echo "default mode is tftp" ++echo "type update -t kernel -d <nor|nand> [-m tftp|xmodem] [-f imagename] to update kernel into flash" ++echo "type update -t rootfs -d <nor|nand> [-m tftp|xmodem] [-f imagename] to update rootfs into flash" ++echo "type update -t barebox -d <nor|nand> [-m tftp|xmodem] [-f imagename] to update barebox into flash" +diff --git a/defaultenv/bin/boot b/defaultenv/bin/boot +index 6476bdb..42c7ec2 100644 +--- a/defaultenv/bin/boot ++++ b/defaultenv/bin/boot +@@ -16,7 +16,7 @@ fi + if [ x$ip = xdhcp ]; then + bootargs="$bootargs ip=dhcp" + elif [ x$ip = xnone ]; then +- bootargs="ip=none" ++ bootargs="$bootargs ip=none" + else + bootargs="$bootargs ip=$eth0.ipaddr::$eth0.gateway:$eth0.netmask:::" + fi +@@ -51,7 +51,7 @@ if [ -n $nand_parts ]; then + fi + + if [ -n $mtdparts ]; then +- bootargs="${bootargs} mtdparts=\"${mtdparts}\"" ++ bootargs="${bootargs} mtdparts=${mtdparts}" + fi + + if [ ! -e /dev/ram0.kernelraw ]; then +diff --git a/defaultenv/bin/init b/defaultenv/bin/init +index a55e8e6..96a5716 100644 +--- a/defaultenv/bin/init ++++ b/defaultenv/bin/init +@@ -8,6 +8,10 @@ if [ -e /dev/nor0 ]; then + addpart /dev/nor0 $nor_parts + fi + ++if [ -e /dev/disk0 ]; then ++ addpart /dev/disk0 $disk_parts ++fi ++ + if [ -e /dev/nand0 ]; then + addpart /dev/nand0 $nand_parts + +@@ -25,8 +29,7 @@ echo -n "Hit any key to stop autoboot: " + timeout -a $autoboot_timeout + if [ $? != 0 ]; then + echo +- echo "type update_kernel nand|nor [<imagename>] to update kernel into flash" +- echo "type update_rootfs nand|nor [<imagename>] to update rootfs into flash" ++ update -h + echo + exit + fi +diff --git a/defaultenv/bin/update b/defaultenv/bin/update +new file mode 100644 +index 0000000..3601177 +--- /dev/null ++++ b/defaultenv/bin/update +@@ -0,0 +1,65 @@ ++#!/bin/sh ++ ++. /env/config ++ ++type="" ++device_type="" ++check=n ++mode=tftp ++ ++while getopt "ht:d:f:m:c" Option ++do ++if [ ${Option} = t ]; then ++ type=${OPTARG} ++elif [ ${Option} = d ]; then ++ device_type=${OPTARG} ++elif [ ${Option} = f ]; then ++ imagename=${OPTARG} ++elif [ ${Option} = c ]; then ++ check=y ++elif [ ${Option} = m ]; then ++ mode=${OPTARG} ++else ++ . /env/bin/_update_help ++ exit 0 ++fi ++done ++ ++if [ x${type} = xkernel ]; then ++ image=$kernelimage ++elif [ x${type} = xrootfs ]; then ++ image=$rootfsimage ++ type=root ++elif [ x${type} = xbarebox ]; then ++ image=$bareboximage ++ if [ x${image} = x ]; then ++ imamge=barebox.bin ++ fi ++else ++ . /env/bin/_update_help ++ exit 1 ++fi ++ ++if [ x${imagename} != x ]; then ++ image=${imagename} ++fi ++ ++if [ x${device_type} = xnand ]; then ++ part=/dev/nand0.${type}.bb ++elif [ x${device_type} = xnor ]; then ++ part=/dev/nor0.${type} ++else ++ . /env/bin/_update_help ++ exit 1 ++fi ++ ++if [ x${mode} != xtftp ] && [ x${mode} != xxmodem ] ; then ++ echo "unsupported mode ${mode}." ++ . /env/bin/_update_help ++ exit 1 ++fi ++ ++. /env/bin/_update ++if [ x${check} = xy ]; then ++ crc32 -f $image -F $part ++fi +diff --git a/defaultenv/bin/update_kernel b/defaultenv/bin/update_kernel +deleted file mode 100644 +index 1d35ed9..0000000 +--- a/defaultenv/bin/update_kernel ++++ /dev/null +@@ -1,15 +0,0 @@ +-#!/bin/sh +- +-. /env/config +-image=$kernelimage +- +-if [ x$1 = xnand ]; then +- part=/dev/nand0.kernel.bb +-elif [ x$1 = xnor ]; then +- part=/dev/nor0.kernel +-else +- echo "usage: $0 nor|nand [imagename]" +- exit 1 +-fi +- +-. /env/bin/_update $2 +diff --git a/defaultenv/bin/update_rootfs b/defaultenv/bin/update_rootfs +deleted file mode 100644 +index 6366315..0000000 +--- a/defaultenv/bin/update_rootfs ++++ /dev/null +@@ -1,16 +0,0 @@ +-#!/bin/sh +- +-. /env/config +- +-image=$rootfsimage +- +-if [ x$1 = xnand ]; then +- part=/dev/nand0.root.bb +-elif [ x$1 = xnor ]; then +- part=/dev/nor0.root +-else +- echo "usage: $0 nor|nand [imagename]" +- exit 1 +-fi +- +-. /env/bin/_update $2 +diff --git a/drivers/Kconfig b/drivers/Kconfig +index f7154c6..d94017b 100644 +--- a/drivers/Kconfig ++++ b/drivers/Kconfig +@@ -9,6 +9,8 @@ source "drivers/mtd/Kconfig" + source "drivers/ata/Kconfig" + source "drivers/usb/Kconfig" + source "drivers/video/Kconfig" ++source "drivers/mci/Kconfig" + source "drivers/clk/Kconfig" ++source "drivers/mfd/Kconfig" + + endmenu +diff --git a/drivers/Makefile b/drivers/Makefile +index 706e1c8..242a564 100644 +--- a/drivers/Makefile ++++ b/drivers/Makefile +@@ -6,5 +6,7 @@ obj-y += usb/ + obj-$(CONFIG_ATA) += ata/ + obj-$(CONFIG_SPI) += spi/ + obj-$(CONFIG_I2C) += i2c/ ++obj-$(CONFIG_MCI) += mci/ + obj-$(CONFIG_VIDEO) += video/ + obj-y += clk/ ++obj-y += mfd/ +diff --git a/drivers/ata/disk_drive.c b/drivers/ata/disk_drive.c +index 250dada..a54429a 100644 +--- a/drivers/ata/disk_drive.c ++++ b/drivers/ata/disk_drive.c +@@ -23,6 +23,7 @@ + * @brief Generic disk drive support + * + * @todo Support for disks larger than 4 GiB ++ * @todo Reliable size detection for BIOS based disks (on x86 only) + */ + + #include <stdio.h> +@@ -34,6 +35,7 @@ + #include <errno.h> + #include <string.h> + #include <linux/kernel.h> ++#include <malloc.h> + + /** + * Description of one partition table entry (D*S type) +@@ -105,7 +107,8 @@ static int disk_register_partitions(struct device_d *dev, struct partition_entry + if (table[part_order[i]].partition_size > 0x7fffff) + continue; + #endif +- dev_info(dev, "Registering partition %s to drive %s\n", partition_name, drive_name); ++ dev_dbg(dev, "Registering partition %s to drive %s\n", ++ partition_name, drive_name); + rc = devfs_add_partition(drive_name, + table[part_order[i]].partition_start * SECTOR_SIZE, + table[part_order[i]].partition_size * SECTOR_SIZE, +@@ -268,23 +271,22 @@ static struct file_operations disk_ops = { + */ + static int disk_probe(struct device_d *dev) + { +- uint8_t sector[512]; ++ uint8_t *sector; + int rc; + struct ata_interface *intf = dev->platform_data; + struct cdev *disk_cdev; + ++ sector = xmalloc(SECTOR_SIZE); ++ + rc = intf->read(dev, 0, 1, sector); + if (rc != 0) { + dev_err(dev, "Cannot read MBR of this device\n"); +- return -1; ++ rc = -ENODEV; ++ goto on_error; + } + + /* It seems a valuable disk. Register it */ + disk_cdev = xzalloc(sizeof(struct cdev)); +- if (disk_cdev == NULL) { +- dev_err(dev, "Out of memory\n"); +- return -ENOMEM; +- } + + /* + * BIOS based disks needs special handling. Not the driver can +@@ -298,28 +300,39 @@ static int disk_probe(struct device_d *dev) + else + #endif + disk_cdev->name = asprintf("disk%d", dev->id); +- /** +- * @todo we need the size of the drive, else its nearly impossible +- * to do anything with it (at least with the generic routines) +- */ +- disk_cdev->size = 32; /* FIXME */ ++ ++ /* On x86, BIOS based disks are coming without a valid .size field */ ++ if (dev->size == 0) { ++ /* ++ * We need always the size of the drive, else its nearly impossible ++ * to do anything with it (at least with the generic routines) ++ */ ++ disk_cdev->size = 32; ++ } else ++ disk_cdev->size = dev->size; + disk_cdev->ops = &disk_ops; + disk_cdev->dev = dev; + devfs_create(disk_cdev); + + if ((sector[510] != 0x55) || (sector[511] != 0xAA)) { + dev_info(dev, "No partition table found\n"); +- return 0; ++ rc = 0; ++ goto on_error; + } + +- /* guess the size of this drive */ +- dev->size = disk_guess_size(dev, (struct partition_entry*)§or[446]) * SECTOR_SIZE; +- dev_info(dev, "Drive size guessed to %u kiB\n", dev->size / 1024); +- disk_cdev->size = dev->size; ++ if (dev->size == 0) { ++ /* guess the size of this drive if not otherwise given */ ++ dev->size = disk_guess_size(dev, ++ (struct partition_entry*)§or[446]) * SECTOR_SIZE; ++ dev_info(dev, "Drive size guessed to %u kiB\n", dev->size / 1024); ++ disk_cdev->size = dev->size; ++ } + +- disk_register_partitions(dev, (struct partition_entry*)§or[446]); ++ rc = disk_register_partitions(dev, (struct partition_entry*)§or[446]); + +- return 0; ++on_error: ++ free(sector); ++ return rc; + } + + #ifdef CONFIG_ATA_BIOS +diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig +index 9ce1655..c2af818 100644 +--- a/drivers/i2c/Kconfig ++++ b/drivers/i2c/Kconfig +@@ -5,20 +5,4 @@ if I2C + + source drivers/i2c/busses/Kconfig + +-config I2C_MC13892 +- bool "MC13892 a.k.a. PMIC driver" +- +-config I2C_MC34704 +- bool "MC34704 PMIC driver" +- +-config I2C_MC9SDZ60 +- bool "MC9SDZ60 driver" +- +-config I2C_LP3972 +- bool "LP3972 driver" +- +-config I2C_TWL4030 +- bool "TWL4030 driver" +- select GPIO +- + endif +diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile +index 0584b55..42e22c0 100644 +--- a/drivers/i2c/Makefile ++++ b/drivers/i2c/Makefile +@@ -1,7 +1 @@ + obj-$(CONFIG_I2C) += i2c.o busses/ +- +-obj-$(CONFIG_I2C_MC13892) += mc13892.o +-obj-$(CONFIG_I2C_MC34704) += mc34704.o +-obj-$(CONFIG_I2C_MC9SDZ60) += mc9sdz60.o +-obj-$(CONFIG_I2C_LP3972) += lp3972.o +-obj-$(CONFIG_I2C_TWL4030) += twl4030.o +diff --git a/drivers/i2c/lp3972.c b/drivers/i2c/lp3972.c +deleted file mode 100644 +index 9826699..0000000 +--- a/drivers/i2c/lp3972.c ++++ /dev/null +@@ -1,110 +0,0 @@ +-/* +- * Copyright (C) 2007 Sascha Hauer, Pengutronix +- * 2009 Marc Kleine-Budde <mkl@pengutronix.de> +- * 2009 Eric Benard <eric@eukrea.com> +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- * +- */ +- +-#include <common.h> +-#include <init.h> +-#include <driver.h> +-#include <xfuncs.h> +-#include <errno.h> +- +-#include <i2c/i2c.h> +- +-#include <asm/byteorder.h> +- +-#define DRIVERNAME "lp3972" +- +-struct lp_priv { +- struct cdev cdev; +- struct i2c_client *client; +-}; +- +-#define to_lp_priv(a) container_of(a, struct lp_priv, cdev) +- +-static struct lp_priv *lp_dev; +- +-struct i2c_client *lp3972_get_client(void) +-{ +- if (!lp_dev) +- return NULL; +- +- return lp_dev->client; +-} +- +-static u32 lp_read_reg(struct lp_priv *lp, int reg) +-{ +- u8 buf; +- +- i2c_read_reg(lp->client, reg, &buf, sizeof(buf)); +- +- return buf; +-} +- +-static ssize_t lp_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) +-{ +- struct lp_priv *priv = to_lp_priv(cdev); +- int i = count; +- u8 *buf = _buf; +- +- while (i) { +- *buf = lp_read_reg(priv, offset); +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static struct file_operations lp_fops = { +- .lseek = dev_lseek_default, +- .read = lp_read, +-}; +- +-static int lp_probe(struct device_d *dev) +-{ +- if (lp_dev) +- return -EBUSY; +- +- lp_dev = xzalloc(sizeof(struct lp_priv)); +- lp_dev->cdev.name = DRIVERNAME; +- lp_dev->client = to_i2c_client(dev); +- lp_dev->cdev.size = 256; +- lp_dev->cdev.dev = dev; +- lp_dev->cdev.ops = &lp_fops; +- +- devfs_create(&lp_dev->cdev); +- +- return 0; +-} +- +-static struct driver_d lp_driver = { +- .name = DRIVERNAME, +- .probe = lp_probe, +-}; +- +-static int lp_init(void) +-{ +- register_driver(&lp_driver); +- return 0; +-} +- +-device_initcall(lp_init); +diff --git a/drivers/i2c/mc13892.c b/drivers/i2c/mc13892.c +deleted file mode 100644 +index 67d4232..0000000 +--- a/drivers/i2c/mc13892.c ++++ /dev/null +@@ -1,164 +0,0 @@ +-/* +- * Copyright (C) 2007 Sascha Hauer, Pengutronix +- * 2009 Marc Kleine-Budde <mkl@pengutronix.de> +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- * +- */ +- +-#include <common.h> +-#include <init.h> +-#include <driver.h> +-#include <xfuncs.h> +-#include <errno.h> +- +-#include <i2c/i2c.h> +-#include <i2c/mc13892.h> +- +-#define DRIVERNAME "mc13892" +- +-#define to_mc13892(a) container_of(a, struct mc13892, cdev) +- +-static struct mc13892 *mc_dev; +- +-struct mc13892 *mc13892_get(void) +-{ +- if (!mc_dev) +- return NULL; +- +- return mc_dev; +-} +-EXPORT_SYMBOL(mc13892_get); +- +-int mc13892_reg_read(struct mc13892 *mc13892, enum mc13892_reg reg, u32 *val) +-{ +- u8 buf[3]; +- int ret; +- +- ret = i2c_read_reg(mc13892->client, reg, buf, 3); +- *val = buf[0] << 16 | buf[1] << 8 | buf[2] << 0; +- +- return ret == 3 ? 0 : ret; +-} +-EXPORT_SYMBOL(mc13892_reg_read) +- +-int mc13892_reg_write(struct mc13892 *mc13892, enum mc13892_reg reg, u32 val) +-{ +- u8 buf[] = { +- val >> 16, +- val >> 8, +- val >> 0, +- }; +- int ret; +- +- ret = i2c_write_reg(mc13892->client, reg, buf, 3); +- +- return ret == 3 ? 0 : ret; +-} +-EXPORT_SYMBOL(mc13892_reg_write) +- +-int mc13892_set_bits(struct mc13892 *mc13892, enum mc13892_reg reg, u32 mask, u32 val) +-{ +- u32 tmp; +- int err; +- +- err = mc13892_reg_read(mc13892, reg, &tmp); +- tmp = (tmp & ~mask) | val; +- +- if (!err) +- err = mc13892_reg_write(mc13892, reg, tmp); +- +- return err; +-} +-EXPORT_SYMBOL(mc13892_set_bits); +- +-static ssize_t mc_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) +-{ +- struct mc13892 *priv = to_mc13892(cdev); +- u32 *buf = _buf; +- size_t i = count >> 2; +- int err; +- +- offset >>= 2; +- +- while (i) { +- err = mc13892_reg_read(priv, offset, buf); +- if (err) +- return (ssize_t)err; +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static ssize_t mc_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags) +-{ +- struct mc13892 *mc13892 = to_mc13892(cdev); +- const u32 *buf = _buf; +- size_t i = count >> 2; +- int err; +- +- offset >>= 2; +- +- while (i) { +- err = mc13892_reg_write(mc13892, offset, *buf); +- if (err) +- return (ssize_t)err; +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static struct file_operations mc_fops = { +- .lseek = dev_lseek_default, +- .read = mc_read, +- .write = mc_write, +-}; +- +-static int mc_probe(struct device_d *dev) +-{ +- if (mc_dev) +- return -EBUSY; +- +- mc_dev = xzalloc(sizeof(struct mc13892)); +- mc_dev->cdev.name = DRIVERNAME; +- mc_dev->client = to_i2c_client(dev); +- mc_dev->cdev.size = 256; +- mc_dev->cdev.dev = dev; +- mc_dev->cdev.ops = &mc_fops; +- +- devfs_create(&mc_dev->cdev); +- +- return 0; +-} +- +-static struct driver_d mc_driver = { +- .name = DRIVERNAME, +- .probe = mc_probe, +-}; +- +-static int mc_init(void) +-{ +- register_driver(&mc_driver); +- return 0; +-} +- +-device_initcall(mc_init); +diff --git a/drivers/i2c/mc34704.c b/drivers/i2c/mc34704.c +deleted file mode 100644 +index 51a8737..0000000 +--- a/drivers/i2c/mc34704.c ++++ /dev/null +@@ -1,140 +0,0 @@ +-/* +- * Copyright (C) 2007 Sascha Hauer, Pengutronix +- * 2009 Marc Kleine-Budde <mkl@pengutronix.de> +- * Copyright (C) 2010 Baruch Siach <baruch@tkos.co.il> +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- * +- */ +- +-#include <common.h> +-#include <init.h> +-#include <driver.h> +-#include <xfuncs.h> +-#include <errno.h> +- +-#include <i2c/i2c.h> +-#include <i2c/mc34704.h> +- +-#define DRIVERNAME "mc34704" +- +-#define to_mc34704(a) container_of(a, struct mc34704, cdev) +- +-static struct mc34704 *mc34704_dev; +- +-struct mc34704 *mc34704_get(void) +-{ +- if (!mc34704_dev) +- return NULL; +- +- return mc34704_dev; +-} +-EXPORT_SYMBOL(mc34704_get); +- +-int mc34704_reg_read(struct mc34704 *mc34704, u8 reg, u8 *val) +-{ +- int ret; +- +- ret = i2c_read_reg(mc34704->client, reg, val, 1); +- +- return ret == 1 ? 0 : ret; +-} +-EXPORT_SYMBOL(mc34704_reg_read) +- +-int mc34704_reg_write(struct mc34704 *mc34704, u8 reg, u8 val) +-{ +- int ret; +- +- ret = i2c_write_reg(mc34704->client, reg, &val, 1); +- +- return ret == 1 ? 0 : ret; +-} +-EXPORT_SYMBOL(mc34704_reg_write) +- +-static ssize_t mc34704_read(struct cdev *cdev, void *_buf, size_t count, +- ulong offset, ulong flags) +-{ +- struct mc34704 *priv = to_mc34704(cdev); +- u8 *buf = _buf; +- size_t i = count; +- int err; +- +- while (i) { +- err = mc34704_reg_read(priv, offset, buf); +- if (err) +- return (ssize_t)err; +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static ssize_t mc34704_write(struct cdev *cdev, const void *_buf, size_t count, +- ulong offset, ulong flags) +-{ +- struct mc34704 *mc34704 = to_mc34704(cdev); +- const u8 *buf = _buf; +- size_t i = count; +- int err; +- +- while (i) { +- err = mc34704_reg_write(mc34704, offset, *buf); +- if (err) +- return (ssize_t)err; +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static struct file_operations mc34704_fops = { +- .lseek = dev_lseek_default, +- .read = mc34704_read, +- .write = mc34704_write, +-}; +- +-static int mc34704_probe(struct device_d *dev) +-{ +- if (mc34704_dev) +- return -EBUSY; +- +- mc34704_dev = xzalloc(sizeof(struct mc34704)); +- mc34704_dev->cdev.name = DRIVERNAME; +- mc34704_dev->client = to_i2c_client(dev); +- mc34704_dev->cdev.size = 256; +- mc34704_dev->cdev.dev = dev; +- mc34704_dev->cdev.ops = &mc34704_fops; +- +- devfs_create(&mc34704_dev->cdev); +- +- return 0; +-} +- +-static struct driver_d mc34704_driver = { +- .name = DRIVERNAME, +- .probe = mc34704_probe, +-}; +- +-static int mc34704_init(void) +-{ +- register_driver(&mc34704_driver); +- return 0; +-} +-device_initcall(mc34704_init); +diff --git a/drivers/i2c/mc9sdz60.c b/drivers/i2c/mc9sdz60.c +deleted file mode 100644 +index 3580af8..0000000 +--- a/drivers/i2c/mc9sdz60.c ++++ /dev/null +@@ -1,153 +0,0 @@ +-/* +- * Copyright (C) 2007 Sascha Hauer, Pengutronix +- * 2009 Marc Kleine-Budde <mkl@pengutronix.de> +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- * +- */ +- +-#include <common.h> +-#include <init.h> +-#include <driver.h> +-#include <xfuncs.h> +-#include <errno.h> +- +-#include <i2c/i2c.h> +-#include <i2c/mc9sdz60.h> +- +-#define DRIVERNAME "mc9sdz60" +- +-#define to_mc9sdz60(a) container_of(a, struct mc9sdz60, cdev) +- +-static struct mc9sdz60 *mc_dev; +- +-struct mc9sdz60 *mc9sdz60_get(void) +-{ +- if (!mc_dev) +- return NULL; +- +- return mc_dev; +-} +-EXPORT_SYMBOL(mc9sdz60_get); +- +-int mc9sdz60_reg_read(struct mc9sdz60 *mc9sdz60, enum mc9sdz60_reg reg, u8 *val) +-{ +- int ret; +- +- ret = i2c_read_reg(mc9sdz60->client, reg, val, 1); +- +- return ret == 1 ? 0 : ret; +-} +-EXPORT_SYMBOL(mc9sdz60_reg_read) +- +-int mc9sdz60_reg_write(struct mc9sdz60 *mc9sdz60, enum mc9sdz60_reg reg, u8 val) +-{ +- int ret; +- +- ret = i2c_write_reg(mc9sdz60->client, reg, &val, 1); +- +- return ret == 1 ? 0 : ret; +-} +-EXPORT_SYMBOL(mc9sdz60_reg_write) +- +-int mc9sdz60_set_bits(struct mc9sdz60 *mc9sdz60, enum mc9sdz60_reg reg, u8 mask, u8 val) +-{ +- u8 tmp; +- int err; +- +- err = mc9sdz60_reg_read(mc9sdz60, reg, &tmp); +- tmp = (tmp & ~mask) | val; +- +- if (!err) +- err = mc9sdz60_reg_write(mc9sdz60, reg, tmp); +- +- return err; +-} +-EXPORT_SYMBOL(mc9sdz60_set_bits); +- +-static ssize_t mc_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) +-{ +- struct mc9sdz60 *mc9sdz60 = to_mc9sdz60(cdev); +- u8 *buf = _buf; +- size_t i = count; +- int err; +- +- while (i) { +- err = mc9sdz60_reg_read(mc9sdz60, offset, buf); +- if (err) +- return (ssize_t)err; +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static ssize_t mc_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags) +-{ +- struct mc9sdz60 *mc9sdz60 = to_mc9sdz60(cdev); +- const u8 *buf = _buf; +- size_t i = count; +- int err; +- +- while (i) { +- err = mc9sdz60_reg_write(mc9sdz60, offset, *buf); +- if (err) +- return (ssize_t)err; +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static struct file_operations mc_fops = { +- .lseek = dev_lseek_default, +- .read = mc_read, +- .write = mc_write, +-}; +- +-static int mc_probe(struct device_d *dev) +-{ +- if (mc_dev) +- return -EBUSY; +- +- mc_dev = xzalloc(sizeof(struct mc9sdz60)); +- mc_dev->cdev.name = DRIVERNAME; +- mc_dev->client = to_i2c_client(dev); +- mc_dev->cdev.size = 64; /* 35 known registers */ +- mc_dev->cdev.dev = dev; +- mc_dev->cdev.ops = &mc_fops; +- +- devfs_create(&mc_dev->cdev); +- +- return 0; +-} +- +-static struct driver_d mc_driver = { +- .name = DRIVERNAME, +- .probe = mc_probe, +-}; +- +-static int mc_init(void) +-{ +- register_driver(&mc_driver); +- return 0; +-} +- +-device_initcall(mc_init); +diff --git a/drivers/i2c/twl4030.c b/drivers/i2c/twl4030.c +deleted file mode 100644 +index 5305ec6..0000000 +--- a/drivers/i2c/twl4030.c ++++ /dev/null +@@ -1,186 +0,0 @@ +-/* +- * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de> +- * +- * This file is released under the GPLv2 +- * +- */ +- +-#include <common.h> +-#include <init.h> +-#include <driver.h> +-#include <xfuncs.h> +-#include <errno.h> +- +-#include <i2c/i2c.h> +-#include <i2c/twl4030.h> +- +-#define DRIVERNAME "twl4030" +- +-#define to_twl4030(a) container_of(a, struct twl4030, cdev) +- +-static struct twl4030 *twl_dev; +- +-struct twl4030 *twl4030_get(void) +-{ +- if (!twl_dev) +- return NULL; +- +- return twl_dev; +-} +-EXPORT_SYMBOL(twl4030_get); +- +-int twl4030_reg_read(struct twl4030 *twl4030, u16 reg, u8 *val) +-{ +- int ret; +- struct i2c_msg xfer_msg[2]; +- struct i2c_msg *msg; +- int i2c_addr; +- unsigned char buf = reg & 0xff; +- +- i2c_addr = twl4030->client->addr + (reg / 0x100); +- +- /* [MSG1] fill the register address data */ +- msg = &xfer_msg[0]; +- msg->addr = i2c_addr; +- msg->len = 1; +- msg->flags = 0; /* Read the register value */ +- msg->buf = &buf; +- /* [MSG2] fill the data rx buffer */ +- msg = &xfer_msg[1]; +- msg->addr = i2c_addr; +- msg->flags = I2C_M_RD; /* Read the register value */ +- msg->len = 1; /* only n bytes */ +- msg->buf = val; +- ret = i2c_transfer(twl4030->client->adapter, xfer_msg, 2); +- +- /* i2c_transfer returns number of messages transferred */ +- if (ret < 0) { +- pr_err("%s: failed to transfer all messages: %s\n", __func__, strerror(-ret)); +- return ret; +- } +- return 0; +-} +-EXPORT_SYMBOL(twl4030_reg_read) +- +-int twl4030_reg_write(struct twl4030 *twl4030, u16 reg, u8 val) +-{ +- int ret; +- struct i2c_msg xfer_msg[1]; +- struct i2c_msg *msg; +- int i2c_addr; +- u8 buf[2]; +- +- buf[0] = reg & 0xff; +- buf[1] = val; +- +- i2c_addr = twl4030->client->addr + (reg / 0x100); +- +- /* +- * [MSG1]: fill the register address data +- * fill the data Tx buffer +- */ +- msg = xfer_msg; +- msg->addr = i2c_addr; +- msg->len = 2; +- msg->flags = 0; +- msg->buf = buf; +- /* over write the first byte of buffer with the register address */ +- ret = i2c_transfer(twl4030->client->adapter, xfer_msg, 1); +- +- /* i2c_transfer returns number of messages transferred */ +- if (ret < 0) { +- pr_err("%s: failed to transfer all messages: %s\n", __func__, strerror(-ret)); +- return ret; +- } +- return 0; +-} +-EXPORT_SYMBOL(twl4030_reg_write) +- +-int twl4030_set_bits(struct twl4030 *twl4030, enum twl4030_reg reg, u8 mask, u8 val) +-{ +- u8 tmp; +- int err; +- +- err = twl4030_reg_read(twl4030, reg, &tmp); +- tmp = (tmp & ~mask) | val; +- +- if (!err) +- err = twl4030_reg_write(twl4030, reg, tmp); +- +- return err; +-} +-EXPORT_SYMBOL(twl4030_set_bits); +- +-static ssize_t twl_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) +-{ +- struct twl4030 *priv = to_twl4030(cdev); +- u8 *buf = _buf; +- size_t i = count; +- int err; +- +- while (i) { +- err = twl4030_reg_read(priv, offset, buf); +- if (err) +- return (ssize_t)err; +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static ssize_t twl_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags) +-{ +- struct twl4030 *twl4030 = to_twl4030(cdev); +- const u8 *buf = _buf; +- size_t i = count; +- int err; +- +- while (i) { +- err = twl4030_reg_write(twl4030, offset, *buf); +- if (err) +- return (ssize_t)err; +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static struct file_operations twl_fops = { +- .lseek = dev_lseek_default, +- .read = twl_read, +- .write = twl_write, +-}; +- +-static int twl_probe(struct device_d *dev) +-{ +- if (twl_dev) +- return -EBUSY; +- +- twl_dev = xzalloc(sizeof(struct twl4030)); +- twl_dev->cdev.name = DRIVERNAME; +- twl_dev->client = to_i2c_client(dev); +- twl_dev->cdev.size = 1024; +- twl_dev->cdev.dev = dev; +- twl_dev->cdev.ops = &twl_fops; +- +- devfs_create(&twl_dev->cdev); +- +- return 0; +-} +- +-static struct driver_d twl_driver = { +- .name = DRIVERNAME, +- .probe = twl_probe, +-}; +- +-static int twl_init(void) +-{ +- register_driver(&twl_driver); +- return 0; +-} +- +-device_initcall(twl_init); +diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig +new file mode 100644 +index 0000000..b1f2773 +--- /dev/null ++++ b/drivers/mci/Kconfig +@@ -0,0 +1,64 @@ ++menuconfig MCI ++ bool "MCI drivers " ++ select ATA ++ select ATA_DISK ++ help ++ Add support for MCI drivers, used to handle MMC and SD cards ++ ++if MCI ++ ++comment "--- Feature list ---" ++ ++config MCI_STARTUP ++ bool "Probe on system start" ++ help ++ Say 'y' here if the MCI framework should probe for attached MCI cards ++ on system start up. This is required if the card carries barebox's ++ environment (for example on systems where the MCI card is the sole ++ bootmedia). Otherwise probing run on demand with "mci*.probe=1" ++ ++config MCI_INFO ++ bool "MCI Info" ++ depends on CMD_DEVINFO ++ default y ++ help ++ This entry adds more info about the attached MCI card, when the ++ 'devinfo' command is used on the mci device. ++ ++comment "--- MCI host drivers ---" ++ ++config MCI_STM378X ++ bool "i.MX23" ++ depends on ARCH_STM ++ help ++ Enable this entry to add support to read and write SD cards on a ++ i.MX23 based system. ++ ++config MCI_S3C ++ bool "S3C" ++ depends on ARCH_S3C24xx ++ help ++ Enable this entry to add support to read and write SD cards on a ++ Samsung S3C24xx based system. ++ ++config MCI_IMX ++ bool "i.MX" ++ depends on ARCH_IMX27 || ARCH_IMX31 ++ help ++ Enable this entry to add support to read and write SD cards on a ++ Freescale i.MX based system. ++ ++config MCI_IMX_ESDHC ++ bool "i.MX esdhc" ++ depends on ARCH_IMX25 || ARCH_IMX35 || ARCH_IMX51 ++ help ++ Enable this entry to add support to read and write SD cards on a ++ Freescale i.MX25/35/51 based system. ++ ++config MCI_IMX_ESDHC_PIO ++ bool "use PIO mode" ++ depends on MCI_IMX_ESDHC ++ help ++ mostly useful for debugging. Normally you should use DMA. ++ ++endif +diff --git a/drivers/mci/Makefile b/drivers/mci/Makefile +new file mode 100644 +index 0000000..a10cb47 +--- /dev/null ++++ b/drivers/mci/Makefile +@@ -0,0 +1,5 @@ ++obj-$(CONFIG_MCI) += mci-core.o ++obj-$(CONFIG_MCI_STM378X) += stm378x.o ++obj-$(CONFIG_MCI_S3C) += s3c.o ++obj-$(CONFIG_MCI_IMX) += imx.o ++obj-$(CONFIG_MCI_IMX_ESDHC) += imx-esdhc.o +diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c +new file mode 100644 +index 0000000..63cd059 +--- /dev/null ++++ b/drivers/mci/imx-esdhc.c +@@ -0,0 +1,512 @@ ++/* ++ * Copyright 2007,2010 Freescale Semiconductor, Inc ++ * Andy Fleming ++ * ++ * Based vaguely on the pxa mmc code: ++ * (C) Copyright 2003 ++ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <config.h> ++#include <common.h> ++#include <driver.h> ++#include <init.h> ++#include <malloc.h> ++#include <mci.h> ++#include <clock.h> ++#include <asm/io.h> ++#include <asm/mmu.h> ++#include <mach/clock.h> ++ ++#include "imx-esdhc.h" ++ ++struct fsl_esdhc { ++ u32 dsaddr; ++ u32 blkattr; ++ u32 cmdarg; ++ u32 xfertyp; ++ u32 cmdrsp0; ++ u32 cmdrsp1; ++ u32 cmdrsp2; ++ u32 cmdrsp3; ++ u32 datport; ++ u32 prsstat; ++ u32 proctl; ++ u32 sysctl; ++ u32 irqstat; ++ u32 irqstaten; ++ u32 irqsigen; ++ u32 autoc12err; ++ u32 hostcapblt; ++ u32 wml; ++ char reserved1[8]; ++ u32 fevt; ++ char reserved2[168]; ++ u32 hostver; ++ char reserved3[780]; ++ u32 scr; ++}; ++ ++struct fsl_esdhc_host { ++ struct mci_host mci; ++ struct fsl_esdhc *regs; ++ u32 no_snoop; ++ unsigned long cur_clock; ++ struct device_d *dev; ++}; ++ ++#define to_fsl_esdhc(mci) container_of(mci, struct fsl_esdhc_host, mci) ++ ++/* Return the XFERTYP flags for a given command and data packet */ ++u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data) ++{ ++ u32 xfertyp = 0; ++ ++ if (data) { ++ xfertyp |= XFERTYP_DPSEL; ++#ifndef CONFIG_MCI_IMX_ESDHC_PIO ++ xfertyp |= XFERTYP_DMAEN; ++#endif ++ if (data->blocks > 1) { ++ xfertyp |= XFERTYP_MSBSEL; ++ xfertyp |= XFERTYP_BCEN; ++ } ++ ++ if (data->flags & MMC_DATA_READ) ++ xfertyp |= XFERTYP_DTDSEL; ++ } ++ ++ if (cmd->resp_type & MMC_RSP_CRC) ++ xfertyp |= XFERTYP_CCCEN; ++ if (cmd->resp_type & MMC_RSP_OPCODE) ++ xfertyp |= XFERTYP_CICEN; ++ if (cmd->resp_type & MMC_RSP_136) ++ xfertyp |= XFERTYP_RSPTYP_136; ++ else if (cmd->resp_type & MMC_RSP_BUSY) ++ xfertyp |= XFERTYP_RSPTYP_48_BUSY; ++ else if (cmd->resp_type & MMC_RSP_PRESENT) ++ xfertyp |= XFERTYP_RSPTYP_48; ++ ++ return XFERTYP_CMD(cmd->cmdidx) | xfertyp; ++} ++ ++#ifdef CONFIG_MCI_IMX_ESDHC_PIO ++/* ++ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. ++ */ ++static void ++esdhc_pio_read_write(struct mci_host *mci, struct mci_data *data) ++{ ++ struct fsl_esdhc_host *host = to_fsl_esdhc(mci); ++ struct fsl_esdhc *regs = host->regs; ++ u32 blocks; ++ char *buffer; ++ u32 databuf; ++ u32 size; ++ u32 irqstat; ++ u32 timeout; ++ ++ if (data->flags & MMC_DATA_READ) { ++ blocks = data->blocks; ++ buffer = data->dest; ++ while (blocks) { ++ timeout = PIO_TIMEOUT; ++ size = data->blocksize; ++ irqstat = esdhc_read32(®s->irqstat); ++ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN) ++ && --timeout); ++ if (timeout <= 0) { ++ printf("\nData Read Failed in PIO Mode."); ++ return; ++ } ++ while (size && (!(irqstat & IRQSTAT_TC))) { ++ udelay(100); /* Wait before last byte transfer complete */ ++ irqstat = esdhc_read32(®s->irqstat); ++ databuf = esdhc_read32(®s->datport); ++ *((u32 *)buffer) = databuf; ++ buffer += 4; ++ size -= 4; ++ } ++ blocks--; ++ } ++ } else { ++ blocks = data->blocks; ++ buffer = (char *)data->src; ++ while (blocks) { ++ timeout = PIO_TIMEOUT; ++ size = data->blocksize; ++ irqstat = esdhc_read32(®s->irqstat); ++ while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN) ++ && --timeout); ++ if (timeout <= 0) { ++ printf("\nData Write Failed in PIO Mode."); ++ return; ++ } ++ while (size && (!(irqstat & IRQSTAT_TC))) { ++ udelay(100); /* Wait before last byte transfer complete */ ++ databuf = *((u32 *)buffer); ++ buffer += 4; ++ size -= 4; ++ irqstat = esdhc_read32(®s->irqstat); ++ esdhc_write32(®s->datport, databuf); ++ } ++ blocks--; ++ } ++ } ++} ++#endif ++ ++static int esdhc_setup_data(struct mci_host *mci, struct mci_data *data) ++{ ++ struct fsl_esdhc_host *host = to_fsl_esdhc(mci); ++ struct fsl_esdhc *regs = host->regs; ++#ifndef CONFIG_MCI_IMX_ESDHC_PIO ++ u32 wml_value; ++ ++ wml_value = data->blocksize/4; ++ ++ if (data->flags & MMC_DATA_READ) { ++ if (wml_value > 0x10) ++ wml_value = 0x10; ++ ++ esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); ++ esdhc_write32(®s->dsaddr, (u32)data->dest); ++ } else { ++ if (wml_value > 0x80) ++ wml_value = 0x80; ++ if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { ++ printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); ++ return -ETIMEDOUT; ++ } ++ ++ esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, ++ wml_value << 16); ++ esdhc_write32(®s->dsaddr, (u32)data->src); ++ } ++#else /* CONFIG_MCI_IMX_ESDHC_PIO */ ++ if (!(data->flags & MMC_DATA_READ)) { ++ if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { ++ printf("\nThe SD card is locked. " ++ "Can not write to a locked card.\n\n"); ++ return -ETIMEDOUT; ++ } ++ esdhc_write32(®s->dsaddr, (u32)data->src); ++ } else ++ esdhc_write32(®s->dsaddr, (u32)data->dest); ++#endif /* CONFIG_MCI_IMX_ESDHC_PIO */ ++ ++ esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); ++ ++ return 0; ++} ++ ++ ++/* ++ * Sends a command out on the bus. Takes the mci pointer, ++ * a command pointer, and an optional data pointer. ++ */ ++static int ++esdhc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data) ++{ ++ u32 xfertyp; ++ u32 irqstat; ++ struct fsl_esdhc_host *host = to_fsl_esdhc(mci); ++ struct fsl_esdhc *regs = host->regs; ++ ++ esdhc_write32(®s->irqstat, -1); ++ ++ /* Wait for the bus to be idle */ ++ while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || ++ (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) ++ ; ++ ++ while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) ++ ; ++ ++ /* Wait at least 8 SD clock cycles before the next command */ ++ /* ++ * Note: This is way more than 8 cycles, but 1ms seems to ++ * resolve timing issues with some cards ++ */ ++ udelay(1000); ++ ++ /* Set up for a data transfer if we have one */ ++ if (data) { ++ int err; ++ ++ err = esdhc_setup_data(mci, data); ++ if(err) ++ return err; ++ if (data->flags & MMC_DATA_WRITE) { ++ dma_flush_range((unsigned long)data->src, ++ (unsigned long)(data->src + 512)); ++ } else ++ dma_clean_range((unsigned long)data->src, ++ (unsigned long)(data->src + 512)); ++ ++ } ++ ++ /* Figure out the transfer arguments */ ++ xfertyp = esdhc_xfertyp(cmd, data); ++ ++ /* Send the command */ ++ esdhc_write32(®s->cmdarg, cmd->cmdarg); ++ esdhc_write32(®s->xfertyp, xfertyp); ++ ++ /* Wait for the command to complete */ ++ while (!(esdhc_read32(®s->irqstat) & IRQSTAT_CC)) ++ ; ++ ++ irqstat = esdhc_read32(®s->irqstat); ++ esdhc_write32(®s->irqstat, irqstat); ++ ++ if (irqstat & CMD_ERR) ++ return -EIO; ++ ++ if (irqstat & IRQSTAT_CTOE) ++ return -ETIMEDOUT; ++ ++ /* Copy the response to the response buffer */ ++ if (cmd->resp_type & MMC_RSP_136) { ++ u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; ++ ++ cmdrsp3 = esdhc_read32(®s->cmdrsp3); ++ cmdrsp2 = esdhc_read32(®s->cmdrsp2); ++ cmdrsp1 = esdhc_read32(®s->cmdrsp1); ++ cmdrsp0 = esdhc_read32(®s->cmdrsp0); ++ cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); ++ cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); ++ cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); ++ cmd->response[3] = (cmdrsp0 << 8); ++ } else ++ cmd->response[0] = esdhc_read32(®s->cmdrsp0); ++ ++ /* Wait until all of the blocks are transferred */ ++ if (data) { ++#ifdef CONFIG_MCI_IMX_ESDHC_PIO ++ esdhc_pio_read_write(mci, data); ++#else ++ do { ++ irqstat = esdhc_read32(®s->irqstat); ++ ++ if (irqstat & DATA_ERR) ++ return -EIO; ++ ++ if (irqstat & IRQSTAT_DTOE) ++ return -ETIMEDOUT; ++ } while (!(irqstat & IRQSTAT_TC) && ++ (esdhc_read32(®s->prsstat) & PRSSTAT_DLA)); ++ ++ if (data->flags & MMC_DATA_READ) { ++ dma_inv_range((unsigned long)data->dest, ++ (unsigned long)(data->dest + 512)); ++ } ++#endif ++ } ++ ++ esdhc_write32(®s->irqstat, -1); ++ ++ return 0; ++} ++ ++void set_sysctl(struct mci_host *mci, u32 clock) ++{ ++ int div, pre_div; ++ struct fsl_esdhc_host *host = to_fsl_esdhc(mci); ++ struct fsl_esdhc *regs = host->regs; ++ int sdhc_clk = imx_get_mmcclk(); ++ u32 clk; ++ ++ if (clock < mci->f_min) ++ clock = mci->f_min; ++ ++ pre_div = 0; ++ ++ for (pre_div = 1; pre_div < 256; pre_div <<= 1) { ++ if (sdhc_clk / pre_div < clock * 16) ++ break; ++ }; ++ ++ div = sdhc_clk / pre_div / clock; ++ ++ if (sdhc_clk / pre_div / div > clock) ++ div++; ++ ++ host->cur_clock = sdhc_clk / pre_div / div; ++ ++ div -= 1; ++ pre_div >>= 1; ++ ++ dev_dbg(host->dev, "set clock: wanted: %d got: %d\n", clock, host->cur_clock); ++ dev_dbg(host->dev, "pre_div: %d div: %d\n", pre_div, div); ++ ++ clk = (pre_div << 8) | (div << 4); ++ ++ esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); ++ ++ esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); ++ ++ udelay(10000); ++ ++ clk = SYSCTL_PEREN | SYSCTL_CKEN; ++ ++ esdhc_setbits32(®s->sysctl, clk); ++} ++ ++static void esdhc_set_ios(struct mci_host *mci, struct device_d *dev, ++ unsigned bus_width, unsigned clock) ++{ ++ struct fsl_esdhc_host *host = to_fsl_esdhc(mci); ++ struct fsl_esdhc *regs = host->regs; ++ ++ /* Set the clock speed */ ++ set_sysctl(mci, clock); ++ ++ /* Set the bus width */ ++ esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); ++ ++ if (bus_width == 4) ++ esdhc_setbits32(®s->proctl, PROCTL_DTW_4); ++ else if (bus_width == 8) ++ esdhc_setbits32(®s->proctl, PROCTL_DTW_8); ++ ++} ++ ++static int esdhc_init(struct mci_host *mci, struct device_d *dev) ++{ ++ struct fsl_esdhc_host *host = to_fsl_esdhc(mci); ++ struct fsl_esdhc *regs = host->regs; ++ int timeout = 1000; ++ int ret = 0; ++ ++ /* Enable cache snooping */ ++ if (host && !host->no_snoop) ++ esdhc_write32(®s->scr, 0x00000040); ++ ++ /* Reset the entire host controller */ ++ esdhc_write32(®s->sysctl, SYSCTL_RSTA); ++ ++ /* Wait until the controller is available */ ++ while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA) && --timeout) ++ udelay(1000); ++ ++ esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); ++ ++ /* Set the initial clock speed */ ++ set_sysctl(mci, 400000); ++ ++ /* Disable the BRR and BWR bits in IRQSTAT */ ++ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); ++ ++ /* Put the PROCTL reg back to the default */ ++ esdhc_write32(®s->proctl, PROCTL_INIT); ++ ++ /* Set timout to the maximum value */ ++ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); ++ ++ return ret; ++} ++ ++static int esdhc_reset(struct fsl_esdhc *regs) ++{ ++ uint64_t start; ++ ++ /* reset the controller */ ++ esdhc_write32(®s->sysctl, SYSCTL_RSTA); ++ ++ start = get_time_ns(); ++ /* hardware clears the bit when it is done */ ++ while (1) { ++ if (!(esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) ++ break; ++ if (is_timeout(start, 100 * MSECOND)) { ++ printf("MMC/SD: Reset never completed.\n"); ++ return -EIO; ++ } ++ } ++ ++ return 0; ++} ++ ++static int fsl_esdhc_probe(struct device_d *dev) ++{ ++ struct fsl_esdhc_host *host; ++ struct mci_host *mci; ++ u32 caps; ++ int ret; ++ ++ host = xzalloc(sizeof(*host)); ++ mci = &host->mci; ++ ++ host->dev = dev; ++ host->regs = (struct fsl_esdhc *)dev->map_base; ++ ++ /* First reset the eSDHC controller */ ++ ret = esdhc_reset(host->regs); ++ if (ret) { ++ free(host); ++ return ret; ++ } ++ ++ caps = esdhc_read32(&host->regs->hostcapblt); ++ ++ if (caps & ESDHC_HOSTCAPBLT_VS18) ++ mci->voltages |= MMC_VDD_165_195; ++ if (caps & ESDHC_HOSTCAPBLT_VS30) ++ mci->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; ++ if (caps & ESDHC_HOSTCAPBLT_VS33) ++ mci->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ mci->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; ++ ++ if (caps & ESDHC_HOSTCAPBLT_HSS) ++ mci->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; ++ ++ host->mci.send_cmd = esdhc_send_cmd; ++ host->mci.set_ios = esdhc_set_ios; ++ host->mci.init = esdhc_init; ++ host->mci.host_caps = MMC_MODE_4BIT; ++ ++ host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ host->mci.f_min = imx_get_mmcclk() >> 12; ++ if (host->mci.f_min < 200000) ++ host->mci.f_min = 200000; ++ host->mci.f_max = imx_get_mmcclk(); ++ ++ mci_register(&host->mci); ++ ++ return 0; ++} ++ ++static struct driver_d fsl_esdhc_driver = { ++ .name = "imx-esdhc", ++ .probe = fsl_esdhc_probe, ++}; ++ ++static int fsl_esdhc_init_driver(void) ++{ ++ register_driver(&fsl_esdhc_driver); ++ return 0; ++} ++ ++device_initcall(fsl_esdhc_init_driver); ++ +diff --git a/drivers/mci/imx-esdhc.h b/drivers/mci/imx-esdhc.h +new file mode 100644 +index 0000000..19fed5a +--- /dev/null ++++ b/drivers/mci/imx-esdhc.h +@@ -0,0 +1,164 @@ ++/* ++ * FSL SD/MMC Defines ++ *------------------------------------------------------------------- ++ * ++ * Copyright 2007-2008,2010 Freescale Semiconductor, Inc ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ *------------------------------------------------------------------- ++ * ++ */ ++ ++#ifndef __FSL_ESDHC_H__ ++#define __FSL_ESDHC_H__ ++ ++#include <errno.h> ++#include <asm/byteorder.h> ++ ++/* FSL eSDHC-specific constants */ ++#define SYSCTL 0x0002e02c ++#define SYSCTL_INITA 0x08000000 ++#define SYSCTL_TIMEOUT_MASK 0x000f0000 ++#define SYSCTL_CLOCK_MASK 0x0000fff0 ++#define SYSCTL_RSTA 0x01000000 ++#define SYSCTL_CKEN 0x00000008 ++#define SYSCTL_PEREN 0x00000004 ++#define SYSCTL_HCKEN 0x00000002 ++#define SYSCTL_IPGEN 0x00000001 ++#define SYSCTL_RSTA 0x01000000 ++ ++#define IRQSTAT 0x0002e030 ++#define IRQSTAT_DMAE (0x10000000) ++#define IRQSTAT_AC12E (0x01000000) ++#define IRQSTAT_DEBE (0x00400000) ++#define IRQSTAT_DCE (0x00200000) ++#define IRQSTAT_DTOE (0x00100000) ++#define IRQSTAT_CIE (0x00080000) ++#define IRQSTAT_CEBE (0x00040000) ++#define IRQSTAT_CCE (0x00020000) ++#define IRQSTAT_CTOE (0x00010000) ++#define IRQSTAT_CINT (0x00000100) ++#define IRQSTAT_CRM (0x00000080) ++#define IRQSTAT_CINS (0x00000040) ++#define IRQSTAT_BRR (0x00000020) ++#define IRQSTAT_BWR (0x00000010) ++#define IRQSTAT_DINT (0x00000008) ++#define IRQSTAT_BGE (0x00000004) ++#define IRQSTAT_TC (0x00000002) ++#define IRQSTAT_CC (0x00000001) ++ ++#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) ++#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE) ++ ++#define IRQSTATEN 0x0002e034 ++#define IRQSTATEN_DMAE (0x10000000) ++#define IRQSTATEN_AC12E (0x01000000) ++#define IRQSTATEN_DEBE (0x00400000) ++#define IRQSTATEN_DCE (0x00200000) ++#define IRQSTATEN_DTOE (0x00100000) ++#define IRQSTATEN_CIE (0x00080000) ++#define IRQSTATEN_CEBE (0x00040000) ++#define IRQSTATEN_CCE (0x00020000) ++#define IRQSTATEN_CTOE (0x00010000) ++#define IRQSTATEN_CINT (0x00000100) ++#define IRQSTATEN_CRM (0x00000080) ++#define IRQSTATEN_CINS (0x00000040) ++#define IRQSTATEN_BRR (0x00000020) ++#define IRQSTATEN_BWR (0x00000010) ++#define IRQSTATEN_DINT (0x00000008) ++#define IRQSTATEN_BGE (0x00000004) ++#define IRQSTATEN_TC (0x00000002) ++#define IRQSTATEN_CC (0x00000001) ++ ++#define PRSSTAT 0x0002e024 ++#define PRSSTAT_CLSL (0x00800000) ++#define PRSSTAT_WPSPL (0x00080000) ++#define PRSSTAT_CDPL (0x00040000) ++#define PRSSTAT_CINS (0x00010000) ++#define PRSSTAT_BREN (0x00000800) ++#define PRSSTAT_BWEN (0x00000400) ++#define PRSSTAT_DLA (0x00000004) ++#define PRSSTAT_CICHB (0x00000002) ++#define PRSSTAT_CIDHB (0x00000001) ++ ++#define PROCTL 0x0002e028 ++#define PROCTL_INIT 0x00000020 ++#define PROCTL_DTW_4 0x00000002 ++#define PROCTL_DTW_8 0x00000004 ++ ++#define CMDARG 0x0002e008 ++ ++#define XFERTYP 0x0002e00c ++#define XFERTYP_CMD(x) ((x & 0x3f) << 24) ++#define XFERTYP_CMDTYP_NORMAL 0x0 ++#define XFERTYP_CMDTYP_SUSPEND 0x00400000 ++#define XFERTYP_CMDTYP_RESUME 0x00800000 ++#define XFERTYP_CMDTYP_ABORT 0x00c00000 ++#define XFERTYP_DPSEL 0x00200000 ++#define XFERTYP_CICEN 0x00100000 ++#define XFERTYP_CCCEN 0x00080000 ++#define XFERTYP_RSPTYP_NONE 0 ++#define XFERTYP_RSPTYP_136 0x00010000 ++#define XFERTYP_RSPTYP_48 0x00020000 ++#define XFERTYP_RSPTYP_48_BUSY 0x00030000 ++#define XFERTYP_MSBSEL 0x00000020 ++#define XFERTYP_DTDSEL 0x00000010 ++#define XFERTYP_AC12EN 0x00000004 ++#define XFERTYP_BCEN 0x00000002 ++#define XFERTYP_DMAEN 0x00000001 ++ ++#define CINS_TIMEOUT 1000 ++#define PIO_TIMEOUT 100000 ++ ++#define DSADDR 0x2e004 ++ ++#define CMDRSP0 0x2e010 ++#define CMDRSP1 0x2e014 ++#define CMDRSP2 0x2e018 ++#define CMDRSP3 0x2e01c ++ ++#define DATPORT 0x2e020 ++ ++#define WML 0x2e044 ++#define WML_WRITE 0x00010000 ++#define WML_RD_WML_MASK 0xff ++#define WML_WR_WML_MASK 0xff0000 ++ ++#define BLKATTR 0x2e004 ++#define BLKATTR_CNT(x) ((x & 0xffff) << 16) ++#define BLKATTR_SIZE(x) (x & 0x1fff) ++#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ ++ ++#define ESDHC_HOSTCAPBLT_VS18 0x04000000 ++#define ESDHC_HOSTCAPBLT_VS30 0x02000000 ++#define ESDHC_HOSTCAPBLT_VS33 0x01000000 ++#define ESDHC_HOSTCAPBLT_SRS 0x00800000 ++#define ESDHC_HOSTCAPBLT_DMAS 0x00400000 ++#define ESDHC_HOSTCAPBLT_HSS 0x00200000 ++ ++struct fsl_esdhc_cfg { ++ u32 esdhc_base; ++ u32 no_snoop; ++}; ++ ++#define esdhc_read32(a) readl(a) ++#define esdhc_write32(a, v) writel(v,a) ++#define esdhc_clrsetbits32(a, c, s) writel((readl(a) & ~(c)) | (s), (a)) ++#define esdhc_clrbits32(a, c) writel(readl(a) & ~(c), (a)) ++#define esdhc_setbits32(a, s) writel(readl(a) | (s), (a)) ++ ++#endif /* __FSL_ESDHC_H__ */ +diff --git a/drivers/mci/imx.c b/drivers/mci/imx.c +new file mode 100644 +index 0000000..8525692 +--- /dev/null ++++ b/drivers/mci/imx.c +@@ -0,0 +1,520 @@ ++/* ++ * This is a driver for the SDHC controller found in Freescale MX2/MX3 ++ * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). ++ * Unlike the hardware found on MX1, this hardware just works and does ++ * not need all the quirks found in imxmmc.c, hence the seperate driver. ++ * ++ * Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com> ++ * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> ++ * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> ++ * ++ * derived from pxamci.c by Russell King ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include <config.h> ++#include <common.h> ++#include <command.h> ++#include <mci.h> ++#include <malloc.h> ++#include <errno.h> ++#include <clock.h> ++#include <init.h> ++#include <driver.h> ++#include <mach/clock.h> ++#include <asm/io.h> ++ ++#define DRIVER_NAME "imx-mmc" ++ ++struct mxcmci_regs { ++ u32 str_stp_clk; ++ u32 status; ++ u32 clk_rate; ++ u32 cmd_dat_cont; ++ u32 res_to; ++ u32 read_to; ++ u32 blk_len; ++ u32 nob; ++ u32 rev_no; ++ u32 int_cntr; ++ u32 cmd; ++ u32 arg; ++ u32 pad; ++ u32 res_fifo; ++ u32 buffer_access; ++}; ++ ++#define STR_STP_CLK_RESET (1 << 3) ++#define STR_STP_CLK_START_CLK (1 << 1) ++#define STR_STP_CLK_STOP_CLK (1 << 0) ++ ++#define STATUS_CARD_INSERTION (1 << 31) ++#define STATUS_CARD_REMOVAL (1 << 30) ++#define STATUS_YBUF_EMPTY (1 << 29) ++#define STATUS_XBUF_EMPTY (1 << 28) ++#define STATUS_YBUF_FULL (1 << 27) ++#define STATUS_XBUF_FULL (1 << 26) ++#define STATUS_BUF_UND_RUN (1 << 25) ++#define STATUS_BUF_OVFL (1 << 24) ++#define STATUS_SDIO_INT_ACTIVE (1 << 14) ++#define STATUS_END_CMD_RESP (1 << 13) ++#define STATUS_WRITE_OP_DONE (1 << 12) ++#define STATUS_DATA_TRANS_DONE (1 << 11) ++#define STATUS_READ_OP_DONE (1 << 11) ++#define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) ++#define STATUS_CARD_BUS_CLK_RUN (1 << 8) ++#define STATUS_BUF_READ_RDY (1 << 7) ++#define STATUS_BUF_WRITE_RDY (1 << 6) ++#define STATUS_RESP_CRC_ERR (1 << 5) ++#define STATUS_CRC_READ_ERR (1 << 3) ++#define STATUS_CRC_WRITE_ERR (1 << 2) ++#define STATUS_TIME_OUT_RESP (1 << 1) ++#define STATUS_TIME_OUT_READ (1 << 0) ++#define STATUS_ERR_MASK 0x2f ++ ++#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) ++#define CMD_DAT_CONT_STOP_READWAIT (1 << 11) ++#define CMD_DAT_CONT_START_READWAIT (1 << 10) ++#define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) ++#define CMD_DAT_CONT_INIT (1 << 7) ++#define CMD_DAT_CONT_WRITE (1 << 4) ++#define CMD_DAT_CONT_DATA_ENABLE (1 << 3) ++#define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) ++#define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) ++#define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) ++ ++#define INT_SDIO_INT_WKP_EN (1 << 18) ++#define INT_CARD_INSERTION_WKP_EN (1 << 17) ++#define INT_CARD_REMOVAL_WKP_EN (1 << 16) ++#define INT_CARD_INSERTION_EN (1 << 15) ++#define INT_CARD_REMOVAL_EN (1 << 14) ++#define INT_SDIO_IRQ_EN (1 << 13) ++#define INT_DAT0_EN (1 << 12) ++#define INT_BUF_READ_EN (1 << 4) ++#define INT_BUF_WRITE_EN (1 << 3) ++#define INT_END_CMD_RES_EN (1 << 2) ++#define INT_WRITE_OP_DONE_EN (1 << 1) ++#define INT_READ_OP_EN (1 << 0) ++ ++struct mxcmci_host { ++ struct mci_host mci; ++ struct mxcmci_regs *base; ++ int irq; ++ int detect_irq; ++ int dma; ++ int do_dma; ++ unsigned int power_mode; ++ ++ struct mci_cmd *cmd; ++ struct mci_data *data; ++ ++ unsigned int dma_nents; ++ unsigned int datasize; ++ unsigned int dma_dir; ++ ++ u16 rev_no; ++ unsigned int cmdat; ++ ++ int clock; ++}; ++ ++#define to_mxcmci(mci) container_of(mci, struct mxcmci_host, mci) ++ ++static void mxcmci_softreset(struct mxcmci_host *host) ++{ ++ int i; ++ ++ /* reset sequence */ ++ writew(STR_STP_CLK_RESET, &host->base->str_stp_clk); ++ writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, ++ &host->base->str_stp_clk); ++ ++ for (i = 0; i < 8; i++) ++ writew(STR_STP_CLK_START_CLK, &host->base->str_stp_clk); ++ ++ writew(0xff, &host->base->res_to); ++} ++ ++static void mxcmci_setup_data(struct mxcmci_host *host, struct mci_data *data) ++{ ++ unsigned int nob = data->blocks; ++ unsigned int blksz = data->blocksize; ++ unsigned int datasize = nob * blksz; ++ ++ host->data = data; ++ ++ writew(nob, &host->base->nob); ++ writew(blksz, &host->base->blk_len); ++ host->datasize = datasize; ++} ++ ++static int mxcmci_start_cmd(struct mxcmci_host *host, struct mci_cmd *cmd, ++ unsigned int cmdat) ++{ ++ if (host->cmd != NULL) ++ printf("mxcmci: error!\n"); ++ host->cmd = cmd; ++ ++ switch (cmd->resp_type) { ++ case MMC_RSP_R1: /* short CRC, OPCODE */ ++ case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */ ++ cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; ++ break; ++ case MMC_RSP_R2: /* long 136 bit + CRC */ ++ cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; ++ break; ++ case MMC_RSP_R3: /* short */ ++ cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; ++ break; ++ case MMC_RSP_NONE: ++ break; ++ default: ++ printf("mxcmci: unhandled response type 0x%x\n", ++ cmd->resp_type); ++ return -EINVAL; ++ } ++ ++ writew(cmd->cmdidx, &host->base->cmd); ++ writel(cmd->cmdarg, &host->base->arg); ++ writew(cmdat, &host->base->cmd_dat_cont); ++ ++ return 0; ++} ++ ++static void mxcmci_finish_request(struct mxcmci_host *host, ++ struct mci_cmd *cmd, struct mci_data *data) ++{ ++ host->cmd = NULL; ++ host->data = NULL; ++} ++ ++static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) ++{ ++ int data_error = 0; ++ ++ if (stat & STATUS_ERR_MASK) { ++ printf("request failed. status: 0x%08x\n", ++ stat); ++ if (stat & STATUS_CRC_READ_ERR) { ++ data_error = -EILSEQ; ++ } else if (stat & STATUS_CRC_WRITE_ERR) { ++ u32 err_code = (stat >> 9) & 0x3; ++ if (err_code == 2) /* No CRC response */ ++ data_error = -ETIMEDOUT; ++ else ++ data_error = -EILSEQ; ++ } else if (stat & STATUS_TIME_OUT_READ) { ++ data_error = -ETIMEDOUT; ++ } else { ++ data_error = -EIO; ++ } ++ } ++ ++ host->data = NULL; ++ ++ return data_error; ++} ++ ++static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) ++{ ++ struct mci_cmd *cmd = host->cmd; ++ int i; ++ u32 a, b, c; ++ u32 *resp = (u32 *)cmd->response; ++ ++ if (!cmd) ++ return 0; ++ ++ if (stat & STATUS_TIME_OUT_RESP) { ++ printf("CMD TIMEOUT\n"); ++ return -ETIMEDOUT; ++ } else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) { ++ printf("cmd crc error\n"); ++ return -EILSEQ; ++ } ++ ++ if (cmd->resp_type & MMC_RSP_PRESENT) { ++ if (cmd->resp_type & MMC_RSP_136) { ++ for (i = 0; i < 4; i++) { ++ a = readw(&host->base->res_fifo); ++ b = readw(&host->base->res_fifo); ++ resp[i] = a << 16 | b; ++ } ++ } else { ++ a = readw(&host->base->res_fifo); ++ b = readw(&host->base->res_fifo); ++ c = readw(&host->base->res_fifo); ++ resp[0] = a << 24 | b << 8 | c >> 8; ++ } ++ } ++ return 0; ++} ++ ++static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) ++{ ++ u32 stat; ++ uint64_t start = get_time_ns(); ++ ++ do { ++ stat = readl(&host->base->status); ++ if (stat & STATUS_ERR_MASK) ++ return stat; ++ if (is_timeout(start, SECOND)) ++ return STATUS_TIME_OUT_READ; ++ if (stat & mask) ++ return 0; ++ } while (1); ++} ++ ++static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) ++{ ++ unsigned int stat; ++ u32 *buf = _buf; ++ ++ while (bytes > 3) { ++ stat = mxcmci_poll_status(host, ++ STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); ++ if (stat) ++ return stat; ++ *buf++ = readl(&host->base->buffer_access); ++ bytes -= 4; ++ } ++ ++ if (bytes) { ++ u8 *b = (u8 *)buf; ++ u32 tmp; ++ ++ stat = mxcmci_poll_status(host, ++ STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); ++ if (stat) ++ return stat; ++ tmp = readl(&host->base->buffer_access); ++ memcpy(b, &tmp, bytes); ++ } ++ ++ return 0; ++} ++ ++static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes) ++{ ++ unsigned int stat; ++ const u32 *buf = _buf; ++ ++ while (bytes > 3) { ++ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); ++ if (stat) ++ return stat; ++ writel(*buf++, &host->base->buffer_access); ++ bytes -= 4; ++ } ++ ++ if (bytes) { ++ const u8 *b = (u8 *)buf; ++ u32 tmp; ++ ++ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); ++ if (stat) ++ return stat; ++ ++ memcpy(&tmp, b, bytes); ++ writel(tmp, &host->base->buffer_access); ++ } ++ ++ stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); ++ if (stat) ++ return stat; ++ ++ return 0; ++} ++ ++static int mxcmci_transfer_data(struct mxcmci_host *host) ++{ ++ struct mci_data *data = host->data; ++ int stat; ++ unsigned long length; ++ ++ length = data->blocks * data->blocksize; ++ host->datasize = 0; ++ ++ if (data->flags & MMC_DATA_READ) { ++ stat = mxcmci_pull(host, data->dest, length); ++ if (stat) ++ return stat; ++ host->datasize += length; ++ } else { ++ stat = mxcmci_push(host, (const void *)(data->src), length); ++ if (stat) ++ return stat; ++ host->datasize += length; ++ stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); ++ if (stat) ++ return stat; ++ } ++ return 0; ++} ++ ++static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) ++{ ++ int datastat; ++ int ret; ++ ++ ret = mxcmci_read_response(host, stat); ++ ++ if (ret) { ++ mxcmci_finish_request(host, host->cmd, host->data); ++ return ret; ++ } ++ ++ if (!host->data) { ++ mxcmci_finish_request(host, host->cmd, host->data); ++ return 0; ++ } ++ ++ datastat = mxcmci_transfer_data(host); ++ ret = mxcmci_finish_data(host, datastat); ++ mxcmci_finish_request(host, host->cmd, host->data); ++ return ret; ++} ++ ++static int mxcmci_request(struct mci_host *mci, struct mci_cmd *cmd, ++ struct mci_data *data) ++{ ++ struct mxcmci_host *host = to_mxcmci(mci); ++ unsigned int cmdat = host->cmdat; ++ u32 stat; ++ int ret; ++ ++ host->cmdat &= ~CMD_DAT_CONT_INIT; ++ if (data) { ++ mxcmci_setup_data(host, data); ++ ++ cmdat |= CMD_DAT_CONT_DATA_ENABLE; ++ ++ if (data->flags & MMC_DATA_WRITE) ++ cmdat |= CMD_DAT_CONT_WRITE; ++ } ++ ++ if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) { ++ mxcmci_finish_request(host, cmd, data); ++ return ret; ++ } ++ ++ do { ++ stat = readl(&host->base->status); ++ writel(stat, &host->base->status); ++ } while (!(stat & STATUS_END_CMD_RESP)); ++ ++ return mxcmci_cmd_done(host, stat); ++} ++ ++static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) ++{ ++ unsigned int divider; ++ int prescaler = 0; ++ unsigned long clk_in = imx_get_mmcclk(); ++ ++ while (prescaler <= 0x800) { ++ for (divider = 1; divider <= 0xF; divider++) { ++ int x; ++ ++ x = (clk_in / (divider + 1)); ++ ++ if (prescaler) ++ x /= (prescaler * 2); ++ ++ if (x <= clk_ios) ++ break; ++ } ++ if (divider < 0x10) ++ break; ++ ++ if (prescaler == 0) ++ prescaler = 1; ++ else ++ prescaler <<= 1; ++ } ++ ++ writew((prescaler << 4) | divider, &host->base->clk_rate); ++} ++ ++static void mxcmci_set_ios(struct mci_host *mci, struct device_d *dev, ++ unsigned bus_width, unsigned clock) ++{ ++ struct mxcmci_host *host = to_mxcmci(mci); ++ ++ if (bus_width == 4) ++ host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; ++ else ++ host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; ++ ++ if (clock) { ++ mxcmci_set_clk_rate(host, clock); ++ writew(STR_STP_CLK_START_CLK, &host->base->str_stp_clk); ++ } else { ++ writew(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk); ++ } ++ ++ host->clock = clock; ++} ++ ++static int mxcmci_init(struct mci_host *mci, struct device_d *dev) ++{ ++ struct mxcmci_host *host = to_mxcmci(mci); ++ ++ mxcmci_softreset(host); ++ ++ host->rev_no = readw(&host->base->rev_no); ++ if (host->rev_no != 0x400) { ++ printf("wrong rev.no. 0x%08x. aborting.\n", ++ host->rev_no); ++ return -ENODEV; ++ } ++ ++ /* recommended in data sheet */ ++ writew(0x2db4, &host->base->read_to); ++ ++ writel(0, &host->base->int_cntr); ++ ++ return 0; ++} ++ ++static int mxcmci_probe(struct device_d *dev) ++{ ++ struct mxcmci_host *host; ++ ++ host = xzalloc(sizeof(*host)); ++ ++ host->mci.send_cmd = mxcmci_request; ++ host->mci.set_ios = mxcmci_set_ios; ++ host->mci.init = mxcmci_init; ++ host->mci.host_caps = MMC_MODE_4BIT; ++ ++ host->base = (struct mxcmci_regs *)dev->map_base; ++ ++ host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ host->mci.f_min = imx_get_mmcclk() >> 7; ++ host->mci.f_max = imx_get_mmcclk() >> 1; ++ ++ mci_register(&host->mci); ++ ++ return 0; ++} ++ ++static struct driver_d mxcmci_driver = { ++ .name = DRIVER_NAME, ++ .probe = mxcmci_probe, ++}; ++ ++static int mxcmci_init_driver(void) ++{ ++ register_driver(&mxcmci_driver); ++ return 0; ++} ++ ++device_initcall(mxcmci_init_driver); ++ +diff --git a/drivers/mci/mci-core.c b/drivers/mci/mci-core.c +new file mode 100644 +index 0000000..a8aa486 +--- /dev/null ++++ b/drivers/mci/mci-core.c +@@ -0,0 +1,1360 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert, Pengutronix ++ * ++ * This code is havily inspired and in parts from the u-boot project: ++ * ++ * Copyright 2008, Freescale Semiconductor, Inc ++ * Andy Fleming ++ * ++ * Based vaguely on the Linux code ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* #define DEBUG */ ++ ++#include <init.h> ++#include <common.h> ++#include <mci.h> ++#include <malloc.h> ++#include <errno.h> ++#include <asm-generic/div64.h> ++#include <asm/byteorder.h> ++#include <ata.h> ++ ++#define MAX_BUFFER_NUMBER 0xffffffff ++ ++/** ++ * @file ++ * @brief Memory Card framework ++ * ++ * Checked with the following cards: ++ * - Canon MMC 16 MiB ++ * - Integral MicroSDHC, 8 GiB (Class 4) ++ * - Kingston 512 MiB ++ * - SanDisk 512 MiB ++ * - Transcend SD Ultra, 1 GiB (Industrial) ++ * - Transcend SDHC, 4 GiB (Class 6) ++ * - Transcend SDHC, 8 GiB (Class 6) ++ */ ++ ++/** ++ * Call the MMC/SD instance driver to run the command on the MMC/SD card ++ * @param mci_dev MCI instance ++ * @param cmd The information about the command to run ++ * @param data The data according to the command (can be NULL) ++ * @return Driver's answer (0 on success) ++ */ ++static int mci_send_cmd(struct device_d *mci_dev, struct mci_cmd *cmd, struct mci_data *data) ++{ ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ ++ return host->send_cmd(host, cmd, data); ++} ++ ++/** ++ * @param p Command definition to setup ++ * @param cmd Valid SD/MMC command (refer MMC_CMD_* / SD_CMD_*) ++ * @param arg Argument for the command (optional) ++ * @param response Command's response type (refer MMC_RSP_*) ++ * ++ * Note: When calling, the 'response' must match command's requirements ++ */ ++static void mci_setup_cmd(struct mci_cmd *p, unsigned cmd, unsigned arg, unsigned response) ++{ ++ p->cmdidx = cmd; ++ p->cmdarg = arg; ++ p->resp_type = response; ++} ++ ++/** ++ * Setup SD/MMC card's blocklength to be used for future transmitts ++ * @param mci_dev MCI instance ++ * @param len Blocklength in bytes ++ * @return Transaction status (0 on success) ++ */ ++static int mci_set_blocklen(struct device_d *mci_dev, unsigned len) ++{ ++ struct mci_cmd cmd; ++ ++ mci_setup_cmd(&cmd, MMC_CMD_SET_BLOCKLEN, len, MMC_RSP_R1); ++ return mci_send_cmd(mci_dev, &cmd, NULL); ++} ++ ++static void *sector_buf; ++ ++/** ++ * Write one block of data to the card ++ * @param mci_dev MCI instance ++ * @param src Where to read from to write to the card ++ * @param blocknum Block number to write ++ * @return Transaction status (0 on success) ++ */ ++static int mci_block_write(struct device_d *mci_dev, const void *src, unsigned blocknum) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ struct mci_cmd cmd; ++ struct mci_data data; ++ const void *buf; ++ ++ if ((unsigned long)src & 0x3) { ++ memcpy(sector_buf, src, 512); ++ buf = sector_buf; ++ } else { ++ buf = src; ++ } ++ ++ mci_setup_cmd(&cmd, ++ MMC_CMD_WRITE_SINGLE_BLOCK, ++ mci->high_capacity != 0 ? blocknum : blocknum * mci->write_bl_len, ++ MMC_RSP_R1); ++ ++ data.src = buf; ++ data.blocks = 1; ++ data.blocksize = mci->write_bl_len; ++ data.flags = MMC_DATA_WRITE; ++ ++ return mci_send_cmd(mci_dev, &cmd, &data); ++} ++ ++/** ++ * Read one block of data from the card ++ * @param mci_dev MCI instance ++ * @param dst Where to store the data read from the card ++ * @param blocknum Block number to read ++ * @param blocks number of blocks to read ++ */ ++static int mci_read_block(struct device_d *mci_dev, void *dst, unsigned blocknum, ++ int blocks) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ struct mci_cmd cmd; ++ struct mci_data data; ++ int ret; ++ unsigned mmccmd; ++ ++ if (blocks > 1) ++ mmccmd = MMC_CMD_READ_MULTIPLE_BLOCK; ++ else ++ mmccmd = MMC_CMD_READ_SINGLE_BLOCK; ++ ++ mci_setup_cmd(&cmd, ++ mmccmd, ++ mci->high_capacity != 0 ? blocknum : blocknum * mci->read_bl_len, ++ MMC_RSP_R1); ++ ++ data.dest = dst; ++ data.blocks = blocks; ++ data.blocksize = mci->read_bl_len; ++ data.flags = MMC_DATA_READ; ++ ++ ret = mci_send_cmd(mci_dev, &cmd, &data); ++ if (ret) ++ return ret; ++ ++ if (blocks > 1) { ++ mci_setup_cmd(&cmd, ++ MMC_CMD_STOP_TRANSMISSION, ++ 0, ++ MMC_RSP_R1b); ++ ret = mci_send_cmd(mci_dev, &cmd, NULL); ++ } ++ return ret; ++} ++ ++/** ++ * Reset the attached MMC/SD card ++ * @param mci_dev MCI instance ++ * @return Transaction status (0 on success) ++ */ ++static int mci_go_idle(struct device_d *mci_dev) ++{ ++ struct mci_cmd cmd; ++ int err; ++ ++ udelay(1000); ++ ++ mci_setup_cmd(&cmd, MMC_CMD_GO_IDLE_STATE, 0, MMC_RSP_NONE); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ ++ if (err) { ++ pr_debug("Activating IDLE state failed: %d\n", err); ++ return err; ++ } ++ ++ udelay(2000); /* WTF? */ ++ ++ return 0; ++} ++ ++/** ++ * FIXME ++ * @param mci_dev MCI instance ++ * @return Transaction status (0 on success) ++ */ ++static int sd_send_op_cond(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ struct mci_cmd cmd; ++ int timeout = 1000; ++ int err; ++ ++ do { ++ mci_setup_cmd(&cmd, MMC_CMD_APP_CMD, 0, MMC_RSP_R1); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Preparing SD for operating conditions failed: %d\n", err); ++ return err; ++ } ++ ++ mci_setup_cmd(&cmd, SD_CMD_APP_SEND_OP_COND, ++ host->voltages | (mci->version == SD_VERSION_2 ? OCR_HCS : 0), ++ MMC_RSP_R3); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("SD operation condition set failed: %d\n", err); ++ return err; ++ } ++ udelay(1000); ++ } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--); ++ ++ if (timeout <= 0) { ++ pr_debug("SD operation condition set timed out\n"); ++ return -ENODEV; ++ } ++ ++ if (mci->version != SD_VERSION_2) ++ mci->version = SD_VERSION_1_0; ++ ++ mci->ocr = cmd.response[0]; ++ ++ mci->high_capacity = ((mci->ocr & OCR_HCS) == OCR_HCS); ++ mci->rca = 0; ++ ++ return 0; ++} ++ ++/** ++ * Setup the operation conditions to a MultiMediaCard ++ * @param mci_dev MCI instance ++ * @return Transaction status (0 on success) ++ */ ++static int mmc_send_op_cond(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ struct mci_cmd cmd; ++ int timeout = 1000; ++ int err; ++ ++ /* Some cards seem to need this */ ++ mci_go_idle(mci_dev); ++ ++ do { ++ mci_setup_cmd(&cmd, MMC_CMD_SEND_OP_COND, OCR_HCS | ++ host->voltages, MMC_RSP_R3); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ ++ if (err) { ++ pr_debug("Preparing MMC for operating conditions failed: %d\n", err); ++ return err; ++ } ++ ++ udelay(1000); ++ } while (!(cmd.response[0] & OCR_BUSY) && timeout--); ++ ++ if (timeout <= 0) { ++ pr_debug("SD operation condition set timed out\n"); ++ return -ENODEV; ++ } ++ ++ mci->version = MMC_VERSION_UNKNOWN; ++ mci->ocr = cmd.response[0]; ++ ++ mci->high_capacity = ((mci->ocr & OCR_HCS) == OCR_HCS); ++ mci->rca = 0; ++ ++ return 0; ++} ++ ++/** ++ * FIXME ++ * @param mci_dev MCI instance ++ * @param ext_csd Buffer for a 512 byte sized extended CSD ++ * @return Transaction status (0 on success) ++ * ++ * Note: Only cards newer than Version 1.1 (Physical Layer Spec) support ++ * this command ++ */ ++static int mci_send_ext_csd(struct device_d *mci_dev, char *ext_csd) ++{ ++ struct mci_cmd cmd; ++ struct mci_data data; ++ ++ /* Get the Card Status Register */ ++ mci_setup_cmd(&cmd, MMC_CMD_SEND_EXT_CSD, 0, MMC_RSP_R1); ++ ++ data.dest = ext_csd; ++ data.blocks = 1; ++ data.blocksize = 512; ++ data.flags = MMC_DATA_READ; ++ ++ return mci_send_cmd(mci_dev, &cmd, &data); ++} ++ ++/** ++ * FIXME ++ * @param mci_dev MCI instance ++ * @param set FIXME ++ * @param index FIXME ++ * @param value FIXME ++ * @return Transaction status (0 on success) ++ */ ++static int mci_switch(struct device_d *mci_dev, unsigned set, unsigned index, ++ unsigned value) ++{ ++ struct mci_cmd cmd; ++ ++ mci_setup_cmd(&cmd, MMC_CMD_SWITCH, ++ (MMC_SWITCH_MODE_WRITE_BYTE << 24) | ++ (index << 16) | ++ (value << 8), ++ MMC_RSP_R1b); ++ ++ return mci_send_cmd(mci_dev, &cmd, NULL); ++} ++ ++/** ++ * Change transfer frequency for an MMC card ++ * @param mci_dev MCI instance ++ * @return Transaction status (0 on success) ++ */ ++static int mmc_change_freq(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ char *ext_csd = sector_buf; ++ char cardtype; ++ int err; ++ ++ mci->card_caps = 0; ++ ++ /* Only version 4 supports high-speed */ ++ if (mci->version < MMC_VERSION_4) ++ return 0; ++ ++ mci->card_caps |= MMC_MODE_4BIT; ++ ++ err = mci_send_ext_csd(mci_dev, ext_csd); ++ if (err) { ++ pr_debug("Preparing for frequency setup failed: %d\n", err); ++ return err; ++ } ++ ++ if (ext_csd[212] || ext_csd[213] || ext_csd[214] || ext_csd[215]) ++ mci->high_capacity = 1; ++ ++ cardtype = ext_csd[196] & 0xf; ++ ++ err = mci_switch(mci_dev, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); ++ ++ if (err) { ++ pr_debug("MMC frequency changing failed: %d\n", err); ++ return err; ++ } ++ ++ /* Now check to see that it worked */ ++ err = mci_send_ext_csd(mci_dev, ext_csd); ++ ++ if (err) { ++ pr_debug("Verifying frequency change failed: %d\n", err); ++ return err; ++ } ++ ++ /* No high-speed support */ ++ if (!ext_csd[185]) ++ return 0; ++ ++ /* High Speed is set, there are two types: 52MHz and 26MHz */ ++ if (cardtype & MMC_HS_52MHZ) ++ mci->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; ++ else ++ mci->card_caps |= MMC_MODE_HS; ++ ++ return 0; ++} ++ ++/** ++ * FIXME ++ * @param mci_dev MCI instance ++ * @param mode FIXME ++ * @param group FIXME ++ * @param value FIXME ++ * @param resp FIXME ++ * @return Transaction status (0 on success) ++ */ ++static int sd_switch(struct device_d *mci_dev, unsigned mode, unsigned group, ++ unsigned value, uint8_t *resp) ++{ ++ struct mci_cmd cmd; ++ struct mci_data data; ++ unsigned arg; ++ ++ arg = (mode << 31) | 0xffffff; ++ arg &= ~(0xf << (group << 2)); ++ arg |= value << (group << 2); ++ ++ /* Switch the frequency */ ++ mci_setup_cmd(&cmd, SD_CMD_SWITCH_FUNC, arg, MMC_RSP_R1); ++ ++ data.dest = resp; ++ data.blocksize = 64; ++ data.blocks = 1; ++ data.flags = MMC_DATA_READ; ++ ++ return mci_send_cmd(mci_dev, &cmd, &data); ++} ++ ++/** ++ * Change transfer frequency for an SD card ++ * @param mci_dev MCI instance ++ * @return Transaction status (0 on success) ++ */ ++static int sd_change_freq(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ struct mci_cmd cmd; ++ struct mci_data data; ++ uint32_t *switch_status = sector_buf; ++ uint32_t *scr = sector_buf; ++ int timeout; ++ int err; ++ ++ pr_debug("Changing transfer frequency\n"); ++ mci->card_caps = 0; ++ ++ /* Read the SCR to find out if this card supports higher speeds */ ++ mci_setup_cmd(&cmd, MMC_CMD_APP_CMD, mci->rca << 16, MMC_RSP_R1); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Query SD card capabilities failed: %d\n", err); ++ return err; ++ } ++ ++ mci_setup_cmd(&cmd, SD_CMD_APP_SEND_SCR, 0, MMC_RSP_R1); ++ ++ timeout = 3; ++ ++retry_scr: ++ pr_debug("Trying to read the SCR (try %d of %d)\n", 4 - timeout, 3); ++ data.dest = (char *)scr; ++ data.blocksize = 8; ++ data.blocks = 1; ++ data.flags = MMC_DATA_READ; ++ ++ err = mci_send_cmd(mci_dev, &cmd, &data); ++ if (err) { ++ pr_debug(" Catch error (%d)", err); ++ if (timeout--) { ++ pr_debug("-- retrying\n"); ++ goto retry_scr; ++ } ++ pr_debug("-- giving up\n"); ++ return err; ++ } ++ ++ mci->scr[0] = __be32_to_cpu(scr[0]); ++ mci->scr[1] = __be32_to_cpu(scr[1]); ++ ++ switch ((mci->scr[0] >> 24) & 0xf) { ++ case 0: ++ mci->version = SD_VERSION_1_0; ++ break; ++ case 1: ++ mci->version = SD_VERSION_1_10; ++ break; ++ case 2: ++ mci->version = SD_VERSION_2; ++ break; ++ default: ++ mci->version = SD_VERSION_1_0; ++ break; ++ } ++ ++ /* Version 1.0 doesn't support switching */ ++ if (mci->version == SD_VERSION_1_0) ++ return 0; ++ ++ timeout = 4; ++ while (timeout--) { ++ err = sd_switch(mci_dev, SD_SWITCH_CHECK, 0, 1, ++ (uint8_t*)switch_status); ++ if (err) { ++ pr_debug("Checking SD transfer switch frequency feature failed: %d\n", err); ++ return err; ++ } ++ ++ /* The high-speed function is busy. Try again */ ++ if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) ++ break; ++ } ++ ++ if (mci->scr[0] & SD_DATA_4BIT) ++ mci->card_caps |= MMC_MODE_4BIT; ++ ++ /* If high-speed isn't supported, we return */ ++ if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) ++ return 0; ++ ++ err = sd_switch(mci_dev, SD_SWITCH_SWITCH, 0, 1, (uint8_t*)switch_status); ++ if (err) { ++ pr_debug("Switching SD transfer frequency failed: %d\n", err); ++ return err; ++ } ++ ++ if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) ++ mci->card_caps |= MMC_MODE_HS; ++ ++ return 0; ++} ++ ++/** ++ * Setup host's interface bus width and transfer frequency ++ * @param mci_dev MCI instance ++ */ ++static void mci_set_ios(struct device_d *mci_dev) ++{ ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ ++ host->set_ios(host, mci_dev, host->bus_width, host->clock); ++} ++ ++/** ++ * Setup host's interface transfer frequency ++ * @param mci_dev MCI instance ++ * @param clock New clock in Hz to set ++ */ ++static void mci_set_clock(struct device_d *mci_dev, unsigned clock) ++{ ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ ++ /* check against any given limits */ ++ if (clock > host->f_max) ++ clock = host->f_max; ++ ++ if (clock < host->f_min) ++ clock = host->f_min; ++ ++ host->clock = clock; /* the new target frequency */ ++ mci_set_ios(mci_dev); ++} ++ ++/** ++ * Setup host's interface bus width ++ * @param mci_dev MCI instance ++ * @param width New interface bit width (1, 4 or 8) ++ */ ++static void mci_set_bus_width(struct device_d *mci_dev, unsigned width) ++{ ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ ++ host->bus_width = width; /* the new target bus width */ ++ mci_set_ios(mci_dev); ++} ++ ++/** ++ * Extract card's version from its CSD ++ * @param mci_dev MCI instance ++ * @return 0 on success ++ */ ++static void mci_detect_version_from_csd(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ int version; ++ ++ if (mci->version == MMC_VERSION_UNKNOWN) { ++ /* the version is coded in the bits 127:126 (left aligned) */ ++ version = (mci->csd[0] >> 26) & 0xf; /* FIXME why other width? */ ++ ++ switch (version) { ++ case 0: ++ printf("Detecting a 1.2 revision card\n"); ++ mci->version = MMC_VERSION_1_2; ++ break; ++ case 1: ++ printf("Detecting a 1.4 revision card\n"); ++ mci->version = MMC_VERSION_1_4; ++ break; ++ case 2: ++ printf("Detecting a 2.2 revision card\n"); ++ mci->version = MMC_VERSION_2_2; ++ break; ++ case 3: ++ printf("Detecting a 3.0 revision card\n"); ++ mci->version = MMC_VERSION_3; ++ break; ++ case 4: ++ printf("Detecting a 4.0 revision card\n"); ++ mci->version = MMC_VERSION_4; ++ break; ++ default: ++ printf("Unknow revision. Falling back to a 1.2 revision card\n"); ++ mci->version = MMC_VERSION_1_2; ++ break; ++ } ++ } ++} ++ ++/** ++ * meaning of the encoded 'unit' bits in the CSD's field 'TRAN_SPEED' ++ * (divided by 10 to be nice to platforms without floating point) ++ */ ++static const unsigned tran_speed_unit[] = { ++ [0] = 10000, /* 100 kbit/s */ ++ [1] = 100000, /* 1 Mbit/s */ ++ [2] = 1000000, /* 10 Mbit/s */ ++ [3] = 10000000, /* 100 Mbit/s */ ++ /* [4]...[7] are reserved */ ++}; ++ ++/** ++ * meaning of the 'time' bits in the CSD's field 'TRAN_SPEED' ++ * (multiplied by 10 to be nice to platforms without floating point) ++ */ ++static const unsigned char tran_speed_time[] = { ++ 0, /* reserved */ ++ 10, /* 1.0 ns */ ++ 12, /* 1.2 ns */ ++ 13, ++ 15, ++ 20, ++ 25, ++ 30, ++ 35, ++ 40, ++ 45, ++ 50, ++ 55, ++ 60, ++ 70, /* 7.0 ns */ ++ 80, /* 8.0 ns */ ++}; ++ ++/** ++ * Extract max. transfer speed from the CSD ++ * @param mci_dev MCI instance ++ * ++ * Encoded in bit 103:96 (103: reserved, 102:99: time, 98:96 unit) ++ */ ++static void mci_extract_max_tran_speed_from_csd(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ unsigned unit, time; ++ ++ unit = tran_speed_unit[(mci->csd[0] & 0x7)]; ++ time = tran_speed_time[((mci->csd[0] >> 3) & 0xf)]; ++ if ((unit == 0) || (time == 0)) { ++ pr_warning("Unsupported 'TRAN_SPEED' unit/time value." ++ " Can't calculate card's max. transfer speed\n"); ++ return; ++ } ++ ++ mci->tran_speed = time * unit; ++ pr_debug("Transfer speed: %u\n", mci->tran_speed); ++} ++ ++/** ++ * Extract max read and write block length from the CSD ++ * @param mci_dev MCI instance ++ * ++ * Encoded in bit 83:80 (read) and 25:22 (write) ++ */ ++static void mci_extract_block_lengths_from_csd(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ ++ mci->read_bl_len = 1 << ((mci->csd[1] >> 16) & 0xf); ++ ++ if (IS_SD(mci)) ++ mci->write_bl_len = mci->read_bl_len; /* FIXME why? */ ++ else ++ mci->write_bl_len = 1 << ((mci->csd[3] >> 22) & 0xf); ++ ++ pr_debug("Max. block length are: Write=%u, Read=%u Bytes\n", ++ mci->read_bl_len, mci->write_bl_len); ++} ++ ++/** ++ * Extract card's capacitiy from the CSD ++ * @param mci_dev MCI instance ++ */ ++static void mci_extract_card_capacity_from_csd(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ uint64_t csize, cmult; ++ ++ if (mci->high_capacity) { ++ csize = (mci->csd[1] & 0x3f) << 16 | (mci->csd[2] & 0xffff0000) >> 16; ++ cmult = 8; ++ } else { ++ csize = (mci->csd[1] & 0x3ff) << 2 | (mci->csd[2] & 0xc0000000) >> 30; ++ cmult = (mci->csd[2] & 0x00038000) >> 15; ++ } ++ ++ mci->capacity = (csize + 1) << (cmult + 2); ++ mci->capacity *= mci->read_bl_len; ++ pr_debug("Capacity: %u MiB\n", (unsigned)mci->capacity >> 20); ++} ++ ++/** ++ * Scan the given host interfaces and detect connected MMC/SD cards ++ * @param mci_dev MCI instance ++ * @return 0 on success, negative value else ++ */ ++static int mci_startup(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ struct mci_cmd cmd; ++ int err; ++ ++ pr_debug("Put the Card in Identify Mode\n"); ++ ++ /* Put the Card in Identify Mode */ ++ mci_setup_cmd(&cmd, MMC_CMD_ALL_SEND_CID, 0, MMC_RSP_R2); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Can't bring card into identify mode: %d\n", err); ++ return err; ++ } ++ ++ memcpy(mci->cid, cmd.response, 16); ++ ++ pr_debug("Card's identification data is: %08X-%08X-%08X-%08X\n", ++ mci->cid[0], mci->cid[1], mci->cid[2], mci->cid[3]); ++ ++ /* ++ * For MMC cards, set the Relative Address. ++ * For SD cards, get the Relatvie Address. ++ * This also puts the cards into Standby State ++ */ ++ pr_debug("Get/Set relative address\n"); ++ mci_setup_cmd(&cmd, SD_CMD_SEND_RELATIVE_ADDR, mci->rca << 16, MMC_RSP_R6); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Get/Set relative address failed: %d\n", err); ++ return err; ++ } ++ ++ if (IS_SD(mci)) ++ mci->rca = (cmd.response[0] >> 16) & 0xffff; ++ ++ pr_debug("Get card's specific data\n"); ++ /* Get the Card-Specific Data */ ++ mci_setup_cmd(&cmd, MMC_CMD_SEND_CSD, mci->rca << 16, MMC_RSP_R2); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Getting card's specific data failed: %d\n", err); ++ return err; ++ } ++ ++ /* CSD is of 128 bit */ ++ memcpy(mci->csd, cmd.response, 16); ++ ++ pr_debug("Card's specific data is: %08X-%08X-%08X-%08X\n", ++ mci->csd[0], mci->csd[1], mci->csd[2], mci->csd[3]); ++ ++ mci_detect_version_from_csd(mci_dev); ++ mci_extract_max_tran_speed_from_csd(mci_dev); ++ mci_extract_block_lengths_from_csd(mci_dev); ++ mci_extract_card_capacity_from_csd(mci_dev); ++ ++ /* sanitiy? */ ++ if (mci->read_bl_len > 512) { ++ mci->read_bl_len = 512; ++ pr_warning("Limiting max. read block size down to %u\n", ++ mci->read_bl_len); ++ } ++ ++ if (mci->write_bl_len > 512) { ++ mci->write_bl_len = 512; ++ pr_warning("Limiting max. write block size down to %u\n", ++ mci->read_bl_len); ++ } ++ pr_debug("Read block length: %u, Write block length: %u\n", ++ mci->read_bl_len, mci->write_bl_len); ++ ++ pr_debug("Select the card, and put it into Transfer Mode\n"); ++ /* Select the card, and put it into Transfer Mode */ ++ mci_setup_cmd(&cmd, MMC_CMD_SELECT_CARD, mci->rca << 16, MMC_RSP_R1b); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Putting in transfer mode failed: %d\n", err); ++ return err; ++ } ++ ++ if (IS_SD(mci)) ++ err = sd_change_freq(mci_dev); ++ else ++ err = mmc_change_freq(mci_dev); ++ ++ if (err) ++ return err; ++ ++ /* Restrict card's capabilities by what the host can do */ ++ mci->card_caps &= host->host_caps; ++ ++ if (IS_SD(mci)) { ++ if (mci->card_caps & MMC_MODE_4BIT) { ++ pr_debug("Prepare for bus width change\n"); ++ mci_setup_cmd(&cmd, MMC_CMD_APP_CMD, mci->rca << 16, MMC_RSP_R1); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Preparing SD for bus width change failed: %d\n", err); ++ return err; ++ } ++ ++ pr_debug("Set SD bus width to 4 bit\n"); ++ mci_setup_cmd(&cmd, SD_CMD_APP_SET_BUS_WIDTH, 2, MMC_RSP_R1); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Changing SD bus width failed: %d\n", err); ++ /* TODO continue with 1 bit? */ ++ return err; ++ } ++ mci_set_bus_width(mci_dev, 4); ++ } ++ /* if possible, speed up the transfer */ ++ if (mci->card_caps & MMC_MODE_HS) ++ mci_set_clock(mci_dev, 50000000); ++ else ++ mci_set_clock(mci_dev, 25000000); ++ } else { ++ if (mci->card_caps & MMC_MODE_4BIT) { ++ pr_debug("Set MMC bus width to 4 bit\n"); ++ /* Set the card to use 4 bit*/ ++ err = mci_switch(mci_dev, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_4); ++ if (err) { ++ pr_debug("Changing MMC bus width failed: %d\n", err); ++ return err; ++ } ++ mci_set_bus_width(mci_dev, 4); ++ } else if (mci->card_caps & MMC_MODE_8BIT) { ++ pr_debug("Set MMC bus width to 8 bit\n"); ++ /* Set the card to use 8 bit*/ ++ err = mci_switch(mci_dev, EXT_CSD_CMD_SET_NORMAL, ++ EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8); ++ if (err) { ++ pr_debug("Changing MMC bus width failed: %d\n", err); ++ return err; ++ } ++ mci_set_bus_width(mci_dev, 8); ++ } ++ /* if possible, speed up the transfer */ ++ if (mci->card_caps & MMC_MODE_HS) { ++ if (mci->card_caps & MMC_MODE_HS_52MHz) ++ mci_set_clock(mci_dev, 52000000); ++ else ++ mci_set_clock(mci_dev, 26000000); ++ } else ++ mci_set_clock(mci_dev, 20000000); ++ } ++ ++ /* we setup the blocklength only one times for all accesses to this media */ ++ err = mci_set_blocklen(mci_dev, mci->read_bl_len); ++ ++ return err; ++} ++ ++/** ++ * Detect a SD 2.0 card and enable its features ++ * @param mci_dev MCI instance ++ * @return Transfer status (0 on success) ++ * ++ * By issuing the CMD8 command SDHC/SDXC cards realize that the host supports ++ * the Physical Layer Version 2.00 or later and the card can enable ++ * corresponding new functions. ++ * ++ * If this CMD8 command will end with a timeout it is a MultiMediaCard only. ++ */ ++static int sd_send_if_cond(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ struct mci_cmd cmd; ++ int err; ++ ++ mci_setup_cmd(&cmd, SD_CMD_SEND_IF_COND, ++ /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ ++ ((host->voltages & 0x00ff8000) != 0) << 8 | 0xaa, ++ MMC_RSP_R7); ++ err = mci_send_cmd(mci_dev, &cmd, NULL); ++ if (err) { ++ pr_debug("Query interface conditions failed: %d\n", err); ++ return err; ++ } ++ ++ if ((cmd.response[0] & 0xff) != 0xaa) { ++ pr_debug("Card cannot work with hosts supply voltages\n"); ++ return -EINVAL; ++ } else { ++ pr_debug("SD Card Rev. 2.00 or later detected\n"); ++ mci->version = SD_VERSION_2; ++ } ++ ++ return 0; ++} ++ ++/* ------------------ attach to the ATA API --------------------------- */ ++ ++/** ++ * Write a chunk of sectors to media ++ * @param disk_dev Disk device instance ++ * @param sector_start Sector's number to start write to ++ * @param sector_count Sectors to write ++ * @param buffer Buffer to write from ++ * @return 0 on success, anything else on failure ++ * ++ * This routine expects the buffer has the correct size to read all data! ++ */ ++static int mci_sd_write(struct device_d *disk_dev, uint64_t sector_start, ++ unsigned sector_count, const void *buffer) ++{ ++ struct ata_interface *intf = disk_dev->platform_data; ++ struct device_d *mci_dev = intf->priv; ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ int rc; ++ ++ pr_debug("%s called: Write %u block(s), starting at %lu", ++ __func__, sector_count, (unsigned)sector_count); ++ ++ if (mci->write_bl_len != 512) { ++ pr_warning("MMC/SD block size is not 512 bytes (its %u bytes instead)\n", ++ mci->read_bl_len); ++ return -EINVAL; ++ } ++ ++ while (sector_count) { ++ /* size of the block number field in the MMC/SD command is 32 bit only */ ++ if (sector_start > MAX_BUFFER_NUMBER) { ++ pr_err("Cannot handle block number %llu. Too large!\n", ++ sector_start); ++ return -EINVAL; ++ } ++ rc = mci_block_write(mci_dev, buffer, sector_start); ++ if (rc != 0) { ++ pr_err("Writing block %u failed with %d\n", (unsigned)sector_start, rc); ++ return rc; ++ } ++ sector_count--; ++ buffer += mci->write_bl_len; ++ sector_start++; ++ } ++ ++ return 0; ++} ++ ++/** ++ * Read a chunk of sectors from media ++ * @param disk_dev Disk device instance ++ * @param sector_start Sector's number to start read from ++ * @param sector_count Sectors to read ++ * @param buffer Buffer to read into ++ * @return 0 on success, anything else on failure ++ * ++ * This routine expects the buffer has the correct size to store all data! ++ */ ++static int mci_sd_read(struct device_d *disk_dev, uint64_t sector_start, ++ unsigned sector_count, void *buffer) ++{ ++ struct ata_interface *intf = disk_dev->platform_data; ++ struct device_d *mci_dev = intf->priv; ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ int rc; ++ ++ pr_debug("%s called: Read %u block(s), starting at %lu to %08X\n", ++ __func__, sector_count, (unsigned)sector_start, buffer); ++ ++ if (mci->read_bl_len != 512) { ++ pr_warning("MMC/SD block size is not 512 bytes (its %u bytes instead)\n", ++ mci->read_bl_len); ++ return -EINVAL; ++ } ++ ++ while (sector_count) { ++ int now = min(sector_count, 32); ++ if (sector_start > MAX_BUFFER_NUMBER) { ++ pr_err("Cannot handle block number %lu. Too large!\n", ++ (unsigned)sector_start); ++ return -EINVAL; ++ } ++ rc = mci_read_block(mci_dev, buffer, (unsigned)sector_start, now); ++ if (rc != 0) { ++ pr_err("Reading block %lu failed with %d\n", (unsigned)sector_start, rc); ++ return rc; ++ } ++ sector_count -= now; ++ buffer += mci->read_bl_len * now; ++ sector_start += now; ++ } ++ ++ return 0; ++} ++ ++/* ------------------ attach to the device API --------------------------- */ ++ ++#ifdef CONFIG_MCI_INFO ++/** ++ * Extract the Manufacturer ID from the CID ++ * @param mci Instance data ++ * ++ * The 'MID' is encoded in bit 127:120 in the CID ++ */ ++static unsigned extract_mid(struct mci *mci) ++{ ++ return mci->cid[0] >> 24; ++} ++ ++/** ++ * Extract the OEM/Application ID from the CID ++ * @param mci Instance data ++ * ++ * The 'OID' is encoded in bit 119:104 in the CID ++ */ ++static unsigned extract_oid(struct mci *mci) ++{ ++ return (mci->cid[0] >> 8) & 0xffff; ++} ++ ++/** ++ * Extract the product revision from the CID ++ * @param mci Instance data ++ * ++ * The 'PRV' is encoded in bit 63:56 in the CID ++ */ ++static unsigned extract_prv(struct mci *mci) ++{ ++ return mci->cid[2] >> 24; ++} ++ ++/** ++ * Extract the product serial number from the CID ++ * @param mci Instance data ++ * ++ * The 'PSN' is encoded in bit 55:24 in the CID ++ */ ++static unsigned extract_psn(struct mci *mci) ++{ ++ return (mci->cid[2] << 8) | (mci->cid[3] >> 24); ++} ++ ++/** ++ * Extract the month of the manufacturing date from the CID ++ * @param mci Instance data ++ * ++ * The 'MTD' is encoded in bit 19:8 in the CID, month in 11:8 ++ */ ++static unsigned extract_mtd_month(struct mci *mci) ++{ ++ return (mci->cid[3] >> 8) & 0xf; ++} ++ ++/** ++ * Extract the year of the manufacturing date from the CID ++ * @param mci Instance data ++ * ++ * The 'MTD' is encoded in bit 19:8 in the CID, year in 19:12 ++ * An encoded 0 means the year 2000 ++ */ ++static unsigned extract_mtd_year(struct mci *mci) ++{ ++ return ((mci->cid[3] >> 12) & 0xff) + 2000U; ++} ++ ++/** ++ * Output some valuable information when the user runs 'devinfo' on an MCI device ++ * @param mci_dev MCI device instance ++ */ ++static void mci_info(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ ++ if (mci->ready_for_use == 0) { ++ printf(" No information available:\n MCI card not probed yet\n"); ++ return; ++ } ++ ++ printf(" Card:\n"); ++ if (mci->version < SD_VERSION_SD) { ++ printf(" Attached is a MultiMediaCard (Version: %u.%u)\n", ++ (mci->version >> 4) & 0xf, mci->version & 0xf); ++ } else { ++ printf(" Attached is an SD Card (Version: %u.%u)\n", ++ (mci->version >> 4) & 0xf, mci->version & 0xf); ++ } ++ printf(" Capacity: %u MiB\n", (unsigned)(mci->capacity >> 20)); ++ ++ if (mci->high_capacity) ++ printf(" High capacity card\n"); ++ printf(" CID: %08X-%08X-%08X-%08X\n", mci->cid[0], mci->cid[1], ++ mci->cid[2], mci->cid[3]); ++ printf(" CSD: %08X-%08X-%08X-%08X\n", mci->csd[0], mci->csd[1], ++ mci->csd[2], mci->csd[3]); ++ printf(" Max. transfer speed: %u Hz\n", mci->tran_speed); ++ printf(" Manufacturer ID: %02X\n", extract_mid(mci)); ++ printf(" OEM/Application ID: %04X\n", extract_oid(mci)); ++ printf(" Product name: '%c%c%c%c%c'\n", mci->cid[0] & 0xff, ++ (mci->cid[1] >> 24), (mci->cid[1] >> 16) & 0xff, ++ (mci->cid[1] >> 8) & 0xff, mci->cid[1] & 0xff); ++ printf(" Product revision: %u.%u\n", extract_prv(mci) >> 4, ++ extract_prv(mci) & 0xf); ++ printf(" Serial no: %0u\n", extract_psn(mci)); ++ printf(" Manufacturing date: %u.%u\n", extract_mtd_month(mci), ++ extract_mtd_year(mci)); ++} ++#endif ++ ++/** ++ * Check if the MCI card is already probed ++ * @param mci_dev MCI device instance ++ * @return 0 when not probed yet, -EPERM if already probed ++ * ++ * @a barebox cannot really cope with hot plugging. So, probing an attached ++ * MCI card is a one time only job. If its already done, there is no way to ++ * return. ++ */ ++static int mci_check_if_already_initialized(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ ++ if (mci->ready_for_use != 0) ++ return -EPERM; ++ ++ return 0; ++} ++ ++/** ++ * Probe an MCI card at the given host interface ++ * @param mci_dev MCI device instance ++ * @return 0 on success, negative values else ++ */ ++static int mci_card_probe(struct device_d *mci_dev) ++{ ++ struct mci *mci = GET_MCI_DATA(mci_dev); ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ struct device_d *disk_dev; ++ struct ata_interface *p; ++ int rc; ++ ++ /* start with a host interface reset */ ++ rc = (host->init)(host, mci_dev); ++ if (rc) { ++ pr_err("Cannot reset the SD/MMC interface\n"); ++ return rc; ++ } ++ ++ mci_set_bus_width(mci_dev, 1); ++ mci_set_clock(mci_dev, 1); /* set the lowest available clock */ ++ ++ /* reset the card */ ++ rc = mci_go_idle(mci_dev); ++ if (rc) { ++ pr_warning("Cannot reset the SD/MMC card\n"); ++ goto on_error; ++ } ++ ++ /* Check if this card can handle the "SD Card Physical Layer Specification 2.0" */ ++ rc = sd_send_if_cond(mci_dev); ++ rc = sd_send_op_cond(mci_dev); ++ if (rc && rc == -ETIMEDOUT) { ++ /* If the command timed out, we check for an MMC card */ ++ pr_debug("Card seems to be a MultiMediaCard\n"); ++ rc = mmc_send_op_cond(mci_dev); ++ } ++ ++ if (rc) ++ goto on_error; ++ ++ rc = mci_startup(mci_dev); ++ if (rc) { ++ printf("Card's startup fails with %d\n", rc); ++ goto on_error; ++ } ++ ++ pr_debug("Card is up and running now, registering as a disk\n"); ++ mci->ready_for_use = 1; /* TODO now or later? */ ++ ++ /* ++ * An MMC/SD card acts like an ordinary disk. ++ * So, re-use the disk driver to gain access to this media ++ */ ++ disk_dev = xzalloc(sizeof(struct device_d) + sizeof(struct ata_interface)); ++ p = (struct ata_interface*)&disk_dev[1]; ++ ++ p->write = mci_sd_write; ++ p->read = mci_sd_read; ++ p->priv = mci_dev; ++ ++ strcpy(disk_dev->name, "disk"); ++ disk_dev->size = mci->capacity; ++ disk_dev->map_base = 0; ++ disk_dev->platform_data = p; ++ ++ register_device(disk_dev); ++ ++ pr_debug("SD Card successfully added\n"); ++ ++on_error: ++ if (rc != 0) { ++ host->clock = 0; /* disable the MCI clock */ ++ mci_set_ios(mci_dev); ++ } ++ ++ return rc; ++} ++ ++/** ++ * Trigger probing of an attached MCI card ++ * @param mci_dev MCI device instance ++ * @param param FIXME ++ * @param val "0" does nothing, a "1" will probe for a MCI card ++ * @return 0 on success ++ */ ++static int mci_set_probe(struct device_d *mci_dev, struct param_d *param, ++ const char *val) ++{ ++ int rc, probe; ++ ++ rc = mci_check_if_already_initialized(mci_dev); ++ if (rc != 0) ++ return rc; ++ ++ probe = simple_strtoul(val, NULL, 0); ++ if (probe != 0) { ++ rc = mci_card_probe(mci_dev); ++ if (rc != 0) ++ return rc; ++ } ++ ++ return dev_param_set_generic(mci_dev, param, val); ++} ++ ++/** ++ * Add parameter to the MCI device on demand ++ * @param mci_dev MCI device instance ++ * @return 0 on success ++ * ++ * This parameter is only available (or usefull) if MCI card probing is delayed ++ */ ++static int add_mci_parameter(struct device_d *mci_dev) ++{ ++ int rc; ++ ++ /* provide a 'probing right now' parameter for the user */ ++ rc = dev_add_param(mci_dev, "probe", mci_set_probe, NULL, 0); ++ if (rc != 0) ++ return rc; ++ ++ return dev_set_param(mci_dev, "probe", "0"); ++} ++ ++/** ++ * Prepare for MCI card's usage ++ * @param mci_dev MCI device instance ++ * @return 0 on success ++ * ++ * This routine will probe an attached MCI card immediately or provide ++ * a parameter to do it later on user's demand. ++ */ ++static int mci_probe(struct device_d *mci_dev) ++{ ++ struct mci *mci; ++ int rc; ++ ++ mci = xzalloc(sizeof(struct mci)); ++ mci_dev->priv = mci; ++ ++#ifdef CONFIG_MCI_STARTUP ++ /* if enabled, probe the attached card immediately */ ++ rc = mci_card_probe(mci_dev); ++ if (rc == -ENODEV) { ++ /* ++ * If it fails, add the 'probe' parameter to give the user ++ * a chance to insert a card and try again. Note: This may fail ++ * systems that rely on the MCI card for startup (for the ++ * persistant environment for example) ++ */ ++ rc = add_mci_parameter(mci_dev); ++ if (rc != 0) { ++ pr_err("Failed to add 'probe' parameter to the MCI device\n"); ++ goto on_error; ++ } ++ } ++#endif ++ ++#ifndef CONFIG_MCI_STARTUP ++ /* add params on demand */ ++ rc = add_mci_parameter(mci_dev); ++ if (rc != 0) { ++ pr_err("Failed to add 'probe' parameter to the MCI device\n"); ++ goto on_error; ++ } ++#endif ++ ++ return rc; ++ ++on_error: ++ free(mci); ++ return rc; ++} ++ ++static struct driver_d mci_driver = { ++ .name = "mci", ++ .probe = mci_probe, ++ .info = mci_info, ++}; ++ ++static int mci_init(void) ++{ ++ sector_buf = memalign(32, 512); ++ if (!sector_buf) ++ return -ENOMEM; ++ ++ return register_driver(&mci_driver); ++} ++ ++device_initcall(mci_init); ++ ++/** ++ * Create a new mci device (for convenience) ++ * @param host mci_host for this MCI device ++ * @return 0 on success ++ */ ++int mci_register(struct mci_host *host) ++{ ++ struct device_d *mci_dev; ++ ++ mci_dev = xzalloc(sizeof(struct device_d)); ++ ++ strcpy(mci_dev->name, mci_driver.name); ++ mci_dev->platform_data = (void*)host; ++ ++ return register_device(mci_dev); ++} +diff --git a/drivers/mci/s3c.c b/drivers/mci/s3c.c +new file mode 100644 +index 0000000..9810683 +--- /dev/null ++++ b/drivers/mci/s3c.c +@@ -0,0 +1,817 @@ ++/* ++ * Copyright (C) 2010 Juergen Beisert <juergen@kreuzholzen.de> ++ * ++ * This code is partially based on u-boot code: ++ * ++ * This code is based on various Linux and u-boot sources: ++ * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de> ++ * Copyright (C) 2008 Simtec Electronics <ben-linux@fluff.org> ++ * (C) Copyright 2006 by OpenMoko, Inc. ++ * Author: Harald Welte <laforge@openmoko.org> ++ * based on u-boot pxa MMC driver and linux/drivers/mmc/s3c2410mci.c ++ * (C) 2005-2005 Thomas Kleffel ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/** ++ * @file ++ * @brief MCI card host interface for S3C2440 CPU ++ */ ++ ++/* #define DEBUG */ ++ ++#include <common.h> ++#include <init.h> ++#include <mci.h> ++#include <errno.h> ++#include <clock.h> ++#include <asm/io.h> ++#include <mach/mci.h> ++#include <mach/s3c24xx-generic.h> ++#include <mach/s3c24x0-iomap.h> ++ ++#define SDICON 0x0 ++# define SDICON_SDRESET (1 << 8) ++# define SDICON_MMCCLOCK (1 << 5) /* this is a clock type SD or MMC style WTF? */ ++# define SDICON_BYTEORDER (1 << 4) ++# define SDICON_SDIOIRQ (1 << 3) ++# define SDICON_RWAITEN (1 << 2) ++# define SDICON_FIFORESET (1 << 1) /* reserved bit on 2440 ????? */ ++# define SDICON_CLKEN (1 << 0) /* enable/disable external clock */ ++ ++#define SDIPRE 0x4 ++ ++#define SDICMDARG 0x8 ++ ++#define SDICMDCON 0xc ++# define SDICMDCON_ABORT (1 << 12) ++# define SDICMDCON_WITHDATA (1 << 11) ++# define SDICMDCON_LONGRSP (1 << 10) ++# define SDICMDCON_WAITRSP (1 << 9) ++# define SDICMDCON_CMDSTART (1 << 8) ++# define SDICMDCON_SENDERHOST (1 << 6) ++# define SDICMDCON_INDEX (0x3f) ++ ++#define SDICMDSTAT 0x10 ++# define SDICMDSTAT_CRCFAIL (1 << 12) ++# define SDICMDSTAT_CMDSENT (1 << 11) ++# define SDICMDSTAT_CMDTIMEOUT (1 << 10) ++# define SDICMDSTAT_RSPFIN (1 << 9) ++# define SDICMDSTAT_XFERING (1 << 8) ++# define SDICMDSTAT_INDEX (0xff) ++ ++#define SDIRSP0 0x14 ++#define SDIRSP1 0x18 ++#define SDIRSP2 0x1C ++#define SDIRSP3 0x20 ++ ++#define SDITIMER 0x24 ++#define SDIBSIZE 0x28 ++ ++#define SDIDCON 0x2c ++# define SDIDCON_DS_BYTE (0 << 22) ++# define SDIDCON_DS_HALFWORD (1 << 22) ++# define SDIDCON_DS_WORD (2 << 22) ++# define SDIDCON_IRQPERIOD (1 << 21) ++# define SDIDCON_TXAFTERRESP (1 << 20) ++# define SDIDCON_RXAFTERCMD (1 << 19) ++# define SDIDCON_BUSYAFTERCMD (1 << 18) ++# define SDIDCON_BLOCKMODE (1 << 17) ++# define SDIDCON_WIDEBUS (1 << 16) ++# define SDIDCON_DMAEN (1 << 15) ++# define SDIDCON_STOP (0 << 14) ++# define SDIDCON_DATSTART (1 << 14) ++# define SDIDCON_DATMODE (3 << 12) ++# define SDIDCON_BLKNUM (0xfff) ++# define SDIDCON_XFER_READY (0 << 12) ++# define SDIDCON_XFER_CHKSTART (1 << 12) ++# define SDIDCON_XFER_RXSTART (2 << 12) ++# define SDIDCON_XFER_TXSTART (3 << 12) ++ ++#define SDIDCNT 0x30 ++# define SDIDCNT_BLKNUM_SHIFT 12 ++ ++#define SDIDSTA 0x34 ++# define SDIDSTA_RDYWAITREQ (1 << 10) ++# define SDIDSTA_SDIOIRQDETECT (1 << 9) ++# define SDIDSTA_FIFOFAIL (1 << 8) /* reserved on 2440 */ ++# define SDIDSTA_CRCFAIL (1 << 7) ++# define SDIDSTA_RXCRCFAIL (1 << 6) ++# define SDIDSTA_DATATIMEOUT (1 << 5) ++# define SDIDSTA_XFERFINISH (1 << 4) ++# define SDIDSTA_BUSYFINISH (1 << 3) ++# define SDIDSTA_SBITERR (1 << 2) /* reserved on 2410a/2440 */ ++# define SDIDSTA_TXDATAON (1 << 1) ++# define SDIDSTA_RXDATAON (1 << 0) ++ ++#define SDIFSTA 0x38 ++# define SDIFSTA_FIFORESET (1<<16) ++# define SDIFSTA_FIFOFAIL (3<<14) /* 3 is correct (2 bits) */ ++# define SDIFSTA_TFDET (1<<13) ++# define SDIFSTA_RFDET (1<<12) ++# define SDIFSTA_TFHALF (1<<11) ++# define SDIFSTA_TFEMPTY (1<<10) ++# define SDIFSTA_RFLAST (1<<9) ++# define SDIFSTA_RFFULL (1<<8) ++# define SDIFSTA_RFHALF (1<<7) ++# define SDIFSTA_COUNTMASK (0x7f) ++ ++#define SDIIMSK 0x3C ++# define SDIIMSK_RESPONSECRC (1<<17) ++# define SDIIMSK_CMDSENT (1<<16) ++# define SDIIMSK_CMDTIMEOUT (1<<15) ++# define SDIIMSK_RESPONSEND (1<<14) ++# define SDIIMSK_READWAIT (1<<13) ++# define SDIIMSK_SDIOIRQ (1<<12) ++# define SDIIMSK_FIFOFAIL (1<<11) ++# define SDIIMSK_CRCSTATUS (1<<10) ++# define SDIIMSK_DATACRC (1<<9) ++# define SDIIMSK_DATATIMEOUT (1<<8) ++# define SDIIMSK_DATAFINISH (1<<7) ++# define SDIIMSK_BUSYFINISH (1<<6) ++# define SDIIMSK_SBITERR (1<<5) /* reserved 2440/2410a */ ++# define SDIIMSK_TXFIFOHALF (1<<4) ++# define SDIIMSK_TXFIFOEMPTY (1<<3) ++# define SDIIMSK_RXFIFOLAST (1<<2) ++# define SDIIMSK_RXFIFOFULL (1<<1) ++# define SDIIMSK_RXFIFOHALF (1<<0) ++ ++#define SDIDATA 0x40 ++ ++struct s3c_mci_host { ++ int bus_width:2; /* 0 = 1 bit, 1 = 4 bit, 2 = 8 bit */ ++ unsigned clock; /* current clock in Hz */ ++ unsigned data_size; /* data transfer in bytes */ ++}; ++ ++/* ++ * There is only one host MCI hardware instance available. ++ * It makes no sense to dynamically allocate this data ++ */ ++static struct s3c_mci_host host_data; ++ ++/** ++ * Finish a request ++ * @param hw_dev Host interface instance ++ * ++ * Just a little bit paranoia. ++ */ ++static void s3c_finish_request(struct device_d *hw_dev) ++{ ++ /* TODO ensure the engines are stopped */ ++} ++ ++/* TODO GPIO feature is required for this architecture */ ++static unsigned gpio_get_value(unsigned val) ++{ ++ return 0; ++} ++ ++/** ++ * Detect if a card is plugged in ++ * @param hw_dev Host interface instance ++ * @return 0 if a card is plugged in ++ * ++ * Note: If there is no GPIO registered to detect if a card is present, we ++ * assume a card _is_ present. ++ */ ++static int s3c_mci_card_present(struct device_d *hw_dev) ++{ ++ struct s3c_mci_platform_data *pd = GET_HOST_PDATA(hw_dev); ++ int ret; ++ ++ if (pd->gpio_detect == 0) ++ return 0; /* assume the card is present */ ++ ++ ret = gpio_get_value(pd->gpio_detect) ? 0 : 1; ++ return ret ^ pd->detect_invert; ++} ++ ++/** ++ * Setup a new clock frequency on this MCI bus ++ * @param hw_dev Host interface instance ++ * @param nc New clock value in Hz (can be 0) ++ * @return New clock value (may differ from 'nc') ++ */ ++static unsigned s3c_setup_clock_speed(struct device_d *hw_dev, unsigned nc) ++{ ++ unsigned clock; ++ uint32_t mci_psc; ++ ++ if (nc == 0) ++ return 0; ++ ++ clock = s3c24xx_get_pclk(); ++ /* Calculate the required prescaler value to get the requested frequency */ ++ mci_psc = (clock + (nc >> 2)) / nc; ++ ++ if (mci_psc > 256) { ++ mci_psc = 256; ++ pr_warning("SD/MMC clock might be too high!\n"); ++ } ++ ++ writel(mci_psc - 1, hw_dev->map_base + SDIPRE); ++ ++ return clock / mci_psc; ++} ++ ++/** ++ * Reset the MCI engine (the hard way) ++ * @param hw_dev Host interface instance ++ * ++ * This will reset everything in all registers of this unit! ++ */ ++static void s3c_mci_reset(struct device_d *hw_dev) ++{ ++ /* reset the hardware */ ++ writel(SDICON_SDRESET, hw_dev->map_base + SDICON); ++ /* wait until reset it finished */ ++ while (readl(hw_dev->map_base + SDICON) & SDICON_SDRESET) ++ ; ++} ++ ++/** ++ * Initialize hard and software ++ * @param hw_dev Host interface instance ++ * @param mci_dev MCI device instance (might be NULL) ++ */ ++static int s3c_mci_initialize(struct device_d *hw_dev, struct device_d *mci_dev) ++{ ++ struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev); ++ ++ s3c_mci_reset(hw_dev); ++ ++ /* restore last settings */ ++ host_data->clock = s3c_setup_clock_speed(hw_dev, host_data->clock); ++ writel(0x007FFFFF, hw_dev->map_base + SDITIMER); ++ writel(SDICON_MMCCLOCK, hw_dev->map_base + SDICON); ++ writel(512, hw_dev->map_base + SDIBSIZE); ++ ++ return 0; ++} ++ ++/** ++ * Prepare engine's bits for the next command transfer ++ * @param cmd_flags MCI's command flags ++ * @param data_flags MCI's data flags ++ * @return Register bits for this transfer ++ */ ++static uint32_t s3c_prepare_command_setup(unsigned cmd_flags, unsigned data_flags) ++{ ++ uint32_t reg; ++ ++ /* source (=host) */ ++ reg = SDICMDCON_SENDERHOST; ++ ++ if (cmd_flags & MMC_RSP_PRESENT) { ++ reg |= SDICMDCON_WAITRSP; ++ pr_debug("Command with response\n"); ++ } ++ if (cmd_flags & MMC_RSP_136) { ++ reg |= SDICMDCON_LONGRSP; ++ pr_debug("Command with long response\n"); ++ } ++ if (cmd_flags & MMC_RSP_CRC) ++ ; /* FIXME */ ++ if (cmd_flags & MMC_RSP_BUSY) ++ ; /* FIXME */ ++ if (cmd_flags & MMC_RSP_OPCODE) ++ ; /* FIXME */ ++ if (data_flags != 0) ++ reg |= SDICMDCON_WITHDATA; ++ ++ return reg; ++} ++ ++/** ++ * Prepare engine's bits for the next data transfer ++ * @param hw_dev Host interface device instance ++ * @param data_flags MCI's data flags ++ * @return Register bits for this transfer ++ */ ++static uint32_t s3c_prepare_data_setup(struct device_d *hw_dev, unsigned data_flags) ++{ ++ struct s3c_mci_host *host_data = (struct s3c_mci_host*)GET_HOST_DATA(hw_dev); ++ uint32_t reg = SDIDCON_BLOCKMODE; /* block mode only is supported */ ++ ++ if (host_data->bus_width == 1) ++ reg |= SDIDCON_WIDEBUS; ++ ++ /* enable any kind of data transfers on demand only */ ++ if (data_flags & MMC_DATA_WRITE) ++ reg |= SDIDCON_TXAFTERRESP | SDIDCON_XFER_TXSTART; ++ ++ if (data_flags & MMC_DATA_READ) ++ reg |= SDIDCON_RXAFTERCMD | SDIDCON_XFER_RXSTART; ++ ++ /* TODO: Support more than the 2440 CPU */ ++ reg |= SDIDCON_DS_WORD | SDIDCON_DATSTART; ++ ++ return reg; ++} ++ ++/** ++ * Terminate a current running transfer ++ * @param hw_dev Host interface device instance ++ * @return 0 on success ++ * ++ * Note: Try to stop a running transfer. This should not happen, as all ++ * transfers must complete in this driver. But who knows... ;-) ++ */ ++static int s3c_terminate_transfer(struct device_d *hw_dev) ++{ ++ unsigned stoptries = 3; ++ ++ while (readl(hw_dev->map_base + SDIDSTA) & (SDIDSTA_TXDATAON | SDIDSTA_RXDATAON)) { ++ pr_debug("Transfer still in progress.\n"); ++ ++ writel(SDIDCON_STOP, hw_dev->map_base + SDIDCON); ++ s3c_mci_initialize(hw_dev, NULL); ++ ++ if ((stoptries--) == 0) { ++ pr_warning("Cannot stop the engine!\n"); ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * Setup registers for data transfer ++ * @param hw_dev Host interface device instance ++ * @param data The data information (buffer, direction aso.) ++ * @return 0 on success ++ */ ++static int s3c_prepare_data_transfer(struct device_d *hw_dev, struct mci_data *data) ++{ ++ uint32_t reg; ++ ++ writel(data->blocksize, hw_dev->map_base + SDIBSIZE); ++ reg = s3c_prepare_data_setup(hw_dev, data->flags); ++ reg |= data->blocks & SDIDCON_BLKNUM; ++ writel(reg, hw_dev->map_base + SDIDCON); ++ writel(0x007FFFFF, hw_dev->map_base + SDITIMER); ++ ++ return 0; ++} ++ ++/** ++ * Send a command and receive the response ++ * @param hw_dev Host interface device instance ++ * @param cmd The command to handle ++ * @param data The data information (buffer, direction aso.) ++ * @return 0 on success ++ */ ++static int s3c_send_command(struct device_d *hw_dev, struct mci_cmd *cmd, ++ struct mci_data *data) ++{ ++ uint32_t reg, t1; ++ int rc; ++ ++ writel(0x007FFFFF, hw_dev->map_base + SDITIMER); ++ ++ /* setup argument */ ++ writel(cmd->cmdarg, hw_dev->map_base + SDICMDARG); ++ ++ /* setup command and transfer characteristic */ ++ reg = s3c_prepare_command_setup(cmd->resp_type, data != NULL ? data->flags : 0); ++ reg |= cmd->cmdidx & SDICMDCON_INDEX; ++ ++ /* run the command right now */ ++ writel(reg | SDICMDCON_CMDSTART, hw_dev->map_base + SDICMDCON); ++ t1 = readl(hw_dev->map_base + SDICMDSTAT); ++ /* wait until command is done */ ++ while (1) { ++ reg = readl(hw_dev->map_base + SDICMDSTAT); ++ /* done? */ ++ if (cmd->resp_type & MMC_RSP_PRESENT) { ++ if (reg & SDICMDSTAT_RSPFIN) { ++ writel(SDICMDSTAT_RSPFIN, ++ hw_dev->map_base + SDICMDSTAT); ++ rc = 0; ++ break; ++ } ++ } else { ++ if (reg & SDICMDSTAT_CMDSENT) { ++ writel(SDICMDSTAT_CMDSENT, ++ hw_dev->map_base + SDICMDSTAT); ++ rc = 0; ++ break; ++ } ++ } ++ /* timeout? */ ++ if (reg & SDICMDSTAT_CMDTIMEOUT) { ++ writel(SDICMDSTAT_CMDTIMEOUT, ++ hw_dev->map_base + SDICMDSTAT); ++ rc = -ETIMEDOUT; ++ break; ++ } ++ } ++ ++ if ((rc == 0) && (cmd->resp_type & MMC_RSP_PRESENT)) { ++ cmd->response[0] = readl(hw_dev->map_base + SDIRSP0); ++ cmd->response[1] = readl(hw_dev->map_base + SDIRSP1); ++ cmd->response[2] = readl(hw_dev->map_base + SDIRSP2); ++ cmd->response[3] = readl(hw_dev->map_base + SDIRSP3); ++ } ++ /* do not disable the clock! */ ++ return rc; ++} ++ ++/** ++ * Clear major registers prior a new transaction ++ * @param hw_dev Host interface device instance ++ * @return 0 on success ++ * ++ * FIFO clear is only necessary on 2440, but doesn't hurt on 2410 ++ */ ++static int s3c_prepare_engine(struct device_d *hw_dev) ++{ ++ int rc; ++ ++ rc = s3c_terminate_transfer(hw_dev); ++ if (rc != 0) ++ return rc; ++ ++ writel(-1, hw_dev->map_base + SDICMDSTAT); ++ writel(-1, hw_dev->map_base + SDIDSTA); ++ writel(-1, hw_dev->map_base + SDIFSTA); ++ ++ return 0; ++} ++ ++/** ++ * Handle MCI commands without data ++ * @param hw_dev Host interface device instance ++ * @param cmd The command to handle ++ * @return 0 on success ++ * ++ * This functions handles the following MCI commands: ++ * - "broadcast command (BC)" without a response ++ * - "broadcast commands with response (BCR)" ++ * - "addressed command (AC)" with response, but without data ++ */ ++static int s3c_mci_std_cmds(struct device_d *hw_dev, struct mci_cmd *cmd) ++{ ++ int rc; ++ ++ rc = s3c_prepare_engine(hw_dev); ++ if (rc != 0) ++ return 0; ++ ++ return s3c_send_command(hw_dev, cmd, NULL); ++} ++ ++/** ++ * Read one block of data from the FIFO ++ * @param hw_dev Host interface device instance ++ * @param data The data information (buffer, direction aso.) ++ * @return 0 on success ++ */ ++static int s3c_mci_read_block(struct device_d *hw_dev, struct mci_data *data) ++{ ++ uint32_t *p; ++ unsigned cnt, data_size; ++ ++#define READ_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_RXCRCFAIL | SDIDSTA_DATATIMEOUT) ++ ++ p = (uint32_t*)data->dest; ++ data_size = data->blocksize * data->blocks; ++ ++ while (data_size > 0) { ++ ++ /* serious error? */ ++ if (readl(hw_dev->map_base + SDIDSTA) & READ_REASON_TO_FAIL) { ++ pr_err("Failed while reading data\n"); ++ return -EIO; ++ } ++ ++ /* now check the FIFO status */ ++ if (readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_FIFOFAIL) { ++ pr_err("Data loss due to FIFO overflow when reading\n"); ++ return -EIO; ++ } ++ ++ /* we only want to read full words */ ++ cnt = (readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_COUNTMASK) >> 2; ++ ++ /* read one chunk of data from the FIFO */ ++ while (cnt--) { ++ *p = readl(hw_dev->map_base + SDIDATA); ++ p++; ++ if (data_size >= 4) ++ data_size -= 4; ++ else { ++ data_size = 0; ++ break; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * Write one block of data into the FIFO ++ * @param hw_dev Host interface device instance ++ * @param cmd The command to handle ++ * @param data The data information (buffer, direction aso.) ++ * @return 0 on success ++ * ++ * We must ensure data in the FIFO when the command phase changes into the ++ * data phase. To ensure this, the FIFO gets filled first, then the command. ++ */ ++static int s3c_mci_write_block(struct device_d *hw_dev, struct mci_cmd *cmd, ++ struct mci_data *data) ++{ ++ const uint32_t *p = (const uint32_t*)data->src; ++ unsigned cnt, data_size; ++ uint32_t reg; ++ ++#define WRITE_REASON_TO_FAIL (SDIDSTA_CRCFAIL | SDIDSTA_DATATIMEOUT) ++ ++ data_size = data->blocksize * data->blocks; ++ /* ++ * With high clock rates we must fill the FIFO as early as possible ++ * Its size is 16 words. We assume its empty, when this function is ++ * entered. ++ */ ++ cnt = 16; ++ while (cnt--) { ++ writel(*p, hw_dev->map_base + SDIDATA); ++ p++; ++ if (data_size >= 4) ++ data_size -= 4; ++ else { ++ data_size = 0; ++ break; ++ } ++ } ++ ++ /* data is now in place and waits for transmitt. Start the command right now */ ++ s3c_send_command(hw_dev, cmd, data); ++ ++ if ((reg = readl(hw_dev->map_base + SDIFSTA)) & SDIFSTA_FIFOFAIL) { ++ pr_err("Command fails immediatly due to FIFO underrun when writing %08X\n", ++ reg); ++ return -EIO; ++ } ++ ++ while (data_size > 0) { ++ ++ if (readl(hw_dev->map_base + SDIDSTA) & WRITE_REASON_TO_FAIL) { ++ pr_err("Failed writing data\n"); ++ return -EIO; ++ } ++ ++ /* now check the FIFO status */ ++ if ((reg = readl(hw_dev->map_base + SDIFSTA)) & SDIFSTA_FIFOFAIL) { ++ pr_err("Data loss due to FIFO underrun when writing %08X\n", ++ reg); ++ return -EIO; ++ } ++ ++ /* we only want to write full words */ ++ cnt = 16 - (((readl(hw_dev->map_base + SDIFSTA) & SDIFSTA_COUNTMASK) + 3) >> 2); ++ ++ /* fill the FIFO if it has free entries */ ++ while (cnt--) { ++ writel(*p, hw_dev->map_base + SDIDATA); ++ p++; ++ if (data_size >= 4) ++ data_size -= 4; ++ else { ++ data_size = 0; ++ break; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++/** ++ * Handle MCI commands with or without data ++ * @param hw_dev Host interface device instance ++ * @param cmd The command to handle ++ * @param data The data information (buffer, direction aso.) ++ * @return 0 on success ++*/ ++static int s3c_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd, ++ struct mci_data *data) ++{ ++ int rc; ++ ++ rc = s3c_prepare_engine(hw_dev); ++ if (rc != 0) ++ return rc; ++ ++ rc = s3c_prepare_data_transfer(hw_dev, data); ++ if (rc != 0) ++ return rc; ++ ++ if (data->flags & MMC_DATA_READ) { ++ s3c_send_command(hw_dev, cmd, data); ++ rc = s3c_mci_read_block(hw_dev, data); ++ if (rc == 0) { ++ while (!(readl(hw_dev->map_base + SDIDSTA) & SDIDSTA_XFERFINISH)) ++ ; ++ } else ++ s3c_terminate_transfer(hw_dev); ++ } ++ ++ if (data->flags & MMC_DATA_WRITE) { ++ rc = s3c_mci_write_block(hw_dev, cmd, data); ++ if (rc == 0) { ++ while (!(readl(hw_dev->map_base + SDIDSTA) & SDIDSTA_XFERFINISH)) ++ ; ++ } else ++ s3c_terminate_transfer(hw_dev); ++ } ++ writel(0, hw_dev->map_base + SDIDCON); ++ ++ return rc; ++} ++ ++/* ------------------------- MCI API -------------------------------------- */ ++ ++/** ++ * Keep the attached MMC/SD unit in a well know state ++ * @param mci_pdata MCI platform data ++ * @param mci_dev MCI device instance ++ * @return 0 on success, negative value else ++ */ ++static int mci_reset(struct mci_host *mci_pdata, struct device_d *mci_dev) ++{ ++ struct device_d *hw_dev = mci_pdata->hw_dev; ++ ++ return s3c_mci_initialize(hw_dev, mci_dev); ++} ++ ++/** ++ * Process one command to the MCI card ++ * @param mci_pdata MCI platform data ++ * @param cmd The command to process ++ * @param data The data to handle in the command (can be NULL) ++ * @return 0 on success, negative value else ++ */ ++static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd, ++ struct mci_data *data) ++{ ++ struct device_d *hw_dev = mci_pdata->hw_dev; ++ int rc; ++ ++ /* enable clock */ ++ writel(readl(hw_dev->map_base + SDICON) | SDICON_CLKEN, ++ hw_dev->map_base + SDICON); ++ ++ if ((cmd->resp_type == 0) || (data == NULL)) ++ rc = s3c_mci_std_cmds(hw_dev, cmd); ++ else ++ rc = s3c_mci_adtc(hw_dev, cmd, data); /* with response and data */ ++ ++ s3c_finish_request(hw_dev); ++ ++ /* disable clock */ ++ writel(readl(hw_dev->map_base + SDICON) & ~SDICON_CLKEN, ++ hw_dev->map_base + SDICON); ++ return rc; ++} ++ ++/** ++ * Setup the bus width and IO speed ++ * @param mci_pdata MCI platform data ++ * @param mci_dev MCI device instance ++ * @param bus_width New bus width value (1, 4 or 8) ++ * @param clock New clock in Hz (can be '0' to disable the clock) ++ */ ++static void mci_set_ios(struct mci_host *mci_pdata, struct device_d *mci_dev, ++ unsigned bus_width, unsigned clock) ++{ ++ struct device_d *hw_dev = mci_pdata->hw_dev; ++ struct s3c_mci_host *host_data = GET_HOST_DATA(hw_dev); ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ uint32_t reg; ++ ++ switch (bus_width) { ++ case 8: /* no 8 bit support, fall back to 4 bit */ ++ case 4: ++ host_data->bus_width = 1; ++ host->bus_width = 4; /* 4 bit is possible */ ++ break; ++ default: ++ host_data->bus_width = 0; ++ host->bus_width = 1; /* 1 bit is possible */ ++ break; ++ } ++ ++ reg = readl(hw_dev->map_base + SDICON); ++ if (clock) { ++ /* setup the IO clock frequency and enable it */ ++ host->clock = host_data->clock = s3c_setup_clock_speed(hw_dev, clock); ++ reg |= SDICON_CLKEN; /* enable the clock */ ++ } else { ++ reg &= ~SDICON_CLKEN; /* disable the clock */ ++ host->clock = host_data->clock = 0; ++ } ++ writel(reg, hw_dev->map_base + SDICON); ++ ++ pr_debug("IO settings: bus width=%d, frequency=%u Hz\n", ++ host->bus_width, host->clock); ++} ++ ++/* ----------------------------------------------------------------------- */ ++ ++#ifdef CONFIG_MCI_INFO ++static void s3c_info(struct device_d *hw_dev) ++{ ++ struct s3c_mci_host *host = hw_dev->priv; ++ struct s3c_mci_platform_data *pd = hw_dev->platform_data; ++ ++ printf(" Bus data width: %d bit\n", host->bus_width == 1 ? 4 : 1); ++ printf(" Bus frequency: %u Hz\n", host->clock); ++ printf(" Frequency limits: "); ++ if (pd->f_min == 0) ++ printf("no lower limit "); ++ else ++ printf("%u Hz lower limit ", pd->f_min); ++ if (pd->f_max == 0) ++ printf("- no upper limit"); ++ else ++ printf("- %u Hz upper limit", pd->f_max); ++ printf("\n Card detection support: %s\n", ++ pd->gpio_detect != 0 ? "yes" : "no"); ++} ++#endif ++ ++/* ++ * There is only one host MCI hardware instance available. ++ * It makes no sense to dynamically allocate this data ++ */ ++static struct mci_host mci_pdata = { ++ .send_cmd = mci_request, ++ .set_ios = mci_set_ios, ++ .init = mci_reset, ++}; ++ ++static int s3c_mci_probe(struct device_d *hw_dev) ++{ ++ struct s3c_mci_platform_data *pd = hw_dev->platform_data; ++ ++ /* TODO replace by the global func: enable the SDI unit clock */ ++ writel(readl(S3C24X0_CLOCK_POWER_BASE + 0x0c) | 0x200, ++ S3C24X0_CLOCK_POWER_BASE + 0x0c); ++ ++ if (pd == NULL) { ++ pr_err("Missing platform data\n"); ++ return -EINVAL; ++ } ++ ++ hw_dev->priv = &host_data; ++ mci_pdata.hw_dev = hw_dev; ++ ++ /* feed forward the platform specific values */ ++ mci_pdata.voltages = pd->voltages; ++ mci_pdata.host_caps = pd->caps; ++ mci_pdata.f_min = pd->f_min == 0 ? s3c24xx_get_pclk() / 256 : pd->f_min; ++ mci_pdata.f_max = pd->f_max == 0 ? s3c24xx_get_pclk() / 2 : pd->f_max; ++ ++ /* ++ * Start the clock to let the engine and the card finishes its startup ++ */ ++ host_data.clock = s3c_setup_clock_speed(hw_dev, mci_pdata.f_min); ++ writel(SDICON_FIFORESET | SDICON_MMCCLOCK, hw_dev->map_base + SDICON); ++ ++ return mci_register(&mci_pdata); ++} ++ ++static struct driver_d s3c_mci_driver = { ++ .name = "s3c_mci", ++ .probe = s3c_mci_probe, ++#ifdef CONFIG_MCI_INFO ++ .info = s3c_info, ++#endif ++}; ++ ++static int s3c_mci_init_driver(void) ++{ ++ register_driver(&s3c_mci_driver); ++ return 0; ++} ++ ++device_initcall(s3c_mci_init_driver); +diff --git a/drivers/mci/stm378x.c b/drivers/mci/stm378x.c +new file mode 100644 +index 0000000..420c2ea +--- /dev/null ++++ b/drivers/mci/stm378x.c +@@ -0,0 +1,699 @@ ++/* ++ * Copyright (C) 2010 Juergen Beisert, Pengutronix <jbe@pengutronix.de> ++ * ++ * This code is based on: ++ * ++ * Copyright (C) 2007 SigmaTel, Inc., Ioannis Kappas <ikappas@sigmatel.com> ++ * ++ * Portions copyright (C) 2003 Russell King, PXA MMCI Driver ++ * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver ++ * ++ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/** ++ * @file ++ * @brief MCI card host interface for i.MX23 CPU ++ */ ++ ++/* #define DEBUG */ ++ ++#include <common.h> ++#include <init.h> ++#include <mci.h> ++#include <errno.h> ++#include <clock.h> ++#include <asm/io.h> ++#include <asm/bitops.h> ++#include <mach/imx-regs.h> ++#include <mach/mci.h> ++#include <mach/clock.h> ++ ++#define CLOCKRATE_MIN (1 * 1000 * 1000) ++#define CLOCKRATE_MAX (480 * 1000 * 1000) ++ ++#define HW_SSP_CTRL0 0x000 ++# define SSP_CTRL0_SFTRST (1 << 31) ++# define SSP_CTRL0_CLKGATE (1 << 30) ++# define SSP_CTRL0_RUN (1 << 29) ++# define SSP_CTRL0_LOCK_CS (1 << 29) ++# define SSP_CTRL0_READ (1 << 25) ++# define SSP_CTRL0_IGNORE_CRC (1 << 26) ++# define SSP_CTRL0_DATA_XFER (1 << 24) ++# define SSP_CTRL0_BUS_WIDTH(x) (((x) & 0x3) << 22) ++# define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) ++# define SSP_CTRL0_LONG_RESP (1 << 19) ++# define SSP_CTRL0_GET_RESP (1 << 17) ++# define SSP_CTRL0_ENABLE (1 << 16) ++# define SSP_CTRL0_XFER_COUNT(x) ((x) & 0xffff) ++ ++#define HW_SSP_CMD0 0x010 ++# define SSP_CMD0_SLOW_CLK (1 << 22) ++# define SSP_CMD0_CONT_CLK (1 << 21) ++# define SSP_CMD0_APPEND_8CYC (1 << 20) ++# define SSP_CMD0_BLOCK_SIZE(x) (((x) & 0xf) << 16) ++# define SSP_CMD0_BLOCK_COUNT(x) (((x) & 0xff) << 8) ++# define SSP_CMD0_CMD(x) ((x) & 0xff) ++ ++#define HW_SSP_CMD1 0x020 ++#define HW_SSP_COMPREF 0x030 ++#define HW_SSP_COMPMASK 0x040 ++#define HW_SSP_TIMING 0x050 ++# define SSP_TIMING_TIMEOUT_MASK (0xffff0000) ++# define SSP_TIMING_TIMEOUT(x) ((x) << 16) ++# define SSP_TIMING_CLOCK_DIVIDE(x) (((x) & 0xff) << 8) ++# define SSP_TIMING_CLOCK_RATE(x) ((x) & 0xff) ++ ++#define HW_SSP_CTRL1 0x060 ++# define SSP_CTRL1_POLARITY (1 << 9) ++# define SSP_CTRL1_WORD_LENGTH(x) (((x) & 0xf) << 4) ++# define SSP_CTRL1_SSP_MODE(x) ((x) & 0xf) ++ ++#define HW_SSP_DATA 0x070 ++#define HW_SSP_SDRESP0 0x080 ++#define HW_SSP_SDRESP1 0x090 ++#define HW_SSP_SDRESP2 0x0A0 ++#define HW_SSP_SDRESP3 0x0B0 ++ ++#define HW_SSP_STATUS 0x0C0 ++# define SSP_STATUS_PRESENT (1 << 31) ++# define SSP_STATUS_SD_PRESENT (1 << 29) ++# define SSP_STATUS_CARD_DETECT (1 << 28) ++# define SSP_STATUS_RESP_CRC_ERR (1 << 16) ++# define SSP_STATUS_RESP_ERR (1 << 15) ++# define SSP_STATUS_RESP_TIMEOUT (1 << 14) ++# define SSP_STATUS_DATA_CRC_ERR (1 << 13) ++# define SSP_STATUS_TIMEOUT (1 << 12) ++# define SSP_STATUS_FIFO_OVRFLW (1 << 9) ++# define SSP_STATUS_FIFO_FULL (1 << 8) ++# define SSP_STATUS_FIFO_EMPTY (1 << 5) ++# define SSP_STATUS_FIFO_UNDRFLW (1 << 4) ++# define SSP_STATUS_CMD_BUSY (1 << 3) ++# define SSP_STATUS_DATA_BUSY (1 << 2) ++# define SSP_STATUS_BUSY (1 << 0) ++# define SSP_STATUS_ERROR (SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW | \ ++ SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR | \ ++ SSP_STATUS_RESP_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | SSP_STATUS_TIMEOUT) ++ ++#define HW_SSP_DEBUG 0x100 ++#define HW_SSP_VERSION 0x110 ++ ++struct stm_mci_host { ++ unsigned clock; /* current clock speed in Hz ("0" if disabled) */ ++#ifdef CONFIG_MCI_INFO ++ unsigned f_min; ++ unsigned f_max; ++#endif ++ int bus_width:2; /* 0 = 1 bit, 1 = 4 bit, 2 = 8 bit */ ++}; ++ ++/** ++ * Get MCI cards response if defined for the type of command ++ * @param hw_dev Host interface device instance ++ * @param cmd Command description ++ * @return Response bytes count, -EINVAL for unsupported response types ++ */ ++static int get_cards_response(struct device_d *hw_dev, struct mci_cmd *cmd) ++{ ++ switch (cmd->resp_type) { ++ case MMC_RSP_NONE: ++ return 0; ++ ++ case MMC_RSP_R1: ++ case MMC_RSP_R1b: ++ case MMC_RSP_R3: ++ cmd->response[0] = readl(hw_dev->map_base + HW_SSP_SDRESP0); ++ return 1; ++ ++ case MMC_RSP_R2: ++ cmd->response[3] = readl(hw_dev->map_base + HW_SSP_SDRESP0); ++ cmd->response[2] = readl(hw_dev->map_base + HW_SSP_SDRESP1); ++ cmd->response[1] = readl(hw_dev->map_base + HW_SSP_SDRESP2); ++ cmd->response[0] = readl(hw_dev->map_base + HW_SSP_SDRESP3); ++ return 4; ++ } ++ ++ return -EINVAL; ++} ++ ++/** ++ * Finish a request to the MCI card ++ * @param hw_dev Host interface device instance ++ * ++ * Can also stop the clock to save power ++ */ ++static void finish_request(struct device_d *hw_dev) ++{ ++ /* stop the engines (normaly already done) */ ++ writel(SSP_CTRL0_RUN, hw_dev->map_base + HW_SSP_CTRL0 + 8); ++} ++ ++/** ++ * Check if the last command failed and if, why it failed ++ * @param status HW_SSP_STATUS's content ++ * @return 0 if no error, negative values else ++ */ ++static int get_cmd_error(unsigned status) ++{ ++ if (status & SSP_STATUS_ERROR) ++ pr_debug("Status Reg reports %08X\n", status); ++ ++ if (status & SSP_STATUS_TIMEOUT) { ++ pr_debug("CMD timeout\n"); ++ return -ETIMEDOUT; ++ } else if (status & SSP_STATUS_RESP_TIMEOUT) { ++ pr_debug("RESP timeout\n"); ++ return -ETIMEDOUT; ++ } else if (status & SSP_STATUS_RESP_CRC_ERR) { ++ pr_debug("CMD crc error\n"); ++ return -EILSEQ; ++ } else if (status & SSP_STATUS_RESP_ERR) { ++ pr_debug("RESP error\n"); ++ return -EIO; ++ } ++ ++ return 0; ++} ++ ++/** ++ * Define the timout for the next command ++ * @param hw_dev Host interface device instance ++ * @param to Timeout value in MCI card's bus clocks ++ */ ++static void stm_setup_timout(struct device_d *hw_dev, unsigned to) ++{ ++ uint32_t reg; ++ ++ reg = readl(hw_dev->map_base + HW_SSP_TIMING) & ~SSP_TIMING_TIMEOUT_MASK; ++ reg |= SSP_TIMING_TIMEOUT(to); ++ writel(reg, hw_dev->map_base + HW_SSP_TIMING); ++} ++ ++/** ++ * Read data from the MCI card ++ * @param hw_dev Host interface device instance ++ * @param buffer To write data into ++ * @param length Count of bytes to read (must be multiples of 4) ++ * @return 0 on success, negative values else ++ * ++ * @note This routine uses PIO to read in the data bytes from the FIFO. This ++ * may fail whith high clock speeds. If you receive -EIO errors you can try ++ * again with reduced clock speeds. ++ */ ++static int read_data(struct device_d *hw_dev, void *buffer, unsigned length) ++{ ++ uint32_t *p = buffer; ++ ++ if (length & 0x3) { ++ pr_debug("Cannot read data sizes not multiple of 4 (request for %u detected)\n", ++ length); ++ return -EINVAL; ++ } ++ ++ while ((length != 0) && ++ ((readl(hw_dev->map_base + HW_SSP_STATUS) & SSP_STATUS_ERROR) == 0)) { ++ /* TODO sort out FIFO overflows and emit -EOI for this case */ ++ if ((readl(hw_dev->map_base + HW_SSP_STATUS) & SSP_STATUS_FIFO_EMPTY) == 0) { ++ *p = readl(hw_dev->map_base + HW_SSP_DATA); ++ p++; ++ length -= 4; ++ } ++ } ++ ++ if (length == 0) ++ return 0; ++ ++ return -EINVAL; ++} ++ ++ ++/** ++ * Write data into the MCI card ++ * @param hw_dev Host interface device instance ++ * @param buffer To read the data from ++ * @param length Count of bytes to write (must be multiples of 4) ++ * @return 0 on success, negative values else ++ * ++ * @note This routine uses PIO to write the data bytes into the FIFO. This ++ * may fail with high clock speeds. If you receive -EIO errors you can try ++ * again with reduced clock speeds. ++ */ ++static int write_data(struct device_d *hw_dev, const void *buffer, unsigned length) ++{ ++ const uint32_t *p = buffer; ++ ++ if (length & 0x3) { ++ pr_debug("Cannot write data sizes not multiple of 4 (request for %u detected)\n", ++ length); ++ return -EINVAL; ++ } ++ ++ while ((length != 0) && ++ ((readl(hw_dev->map_base + HW_SSP_STATUS) & SSP_STATUS_ERROR) == 0)) { ++ /* TODO sort out FIFO overflows and emit -EOI for this case */ ++ if ((readl(hw_dev->map_base + HW_SSP_STATUS) & SSP_STATUS_FIFO_FULL) == 0) { ++ writel(*p, hw_dev->map_base + HW_SSP_DATA); ++ p++; ++ length -= 4; ++ } ++ } ++ if (length == 0) ++ return 0; ++ ++ return -EINVAL; ++} ++ ++/** ++ * Start the transaction with or without data ++ * @param hw_dev Host interface device instance ++ * @param data Data transfer description (might be NULL) ++ * @return 0 on success ++ */ ++static int transfer_data(struct device_d *hw_dev, struct mci_data *data) ++{ ++ unsigned length; ++ ++ if (data != NULL) { ++ length = data->blocks * data->blocksize; ++#if 0 ++ /* ++ * For the records: When writing data with high clock speeds it ++ * could be a good idea to fill the FIFO prior starting the ++ * transaction. ++ * But last time I tried it, it failed badly. Don't know why yet ++ */ ++ if (data->flags & MMC_DATA_WRITE) { ++ err = write_data(host, data->src, 16); ++ data->src += 16; ++ length -= 16; ++ } ++#endif ++ } ++ ++ /* ++ * Everything is ready for the transaction now: ++ * - transfer configuration ++ * - command and its parameters ++ * ++ * Start the transaction right now ++ */ ++ writel(SSP_CTRL0_RUN, hw_dev->map_base + HW_SSP_CTRL0 + 4); ++ ++ if (data != NULL) { ++ if (data->flags & MMC_DATA_READ) ++ return read_data(hw_dev, data->dest, length); ++ else ++ return write_data(hw_dev, data->src, length); ++ } ++ ++ return 0; ++} ++ ++/** ++ * Configure the MCI hardware for the next transaction ++ * @param cmd_flags Command information ++ * @param data_flags Data information (may be 0) ++ * @return Corresponding setting for the SSP_CTRL0 register ++ */ ++static uint32_t prepare_transfer_setup(unsigned cmd_flags, unsigned data_flags) ++{ ++ uint32_t reg = 0; ++ ++ if (cmd_flags & MMC_RSP_PRESENT) ++ reg |= SSP_CTRL0_GET_RESP; ++ if ((cmd_flags & MMC_RSP_CRC) == 0) ++ reg |= SSP_CTRL0_IGNORE_CRC; ++ if (cmd_flags & MMC_RSP_136) ++ reg |= SSP_CTRL0_LONG_RESP; ++ if (cmd_flags & MMC_RSP_BUSY) ++ reg |= SSP_CTRL0_WAIT_FOR_IRQ; /* FIXME correct? */ ++#if 0 ++ if (cmd_flags & MMC_RSP_OPCODE) ++ /* TODO */ ++#endif ++ if (data_flags & MMC_DATA_READ) ++ reg |= SSP_CTRL0_READ; ++ ++ return reg; ++} ++ ++/** ++ * Handle MCI commands without data ++ * @param hw_dev Host interface device instance ++ * @param cmd The command to handle ++ * @return 0 on success ++ * ++ * This functions handles the following MCI commands: ++ * - "broadcast command (BC)" without a response ++ * - "broadcast commands with response (BCR)" ++ * - "addressed command (AC)" with response, but without data ++ */ ++static int stm_mci_std_cmds(struct device_d *hw_dev, struct mci_cmd *cmd) ++{ ++ /* setup command and transfer parameters */ ++ writel(prepare_transfer_setup(cmd->resp_type, 0) | ++ SSP_CTRL0_ENABLE, hw_dev->map_base + HW_SSP_CTRL0); ++ ++ /* prepare the command, when no response is expected add a few trailing clocks */ ++ writel(SSP_CMD0_CMD(cmd->cmdidx) | ++ (cmd->resp_type & MMC_RSP_PRESENT ? 0 : SSP_CMD0_APPEND_8CYC), ++ hw_dev->map_base + HW_SSP_CMD0); ++ ++ /* prepare command's arguments */ ++ writel(cmd->cmdarg, hw_dev->map_base + HW_SSP_CMD1); ++ ++ stm_setup_timout(hw_dev, 0xffff); ++ ++ /* start the transfer */ ++ writel(SSP_CTRL0_RUN, hw_dev->map_base + HW_SSP_CTRL0 + 4); ++ ++ /* wait until finished */ ++ while (readl(hw_dev->map_base + HW_SSP_CTRL0) & SSP_CTRL0_RUN) ++ ; ++ ++ if (cmd->resp_type & MMC_RSP_PRESENT) ++ get_cards_response(hw_dev, cmd); ++ ++ return get_cmd_error(readl(hw_dev->map_base + HW_SSP_STATUS)); ++} ++ ++/** ++ * Handle an "addressed data transfer command " with or without data ++ * @param hw_dev Host interface device instance ++ * @param cmd The command to handle ++ * @param data The data information (buffer, direction aso.) May be NULL ++ * @return 0 on success ++ */ ++static int stm_mci_adtc(struct device_d *hw_dev, struct mci_cmd *cmd, ++ struct mci_data *data) ++{ ++ struct stm_mci_host *host_data = (struct stm_mci_host*)GET_HOST_DATA(hw_dev); ++ uint32_t xfer_cnt, log2blocksize, block_cnt; ++ int err; ++ ++ /* Note: 'data' can be NULL! */ ++ if (data != NULL) { ++ xfer_cnt = data->blocks * data->blocksize; ++ block_cnt = data->blocks - 1; /* can be 0 */ ++ log2blocksize = find_first_bit((const unsigned long*)&data->blocksize, ++ 32); ++ } else ++ xfer_cnt = log2blocksize = block_cnt = 0; ++ ++ /* setup command and transfer parameters */ ++ writel(prepare_transfer_setup(cmd->resp_type, data != NULL ? data->flags : 0) | ++ SSP_CTRL0_BUS_WIDTH(host_data->bus_width) | ++ (xfer_cnt != 0 ? SSP_CTRL0_DATA_XFER : 0) | /* command plus data */ ++ SSP_CTRL0_ENABLE | ++ SSP_CTRL0_XFER_COUNT(xfer_cnt), /* byte count to be transfered */ ++ hw_dev->map_base + HW_SSP_CTRL0); ++ ++ /* prepare the command and the transfered data count */ ++ writel(SSP_CMD0_CMD(cmd->cmdidx) | ++ SSP_CMD0_BLOCK_SIZE(log2blocksize) | ++ SSP_CMD0_BLOCK_COUNT(block_cnt) | ++ (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ? SSP_CMD0_APPEND_8CYC : 0), ++ hw_dev->map_base + HW_SSP_CMD0); ++ ++ /* prepare command's arguments */ ++ writel(cmd->cmdarg, hw_dev->map_base + HW_SSP_CMD1); ++ ++ stm_setup_timout(hw_dev, 0xffff); ++ ++ err = transfer_data(hw_dev, data); ++ if (err != 0) { ++ pr_debug(" Transfering data failed\n"); ++ return err; ++ } ++ ++ /* wait until finished */ ++ while (readl(hw_dev->map_base + HW_SSP_CTRL0) & SSP_CTRL0_RUN) ++ ; ++ ++ get_cards_response(hw_dev, cmd); ++ ++ return 0; ++} ++ ++ ++/** ++ * @param hw_dev Host interface device instance ++ * @param nc New Clock in [Hz] (may be 0 to disable the clock) ++ * @return The real clock frequency ++ * ++ * The SSP unit clock can base on the external 24 MHz or the internal 480 MHz ++ * Its unit clock value is derived from the io clock, from the SSP divider ++ * and at least the SSP bus clock itself is derived from the SSP unit's divider ++ * ++ * @code ++ * |------------------- generic -------------|-peripheral specific-|-----all SSPs-----|-per SSP unit-| ++ * 24 MHz ---------------------------- ++ * \ \ ++ * \ |----| FRAC |----IO CLK----| SSP unit DIV |---| SSP DIV |--- SSP output clock ++ * \- | PLL |--- 480 MHz ---/ ++ * @endcode ++ * ++ * @note Up to "SSP unit DIV" the outer world must care. This routine only ++ * handles the "SSP DIV". ++ */ ++static unsigned setup_clock_speed(struct device_d *hw_dev, unsigned nc) ++{ ++ unsigned ssp, div, rate, reg; ++ ++ if (nc == 0U) { ++ /* TODO stop the clock */ ++ return 0; ++ } ++ ++ ssp = imx_get_sspclk(0) * 1000; ++ ++ for (div = 2; div < 255; div += 2) { ++ rate = (((ssp + (nc >> 1) ) / nc) + (div >> 1)) / div; ++ if (rate <= 0x100) ++ break; ++ } ++ if (div >= 255) { ++ pr_warning("Cannot set clock to %d Hz\n", nc); ++ return 0; ++ } ++ ++ reg = readl(hw_dev->map_base + HW_SSP_TIMING) & SSP_TIMING_TIMEOUT_MASK; ++ reg |= SSP_TIMING_CLOCK_DIVIDE(div) | SSP_TIMING_CLOCK_RATE(rate - 1); ++ writel(reg, hw_dev->map_base + HW_SSP_TIMING); ++ ++ return ssp / div / rate; ++} ++ ++/** ++ * Reset the MCI engine (the hard way) ++ * @param hw_dev Host interface instance ++ * ++ * This will reset everything in all registers of this unit! (FIXME) ++ */ ++static void stm_mci_reset(struct device_d *hw_dev) ++{ ++ writel(SSP_CTRL0_SFTRST, hw_dev->map_base + HW_SSP_CTRL0 + 8); ++ while (readl(hw_dev->map_base + HW_SSP_CTRL0) & SSP_CTRL0_SFTRST) ++ ; ++} ++ ++/** ++ * Initialize the engine ++ * @param hw_dev Host interface instance ++ * @param mci_dev MCI device instance ++ */ ++static int stm_mci_initialize(struct device_d *hw_dev, struct device_d *mci_dev) ++{ ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ struct stm_mci_host *host_data = (struct stm_mci_host*)GET_HOST_DATA(hw_dev); ++ ++ /* enable the clock to this unit to be able to reset it */ ++ writel(SSP_CTRL0_CLKGATE, hw_dev->map_base + HW_SSP_CTRL0 + 8); ++ ++ /* reset the unit */ ++ stm_mci_reset(hw_dev); ++ ++ /* restore the last settings */ ++ host->clock = host_data->clock = setup_clock_speed(hw_dev, host->clock); ++ stm_setup_timout(hw_dev, 0xffff); ++ writel(SSP_CTRL0_IGNORE_CRC | ++ SSP_CTRL0_BUS_WIDTH(host_data->bus_width), ++ hw_dev->map_base + HW_SSP_CTRL0); ++ writel(SSP_CTRL1_POLARITY | ++ SSP_CTRL1_SSP_MODE(3) | ++ SSP_CTRL1_WORD_LENGTH(7), hw_dev->map_base + HW_SSP_CTRL1); ++ ++ return 0; ++} ++ ++/* ------------------------- MCI API -------------------------------------- */ ++ ++/** ++ * Keep the attached MMC/SD unit in a well know state ++ * @param mci_pdata MCI platform data ++ * @param mci_dev MCI device instance ++ * @return 0 on success, negative value else ++ */ ++static int mci_reset(struct mci_host *mci_pdata, struct device_d *mci_dev) ++{ ++ struct device_d *hw_dev = mci_pdata->hw_dev; ++ ++ return stm_mci_initialize(hw_dev, mci_dev); ++} ++ ++/** ++ * Process one command to the MCI card ++ * @param mci_pdata MCI platform data ++ * @param cmd The command to process ++ * @param data The data to handle in the command (can be NULL) ++ * @return 0 on success, negative value else ++ */ ++static int mci_request(struct mci_host *mci_pdata, struct mci_cmd *cmd, ++ struct mci_data *data) ++{ ++ struct device_d *hw_dev = mci_pdata->hw_dev; ++ int rc; ++ ++ if ((cmd->resp_type == 0) || (data == NULL)) ++ rc = stm_mci_std_cmds(hw_dev, cmd); ++ else ++ rc = stm_mci_adtc(hw_dev, cmd, data); /* with response and data */ ++ ++ finish_request(hw_dev); /* TODO */ ++ return rc; ++} ++ ++/** ++ * Setup the bus width and IO speed ++ * @param mci_pdata MCI platform data ++ * @param mci_dev MCI device instance ++ * @param bus_width New bus width value (1, 4 or 8) ++ * @param clock New clock in Hz (can be '0' to disable the clock) ++ * ++ * Drivers currently realized values are stored in MCI's platformdata ++ */ ++static void mci_set_ios(struct mci_host *mci_pdata, struct device_d *mci_dev, ++ unsigned bus_width, unsigned clock) ++{ ++ struct device_d *hw_dev = mci_pdata->hw_dev; ++ struct stm_mci_host *host_data = (struct stm_mci_host*)GET_HOST_DATA(hw_dev); ++ struct mci_host *host = GET_MCI_PDATA(mci_dev); ++ ++ switch (bus_width) { ++ case 8: ++ host_data->bus_width = 2; ++ host->bus_width = 8; /* 8 bit is possible */ ++ break; ++ case 4: ++ host_data->bus_width = 1; ++ host->bus_width = 4; /* 4 bit is possible */ ++ break; ++ default: ++ host_data->bus_width = 0; ++ host->bus_width = 1; /* 1 bit is possible */ ++ break; ++ } ++ ++ host->clock = host_data->clock = setup_clock_speed(hw_dev, clock); ++ pr_debug("IO settings: bus width=%d, frequency=%u Hz\n", host->bus_width, ++ host->clock); ++} ++ ++/* ----------------------------------------------------------------------- */ ++ ++#ifdef CONFIG_MCI_INFO ++const unsigned char bus_width[3] = { 1, 4, 8 }; ++ ++static void stm_info(struct device_d *hw_dev) ++{ ++ struct stm_mci_host *host_data = GET_HOST_DATA(hw_dev); ++ ++ printf(" Interface\n"); ++ printf(" Min. bus clock: %u Hz\n", host_data->f_min); ++ printf(" Max. bus clock: %u Hz\n", host_data->f_max); ++ printf(" Current bus clock: %u Hz\n", host_data->clock); ++ printf(" Bus width: %u bit\n", bus_width[host_data->bus_width]); ++ printf("\n"); ++} ++#endif ++ ++static int stm_mci_probe(struct device_d *hw_dev) ++{ ++ struct stm_mci_platform_data *pd = hw_dev->platform_data; ++ struct stm_mci_host *host_data; ++ struct mci_host *host; ++ ++ if (hw_dev->platform_data == NULL) { ++ pr_err("Missing platform data\n"); ++ return -EINVAL; ++ } ++ ++ host = xzalloc(sizeof(struct stm_mci_host) + sizeof(struct mci_host)); ++ host_data = (struct stm_mci_host*)&host[1]; ++ ++ hw_dev->priv = host_data; ++ host->hw_dev = hw_dev; ++ host->send_cmd = mci_request, ++ host->set_ios = mci_set_ios, ++ host->init = mci_reset, ++ ++ /* feed forward the platform specific values */ ++ host->voltages = pd->voltages; ++ host->host_caps = pd->caps; ++ ++ if (pd->f_min == 0) { ++ host->f_min = imx_get_sspclk(0) / 254U / 256U * 1000U; ++ pr_debug("Min. frequency is %u Hz\n", host->f_min); ++ } else { ++ host->f_min = pd->f_min; ++ pr_debug("Min. frequency is %u Hz, could be %u Hz\n", ++ host->f_min, imx_get_sspclk(0) / 254U / 256U * 1000U); ++ } ++ if (pd->f_max == 0) { ++ host->f_max = imx_get_sspclk(0) / 2U / 1U * 1000U; ++ pr_debug("Max. frequency is %u Hz\n", host->f_max); ++ } else { ++ host->f_max = pd->f_max; ++ pr_debug("Max. frequency is %u Hz, could be %u Hz\n", ++ host->f_max, imx_get_sspclk(0) / 2U / 1U * 1000U); ++ } ++ ++#ifdef CONFIG_MCI_INFO ++ host_data->f_min = host->f_min; ++ host_data->f_max = host->f_max; ++#endif ++ ++ return mci_register(host); ++} ++ ++static struct driver_d stm_mci_driver = { ++ .name = "stm_mci", ++ .probe = stm_mci_probe, ++#ifdef CONFIG_MCI_INFO ++ .info = stm_info, ++#endif ++}; ++ ++static int stm_mci_init_driver(void) ++{ ++ register_driver(&stm_mci_driver); ++ return 0; ++} ++ ++device_initcall(stm_mci_init_driver); +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +new file mode 100644 +index 0000000..96440d8 +--- /dev/null ++++ b/drivers/mfd/Kconfig +@@ -0,0 +1,28 @@ ++menu MFD ++ ++config I2C_MC13892 ++ depends on I2C || SPI ++ bool "MC13892 a.k.a. PMIC driver" ++ ++config I2C_MC34704 ++ depends on I2C ++ bool "MC34704 PMIC driver" ++ ++config I2C_MC9SDZ60 ++ depends on I2C ++ bool "MC9SDZ60 driver" ++ ++config I2C_LP3972 ++ depends on I2C ++ bool "LP3972 driver" ++ ++config I2C_TWL4030 ++ depends on I2C ++ bool "TWL4030 driver" ++ select GPIO ++ ++config DRIVER_SPI_MC13783 ++ depends on SPI ++ bool "MC13783 a.k.a. PMIC driver" ++ ++endmenu +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +new file mode 100644 +index 0000000..d411f23 +--- /dev/null ++++ b/drivers/mfd/Makefile +@@ -0,0 +1,6 @@ ++obj-$(CONFIG_I2C_MC13892) += mc13892.o ++obj-$(CONFIG_I2C_MC34704) += mc34704.o ++obj-$(CONFIG_I2C_MC9SDZ60) += mc9sdz60.o ++obj-$(CONFIG_I2C_LP3972) += lp3972.o ++obj-$(CONFIG_I2C_TWL4030) += twl4030.o ++obj-$(CONFIG_DRIVER_SPI_MC13783) += mc13783.o +diff --git a/drivers/mfd/lp3972.c b/drivers/mfd/lp3972.c +new file mode 100644 +index 0000000..9826699 +--- /dev/null ++++ b/drivers/mfd/lp3972.c +@@ -0,0 +1,110 @@ ++/* ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * 2009 Marc Kleine-Budde <mkl@pengutronix.de> ++ * 2009 Eric Benard <eric@eukrea.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <driver.h> ++#include <xfuncs.h> ++#include <errno.h> ++ ++#include <i2c/i2c.h> ++ ++#include <asm/byteorder.h> ++ ++#define DRIVERNAME "lp3972" ++ ++struct lp_priv { ++ struct cdev cdev; ++ struct i2c_client *client; ++}; ++ ++#define to_lp_priv(a) container_of(a, struct lp_priv, cdev) ++ ++static struct lp_priv *lp_dev; ++ ++struct i2c_client *lp3972_get_client(void) ++{ ++ if (!lp_dev) ++ return NULL; ++ ++ return lp_dev->client; ++} ++ ++static u32 lp_read_reg(struct lp_priv *lp, int reg) ++{ ++ u8 buf; ++ ++ i2c_read_reg(lp->client, reg, &buf, sizeof(buf)); ++ ++ return buf; ++} ++ ++static ssize_t lp_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ struct lp_priv *priv = to_lp_priv(cdev); ++ int i = count; ++ u8 *buf = _buf; ++ ++ while (i) { ++ *buf = lp_read_reg(priv, offset); ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static struct file_operations lp_fops = { ++ .lseek = dev_lseek_default, ++ .read = lp_read, ++}; ++ ++static int lp_probe(struct device_d *dev) ++{ ++ if (lp_dev) ++ return -EBUSY; ++ ++ lp_dev = xzalloc(sizeof(struct lp_priv)); ++ lp_dev->cdev.name = DRIVERNAME; ++ lp_dev->client = to_i2c_client(dev); ++ lp_dev->cdev.size = 256; ++ lp_dev->cdev.dev = dev; ++ lp_dev->cdev.ops = &lp_fops; ++ ++ devfs_create(&lp_dev->cdev); ++ ++ return 0; ++} ++ ++static struct driver_d lp_driver = { ++ .name = DRIVERNAME, ++ .probe = lp_probe, ++}; ++ ++static int lp_init(void) ++{ ++ register_driver(&lp_driver); ++ return 0; ++} ++ ++device_initcall(lp_init); +diff --git a/drivers/mfd/mc13783.c b/drivers/mfd/mc13783.c +new file mode 100644 +index 0000000..19e2780 +--- /dev/null ++++ b/drivers/mfd/mc13783.c +@@ -0,0 +1,237 @@ ++/* ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <driver.h> ++#include <spi/spi.h> ++#include <xfuncs.h> ++#include <errno.h> ++#include <mach/pmic.h> ++ ++#define REG_INTERRUPT_STATUS_0 0x0 ++#define REG_INTERRUPT_MASK 0x1 ++#define REG_INTERRUPT_SENSE_0 0x2 ++#define REG_INTERRUPT_STATUS_1 0x3 ++#define REG_INTERRUPT_MASK_1 0x4 ++#define REG_INTERRUPT_SENSE_1 0x5 ++#define REG_POWER_UP_MODE_SENSE 0x6 ++#define REG_REVISION 0x7 ++#define REG_SEMAPHORE 0x8 ++#define REG_ARBITRATION_PERIPHERAL_AUDIO 0x9 ++#define REG_ARBITRATION_SWITCHERS 0xa ++#define REG_ARBITRATION_REGULATORS(x) (0xb + (x)) /* 0 .. 1 */ ++#define REG_POWER_CONTROL(x) (0xd + (x)) /* 0 .. 2 */ ++#define REG_REGEN_ASSIGNMENT 0x10 ++#define REG_CONTROL_SPARE 0x11 ++#define REG_MEMORY_A 0x12 ++#define REG_MEMORY_B 0x13 ++#define REG_RTC_TIME 0x14 ++#define REG_RTC_ALARM 0x15 ++#define REG_RTC_DAY 0x16 ++#define REG_RTC_DAY_ALARM 0x17 ++#define REG_SWITCHERS(x) (0x18 + (x)) /* 0 .. 5 */ ++#define REG_REGULATOR_SETTING(x) (0x1e + (x)) /* 0 .. 1 */ ++#define REG_REGULATOR_MODE(x) (0x20 + (x)) /* 0 .. 1 */ ++#define REG_POWER_MISCELLANEOUS 0x22 ++#define REG_POWER_SPARE 0x23 ++#define REG_AUDIO_RX_0 0x24 ++#define REG_AUDIO_RX_1 0x25 ++#define REG_AUDIO_TX 0x26 ++#define REG_AUDIO_SSI_NETWORK 0x27 ++#define REG_AUDIO_CODEC 0x28 ++#define REG_AUDIO_STEREO_DAC 0x29 ++#define REG_AUDIO_SPARE 0x2a ++#define REG_ADC(x) (0x2b + (x)) /* 0 .. 4 */ ++#define REG_CHARGER 0x30 ++#define REG_USB 0x31 ++#define REG_CHARGE_USB_SPARE 0x32 ++#define REG_LED_CONTROL(x) (0x33 + (x)) /* 0 .. 5 */ ++#define REG_SPARE 0x39 ++#define REG_TRIM(x) (0x3a + (x)) /* 0 .. 1 */ ++#define REG_TEST(x) (0x3c + (x)) /* 0 .. 3 */ ++ ++#define MXC_PMIC_REG_NUM(reg) (((reg) & 0x3f) << 25) ++#define MXC_PMIC_WRITE (1 << 31) ++ ++#define SWX_VOLTAGE(x) ((x) & 0x3f) ++#define SWX_VOLTAGE_DVS(x) (((x) & 0x3f) << 6) ++#define SWX_VOLTAGE_STANDBY(x) (((x) & 0x3f) << 12) ++#define SWX_VOLTAGE_1_450 0x16 ++ ++#define SWX_MODE_OFF 0 ++#define SWX_MODE_NO_PULSE_SKIP 1 ++#define SWX_MODE_PULSE_SKIP 2 ++#define SWX_MODE_LOW_POWER_PFM 3 ++ ++#define SW1A_MODE(x) (((x) & 0x3) << 0) ++#define SW1A_MODE_STANDBY(x) (((x) & 0x3) << 2) ++#define SW1B_MODE(x) (((x) & 0x3) << 10) ++#define SW1B_MODE_STANDBY(x) (((x) & 0x3) << 12) ++#define SW1A_SOFTSTART (1 << 9) ++#define SW1B_SOFTSTART (1 << 17) ++#define SW_PLL_FACTOR(x) (((x) - 28) << 19) ++ ++struct pmic_priv { ++ struct cdev cdev; ++ struct spi_device *spi; ++}; ++ ++static int spi_rw(struct spi_device *spi, void * buf, size_t len) ++{ ++ int ret; ++ ++ struct spi_transfer t = { ++ .tx_buf = (const void *)buf, ++ .rx_buf = buf, ++ .len = len, ++ .cs_change = 0, ++ .delay_usecs = 0, ++ }; ++ struct spi_message m; ++ ++ spi_message_init(&m); ++ spi_message_add_tail(&t, &m); ++ if ((ret = spi_sync(spi, &m))) ++ return ret; ++ return 0; ++} ++ ++static uint32_t pmic_read_reg(struct pmic_priv *pmic, int reg) ++{ ++ uint32_t buf; ++ ++ buf = MXC_PMIC_REG_NUM(reg); ++ ++ spi_rw(pmic->spi, &buf, 4); ++ ++ return buf; ++} ++ ++static void pmic_write_reg(struct pmic_priv *pmic, int reg, uint32_t val) ++{ ++ uint32_t buf = MXC_PMIC_REG_NUM(reg) | MXC_PMIC_WRITE | (val & 0xffffff); ++ ++ spi_rw(pmic->spi, &buf, 4); ++} ++ ++static struct pmic_priv *pmic_device; ++ ++int pmic_power(void) ++{ ++ if(!pmic_device) { ++ printf("%s: no pmic device available\n", __FUNCTION__); ++ return -ENODEV; ++ } ++ ++ pmic_write_reg(pmic_device, REG_SWITCHERS(0), ++ SWX_VOLTAGE(SWX_VOLTAGE_1_450) | ++ SWX_VOLTAGE_DVS(SWX_VOLTAGE_1_450) | ++ SWX_VOLTAGE_STANDBY(SWX_VOLTAGE_1_450)); ++ ++ pmic_write_reg(pmic_device, REG_SWITCHERS(4), ++ SW1A_MODE(SWX_MODE_NO_PULSE_SKIP) | ++ SW1A_MODE_STANDBY(SWX_MODE_NO_PULSE_SKIP)| ++ SW1A_SOFTSTART | ++ SW1B_MODE(SWX_MODE_NO_PULSE_SKIP) | ++ SW1B_MODE_STANDBY(SWX_MODE_NO_PULSE_SKIP) | ++ SW1B_SOFTSTART | ++ SW_PLL_FACTOR(32) ++ ); ++ ++ return 0; ++} ++ ++ssize_t pmic_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ int i = count >> 2; ++ uint32_t *buf = _buf; ++ ++ offset >>= 2; ++ ++ while (i) { ++ *buf = pmic_read_reg(pmic_device, offset); ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++ssize_t pmic_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ int i = count >> 2; ++ const uint32_t *buf = _buf; ++ ++ offset >>= 2; ++ ++ while (i) { ++ pmic_write_reg(pmic_device, offset, *buf); ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static struct file_operations pmic_fops = { ++ .lseek = dev_lseek_default, ++ .read = pmic_read, ++ .write = pmic_write, ++}; ++ ++static int pmic_probe(struct device_d *dev) ++{ ++ struct spi_device *spi = (struct spi_device *)dev->type_data; ++ ++ if (pmic_device) ++ return -EBUSY; ++ ++ pmic_device = xzalloc(sizeof(*pmic_device)); ++ ++ pmic_device->cdev.name = "pmic"; ++ pmic_device->cdev.size = 256; ++ pmic_device->cdev.dev = dev; ++ pmic_device->cdev.ops = &pmic_fops; ++ ++ spi->mode = SPI_MODE_0 | SPI_CS_HIGH; ++ spi->bits_per_word = 32; ++ pmic_device->spi = spi; ++ ++ devfs_create(&pmic_device->cdev); ++ ++ return 0; ++} ++ ++static struct driver_d pmic_driver = { ++ .name = "mc13783", ++ .probe = pmic_probe, ++}; ++ ++static int pmic_init(void) ++{ ++ register_driver(&pmic_driver); ++ return 0; ++} ++ ++device_initcall(pmic_init); ++ +diff --git a/drivers/mfd/mc13892.c b/drivers/mfd/mc13892.c +new file mode 100644 +index 0000000..08a439b +--- /dev/null ++++ b/drivers/mfd/mc13892.c +@@ -0,0 +1,327 @@ ++/* ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * 2009 Marc Kleine-Budde <mkl@pengutronix.de> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <driver.h> ++#include <xfuncs.h> ++#include <errno.h> ++#include <spi/spi.h> ++#include <malloc.h> ++ ++#include <i2c/i2c.h> ++#include <mfd/mc13892.h> ++ ++#define DRIVERNAME "mc13892" ++ ++#define to_mc13892(a) container_of(a, struct mc13892, cdev) ++ ++static struct mc13892 *mc_dev; ++ ++struct mc13892 *mc13892_get(void) ++{ ++ if (!mc_dev) ++ return NULL; ++ ++ return mc_dev; ++} ++EXPORT_SYMBOL(mc13892_get); ++ ++#ifdef CONFIG_SPI ++static int spi_rw(struct spi_device *spi, void * buf, size_t len) ++{ ++ int ret; ++ ++ struct spi_transfer t = { ++ .tx_buf = (const void *)buf, ++ .rx_buf = buf, ++ .len = len, ++ .cs_change = 0, ++ .delay_usecs = 0, ++ }; ++ struct spi_message m; ++ ++ spi_message_init(&m); ++ spi_message_add_tail(&t, &m); ++ ++ if ((ret = spi_sync(spi, &m))) ++ return ret; ++ return 0; ++} ++ ++#define MXC_PMIC_REG_NUM(reg) (((reg) & 0x3f) << 25) ++#define MXC_PMIC_WRITE (1 << 31) ++ ++static int mc13892_spi_reg_read(struct mc13892 *mc13892, enum mc13892_reg reg, u32 *val) ++{ ++ uint32_t buf; ++ ++ buf = MXC_PMIC_REG_NUM(reg); ++ ++ spi_rw(mc13892->spi, &buf, 4); ++ ++ *val = buf; ++ ++ return 0; ++} ++ ++static int mc13892_spi_reg_write(struct mc13892 *mc13892, enum mc13892_reg reg, u32 val) ++{ ++ uint32_t buf = MXC_PMIC_REG_NUM(reg) | MXC_PMIC_WRITE | (val & 0xffffff); ++ ++ spi_rw(mc13892->spi, &buf, 4); ++ ++ return 0; ++} ++#endif ++ ++#ifdef CONFIG_I2C ++static int mc13892_i2c_reg_read(struct mc13892 *mc13892, enum mc13892_reg reg, u32 *val) ++{ ++ u8 buf[3]; ++ int ret; ++ ++ ret = i2c_read_reg(mc13892->client, reg, buf, 3); ++ *val = buf[0] << 16 | buf[1] << 8 | buf[2] << 0; ++ ++ return ret == 3 ? 0 : ret; ++} ++ ++static int mc13892_i2c_reg_write(struct mc13892 *mc13892, enum mc13892_reg reg, u32 val) ++{ ++ u8 buf[] = { ++ val >> 16, ++ val >> 8, ++ val >> 0, ++ }; ++ int ret; ++ ++ ret = i2c_write_reg(mc13892->client, reg, buf, 3); ++ ++ return ret == 3 ? 0 : ret; ++} ++#endif ++ ++int mc13892_reg_write(struct mc13892 *mc13892, enum mc13892_reg reg, u32 val) ++{ ++#ifdef CONFIG_I2C ++ if (mc13892->mode == MC13892_MODE_I2C) ++ return mc13892_i2c_reg_write(mc13892, reg, val); ++#endif ++#ifdef CONFIG_SPI ++ if (mc13892->mode == MC13892_MODE_SPI) ++ return mc13892_spi_reg_write(mc13892, reg, val); ++#endif ++ return -EINVAL; ++} ++EXPORT_SYMBOL(mc13892_reg_write) ++ ++int mc13892_reg_read(struct mc13892 *mc13892, enum mc13892_reg reg, u32 *val) ++{ ++#ifdef CONFIG_I2C ++ if (mc13892->mode == MC13892_MODE_I2C) ++ return mc13892_i2c_reg_read(mc13892, reg, val); ++#endif ++#ifdef CONFIG_SPI ++ if (mc13892->mode == MC13892_MODE_SPI) ++ return mc13892_spi_reg_read(mc13892, reg, val); ++#endif ++ return -EINVAL; ++} ++EXPORT_SYMBOL(mc13892_reg_read) ++ ++int mc13892_set_bits(struct mc13892 *mc13892, enum mc13892_reg reg, u32 mask, u32 val) ++{ ++ u32 tmp; ++ int err; ++ ++ err = mc13892_reg_read(mc13892, reg, &tmp); ++ tmp = (tmp & ~mask) | val; ++ ++ if (!err) ++ err = mc13892_reg_write(mc13892, reg, tmp); ++ ++ return err; ++} ++EXPORT_SYMBOL(mc13892_set_bits); ++ ++static ssize_t mc_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ struct mc13892 *priv = to_mc13892(cdev); ++ u32 *buf = _buf; ++ size_t i = count >> 2; ++ int err; ++ ++ offset >>= 2; ++ ++ while (i) { ++ err = mc13892_reg_read(priv, offset, buf); ++ if (err) ++ return (ssize_t)err; ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static ssize_t mc_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ struct mc13892 *mc13892 = to_mc13892(cdev); ++ const u32 *buf = _buf; ++ size_t i = count >> 2; ++ int err; ++ ++ offset >>= 2; ++ ++ while (i) { ++ err = mc13892_reg_write(mc13892, offset, *buf); ++ if (err) ++ return (ssize_t)err; ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static struct file_operations mc_fops = { ++ .lseek = dev_lseek_default, ++ .read = mc_read, ++ .write = mc_write, ++}; ++ ++struct mc13892_rev { ++ u16 rev_id; ++ enum mc13892_revision rev; ++ char *revstr; ++}; ++ ++static struct mc13892_rev mc13892_revisions[] = { ++ { 0x01, MC13892_REVISION_1_0, "1.0" }, ++ { 0x09, MC13892_REVISION_1_1, "1.1" }, ++ { 0x0a, MC13892_REVISION_1_2, "1.2" }, ++ { 0x10, MC13892_REVISION_2_0, "2.0" }, ++ { 0x11, MC13892_REVISION_2_1, "2.1" }, ++ { 0x18, MC13892_REVISION_3_0, "3.0" }, ++ { 0x19, MC13892_REVISION_3_1, "3.1" }, ++ { 0x1a, MC13892_REVISION_3_2, "3.2" }, ++ { 0x02, MC13892_REVISION_3_2a, "3.2a" }, ++ { 0x1b, MC13892_REVISION_3_3, "3.3" }, ++ { 0x1d, MC13892_REVISION_3_5, "3.5" }, ++}; ++ ++static int mc13893_query_revision(struct mc13892 *mc13892) ++{ ++ unsigned int rev_id; ++ char *revstr; ++ int rev, i; ++ ++ mc13892_reg_read(mc13892, 7, &rev_id); ++ ++ for (i = 0; i < ARRAY_SIZE(mc13892_revisions); i++) ++ if ((rev_id & 0x1f) == mc13892_revisions[i].rev_id) ++ break; ++ ++ if (i == ARRAY_SIZE(mc13892_revisions)) ++ return -EINVAL; ++ ++ rev = mc13892_revisions[i].rev; ++ revstr = mc13892_revisions[i].revstr; ++ ++ if (rev == MC13892_REVISION_2_0) { ++ if ((rev_id >> 9) & 0x3) { ++ rev = MC13892_REVISION_2_0a; ++ revstr = "2.0a"; ++ } ++ } ++ ++ dev_info(mc_dev->cdev.dev, "PMIC ID: 0x%08x [Rev: %s]\n", ++ rev_id, revstr); ++ ++ mc13892->revision = rev; ++ ++ return rev; ++} ++ ++static int mc_probe(struct device_d *dev, enum mc13892_mode mode) ++{ ++ int rev; ++ ++ if (mc_dev) ++ return -EBUSY; ++ ++ mc_dev = xzalloc(sizeof(struct mc13892)); ++ mc_dev->mode = mode; ++ mc_dev->cdev.name = DRIVERNAME; ++ if (mode == MC13892_MODE_I2C) { ++ mc_dev->client = to_i2c_client(dev); ++ } ++ if (mode == MC13892_MODE_SPI) { ++ mc_dev->spi = dev->type_data; ++ mc_dev->spi->mode = SPI_MODE_0 | SPI_CS_HIGH; ++ mc_dev->spi->bits_per_word = 32; ++ } ++ mc_dev->cdev.size = 256; ++ mc_dev->cdev.dev = dev; ++ mc_dev->cdev.ops = &mc_fops; ++ ++ rev = mc13893_query_revision(mc_dev); ++ if (rev < 0) { ++ free(mc_dev); ++ return -EINVAL; ++ } ++ ++ devfs_create(&mc_dev->cdev); ++ ++ return 0; ++} ++ ++static int mc_i2c_probe(struct device_d *dev) ++{ ++ return mc_probe(dev, MC13892_MODE_I2C); ++} ++ ++static int mc_spi_probe(struct device_d *dev) ++{ ++ return mc_probe(dev, MC13892_MODE_SPI); ++} ++ ++static struct driver_d mc_i2c_driver = { ++ .name = "mc13892-i2c", ++ .probe = mc_i2c_probe, ++}; ++ ++static struct driver_d mc_spi_driver = { ++ .name = "mc13892-spi", ++ .probe = mc_spi_probe, ++}; ++ ++static int mc_init(void) ++{ ++ register_driver(&mc_i2c_driver); ++ register_driver(&mc_spi_driver); ++ return 0; ++} ++ ++device_initcall(mc_init); +diff --git a/drivers/mfd/mc34704.c b/drivers/mfd/mc34704.c +new file mode 100644 +index 0000000..a2171b3 +--- /dev/null ++++ b/drivers/mfd/mc34704.c +@@ -0,0 +1,140 @@ ++/* ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * 2009 Marc Kleine-Budde <mkl@pengutronix.de> ++ * Copyright (C) 2010 Baruch Siach <baruch@tkos.co.il> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <driver.h> ++#include <xfuncs.h> ++#include <errno.h> ++ ++#include <i2c/i2c.h> ++#include <mfd/mc34704.h> ++ ++#define DRIVERNAME "mc34704" ++ ++#define to_mc34704(a) container_of(a, struct mc34704, cdev) ++ ++static struct mc34704 *mc34704_dev; ++ ++struct mc34704 *mc34704_get(void) ++{ ++ if (!mc34704_dev) ++ return NULL; ++ ++ return mc34704_dev; ++} ++EXPORT_SYMBOL(mc34704_get); ++ ++int mc34704_reg_read(struct mc34704 *mc34704, u8 reg, u8 *val) ++{ ++ int ret; ++ ++ ret = i2c_read_reg(mc34704->client, reg, val, 1); ++ ++ return ret == 1 ? 0 : ret; ++} ++EXPORT_SYMBOL(mc34704_reg_read) ++ ++int mc34704_reg_write(struct mc34704 *mc34704, u8 reg, u8 val) ++{ ++ int ret; ++ ++ ret = i2c_write_reg(mc34704->client, reg, &val, 1); ++ ++ return ret == 1 ? 0 : ret; ++} ++EXPORT_SYMBOL(mc34704_reg_write) ++ ++static ssize_t mc34704_read(struct cdev *cdev, void *_buf, size_t count, ++ ulong offset, ulong flags) ++{ ++ struct mc34704 *priv = to_mc34704(cdev); ++ u8 *buf = _buf; ++ size_t i = count; ++ int err; ++ ++ while (i) { ++ err = mc34704_reg_read(priv, offset, buf); ++ if (err) ++ return (ssize_t)err; ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static ssize_t mc34704_write(struct cdev *cdev, const void *_buf, size_t count, ++ ulong offset, ulong flags) ++{ ++ struct mc34704 *mc34704 = to_mc34704(cdev); ++ const u8 *buf = _buf; ++ size_t i = count; ++ int err; ++ ++ while (i) { ++ err = mc34704_reg_write(mc34704, offset, *buf); ++ if (err) ++ return (ssize_t)err; ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static struct file_operations mc34704_fops = { ++ .lseek = dev_lseek_default, ++ .read = mc34704_read, ++ .write = mc34704_write, ++}; ++ ++static int mc34704_probe(struct device_d *dev) ++{ ++ if (mc34704_dev) ++ return -EBUSY; ++ ++ mc34704_dev = xzalloc(sizeof(struct mc34704)); ++ mc34704_dev->cdev.name = DRIVERNAME; ++ mc34704_dev->client = to_i2c_client(dev); ++ mc34704_dev->cdev.size = 256; ++ mc34704_dev->cdev.dev = dev; ++ mc34704_dev->cdev.ops = &mc34704_fops; ++ ++ devfs_create(&mc34704_dev->cdev); ++ ++ return 0; ++} ++ ++static struct driver_d mc34704_driver = { ++ .name = DRIVERNAME, ++ .probe = mc34704_probe, ++}; ++ ++static int mc34704_init(void) ++{ ++ register_driver(&mc34704_driver); ++ return 0; ++} ++device_initcall(mc34704_init); +diff --git a/drivers/mfd/mc9sdz60.c b/drivers/mfd/mc9sdz60.c +new file mode 100644 +index 0000000..db208ec +--- /dev/null ++++ b/drivers/mfd/mc9sdz60.c +@@ -0,0 +1,153 @@ ++/* ++ * Copyright (C) 2007 Sascha Hauer, Pengutronix ++ * 2009 Marc Kleine-Budde <mkl@pengutronix.de> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <driver.h> ++#include <xfuncs.h> ++#include <errno.h> ++ ++#include <i2c/i2c.h> ++#include <mfd/mc9sdz60.h> ++ ++#define DRIVERNAME "mc9sdz60" ++ ++#define to_mc9sdz60(a) container_of(a, struct mc9sdz60, cdev) ++ ++static struct mc9sdz60 *mc_dev; ++ ++struct mc9sdz60 *mc9sdz60_get(void) ++{ ++ if (!mc_dev) ++ return NULL; ++ ++ return mc_dev; ++} ++EXPORT_SYMBOL(mc9sdz60_get); ++ ++int mc9sdz60_reg_read(struct mc9sdz60 *mc9sdz60, enum mc9sdz60_reg reg, u8 *val) ++{ ++ int ret; ++ ++ ret = i2c_read_reg(mc9sdz60->client, reg, val, 1); ++ ++ return ret == 1 ? 0 : ret; ++} ++EXPORT_SYMBOL(mc9sdz60_reg_read) ++ ++int mc9sdz60_reg_write(struct mc9sdz60 *mc9sdz60, enum mc9sdz60_reg reg, u8 val) ++{ ++ int ret; ++ ++ ret = i2c_write_reg(mc9sdz60->client, reg, &val, 1); ++ ++ return ret == 1 ? 0 : ret; ++} ++EXPORT_SYMBOL(mc9sdz60_reg_write) ++ ++int mc9sdz60_set_bits(struct mc9sdz60 *mc9sdz60, enum mc9sdz60_reg reg, u8 mask, u8 val) ++{ ++ u8 tmp; ++ int err; ++ ++ err = mc9sdz60_reg_read(mc9sdz60, reg, &tmp); ++ tmp = (tmp & ~mask) | val; ++ ++ if (!err) ++ err = mc9sdz60_reg_write(mc9sdz60, reg, tmp); ++ ++ return err; ++} ++EXPORT_SYMBOL(mc9sdz60_set_bits); ++ ++static ssize_t mc_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ struct mc9sdz60 *mc9sdz60 = to_mc9sdz60(cdev); ++ u8 *buf = _buf; ++ size_t i = count; ++ int err; ++ ++ while (i) { ++ err = mc9sdz60_reg_read(mc9sdz60, offset, buf); ++ if (err) ++ return (ssize_t)err; ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static ssize_t mc_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ struct mc9sdz60 *mc9sdz60 = to_mc9sdz60(cdev); ++ const u8 *buf = _buf; ++ size_t i = count; ++ int err; ++ ++ while (i) { ++ err = mc9sdz60_reg_write(mc9sdz60, offset, *buf); ++ if (err) ++ return (ssize_t)err; ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static struct file_operations mc_fops = { ++ .lseek = dev_lseek_default, ++ .read = mc_read, ++ .write = mc_write, ++}; ++ ++static int mc_probe(struct device_d *dev) ++{ ++ if (mc_dev) ++ return -EBUSY; ++ ++ mc_dev = xzalloc(sizeof(struct mc9sdz60)); ++ mc_dev->cdev.name = DRIVERNAME; ++ mc_dev->client = to_i2c_client(dev); ++ mc_dev->cdev.size = 64; /* 35 known registers */ ++ mc_dev->cdev.dev = dev; ++ mc_dev->cdev.ops = &mc_fops; ++ ++ devfs_create(&mc_dev->cdev); ++ ++ return 0; ++} ++ ++static struct driver_d mc_driver = { ++ .name = DRIVERNAME, ++ .probe = mc_probe, ++}; ++ ++static int mc_init(void) ++{ ++ register_driver(&mc_driver); ++ return 0; ++} ++ ++device_initcall(mc_init); +diff --git a/drivers/mfd/twl4030.c b/drivers/mfd/twl4030.c +new file mode 100644 +index 0000000..81bf48b +--- /dev/null ++++ b/drivers/mfd/twl4030.c +@@ -0,0 +1,186 @@ ++/* ++ * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de> ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <driver.h> ++#include <xfuncs.h> ++#include <errno.h> ++ ++#include <i2c/i2c.h> ++#include <mfd/twl4030.h> ++ ++#define DRIVERNAME "twl4030" ++ ++#define to_twl4030(a) container_of(a, struct twl4030, cdev) ++ ++static struct twl4030 *twl_dev; ++ ++struct twl4030 *twl4030_get(void) ++{ ++ if (!twl_dev) ++ return NULL; ++ ++ return twl_dev; ++} ++EXPORT_SYMBOL(twl4030_get); ++ ++int twl4030_reg_read(struct twl4030 *twl4030, u16 reg, u8 *val) ++{ ++ int ret; ++ struct i2c_msg xfer_msg[2]; ++ struct i2c_msg *msg; ++ int i2c_addr; ++ unsigned char buf = reg & 0xff; ++ ++ i2c_addr = twl4030->client->addr + (reg / 0x100); ++ ++ /* [MSG1] fill the register address data */ ++ msg = &xfer_msg[0]; ++ msg->addr = i2c_addr; ++ msg->len = 1; ++ msg->flags = 0; /* Read the register value */ ++ msg->buf = &buf; ++ /* [MSG2] fill the data rx buffer */ ++ msg = &xfer_msg[1]; ++ msg->addr = i2c_addr; ++ msg->flags = I2C_M_RD; /* Read the register value */ ++ msg->len = 1; /* only n bytes */ ++ msg->buf = val; ++ ret = i2c_transfer(twl4030->client->adapter, xfer_msg, 2); ++ ++ /* i2c_transfer returns number of messages transferred */ ++ if (ret < 0) { ++ pr_err("%s: failed to transfer all messages: %s\n", __func__, strerror(-ret)); ++ return ret; ++ } ++ return 0; ++} ++EXPORT_SYMBOL(twl4030_reg_read) ++ ++int twl4030_reg_write(struct twl4030 *twl4030, u16 reg, u8 val) ++{ ++ int ret; ++ struct i2c_msg xfer_msg[1]; ++ struct i2c_msg *msg; ++ int i2c_addr; ++ u8 buf[2]; ++ ++ buf[0] = reg & 0xff; ++ buf[1] = val; ++ ++ i2c_addr = twl4030->client->addr + (reg / 0x100); ++ ++ /* ++ * [MSG1]: fill the register address data ++ * fill the data Tx buffer ++ */ ++ msg = xfer_msg; ++ msg->addr = i2c_addr; ++ msg->len = 2; ++ msg->flags = 0; ++ msg->buf = buf; ++ /* over write the first byte of buffer with the register address */ ++ ret = i2c_transfer(twl4030->client->adapter, xfer_msg, 1); ++ ++ /* i2c_transfer returns number of messages transferred */ ++ if (ret < 0) { ++ pr_err("%s: failed to transfer all messages: %s\n", __func__, strerror(-ret)); ++ return ret; ++ } ++ return 0; ++} ++EXPORT_SYMBOL(twl4030_reg_write) ++ ++int twl4030_set_bits(struct twl4030 *twl4030, enum twl4030_reg reg, u8 mask, u8 val) ++{ ++ u8 tmp; ++ int err; ++ ++ err = twl4030_reg_read(twl4030, reg, &tmp); ++ tmp = (tmp & ~mask) | val; ++ ++ if (!err) ++ err = twl4030_reg_write(twl4030, reg, tmp); ++ ++ return err; ++} ++EXPORT_SYMBOL(twl4030_set_bits); ++ ++static ssize_t twl_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ struct twl4030 *priv = to_twl4030(cdev); ++ u8 *buf = _buf; ++ size_t i = count; ++ int err; ++ ++ while (i) { ++ err = twl4030_reg_read(priv, offset, buf); ++ if (err) ++ return (ssize_t)err; ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static ssize_t twl_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags) ++{ ++ struct twl4030 *twl4030 = to_twl4030(cdev); ++ const u8 *buf = _buf; ++ size_t i = count; ++ int err; ++ ++ while (i) { ++ err = twl4030_reg_write(twl4030, offset, *buf); ++ if (err) ++ return (ssize_t)err; ++ buf++; ++ i--; ++ offset++; ++ } ++ ++ return count; ++} ++ ++static struct file_operations twl_fops = { ++ .lseek = dev_lseek_default, ++ .read = twl_read, ++ .write = twl_write, ++}; ++ ++static int twl_probe(struct device_d *dev) ++{ ++ if (twl_dev) ++ return -EBUSY; ++ ++ twl_dev = xzalloc(sizeof(struct twl4030)); ++ twl_dev->cdev.name = DRIVERNAME; ++ twl_dev->client = to_i2c_client(dev); ++ twl_dev->cdev.size = 1024; ++ twl_dev->cdev.dev = dev; ++ twl_dev->cdev.ops = &twl_fops; ++ ++ devfs_create(&twl_dev->cdev); ++ ++ return 0; ++} ++ ++static struct driver_d twl_driver = { ++ .name = DRIVERNAME, ++ .probe = twl_probe, ++}; ++ ++static int twl_init(void) ++{ ++ register_driver(&twl_driver); ++ return 0; ++} ++ ++device_initcall(twl_init); +diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig +index 475499a..034bb6f 100644 +--- a/drivers/mtd/nand/Kconfig ++++ b/drivers/mtd/nand/Kconfig +@@ -11,12 +11,28 @@ if NAND + config NAND_IMX + bool + prompt "i.MX NAND driver" +- depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35 || ARCH_IMX25 ++ depends on ARCH_IMX21 || ARCH_IMX27 || ARCH_IMX31 || ARCH_IMX35 || ARCH_IMX25 || ARCH_IMX51 + + config NAND_IMX_BOOT + bool + prompt "Support Starting barebox from NAND" +- depends on NAND_IMX || NAND_IMX_V2 ++ depends on NAND_IMX && !ARCH_IMX51 ++ ++choice ++ depends on NAND_IMX_BOOT ++ default NAND_IMX_BOOT_512_2K ++ prompt "select nand pagesize you want to support booting from" ++ ++config NAND_IMX_BOOT_512 ++ bool "512 byte page size" ++ ++config NAND_IMX_BOOT_2K ++ bool "2048 byte page size" ++ ++config NAND_IMX_BOOT_512_2K ++ bool "512 byte and 2048 byte pagesize" ++ ++endchoice + + config NAND_OMAP_GPMC + tristate "NAND Flash Support for GPMC based OMAP platforms" +diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c +index b75a450..56fafb0 100644 +--- a/drivers/mtd/nand/nand_base.c ++++ b/drivers/mtd/nand/nand_base.c +@@ -2215,6 +2215,12 @@ static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd, + /* Select the device */ + chip->select_chip(mtd, 0); + ++ /* ++ * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx) ++ * after power-up ++ */ ++ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); ++ + /* Send the command for reading device ID */ + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1); + +diff --git a/drivers/mtd/nand/nand_imx.c b/drivers/mtd/nand/nand_imx.c +index 5454e32..9a15ab2 100644 +--- a/drivers/mtd/nand/nand_imx.c ++++ b/drivers/mtd/nand/nand_imx.c +@@ -30,103 +30,107 @@ + #include <asm/io.h> + #include <errno.h> + +-#define DVR_VER "2.0" +- + #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35()) + #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21()) ++#define nfc_is_v3_2() cpu_is_mx51() ++#define nfc_is_v3() nfc_is_v3_2() ++ ++#define NFC_V1_ECC_STATUS_RESULT 0x0c ++#define NFC_V1_RSLTMAIN_AREA 0x0e ++#define NFC_V1_RSLTSPARE_AREA 0x10 ++ ++#define NFC_V2_ECC_STATUS_RESULT1 0x0c ++#define NFC_V2_ECC_STATUS_RESULT2 0x0e ++#define NFC_V2_SPAS 0x10 ++ ++#define NFC_V1_V2_BUF_SIZE 0x00 ++#define NFC_V1_V2_BUF_ADDR 0x04 ++#define NFC_V1_V2_FLASH_ADDR 0x06 ++#define NFC_V1_V2_FLASH_CMD 0x08 ++#define NFC_V1_V2_CONFIG 0x0a ++ ++#define NFC_V1_V2_WRPROT 0x12 ++#define NFC_V1_UNLOCKSTART_BLKADDR 0x14 ++#define NFC_V1_UNLOCKEND_BLKADDR 0x16 ++#define NFC_V21_UNLOCKSTART_BLKADDR 0x20 ++#define NFC_V21_UNLOCKEND_BLKADDR 0x22 ++#define NFC_V1_V2_NF_WRPRST 0x18 ++#define NFC_V1_V2_CONFIG1 0x1a ++#define NFC_V1_V2_CONFIG2 0x1c ++ ++#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0) ++#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2) ++#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3) ++#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4) ++#define NFC_V1_V2_CONFIG1_BIG (1 << 5) ++#define NFC_V1_V2_CONFIG1_RST (1 << 6) ++#define NFC_V1_V2_CONFIG1_CE (1 << 7) ++#define NFC_V1_V2_CONFIG1_ONE_CYCLE (1 << 8) ++#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9) ++#define NFC_V2_CONFIG1_FP_INT (1 << 11) ++ ++#define NFC_V1_V2_CONFIG2_INT (1 << 15) ++ ++#define NFC_V2_SPAS_SPARESIZE(spas) ((spas) >> 1) + + /* +- * Addresses for NFC registers ++ * Operation modes for the NFC. Valid for v1, v2 and v3 ++ * type controllers. + */ +-#define NFC_BUF_SIZE 0xE00 +-#define NFC_BUF_ADDR 0xE04 +-#define NFC_FLASH_ADDR 0xE06 +-#define NFC_FLASH_CMD 0xE08 +-#define NFC_CONFIG 0xE0A +-#define NFC_ECC_STATUS_RESULT 0xE0C +-#define NFC_RSLTMAIN_AREA 0xE0E +-#define NFC_RSLTSPARE_AREA 0xE10 +-#define NFC_SPAS 0xe10 +-#define NFC_WRPROT 0xE12 +-#define NFC_V1_UNLOCKSTART_BLKADDR 0xe14 +-#define NFC_V1_UNLOCKEND_BLKADDR 0xe16 +-#define NFC_V21_UNLOCKSTART_BLKADDR 0xe20 +-#define NFC_V21_UNLOCKEND_BLKADDR 0xe22 +-#define NFC_NF_WRPRST 0xE18 +-#define NFC_CONFIG1 0xE1A +-#define NFC_CONFIG2 0xE1C +- +-/* +- * Addresses for NFC RAM BUFFER Main area 0 +- */ +-#define MAIN_AREA0 0x000 +-#define MAIN_AREA1 0x200 +-#define MAIN_AREA2 0x400 +-#define MAIN_AREA3 0x600 +- +-/* +- * Addresses for NFC SPARE BUFFER Spare area 0 +- */ +-#define SPARE_AREA0 0x800 +-#define SPARE_AREA1 0x810 +-#define SPARE_AREA2 0x820 +-#define SPARE_AREA3 0x830 +- +-/* +- * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command +- * operation +- */ +-#define NFC_CMD 0x1 +- +-/* +- * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address +- * operation +- */ +-#define NFC_ADDR 0x2 +- +-/* +- * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input +- * operation +- */ +-#define NFC_INPUT 0x4 +- +-/* +- * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data Output +- * operation +- */ +-#define NFC_OUTPUT 0x8 +- +-/* +- * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID +- * operation +- */ +-#define NFC_ID 0x10 +- +-/* +- * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read Status +- * operation +- */ +-#define NFC_STATUS 0x20 +- +-/* +- * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status +- * operation +- */ +-#define NFC_INT 0x8000 +- +-#define NFC_ECC_MODE (1 << 0) +-#define NFC_SP_EN (1 << 2) +-#define NFC_ECC_EN (1 << 3) +-#define NFC_INT_MSK (1 << 4) +-#define NFC_BIG (1 << 5) +-#define NFC_RST (1 << 6) +-#define NFC_CE (1 << 7) +-#define NFC_ONE_CYCLE (1 << 8) +- +-#define NFC_SPAS_16 8 +-#define NFC_SPAS_64 32 +-#define NFC_SPAS_128 64 +-#define NFC_SPAS_218 109 ++#define NFC_CMD (1 << 0) ++#define NFC_ADDR (1 << 1) ++#define NFC_INPUT (1 << 2) ++#define NFC_OUTPUT (1 << 3) ++#define NFC_ID (1 << 4) ++#define NFC_STATUS (1 << 5) ++ ++#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00) ++#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04) ++ ++#define NFC_V3_CONFIG1 (host->regs_axi + 0x34) ++#define NFC_V3_CONFIG1_SP_EN (1 << 0) ++#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4) ++ ++#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38) ++ ++#define NFC_V3_LAUNCH (host->regs_axi + 0x40) ++ ++#define NFC_V3_WRPROT (host->regs_ip + 0x0) ++#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0) ++#define NFC_V3_WRPROT_LOCK (1 << 1) ++#define NFC_V3_WRPROT_UNLOCK (1 << 2) ++#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6) ++ ++#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04) ++ ++#define NFC_V3_CONFIG2 (host->regs_ip + 0x24) ++#define NFC_V3_CONFIG2_PS_512 (0 << 0) ++#define NFC_V3_CONFIG2_PS_2048 (1 << 0) ++#define NFC_V3_CONFIG2_PS_4096 (2 << 0) ++#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2) ++#define NFC_V3_CONFIG2_ECC_EN (1 << 3) ++#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4) ++#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5) ++#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6) ++#define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7) ++#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12) ++#define NFC_V3_CONFIG2_INT_MSK (1 << 15) ++#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24) ++#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16) ++ ++#define NFC_V3_CONFIG3 (host->regs_ip + 0x28) ++#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0) ++#define NFC_V3_CONFIG3_FW8 (1 << 3) ++#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8) ++#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12) ++#define NFC_V3_CONFIG3_RBB_MODE (1 << 15) ++#define NFC_V3_CONFIG3_NO_SDMA (1 << 20) ++ ++#define NFC_V3_IPC (host->regs_ip + 0x2C) ++#define NFC_V3_IPC_CREQ (1 << 0) ++#define NFC_V3_IPC_INT (1 << 31) ++ ++#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34) + + #ifdef CONFIG_NAND_IMX_BOOT + #define __nand_boot_init __bare_init +@@ -142,10 +146,11 @@ struct imx_nand_host { + + void *spare0; + void *main_area0; +- void *main_area1; + + void __iomem *base; + void __iomem *regs; ++ void __iomem *regs_axi; ++ void __iomem *regs_ip; + int status_request; + struct clk *clk; + +@@ -153,7 +158,15 @@ struct imx_nand_host { + uint8_t *data_buf; + unsigned int buf_start; + int spare_len; +- ++ int eccsize; ++ ++ void (*preset)(struct mtd_info *); ++ void (*send_cmd)(struct imx_nand_host *, uint16_t); ++ void (*send_addr)(struct imx_nand_host *, uint16_t); ++ void (*send_page)(struct imx_nand_host *, unsigned int); ++ void (*send_read_id)(struct imx_nand_host *); ++ uint16_t (*get_dev_status)(struct imx_nand_host *); ++ int (*check_int)(struct imx_nand_host *); + }; + + /* +@@ -215,16 +228,35 @@ static void memcpy32(void *trg, const void *src, int size) + *t++ = *s++; + } + +-/* +- * This function polls the NANDFC to wait for the basic operation to complete by +- * checking the INT bit of config2 register. +- * +- * @param max_retries number of retry attempts (separated by 1 us) +- * @param param parameter for debug +- */ +-static void __nand_boot_init wait_op_done(struct imx_nand_host *host) ++static int check_int_v3(struct imx_nand_host *host) ++{ ++ uint32_t tmp; ++ ++ tmp = readl(NFC_V3_IPC); ++ if (!(tmp & NFC_V3_IPC_INT)) ++ return 0; ++ ++ tmp &= ~NFC_V3_IPC_INT; ++ writel(tmp, NFC_V3_IPC); ++ ++ return 1; ++} ++ ++static int check_int_v1_v2(struct imx_nand_host *host) ++{ ++ uint32_t tmp; ++ ++ tmp = readw(host->regs + NFC_V1_V2_CONFIG2); ++ if (!(tmp & NFC_V1_V2_CONFIG2_INT)) ++ return 0; ++ ++ writew(tmp & ~NFC_V1_V2_CONFIG2_INT, host->regs + NFC_V1_V2_CONFIG2); ++ ++ return 1; ++} ++ ++static void wait_op_done(struct imx_nand_host *host) + { +- u32 tmp; + int i; + + /* This is a timeout of roughly 15ms on my system. We +@@ -232,12 +264,8 @@ static void __nand_boot_init wait_op_done(struct imx_nand_host *host) + * here as we might be here from nand booting. + */ + for (i = 0; i < 100000; i++) { +- if (readw(host->regs + NFC_CONFIG2) & NFC_INT) { +- tmp = readw(host->regs + NFC_CONFIG2); +- tmp &= ~NFC_INT; +- writew(tmp, host->regs + NFC_CONFIG2); ++ if (host->check_int(host)) + return; +- } + } + } + +@@ -247,19 +275,31 @@ static void __nand_boot_init wait_op_done(struct imx_nand_host *host) + * + * @param cmd command for NAND Flash + */ +-static void __nand_boot_init send_cmd(struct imx_nand_host *host, u16 cmd) ++static void send_cmd_v3(struct imx_nand_host *host, uint16_t cmd) ++{ ++ /* fill command */ ++ writel(cmd, NFC_V3_FLASH_CMD); ++ ++ /* send out command */ ++ writel(NFC_CMD, NFC_V3_LAUNCH); ++ ++ /* Wait for operation to complete */ ++ wait_op_done(host); ++} ++ ++static void send_cmd_v1_v2(struct imx_nand_host *host, u16 cmd) + { + MTD_DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd); + +- writew(cmd, host->regs + NFC_FLASH_CMD); +- writew(NFC_CMD, host->regs + NFC_CONFIG2); ++ writew(cmd, host->regs + NFC_V1_V2_FLASH_CMD); ++ writew(NFC_CMD, host->regs + NFC_V1_V2_CONFIG2); + + if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) { + /* Reset completion is indicated by NFC_CONFIG2 */ + /* being set to 0 */ + int i; + for (i = 0; i < 100000; i++) { +- if (readw(host->regs + NFC_CONFIG2) == 0) { ++ if (readw(host->regs + NFC_V1_V2_CONFIG2) == 0) { + break; + } + } +@@ -276,12 +316,23 @@ static void __nand_boot_init send_cmd(struct imx_nand_host *host, u16 cmd) + * @param addr address to be written to NFC. + * @param islast True if this is the last address cycle for command + */ +-static void __nand_boot_init noinline send_addr(struct imx_nand_host *host, u16 addr) ++static void send_addr_v3(struct imx_nand_host *host, uint16_t addr) ++{ ++ /* fill address */ ++ writel(addr, NFC_V3_FLASH_ADDR0); ++ ++ /* send out address */ ++ writel(NFC_ADDR, NFC_V3_LAUNCH); ++ ++ wait_op_done(host); ++} ++ ++static void send_addr_v1_v2(struct imx_nand_host *host, u16 addr) + { + MTD_DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast); + +- writew(addr, host->regs + NFC_FLASH_ADDR); +- writew(NFC_ADDR, host->regs + NFC_CONFIG2); ++ writew(addr, host->regs + NFC_V1_V2_FLASH_ADDR); ++ writew(NFC_ADDR, host->regs + NFC_V1_V2_CONFIG2); + + /* Wait for operation to complete */ + wait_op_done(host); +@@ -294,7 +345,21 @@ static void __nand_boot_init noinline send_addr(struct imx_nand_host *host, u16 + * @param buf_id Specify Internal RAM Buffer number (0-3) + * @param spare_only set true if only the spare area is transferred + */ +-static void __nand_boot_init send_page(struct imx_nand_host *host, ++static void send_page_v3(struct imx_nand_host *host, unsigned int ops) ++{ ++ uint32_t tmp; ++ ++ tmp = readl(NFC_V3_CONFIG1); ++ tmp &= ~(7 << 4); ++ writel(tmp, NFC_V3_CONFIG1); ++ ++ /* transfer data from NFC ram to nand */ ++ writel(ops, NFC_V3_LAUNCH); ++ ++ wait_op_done(host); ++} ++ ++static void send_page_v1_v2(struct imx_nand_host *host, + unsigned int ops) + { + int bufs, i; +@@ -306,9 +371,9 @@ static void __nand_boot_init send_page(struct imx_nand_host *host, + + for (i = 0; i < bufs; i++) { + /* NANDFC buffer 0 is used for page read/write */ +- writew(i, host->regs + NFC_BUF_ADDR); ++ writew(i, host->regs + NFC_V1_V2_BUF_ADDR); + +- writew(ops, host->regs + NFC_CONFIG2); ++ writew(ops, host->regs + NFC_V1_V2_CONFIG2); + + /* Wait for operation to complete */ + wait_op_done(host); +@@ -319,20 +384,24 @@ static void __nand_boot_init send_page(struct imx_nand_host *host, + * This function requests the NANDFC to perform a read of the + * NAND device ID. + */ +-static void send_read_id(struct imx_nand_host *host) ++static void send_read_id_v3(struct imx_nand_host *host) ++{ ++ /* Read ID into main buffer */ ++ writel(NFC_ID, NFC_V3_LAUNCH); ++ ++ wait_op_done(host); ++ ++ memcpy(host->data_buf, host->main_area0, 16); ++} ++ ++static void send_read_id_v1_v2(struct imx_nand_host *host) + { + struct nand_chip *this = &host->nand; +- u16 tmp; + + /* NANDFC buffer 0 is used for device ID output */ +- writew(0x0, host->regs + NFC_BUF_ADDR); ++ writew(0x0, host->regs + NFC_V1_V2_BUF_ADDR); + +- /* Read ID into main buffer */ +- tmp = readw(host->regs + NFC_CONFIG1); +- tmp &= ~NFC_SP_EN; +- writew(tmp, host->regs + NFC_CONFIG1); +- +- writew(NFC_ID, host->regs + NFC_CONFIG2); ++ writew(NFC_ID, host->regs + NFC_V1_V2_CONFIG2); + + /* Wait for operation to complete */ + wait_op_done(host); +@@ -359,35 +428,39 @@ static void send_read_id(struct imx_nand_host *host) + * + * @return device status + */ +-static u16 get_dev_status(struct imx_nand_host *host) ++static uint16_t get_dev_status_v3(struct imx_nand_host *host) + { +- volatile u16 *mainbuf = host->main_area1; ++ writew(NFC_STATUS, NFC_V3_LAUNCH); ++ wait_op_done(host); ++ ++ return readl(NFC_V3_CONFIG1) >> 16; ++} ++ ++static u16 get_dev_status_v1_v2(struct imx_nand_host *host) ++{ ++ void *main_buf = host->main_area0; + u32 store; +- u16 ret, tmp; +- /* Issue status request to NAND device */ ++ u16 ret; ++ ++ writew(0x0, host->regs + NFC_V1_V2_BUF_ADDR); + +- /* store the main area1 first word, later do recovery */ +- store = *((u32 *) mainbuf); + /* +- * NANDFC buffer 1 is used for device status to prevent +- * corruption of read/write buffer on status requests. ++ * The device status is stored in main_area0. To ++ * prevent corruption of the buffer save the value ++ * and restore it afterwards. + */ +- writew(1, host->regs + NFC_BUF_ADDR); +- +- /* Read status into main buffer */ +- tmp = readw(host->regs + NFC_CONFIG1); +- tmp &= ~NFC_SP_EN; +- writew(tmp, host->regs + NFC_CONFIG1); ++ store = readl(main_buf); + +- writew(NFC_STATUS, host->regs + NFC_CONFIG2); ++ writew(NFC_STATUS, host->regs + NFC_V1_V2_CONFIG2); + + /* Wait for operation to complete */ + wait_op_done(host); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ +- ret = mainbuf[0]; +- *((u32 *) mainbuf) = store; ++ ret = readw(main_buf); ++ ++ writel(store, main_buf); + + return ret; + } +@@ -416,7 +489,7 @@ static void imx_nand_enable_hwecc(struct mtd_info *mtd, int mode) + */ + } + +-static int imx_nand_correct_data(struct mtd_info *mtd, u_char * dat, ++static int imx_nand_correct_data_v1(struct mtd_info *mtd, u_char * dat, + u_char * read_ecc, u_char * calc_ecc) + { + struct nand_chip *nand_chip = mtd->priv; +@@ -427,7 +500,7 @@ static int imx_nand_correct_data(struct mtd_info *mtd, u_char * dat, + * additional correction. 2-Bit errors cannot be corrected by + * HW ECC, so we need to return failure + */ +- u16 ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT); ++ u16 ecc_status = readw(host->regs + NFC_V1_ECC_STATUS_RESULT); + + if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) { + MTD_DEBUG(MTD_DEBUG_LEVEL0, +@@ -438,6 +511,43 @@ static int imx_nand_correct_data(struct mtd_info *mtd, u_char * dat, + return 0; + } + ++static int imx_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat, ++ u_char *read_ecc, u_char *calc_ecc) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct imx_nand_host *host = nand_chip->priv; ++ u32 ecc_stat, err; ++ int no_subpages = 1; ++ int ret = 0; ++ u8 ecc_bit_mask, err_limit; ++ ++ ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf; ++ err_limit = (host->eccsize == 4) ? 0x4 : 0x8; ++ ++ no_subpages = mtd->writesize >> 9; ++ ++ if (nfc_is_v21()) ++ ecc_stat = readl(host->regs + NFC_V2_ECC_STATUS_RESULT1); ++ else ++ ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT); ++ ++ do { ++ err = ecc_stat & ecc_bit_mask; ++ if (err > err_limit) { ++ printk(KERN_WARNING "UnCorrectable RS-ECC Error\n"); ++ return -1; ++ } else { ++ ret += err; ++ } ++ ecc_stat >>= 4; ++ } while (--no_subpages); ++ ++ mtd->ecc_stats.corrected += ret; ++ pr_debug("%d Symbol Correctable RS-ECC Error\n", ret); ++ ++ return ret; ++} ++ + static int imx_nand_calculate_ecc(struct mtd_info *mtd, const u_char * dat, + u_char * ecc_code) + { +@@ -459,7 +569,7 @@ static u_char imx_nand_read_byte(struct mtd_info *mtd) + + /* Check for status request */ + if (host->status_request) +- return get_dev_status(host) & 0xFF; ++ return host->get_dev_status(host) & 0xFF; + + ret = *(uint8_t *)(host->data_buf + host->buf_start); + host->buf_start++; +@@ -627,37 +737,164 @@ static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr) + * we will used the saved column adress to index into + * the full page. + */ +- send_addr(host, 0); ++ host->send_addr(host, 0); + if (host->pagesize_2k) + /* another col addr cycle for 2k page */ +- send_addr(host, 0); ++ host->send_addr(host, 0); + } + + /* + * Write out page address, if necessary + */ + if (page_addr != -1) { +- send_addr(host, (page_addr & 0xff)); /* paddr_0 - p_addr_7 */ ++ host->send_addr(host, (page_addr & 0xff)); /* paddr_0 - p_addr_7 */ + + if (host->pagesize_2k) { +- send_addr(host, (page_addr >> 8) & 0xFF); ++ host->send_addr(host, (page_addr >> 8) & 0xFF); + if (mtd->size >= 0x10000000) { +- send_addr(host, (page_addr >> 16) & 0xff); ++ host->send_addr(host, (page_addr >> 16) & 0xff); + } + } else { + /* One more address cycle for higher density devices */ + if (mtd->size >= 0x4000000) { + /* paddr_8 - paddr_15 */ +- send_addr(host, (page_addr >> 8) & 0xff); +- send_addr(host, (page_addr >> 16) & 0xff); ++ host->send_addr(host, (page_addr >> 8) & 0xff); ++ host->send_addr(host, (page_addr >> 16) & 0xff); + } else + /* paddr_8 - paddr_15 */ +- send_addr(host, (page_addr >> 8) & 0xff); ++ host->send_addr(host, (page_addr >> 8) & 0xff); + } + } + } + + /* ++ * v2 and v3 type controllers can do 4bit or 8bit ecc depending ++ * on how much oob the nand chip has. For 8bit ecc we need at least ++ * 26 bytes of oob data per 512 byte block. ++ */ ++static int get_eccsize(struct mtd_info *mtd) ++{ ++ int oobbytes_per_512 = 0; ++ ++ oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize; ++ ++ if (oobbytes_per_512 < 26) ++ return 4; ++ else ++ return 8; ++} ++ ++static void preset_v1_v2(struct mtd_info *mtd) ++{ ++ struct nand_chip *nand_chip = mtd->priv; ++ struct imx_nand_host *host = nand_chip->priv; ++ uint16_t config1 = 0; ++ ++ if (nand_chip->ecc.mode == NAND_ECC_HW) ++ config1 |= NFC_V1_V2_CONFIG1_ECC_EN; ++ ++ if (nfc_is_v21()) ++ config1 |= NFC_V2_CONFIG1_FP_INT; ++ ++ if (nfc_is_v21() && mtd->writesize) { ++ uint16_t pages_per_block = mtd->erasesize / mtd->writesize; ++ ++ host->eccsize = get_eccsize(mtd); ++ if (host->eccsize == 4) ++ config1 |= NFC_V2_CONFIG1_ECC_MODE_4; ++ ++ config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6); ++ } else { ++ host->eccsize = 1; ++ } ++ ++ writew(config1, host->regs + NFC_V1_V2_CONFIG1); ++ /* preset operation */ ++ ++ /* Unlock the internal RAM Buffer */ ++ writew(0x2, host->regs + NFC_V1_V2_CONFIG); ++ ++ /* Blocks to be unlocked */ ++ if (nfc_is_v21()) { ++ writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR); ++ writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR); ++ } else if (nfc_is_v1()) { ++ writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR); ++ writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR); ++ } else ++ BUG(); ++ ++ /* Unlock Block Command for given address range */ ++ writew(0x4, host->regs + NFC_V1_V2_WRPROT); ++} ++ ++static void preset_v3(struct mtd_info *mtd) ++{ ++ struct nand_chip *chip = mtd->priv; ++ struct imx_nand_host *host = chip->priv; ++ uint32_t config2, config3; ++ int i, addr_phases; ++ ++ writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1); ++ writel(NFC_V3_IPC_CREQ, NFC_V3_IPC); ++ ++ /* Unlock the internal RAM Buffer */ ++ writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK, ++ NFC_V3_WRPROT); ++ ++ /* Blocks to be unlocked */ ++ for (i = 0; i < NAND_MAX_CHIPS; i++) ++ writel(0x0 | (0xffff << 16), ++ NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2)); ++ ++ writel(0, NFC_V3_IPC); ++ ++ config2 = NFC_V3_CONFIG2_ONE_CYCLE | ++ NFC_V3_CONFIG2_2CMD_PHASES | ++ NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) | ++ NFC_V3_CONFIG2_ST_CMD(0x70) | ++ NFC_V3_CONFIG2_NUM_ADDR_PHASE0; ++ ++ if (chip->ecc.mode == NAND_ECC_HW) ++ config2 |= NFC_V3_CONFIG2_ECC_EN; ++ ++ addr_phases = fls(chip->pagemask) >> 3; ++ ++ if (mtd->writesize == 2048) { ++ config2 |= NFC_V3_CONFIG2_PS_2048; ++ config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); ++ } else if (mtd->writesize == 4096) { ++ config2 |= NFC_V3_CONFIG2_PS_4096; ++ config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases); ++ } else { ++ config2 |= NFC_V3_CONFIG2_PS_512; ++ config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1); ++ } ++ ++ if (mtd->writesize) { ++ config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6); ++ host->eccsize = get_eccsize(mtd); ++ if (host->eccsize == 8) ++ config2 |= NFC_V3_CONFIG2_ECC_MODE_8; ++ } ++ ++ writel(config2, NFC_V3_CONFIG2); ++ ++ config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) | ++ NFC_V3_CONFIG3_NO_SDMA | ++ NFC_V3_CONFIG3_RBB_MODE | ++ NFC_V3_CONFIG3_SBB(6) | /* Reset default */ ++ NFC_V3_CONFIG3_ADD_OP(0); ++ ++ if (!(chip->options & NAND_BUSWIDTH_16)) ++ config3 |= NFC_V3_CONFIG3_FW8; ++ ++ writel(config3, NFC_V3_CONFIG3); ++ ++ writel(0, NFC_V3_DELAY_LINE); ++} ++ ++/* + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * +@@ -685,11 +922,15 @@ static void imx_nand_command(struct mtd_info *mtd, unsigned command, + * Command pre-processing step + */ + switch (command) { ++ case NAND_CMD_RESET: ++ host->preset(mtd); ++ host->send_cmd(host, command); ++ break; + + case NAND_CMD_STATUS: + host->buf_start = 0; + host->status_request = 1; +- send_cmd(host, command); ++ host->send_cmd(host, command); + mxc_do_addr_cycle(mtd, column, page_addr); + break; + +@@ -702,14 +943,14 @@ static void imx_nand_command(struct mtd_info *mtd, unsigned command, + + command = NAND_CMD_READ0; + +- send_cmd(host, command); ++ host->send_cmd(host, command); + mxc_do_addr_cycle(mtd, column, page_addr); + + if (host->pagesize_2k) + /* send read confirm command */ +- send_cmd(host, NAND_CMD_READSTART); ++ host->send_cmd(host, NAND_CMD_READSTART); + +- send_page(host, NFC_OUTPUT); ++ host->send_page(host, NFC_OUTPUT); + + memcpy32(host->data_buf, host->main_area0, mtd->writesize); + copy_spare(mtd, 1); +@@ -733,15 +974,15 @@ static void imx_nand_command(struct mtd_info *mtd, unsigned command, + + /* Set program pointer to spare region */ + if (!host->pagesize_2k) +- send_cmd(host, NAND_CMD_READOOB); ++ host->send_cmd(host, NAND_CMD_READOOB); + } else { + host->buf_start = column; + + /* Set program pointer to page start */ + if (!host->pagesize_2k) +- send_cmd(host, NAND_CMD_READ0); ++ host->send_cmd(host, NAND_CMD_READ0); + } +- send_cmd(host, command); ++ host->send_cmd(host, command); + mxc_do_addr_cycle(mtd, column, page_addr); + + break; +@@ -749,22 +990,21 @@ static void imx_nand_command(struct mtd_info *mtd, unsigned command, + case NAND_CMD_PAGEPROG: + memcpy32(host->main_area0, host->data_buf, mtd->writesize); + copy_spare(mtd, 0); +- send_page(host, NFC_INPUT); +- send_cmd(host, command); ++ host->send_page(host, NFC_INPUT); ++ host->send_cmd(host, command); + mxc_do_addr_cycle(mtd, column, page_addr); + break; + + case NAND_CMD_READID: +- send_cmd(host, command); ++ host->send_cmd(host, command); + mxc_do_addr_cycle(mtd, column, page_addr); + host->buf_start = 0; +- send_read_id(host); ++ host->send_read_id(host); + break; + + case NAND_CMD_ERASE1: + case NAND_CMD_ERASE2: +- case NAND_CMD_RESET: +- send_cmd(host, command); ++ host->send_cmd(host, command); + mxc_do_addr_cycle(mtd, column, page_addr); + break; + } +@@ -839,7 +1079,6 @@ static int __init imxnd_probe(struct device_d *dev) + struct imx_nand_platform_data *pdata = dev->platform_data; + struct imx_nand_host *host; + struct nand_ecclayout *oob_smallpage, *oob_largepage; +- u16 tmp; + int err = 0; + + #ifdef CONFIG_ARCH_IMX27 +@@ -858,20 +1097,45 @@ static int __init imxnd_probe(struct device_d *dev) + host->base = (void __iomem *)dev->map_base; + + host->main_area0 = host->base; +- host->main_area1 = host->base + 0x200; ++ ++ if (nfc_is_v1() || nfc_is_v21()) { ++ host->preset = preset_v1_v2; ++ host->send_cmd = send_cmd_v1_v2; ++ host->send_addr = send_addr_v1_v2; ++ host->send_page = send_page_v1_v2; ++ host->send_read_id = send_read_id_v1_v2; ++ host->get_dev_status = get_dev_status_v1_v2; ++ host->check_int = check_int_v1_v2; ++ } + + if (nfc_is_v21()) { +- host->regs = host->base + 0x1000; ++ host->regs = host->base + 0x1e00; + host->spare0 = host->base + 0x1000; + host->spare_len = 64; + oob_smallpage = &nandv2_hw_eccoob_smallpage; + oob_largepage = &nandv2_hw_eccoob_largepage; + } else if (nfc_is_v1()) { +- host->regs = host->base; ++ host->regs = host->base + 0xe00; + host->spare0 = host->base + 0x800; + host->spare_len = 16; + oob_smallpage = &nandv1_hw_eccoob_smallpage; + oob_largepage = &nandv1_hw_eccoob_largepage; ++ } else if (nfc_is_v3_2()) { ++#ifdef CONFIG_ARCH_IMX51 ++ host->regs_ip = (void *)MX51_NFC_BASE_ADDR; ++#endif ++ host->regs_axi = host->base + 0x1e00; ++ host->spare0 = host->base + 0x1000; ++ host->spare_len = 64; ++ host->preset = preset_v3; ++ host->send_cmd = send_cmd_v3; ++ host->send_addr = send_addr_v3; ++ host->send_page = send_page_v3; ++ host->send_read_id = send_read_id_v3; ++ host->get_dev_status = get_dev_status_v3; ++ host->check_int = check_int_v3; ++ oob_smallpage = &nandv2_hw_eccoob_smallpage; ++ oob_largepage = &nandv2_hw_eccoob_largepage; + } + + host->dev = dev; +@@ -900,52 +1164,20 @@ static int __init imxnd_probe(struct device_d *dev) + clk_enable(host->clk); + #endif + +- tmp = readw(host->regs + NFC_CONFIG1); +- tmp |= NFC_INT_MSK; +- tmp &= ~NFC_SP_EN; +- if (nfc_is_v21()) +- /* currently no support for 218 byte OOB with stronger ECC */ +- tmp |= NFC_ECC_MODE; +- writew(tmp, host->regs + NFC_CONFIG1); +- + if (pdata->hw_ecc) { + this->ecc.calculate = imx_nand_calculate_ecc; + this->ecc.hwctl = imx_nand_enable_hwecc; +- this->ecc.correct = imx_nand_correct_data; ++ if (nfc_is_v1()) ++ this->ecc.correct = imx_nand_correct_data_v1; ++ else ++ this->ecc.correct = imx_nand_correct_data_v2_v3; + this->ecc.mode = NAND_ECC_HW; + this->ecc.size = 512; +- tmp = readw(host->regs + NFC_CONFIG1); +- tmp |= NFC_ECC_EN; +- writew(tmp, host->regs + NFC_CONFIG1); + } else { + this->ecc.size = 512; + this->ecc.mode = NAND_ECC_SOFT; +- tmp = readw(host->regs + NFC_CONFIG1); +- tmp &= ~NFC_ECC_EN; +- writew(tmp, host->regs + NFC_CONFIG1); + } + +- /* Reset NAND */ +- this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); +- +- /* preset operation */ +- /* Unlock the internal RAM Buffer */ +- writew(0x2, host->regs + NFC_CONFIG); +- +- /* Blocks to be unlocked */ +- if (nfc_is_v21()) { +- writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR); +- writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR); +- this->ecc.bytes = 9; +- } else if (nfc_is_v1()) { +- writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR); +- writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR); +- this->ecc.bytes = 3; +- } +- +- /* Unlock Block Command for given address range */ +- writew(0x4, host->regs + NFC_WRPROT); +- + this->ecc.layout = oob_smallpage; + + /* NAND bus width determines access funtions used by upper layer */ +@@ -968,24 +1200,19 @@ static int __init imxnd_probe(struct device_d *dev) + goto escan; + } + ++ /* Call preset again, with correct writesize this time */ ++ host->preset(mtd); ++ + imx_nand_set_layout(mtd->writesize, pdata->width == 2 ? 16 : 8); + + if (mtd->writesize == 2048) { + this->ecc.layout = oob_largepage; + host->pagesize_2k = 1; +- if (nfc_is_v21()) { +- tmp = readw(host->regs + NFC_SPAS); +- tmp &= 0xff00; +- tmp |= NFC_SPAS_64; +- writew(tmp, host->regs + NFC_SPAS); +- } ++ if (nfc_is_v21()) ++ writew(NFC_V2_SPAS_SPARESIZE(64), host->regs + NFC_V2_SPAS); + } else { +- if (nfc_is_v21()) { +- tmp = readw(host->regs + NFC_SPAS); +- tmp &= 0xff00; +- tmp |= NFC_SPAS_16; +- writew(tmp, host->regs + NFC_SPAS); +- } ++ if (nfc_is_v21()) ++ writew(NFC_V2_SPAS_SPARESIZE(16), host->regs + NFC_V2_SPAS); + } + + /* second phase scan */ +@@ -1013,20 +1240,87 @@ static struct driver_d imx_nand_driver = { + }; + + #ifdef CONFIG_NAND_IMX_BOOT ++static void __nand_boot_init noinline imx_nandboot_wait_op_done(void *regs) ++{ ++ u32 r; ++ ++ while (1) { ++ r = readw(regs + NFC_V1_V2_CONFIG2); ++ if (r & NFC_V1_V2_CONFIG2_INT) ++ break; ++ }; + +-static void __nand_boot_init nfc_addr(struct imx_nand_host *host, u32 offs) ++ r &= ~NFC_V1_V2_CONFIG2_INT; ++ ++ writew(r, regs + NFC_V1_V2_CONFIG2); ++} ++ ++/* ++ * This function issues the specified command to the NAND device and ++ * waits for completion. ++ * ++ * @param cmd command for NAND Flash ++ */ ++static void __nand_boot_init imx_nandboot_send_cmd(void *regs, u16 cmd) ++{ ++ writew(cmd, regs + NFC_V1_V2_FLASH_CMD); ++ writew(NFC_CMD, regs + NFC_V1_V2_CONFIG2); ++ ++ imx_nandboot_wait_op_done(regs); ++} ++ ++/* ++ * This function sends an address (or partial address) to the ++ * NAND device. The address is used to select the source/destination for ++ * a NAND command. ++ * ++ * @param addr address to be written to NFC. ++ * @param islast True if this is the last address cycle for command ++ */ ++static void __nand_boot_init noinline imx_nandboot_send_addr(void *regs, u16 addr) + { +- if (host->pagesize_2k) { +- send_addr(host, offs & 0xff); +- send_addr(host, offs & 0xff); +- send_addr(host, (offs >> 11) & 0xff); +- send_addr(host, (offs >> 19) & 0xff); +- send_addr(host, (offs >> 27) & 0xff); ++ writew(addr, regs + NFC_V1_V2_FLASH_ADDR); ++ writew(NFC_ADDR, regs + NFC_V1_V2_CONFIG2); ++ ++ /* Wait for operation to complete */ ++ imx_nandboot_wait_op_done(regs); ++} ++ ++static void __nand_boot_init imx_nandboot_nfc_addr(void *regs, u32 offs, int pagesize_2k) ++{ ++ imx_nandboot_send_addr(regs, offs & 0xff); ++ ++ if (pagesize_2k) { ++ imx_nandboot_send_addr(regs, offs & 0xff); ++ imx_nandboot_send_addr(regs, (offs >> 11) & 0xff); ++ imx_nandboot_send_addr(regs, (offs >> 19) & 0xff); ++ imx_nandboot_send_addr(regs, (offs >> 27) & 0xff); ++ imx_nandboot_send_cmd(regs, NAND_CMD_READSTART); + } else { +- send_addr(host, offs & 0xff); +- send_addr(host, (offs >> 9) & 0xff); +- send_addr(host, (offs >> 17) & 0xff); +- send_addr(host, (offs >> 25) & 0xff); ++ imx_nandboot_send_addr(regs, (offs >> 9) & 0xff); ++ imx_nandboot_send_addr(regs, (offs >> 17) & 0xff); ++ imx_nandboot_send_addr(regs, (offs >> 25) & 0xff); ++ } ++} ++ ++static void __nand_boot_init imx_nandboot_send_page(void *regs, ++ unsigned int ops, int pagesize_2k) ++{ ++ int bufs, i; ++ ++ if (nfc_is_v1() && pagesize_2k) ++ bufs = 4; ++ else ++ bufs = 1; ++ ++ for (i = 0; i < bufs; i++) { ++ /* NANDFC buffer 0 is used for page read/write */ ++ writew(i, regs + NFC_V1_V2_BUF_ADDR); ++ ++ writew(ops, regs + NFC_V1_V2_CONFIG2); ++ ++ /* Wait for operation to complete */ ++ imx_nandboot_wait_op_done(regs); + } + } + +@@ -1040,38 +1334,49 @@ static void __nand_boot_init __memcpy32(void *trg, const void *src, int size) + *t++ = *s++; + } + +-void __nand_boot_init imx_nand_load_image(void *dest, int size) ++static int __maybe_unused is_pagesize_2k(void) + { +- struct imx_nand_host host; +- u32 tmp, page, block, blocksize, pagesize; + #ifdef CONFIG_ARCH_IMX21 +- tmp = readl(IMX_SYSTEM_CTL_BASE + 0x14); +- if (tmp & (1 << 5)) +- host.pagesize_2k = 1; ++ if (readl(IMX_SYSTEM_CTL_BASE + 0x14) & (1 << 5)) ++ return 1; + else +- host.pagesize_2k = 0; ++ return 0; + #endif + #ifdef CONFIG_ARCH_IMX27 +- tmp = readl(IMX_SYSTEM_CTL_BASE + 0x14); +- if (tmp & (1 << 5)) +- host.pagesize_2k = 1; ++ if (readl(IMX_SYSTEM_CTL_BASE + 0x14) & (1 << 5)) ++ return 1; + else +- host.pagesize_2k = 0; ++ return 0; + #endif + #ifdef CONFIG_ARCH_IMX31 +- tmp = readl(IMX_CCM_BASE + CCM_RCSR); +- if (tmp & RCSR_NFMS) +- host.pagesize_2k = 1; ++ if (readl(IMX_CCM_BASE + CCM_RCSR) & RCSR_NFMS) ++ return 1; + else +- host.pagesize_2k = 0; ++ return 0; + #endif + #if defined(CONFIG_ARCH_IMX35) || defined(CONFIG_ARCH_IMX25) + if (readl(IMX_CCM_BASE + CCM_RCSR) & (1 << 8)) +- host.pagesize_2k = 1; ++ return 1; + else +- host.pagesize_2k = 0; ++ return 0; ++#endif ++} ++ ++void __nand_boot_init imx_nand_load_image(void *dest, int size) ++{ ++ u32 tmp, page, block, blocksize, pagesize; ++ int pagesize_2k = 1; ++ void *regs, *base, *spare0; ++ ++#if defined(CONFIG_NAND_IMX_BOOT_512) ++ pagesize_2k = 0; ++#elif defined(CONFIG_NAND_IMX_BOOT_2K) ++ pagesize_2k = 1; ++#else ++ pagesize_2k = is_pagesize_2k(); + #endif +- if (host.pagesize_2k) { ++ ++ if (pagesize_2k) { + pagesize = 2048; + blocksize = 128 * 1024; + } else { +@@ -1079,46 +1384,37 @@ void __nand_boot_init imx_nand_load_image(void *dest, int size) + blocksize = 16 * 1024; + } + +- host.base = (void __iomem *)IMX_NFC_BASE; ++ base = (void __iomem *)IMX_NFC_BASE; + if (nfc_is_v21()) { +- host.regs = host.base + 0x1000; +- host.spare0 = host.base + 0x1000; +- host.spare_len = 64; ++ regs = base + 0x1e00; ++ spare0 = base + 0x1000; + } else if (nfc_is_v1()) { +- host.regs = host.base; +- host.spare0 = host.base + 0x800; +- host.spare_len = 16; ++ regs = base + 0xe00; ++ spare0 = base + 0x800; + } + +- send_cmd(&host, NAND_CMD_RESET); ++ imx_nandboot_send_cmd(regs, NAND_CMD_RESET); + + /* preset operation */ + /* Unlock the internal RAM Buffer */ +- writew(0x2, host.regs + NFC_CONFIG); ++ writew(0x2, regs + NFC_V1_V2_CONFIG); + + /* Unlock Block Command for given address range */ +- writew(0x4, host.regs + NFC_WRPROT); ++ writew(0x4, regs + NFC_V1_V2_WRPROT); + +- tmp = readw(host.regs + NFC_CONFIG1); +- tmp |= NFC_ECC_EN; ++ tmp = readw(regs + NFC_V1_V2_CONFIG1); ++ tmp |= NFC_V1_V2_CONFIG1_ECC_EN; + if (nfc_is_v21()) + /* currently no support for 218 byte OOB with stronger ECC */ +- tmp |= NFC_ECC_MODE; +- tmp &= ~(NFC_SP_EN | NFC_INT_MSK); +- writew(tmp, host.regs + NFC_CONFIG1); ++ tmp |= NFC_V2_CONFIG1_ECC_MODE_4; ++ tmp &= ~(NFC_V1_V2_CONFIG1_SP_EN | NFC_V1_V2_CONFIG1_INT_MSK); ++ writew(tmp, regs + NFC_V1_V2_CONFIG1); + + if (nfc_is_v21()) { +- if (host.pagesize_2k) { +- tmp = readw(host.regs + NFC_SPAS); +- tmp &= 0xff00; +- tmp |= NFC_SPAS_64; +- writew(tmp, host.regs + NFC_SPAS); +- } else { +- tmp = readw(host.regs + NFC_SPAS); +- tmp &= 0xff00; +- tmp |= NFC_SPAS_16; +- writew(tmp, host.regs + NFC_SPAS); +- } ++ if (pagesize_2k) ++ writew(NFC_V2_SPAS_SPARESIZE(64), regs + NFC_V2_SPAS); ++ else ++ writew(NFC_V2_SPAS_SPARESIZE(16), regs + NFC_V2_SPAS); + } + + block = page = 0; +@@ -1132,25 +1428,21 @@ void __nand_boot_init imx_nand_load_image(void *dest, int size) + block * blocksize + + page * pagesize); + +- send_cmd(&host, NAND_CMD_READ0); +- nfc_addr(&host, block * blocksize + +- page * pagesize); +- if (host.pagesize_2k) +- send_cmd(&host, NAND_CMD_READSTART); +- send_page(&host, NFC_OUTPUT); ++ imx_nandboot_send_cmd(regs, NAND_CMD_READ0); ++ imx_nandboot_nfc_addr(regs, block * blocksize + ++ page * pagesize, pagesize_2k); ++ imx_nandboot_send_page(regs, NFC_OUTPUT, pagesize_2k); + page++; + +- if (host.pagesize_2k) { +- if ((readw(host.spare0) & 0xff) +- != 0xff) ++ if (pagesize_2k) { ++ if ((readw(spare0) & 0xff) != 0xff) + continue; + } else { +- if ((readw(host.spare0 + 4) & 0xff00) +- != 0xff00) ++ if ((readw(spare0 + 4) & 0xff00) != 0xff00) + continue; + } + +- __memcpy32(dest, host.base, pagesize); ++ __memcpy32(dest, base, pagesize); + dest += pagesize; + size -= pagesize; + +diff --git a/drivers/mtd/nand/nand_s3c2410.c b/drivers/mtd/nand/nand_s3c2410.c +index b989583..fa4acf4 100644 +--- a/drivers/mtd/nand/nand_s3c2410.c ++++ b/drivers/mtd/nand/nand_s3c2410.c +@@ -96,7 +96,7 @@ struct s3c24x0_nand_host { + struct mtd_partition *parts; + struct device_d *dev; + +- unsigned long base; ++ void __iomem *base; + }; + + /** +@@ -120,7 +120,7 @@ static struct nand_ecclayout nand_hw_eccoob = { + * @param[in] host Base address of the NAND controller + * @param[in] cmd Command for NAND flash + */ +-static void __nand_boot_init send_cmd(unsigned long host, uint8_t cmd) ++static void __nand_boot_init send_cmd(void __iomem *host, uint8_t cmd) + { + writeb(cmd, host + NFCMD); + } +@@ -130,7 +130,7 @@ static void __nand_boot_init send_cmd(unsigned long host, uint8_t cmd) + * @param[in] host Base address of the NAND controller + * @param[in] addr Address for the NAND flash + */ +-static void __nand_boot_init send_addr(unsigned long host, uint8_t addr) ++static void __nand_boot_init send_addr(void __iomem *host, uint8_t addr) + { + writeb(addr, host + NFADDR); + } +@@ -139,7 +139,7 @@ static void __nand_boot_init send_addr(unsigned long host, uint8_t addr) + * Enable the NAND flash access + * @param[in] host Base address of the NAND controller + */ +-static void __nand_boot_init enable_cs(unsigned long host) ++static void __nand_boot_init enable_cs(void __iomem *host) + { + #ifdef CONFIG_CPU_S3C2410 + writew(readw(host + NFCONF) & ~NFCONF_nFCE, host + NFCONF); +@@ -153,7 +153,7 @@ static void __nand_boot_init enable_cs(unsigned long host) + * Disable the NAND flash access + * @param[in] host Base address of the NAND controller + */ +-static void __nand_boot_init disable_cs(unsigned long host) ++static void __nand_boot_init disable_cs(void __iomem *host) + { + #ifdef CONFIG_CPU_S3C2410 + writew(readw(host + NFCONF) | NFCONF_nFCE, host + NFCONF); +@@ -168,7 +168,7 @@ static void __nand_boot_init disable_cs(unsigned long host) + * @param[in] host Base address of the NAND controller + * @param[in] timing Timing to access the NAND memory + */ +-static void __nand_boot_init enable_nand_controller(unsigned long host, uint32_t timing) ++static void __nand_boot_init enable_nand_controller(void __iomem *host, uint32_t timing) + { + #ifdef CONFIG_CPU_S3C2410 + writew(timing + NFCONF_EN + NFCONF_nFCE, host + NFCONF); +@@ -183,7 +183,7 @@ static void __nand_boot_init enable_nand_controller(unsigned long host, uint32_t + * Diable the NAND flash controller + * @param[in] host Base address of the NAND controller + */ +-static void __nand_boot_init disable_nand_controller(unsigned long host) ++static void __nand_boot_init disable_nand_controller(void __iomem *host) + { + #ifdef CONFIG_CPU_S3C2410 + writew(NFCONF_nFCE, host + NFCONF); +@@ -359,7 +359,7 @@ static int s3c24x0_nand_probe(struct device_d *dev) + return -ENOMEM; + + host->dev = dev; +- host->base = dev->map_base; ++ host->base = IOMEM(dev->map_base); + + /* structures must be linked */ + chip = &host->nand; +@@ -375,7 +375,7 @@ static int s3c24x0_nand_probe(struct device_d *dev) + chip->chip_delay = 50; + chip->priv = host; + +- chip->IO_ADDR_R = chip->IO_ADDR_W = (void*)(dev->map_base + NFDATA); ++ chip->IO_ADDR_R = chip->IO_ADDR_W = IOMEM(dev->map_base + NFDATA); + + chip->cmd_ctrl = s3c24x0_nand_hwcontrol; + chip->dev_ready = s3c24x0_nand_devready; +@@ -418,13 +418,13 @@ static struct driver_d s3c24x0_nand_driver = { + + #ifdef CONFIG_S3C24XX_NAND_BOOT + +-static void __nand_boot_init wait_for_completion(unsigned long host) ++static void __nand_boot_init wait_for_completion(void __iomem *host) + { + while (!(readw(host + NFSTAT) & NFSTAT_BUSY)) + ; + } + +-static void __nand_boot_init nfc_addr(unsigned long host, uint32_t offs) ++static void __nand_boot_init nfc_addr(void __iomem *host, uint32_t offs) + { + send_addr(host, offs & 0xff); + send_addr(host, (offs >> 9) & 0xff); +@@ -447,7 +447,7 @@ static void __nand_boot_init nfc_addr(unsigned long host, uint32_t offs) + */ + void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, int pagesize) + { +- unsigned long host = S3C24X0_NAND_BASE; ++ void __iomem *host = (void __iomem *)S3C24X0_NAND_BASE; + int i; + + /* +@@ -469,7 +469,7 @@ void __nand_boot_init s3c24x0_nand_load_image(void *dest, int size, int page, in + wait_for_completion(host); + /* copy one page (do *not* use readsb() here!)*/ + for (i = 0; i < pagesize; i++) +- writeb(readb(host + NFDATA), (unsigned long)(dest + i)); ++ writeb(readb(host + NFDATA), (void __iomem *)(dest + i)); + disable_cs(host); + + page++; +diff --git a/drivers/net/fec_imx.c b/drivers/net/fec_imx.c +index 73b7a54..9c8de77 100644 +--- a/drivers/net/fec_imx.c ++++ b/drivers/net/fec_imx.c +@@ -216,7 +216,7 @@ static void fec_tbd_init(struct fec_priv *fec) + * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 + * @param[in] pRbd buffer descriptor to mark free again + */ +-static void fec_rbd_clean(int last, struct buffer_descriptor *pRbd) ++static void fec_rbd_clean(int last, struct buffer_descriptor __iomem *pRbd) + { + /* + * Reset buffer descriptor as empty +@@ -464,7 +464,7 @@ static int fec_send(struct eth_device *dev, void *eth_data, int data_length) + static int fec_recv(struct eth_device *dev) + { + struct fec_priv *fec = (struct fec_priv *)dev->priv; +- struct buffer_descriptor *rbd = &fec->rbd_base[fec->rbd_index]; ++ struct buffer_descriptor __iomem *rbd = &fec->rbd_base[fec->rbd_index]; + unsigned long ievent; + int frame_length, len = 0; + struct fec_frame *frame; +@@ -568,11 +568,11 @@ static int fec_probe(struct device_d *dev) + sizeof(struct buffer_descriptor) + 2 * DB_ALIGNMENT); + base += (DB_ALIGNMENT - 1); + base &= ~(DB_ALIGNMENT - 1); +- fec->rbd_base = (struct buffer_descriptor *)base; ++ fec->rbd_base = (struct buffer_descriptor __force __iomem *)base; + base += FEC_RBD_NUM * sizeof (struct buffer_descriptor) + + (DB_ALIGNMENT - 1); + base &= ~(DB_ALIGNMENT - 1); +- fec->tbd_base = (struct buffer_descriptor *)base; ++ fec->tbd_base = (struct buffer_descriptor __force __iomem *)base; + + writel((uint32_t)virt_to_phys(fec->tbd_base), fec->regs + FEC_ETDSR); + writel((uint32_t)virt_to_phys(fec->rbd_base), fec->regs + FEC_ERDSR); +diff --git a/drivers/net/fec_imx.h b/drivers/net/fec_imx.h +index e1473a4..ce0fd89 100644 +--- a/drivers/net/fec_imx.h ++++ b/drivers/net/fec_imx.h +@@ -135,11 +135,11 @@ struct buffer_descriptor { + * @brief i.MX27-FEC private structure + */ + struct fec_priv { +- void *regs; ++ void __iomem *regs; + xceiver_type xcv_type; /* transceiver type */ +- struct buffer_descriptor *rbd_base; /* RBD ring */ ++ struct buffer_descriptor __iomem *rbd_base; /* RBD ring */ + int rbd_index; /* next receive BD to read */ +- struct buffer_descriptor *tbd_base; /* TBD ring */ ++ struct buffer_descriptor __iomem *tbd_base; /* TBD ring */ + int tbd_index; /* next transmit BD to write */ + struct mii_device miidev; + }; +diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c +index 605a7d8..535e69a 100644 +--- a/drivers/net/smc91111.c ++++ b/drivers/net/smc91111.c +@@ -440,20 +440,20 @@ + #define MEMORY_WAIT_TIME 16 + + struct accessors { +- void (*ob)(unsigned, unsigned long); +- void (*ow)(unsigned, unsigned long); +- void (*ol)(unsigned long, unsigned long); +- void (*osl)(unsigned long, const void*, int); +- unsigned (*ib)(unsigned long); +- unsigned (*iw)(unsigned long); +- unsigned long (*il)(unsigned long); +- void (*isl)(unsigned long, void*, int); ++ void (*ob)(unsigned, void __iomem *); ++ void (*ow)(unsigned, void __iomem *); ++ void (*ol)(unsigned long, void __iomem *); ++ void (*osl)(void __iomem *, const void *, int); ++ unsigned (*ib)(void __iomem *); ++ unsigned (*iw)(void __iomem *); ++ unsigned long (*il)(void __iomem *); ++ void (*isl)(void __iomem *, void*, int); + }; + + struct smc91c111_priv { + struct mii_device miidev; + struct accessors a; +- unsigned long base; ++ void __iomem *base; + }; + + #if (SMC_DEBUG > 2 ) +@@ -483,44 +483,44 @@ struct smc91c111_priv { + + #define ETH_ZLEN 60 + +-static void a_outb(unsigned value, unsigned long offset) ++static void a_outb(unsigned value, void __iomem *offset) + { + writeb(value, offset); + } + +-static void a_outw(unsigned value, unsigned long offset) ++static void a_outw(unsigned value, void __iomem *offset) + { + writew(value, offset); + } + +-static void a_outl(unsigned long value, unsigned long offset) ++static void a_outl(unsigned long value, void __iomem *offset) + { + writel(value, offset); + } + +-static void a_outsl(unsigned long offset, const void *data, int count) ++static void a_outsl(void __iomem *offset, const void *data, int count) + { +- writesl((void*)offset, data, count); ++ writesl(offset, data, count); + } + +-static unsigned a_inb(unsigned long offset) ++static unsigned a_inb(void __iomem *offset) + { + return readb(offset); + } + +-static unsigned a_inw(unsigned long offset) ++static unsigned a_inw(void __iomem *offset) + { + return readw(offset); + } + +-static unsigned long a_inl(unsigned long offset) ++static unsigned long a_inl(void __iomem *offset) + { + return readl(offset); + } + +-static inline void a_insl(unsigned long offset, void *data, int count) ++static inline void a_insl(void __iomem *offset, void *data, int count) + { +- readsl((void*)offset, data, count); ++ readsl(offset, data, count); + } + + /* access happens via a 32 bit bus */ +@@ -1317,7 +1317,7 @@ static int smc91c111_probe(struct device_d *dev) + priv->miidev.address = 0; + priv->miidev.flags = 0; + priv->miidev.edev = edev; +- priv->base = dev->map_base; ++ priv->base = IOMEM(dev->map_base); + + smc91c111_reset(edev); + +diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig +index c7ea2d9..3a8882f 100644 +--- a/drivers/serial/Kconfig ++++ b/drivers/serial/Kconfig +@@ -18,6 +18,11 @@ config DRIVER_SERIAL_IMX + default y + bool "i.MX serial driver" + ++config DRIVER_SERIAL_STM378X ++ depends on ARCH_STM ++ default y ++ bool "i.MX23 serial driver" ++ + config DRIVER_SERIAL_NETX + depends on ARCH_NETX + default y +diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile +index 959290e..9f0e12b 100644 +--- a/drivers/serial/Makefile ++++ b/drivers/serial/Makefile +@@ -7,6 +7,7 @@ + obj-$(CONFIG_DRIVER_SERIAL_ARM_DCC) += arm_dcc.o + obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o + obj-$(CONFIG_DRIVER_SERIAL_IMX) += serial_imx.o ++obj-$(CONFIG_DRIVER_SERIAL_STM378X) += stm-serial.o + obj-$(CONFIG_DRIVER_SERIAL_ATMEL) += atmel.o + obj-$(CONFIG_DRIVER_SERIAL_NETX) += serial_netx.o + obj-$(CONFIG_DRIVER_SERIAL_LINUX_COMSOLE) += linux_console.o +diff --git a/drivers/serial/serial_imx.c b/drivers/serial/serial_imx.c +index 801004e..a7562f9 100644 +--- a/drivers/serial/serial_imx.c ++++ b/drivers/serial/serial_imx.c +@@ -160,7 +160,8 @@ + # define UCR3_VAL (0x700 | UCR3_RXDMUXSEL) + # define UCR4_VAL UCR4_CTSTL_32 + #endif +-#if defined CONFIG_ARCH_IMX31 || defined CONFIG_ARCH_IMX35 || defined CONFIG_ARCH_IMX25 ++#if defined CONFIG_ARCH_IMX31 || defined CONFIG_ARCH_IMX35 || \ ++ defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX51 + # define UCR1_VAL (0) + # define UCR3_VAL (0x700 | UCR3_RXDMUXSEL) + # define UCR4_VAL UCR4_CTSTL_32 +@@ -170,13 +171,14 @@ struct imx_serial_priv { + struct console_device cdev; + int baudrate; + struct notifier_block notify; ++ void __iomem *regs; + }; + +-static int imx_serial_reffreq(ulong base) ++static int imx_serial_reffreq(void __iomem *regs) + { + ulong rfdiv; + +- rfdiv = (readl(base + UFCR) >> 7) & 7; ++ rfdiv = (readl(regs + UFCR) >> 7) & 7; + rfdiv = rfdiv < 6 ? 6 - rfdiv : 7; + + return imx_get_uartclk() / rfdiv; +@@ -189,108 +191,111 @@ static int imx_serial_reffreq(ulong base) + */ + static int imx_serial_init_port(struct console_device *cdev) + { +- struct device_d *dev = cdev->dev; +- ulong base = dev->map_base; ++ struct imx_serial_priv *priv = container_of(cdev, ++ struct imx_serial_priv, cdev); ++ void __iomem *regs = priv->regs; + uint32_t val; + +- writel(UCR1_VAL, base + UCR1); +- writel(UCR2_WS | UCR2_IRTS, base + UCR2); +- writel(UCR3_VAL, base + UCR3); +- writel(UCR4_VAL, base + UCR4); +- writel(0x0000002B, base + UESC); +- writel(0, base + UTIM); +- writel(0, base + UBIR); +- writel(0, base + UBMR); +- writel(0, base + UTS); ++ writel(UCR1_VAL, regs + UCR1); ++ writel(UCR2_WS | UCR2_IRTS, regs + UCR2); ++ writel(UCR3_VAL, regs + UCR3); ++ writel(UCR4_VAL, regs + UCR4); ++ writel(0x0000002B, regs + UESC); ++ writel(0, regs + UTIM); ++ writel(0, regs + UBIR); ++ writel(0, regs + UBMR); ++ writel(0, regs + UTS); + + + /* Configure FIFOs */ +- writel(0xa81, base + UFCR); ++ writel(0xa81, regs + UFCR); + + #ifdef ONEMS +- writel(imx_serial_reffreq(base) / 1000, base + ONEMS); ++ writel(imx_serial_reffreq(regs) / 1000, regs + ONEMS); + #endif + + /* Enable FIFOs */ +- val = readl(base + UCR2); ++ val = readl(regs + UCR2); + val |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN; +- writel(val, base + UCR2); ++ writel(val, regs + UCR2); + + /* Clear status flags */ +- val = readl(base + USR2); ++ val = readl(regs + USR2); + val |= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_IRINT | USR2_WAKE | + USR2_RTSF | USR2_BRCD | USR2_ORE | USR2_RDR; +- writel(val, base + USR2); ++ writel(val, regs + USR2); + + /* Clear status flags */ +- val = readl(base + USR2); ++ val = readl(regs + USR2); + val |= USR1_PARITYERR | USR1_RTSD | USR1_ESCF | USR1_FRAMERR | USR1_AIRINT | + USR1_AWAKE; +- writel(val, base + USR2); ++ writel(val, regs + USR2); + + return 0; + } + + static void imx_serial_putc(struct console_device *cdev, char c) + { +- struct device_d *dev = cdev->dev; ++ struct imx_serial_priv *priv = container_of(cdev, ++ struct imx_serial_priv, cdev); + + /* Wait for Tx FIFO not full */ +- while (readl(dev->map_base + UTS) & UTS_TXFULL); ++ while (readl(priv->regs + UTS) & UTS_TXFULL); + +- writel(c, dev->map_base + URTX0); ++ writel(c, priv->regs + URTX0); + } + + static int imx_serial_tstc(struct console_device *cdev) + { +- struct device_d *dev = cdev->dev; ++ struct imx_serial_priv *priv = container_of(cdev, ++ struct imx_serial_priv, cdev); + + /* If receive fifo is empty, return false */ +- if (readl(dev->map_base + UTS) & UTS_RXEMPTY) ++ if (readl(priv->regs + UTS) & UTS_RXEMPTY) + return 0; + return 1; + } + + static int imx_serial_getc(struct console_device *cdev) + { +- struct device_d *dev = cdev->dev; ++ struct imx_serial_priv *priv = container_of(cdev, ++ struct imx_serial_priv, cdev); + unsigned char ch; + +- while (readl(dev->map_base + UTS) & UTS_RXEMPTY); ++ while (readl(priv->regs + UTS) & UTS_RXEMPTY); + +- ch = readl(dev->map_base + URXD0); ++ ch = readl(priv->regs + URXD0); + + return ch; + } + + static void imx_serial_flush(struct console_device *cdev) + { +- struct device_d *dev = cdev->dev; ++ struct imx_serial_priv *priv = container_of(cdev, ++ struct imx_serial_priv, cdev); + +- while (!(readl(dev->map_base + USR2) & USR2_TXDC)); ++ while (!(readl(priv->regs + USR2) & USR2_TXDC)); + } + + static int imx_serial_setbaudrate(struct console_device *cdev, int baudrate) + { +- struct device_d *dev = cdev->dev; + struct imx_serial_priv *priv = container_of(cdev, + struct imx_serial_priv, cdev); ++ void __iomem *regs = priv->regs; + uint32_t val; +- +- ulong base = dev->map_base; +- ulong ucr1 = readl(base + UCR1); ++ uint32_t ucr1 = readl(regs + UCR1); + + /* disable UART */ +- val = readl(base + UCR1); ++ val = readl(regs + UCR1); + val &= ~UCR1_UARTEN; +- writel(val, base + UCR1); ++ writel(val, regs + UCR1); + + /* Set the numerator value minus one of the BRM ratio */ +- writel((baudrate / 100) - 1, base + UBIR); ++ writel((baudrate / 100) - 1, regs + UBIR); + /* Set the denominator value minus one of the BRM ratio */ +- writel((imx_serial_reffreq(base) / 1600) - 1, base + UBMR); ++ writel((imx_serial_reffreq(regs) / 1600) - 1, regs + UBMR); + +- writel(ucr1, base + UCR1); ++ writel(ucr1, regs + UCR1); + + priv->baudrate = baudrate; + +@@ -317,6 +322,7 @@ static int imx_serial_probe(struct device_d *dev) + priv = malloc(sizeof(*priv)); + cdev = &priv->cdev; + ++ priv->regs = (void __force __iomem *)dev->map_base; + dev->type_data = cdev; + cdev->dev = dev; + cdev->f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR; +@@ -330,9 +336,9 @@ static int imx_serial_probe(struct device_d *dev) + imx_serial_setbaudrate(cdev, 115200); + + /* Enable UART */ +- val = readl(cdev->dev->map_base + UCR1); ++ val = readl(priv->regs + UCR1); + val |= UCR1_UARTEN; +- writel(val, cdev->dev->map_base + UCR1); ++ writel(val, priv->regs + UCR1); + + console_register(cdev); + priv->notify.notifier_call = imx_clocksource_clock_change; +diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c +index fedddd3..d7eac8f 100644 +--- a/drivers/serial/serial_s3c24x0.c ++++ b/drivers/serial/serial_s3c24x0.c +@@ -113,7 +113,7 @@ static void s3c24x0_serial_flush(struct console_device *cdev) + { + struct device_d *dev = cdev->dev; + +- while (!readb(dev->map_base + UTRSTAT) & 0x4) ++ while (!(readb(dev->map_base + UTRSTAT) & 0x4)) + ; + } + +diff --git a/drivers/serial/stm-serial.c b/drivers/serial/stm-serial.c +new file mode 100644 +index 0000000..90563f5 +--- /dev/null ++++ b/drivers/serial/stm-serial.c +@@ -0,0 +1,202 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This code was inspired by some patches made for u-boot covered by: ++ * (c) 2007 Sascha Hauer <s.hauer@pengutronix.de> ++ * (C) Copyright 2009 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ * ++ */ ++ ++/* ++ * Note: This is the driver for the debug UART. There is ++ * only one of these UARTs on the Freescale/SigmaTel parts ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <notifier.h> ++#include <gpio.h> ++#include <asm/io.h> ++#include <mach/imx-regs.h> ++#include <mach/clock.h> ++ ++#define UARTDBGDR 0x00 ++#define UARTDBGFR 0x18 ++# define TXFF (1 << 5) ++# define RXFE (1 << 4) ++#define UARTDBGIBRD 0x24 ++#define UARTDBGFBRD 0x28 ++#define UARTDBGLCR_H 0x2c ++# define WLEN8 (3 << 5) ++# define WLEN7 (2 << 5) ++# define WLEN6 (1 << 5) ++# define WLEN5 (0 << 5) ++# define FEN (1 << 4) ++#define UARTDBGCR 0x30 ++# define UARTEN (1 << 0) ++# define TXE (1 << 8) ++# define RXE (1 << 9) ++#define UARTDBGIMSC 0x38 ++ ++struct stm_serial_local { ++ struct console_device cdev; ++ int baudrate; ++ struct notifier_block notify; ++}; ++ ++static void stm_serial_putc(struct console_device *cdev, char c) ++{ ++ struct device_d *dev = cdev->dev; ++ ++ /* Wait for room in TX FIFO */ ++ while (readl(dev->map_base + UARTDBGFR) & TXFF) ++ ; ++ ++ writel(c, dev->map_base + UARTDBGDR); ++} ++ ++static int stm_serial_tstc(struct console_device *cdev) ++{ ++ struct device_d *dev = cdev->dev; ++ ++ /* Check if RX FIFO is not empty */ ++ return !(readl(dev->map_base + UARTDBGFR) & RXFE); ++} ++ ++static int stm_serial_getc(struct console_device *cdev) ++{ ++ struct device_d *dev = cdev->dev; ++ ++ /* Wait while TX FIFO is empty */ ++ while (readl(dev->map_base + UARTDBGFR) & RXFE) ++ ; ++ ++ return readl(dev->map_base + UARTDBGDR) & 0xff; ++} ++ ++static void stm_serial_flush(struct console_device *cdev) ++{ ++ struct device_d *dev = cdev->dev; ++ ++ /* Wait for TX FIFO empty */ ++ while (readl(dev->map_base + UARTDBGFR) & TXFF) ++ ; ++} ++ ++static int stm_serial_setbaudrate(struct console_device *cdev, int new_baudrate) ++{ ++ struct device_d *dev = cdev->dev; ++ struct stm_serial_local *local = container_of(cdev, struct stm_serial_local, cdev); ++ uint32_t cr, lcr_h, quot; ++ ++ /* Disable everything */ ++ cr = readl(dev->map_base + UARTDBGCR); ++ writel(0, dev->map_base + UARTDBGCR); ++ ++ /* Calculate and set baudrate */ ++ quot = (imx_get_xclk() * 4000) / new_baudrate; ++ writel(quot & 0x3f, dev->map_base + UARTDBGFBRD); ++ writel(quot >> 6, dev->map_base + UARTDBGIBRD); ++ ++ /* Set 8n1 mode, enable FIFOs */ ++ lcr_h = WLEN8 | FEN; ++ writel(lcr_h, dev->map_base + UARTDBGLCR_H); ++ ++ /* Re-enable debug UART */ ++ writel(cr, dev->map_base + UARTDBGCR); ++ ++ local->baudrate = new_baudrate; ++ ++ return 0; ++} ++ ++static int stm_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data) ++{ ++ struct stm_serial_local *local = container_of(nb, struct stm_serial_local, notify); ++ ++ return stm_serial_setbaudrate(&local->cdev, local->baudrate); ++} ++ ++static int stm_serial_init_port(struct console_device *cdev) ++{ ++ struct device_d *dev = cdev->dev; ++ /* ++ * If the board specific file registers this console we should force ++ * the usage of the debug UART pins, to be able to let the user see ++ * the output, even if the board file forgets to configure these pins. ++ */ ++ imx_gpio_mode(PWM1_DUART_TX); ++ imx_gpio_mode(PWM0_DUART_RX); ++ ++ /* Disable UART */ ++ writel(0, dev->map_base + UARTDBGCR); ++ ++ /* Mask interrupts */ ++ writel(0, dev->map_base + UARTDBGIMSC); ++ ++ return 0; ++} ++ ++static struct stm_serial_local stm_device = { ++ .cdev = { ++ .f_caps = CONSOLE_STDIN | CONSOLE_STDOUT | CONSOLE_STDERR, ++ .tstc = stm_serial_tstc, ++ .putc = stm_serial_putc, ++ .getc = stm_serial_getc, ++ .flush = stm_serial_flush, ++ .setbrg = stm_serial_setbaudrate, ++ }, ++}; ++ ++static int stm_serial_probe(struct device_d *dev) ++{ ++ stm_device.cdev.dev = dev; ++ dev->type_data = &stm_device.cdev; ++ ++ stm_serial_init_port(&stm_device.cdev); ++ stm_serial_setbaudrate(&stm_device.cdev, CONFIG_BAUDRATE); ++ ++ /* Enable UART */ ++ writel(TXE | RXE | UARTEN, dev->map_base + UARTDBGCR); ++ ++ console_register(&stm_device.cdev); ++ stm_device.notify.notifier_call = stm_clocksource_clock_change; ++ clock_register_client(&stm_device.notify); ++ ++ return 0; ++} ++ ++static void stm_serial_remove(struct device_d *dev) ++{ ++ struct console_device *cdev = dev->type_data; ++ ++ stm_serial_flush(cdev); ++} ++ ++static struct driver_d stm_serial_driver = { ++ .name = "stm_serial", ++ .probe = stm_serial_probe, ++ .remove = stm_serial_remove, ++}; ++ ++static int stm_serial_init(void) ++{ ++ register_driver(&stm_serial_driver); ++ return 0; ++} ++ ++console_initcall(stm_serial_init); +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index 3eebd08..a88e179 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -9,8 +9,14 @@ config DRIVER_SPI_IMX + depends on ARCH_IMX + depends on SPI + +-config DRIVER_SPI_MC13783 +- bool "MC13783 a.k.a. PMIC driver" +- depends on SPI ++config DRIVER_SPI_IMX_0_0 ++ bool ++ depends on ARCH_IMX27 ++ default y ++ ++config DRIVER_SPI_IMX_2_3 ++ bool ++ depends on ARCH_IMX51 ++ default y + + endmenu +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 81f2c6b..b2b2f67 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -1,4 +1,2 @@ + obj-$(CONFIG_SPI) += spi.o + obj-$(CONFIG_DRIVER_SPI_IMX) += imx_spi.o +- +-obj-$(CONFIG_DRIVER_SPI_MC13783) += mc13783.o +diff --git a/drivers/spi/imx_spi.c b/drivers/spi/imx_spi.c +index 5c97919..2ad1bfa 100644 +--- a/drivers/spi/imx_spi.c ++++ b/drivers/spi/imx_spi.c +@@ -26,47 +26,104 @@ + #include <asm/io.h> + #include <gpio.h> + #include <mach/spi.h> +- +-#define MXC_CSPIRXDATA 0x00 +-#define MXC_CSPITXDATA 0x04 +-#define MXC_CSPICTRL 0x08 +-#define MXC_CSPIINT 0x0C +-#define MXC_CSPIDMA 0x18 +-#define MXC_CSPISTAT 0x0C +-#define MXC_CSPIPERIOD 0x14 +-#define MXC_CSPITEST 0x10 +-#define MXC_CSPIRESET 0x1C +- +-#define MXC_CSPICTRL_ENABLE (1 << 10) +-#define MXC_CSPICTRL_MASTER (1 << 11) +-#define MXC_CSPICTRL_XCH (1 << 9) +-#define MXC_CSPICTRL_LOWPOL (1 << 5) +-#define MXC_CSPICTRL_PHA (1 << 6) +-#define MXC_CSPICTRL_SSCTL (1 << 7) +-#define MXC_CSPICTRL_HIGHSSPOL (1 << 8) +-#define MXC_CSPICTRL_CS(x) (((x) & 0x3) << 19) +-#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 0) +-#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 14) +- +-#define MXC_CSPICTRL_MAXDATRATE 0x10 +-#define MXC_CSPICTRL_DATAMASK 0x1F +-#define MXC_CSPICTRL_DATASHIFT 14 +- +-#define MXC_CSPISTAT_TE (1 << 0) +-#define MXC_CSPISTAT_TH (1 << 1) +-#define MXC_CSPISTAT_TF (1 << 2) +-#define MXC_CSPISTAT_RR (1 << 4) +-#define MXC_CSPISTAT_RH (1 << 5) +-#define MXC_CSPISTAT_RF (1 << 6) +-#define MXC_CSPISTAT_RO (1 << 7) +- +-#define MXC_CSPIPERIOD_32KHZ (1 << 15) +- +-#define MXC_CSPITEST_LBC (1 << 14) ++#include <mach/generic.h> ++ ++#define CSPI_0_0_RXDATA 0x00 ++#define CSPI_0_0_TXDATA 0x04 ++#define CSPI_0_0_CTRL 0x08 ++#define CSPI_0_0_INT 0x0C ++#define CSPI_0_0_DMA 0x18 ++#define CSPI_0_0_STAT 0x0C ++#define CSPI_0_0_PERIOD 0x14 ++#define CSPI_0_0_TEST 0x10 ++#define CSPI_0_0_RESET 0x1C ++ ++#define CSPI_0_0_CTRL_ENABLE (1 << 10) ++#define CSPI_0_0_CTRL_MASTER (1 << 11) ++#define CSPI_0_0_CTRL_XCH (1 << 9) ++#define CSPI_0_0_CTRL_LOWPOL (1 << 5) ++#define CSPI_0_0_CTRL_PHA (1 << 6) ++#define CSPI_0_0_CTRL_SSCTL (1 << 7) ++#define CSPI_0_0_CTRL_HIGHSSPOL (1 << 8) ++#define CSPI_0_0_CTRL_CS(x) (((x) & 0x3) << 19) ++#define CSPI_0_0_CTRL_BITCOUNT(x) (((x) & 0x1f) << 0) ++#define CSPI_0_0_CTRL_DATARATE(x) (((x) & 0x7) << 14) ++ ++#define CSPI_0_0_CTRL_MAXDATRATE 0x10 ++#define CSPI_0_0_CTRL_DATAMASK 0x1F ++#define CSPI_0_0_CTRL_DATASHIFT 14 ++ ++#define CSPI_0_0_STAT_TE (1 << 0) ++#define CSPI_0_0_STAT_TH (1 << 1) ++#define CSPI_0_0_STAT_TF (1 << 2) ++#define CSPI_0_0_STAT_RR (1 << 4) ++#define CSPI_0_0_STAT_RH (1 << 5) ++#define CSPI_0_0_STAT_RF (1 << 6) ++#define CSPI_0_0_STAT_RO (1 << 7) ++ ++#define CSPI_0_0_PERIOD_32KHZ (1 << 15) ++ ++#define CSPI_0_0_TEST_LBC (1 << 14) ++ ++#define CSPI_2_3_RXDATA 0x00 ++#define CSPI_2_3_TXDATA 0x04 ++#define CSPI_2_3_CTRL 0x08 ++#define CSPI_2_3_CTRL_ENABLE (1 << 0) ++#define CSPI_2_3_CTRL_XCH (1 << 2) ++#define CSPI_2_3_CTRL_MODE(cs) (1 << ((cs) + 4)) ++#define CSPI_2_3_CTRL_POSTDIV_OFFSET 8 ++#define CSPI_2_3_CTRL_PREDIV_OFFSET 12 ++#define CSPI_2_3_CTRL_CS(cs) ((cs) << 18) ++#define CSPI_2_3_CTRL_BL_OFFSET 20 ++ ++#define CSPI_2_3_CONFIG 0x0c ++#define CSPI_2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) ++#define CSPI_2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4)) ++#define CSPI_2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8)) ++#define CSPI_2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12)) ++ ++#define CSPI_2_3_INT 0x10 ++#define CSPI_2_3_INT_TEEN (1 << 0) ++#define CSPI_2_3_INT_RREN (1 << 3) ++ ++#define CSPI_2_3_STAT 0x18 ++#define CSPI_2_3_STAT_RR (1 << 3) ++ ++enum imx_spi_devtype { ++#ifdef CONFIG_DRIVER_SPI_IMX1 ++ SPI_IMX_VER_IMX1, ++#endif ++#ifdef CONFIG_DRIVER_SPI_IMX_0_0 ++ SPI_IMX_VER_0_0, ++#endif ++#ifdef CONFIG_DRIVER_SPI_IMX_0_4 ++ SPI_IMX_VER_0_4, ++#endif ++#ifdef CONFIG_DRIVER_SPI_IMX_0_5 ++ SPI_IMX_VER_0_5, ++#endif ++#ifdef CONFIG_DRIVER_SPI_IMX_0_7 ++ SPI_IMX_VER_0_7, ++#endif ++#ifdef CONFIG_DRIVER_SPI_IMX_2_3 ++ SPI_IMX_VER_2_3, ++#endif ++}; + + struct imx_spi { +- struct spi_master master; +- int *chipselect; ++ struct spi_master master; ++ int *cs_array; ++ void __iomem *regs; ++ ++ unsigned int (*xchg_single)(struct imx_spi *imx, u32 data); ++ void (*chipselect)(struct spi_device *spi, int active); ++ void (*init)(struct imx_spi *imx); ++}; ++ ++struct spi_imx_devtype_data { ++ unsigned int (*xchg_single)(struct imx_spi *imx, u32 data); ++ void (*chipselect)(struct spi_device *spi, int active); ++ void (*init)(struct imx_spi *imx); + }; + + static int imx_spi_setup(struct spi_device *spi) +@@ -77,29 +134,31 @@ static int imx_spi_setup(struct spi_device *spi) + return 0; + } + +-static unsigned int spi_xchg_single(ulong base, unsigned int data) ++#ifdef CONFIG_DRIVER_SPI_IMX_0_0 ++static unsigned int cspi_0_0_xchg_single(struct imx_spi *imx, unsigned int data) + { ++ void __iomem *base = imx->regs; + +- unsigned int cfg_reg = readl(base + MXC_CSPICTRL); ++ unsigned int cfg_reg = readl(base + CSPI_0_0_CTRL); + +- writel(data, base + MXC_CSPITXDATA); ++ writel(data, base + CSPI_0_0_TXDATA); + +- cfg_reg |= MXC_CSPICTRL_XCH; ++ cfg_reg |= CSPI_0_0_CTRL_XCH; + +- writel(cfg_reg, base + MXC_CSPICTRL); ++ writel(cfg_reg, base + CSPI_0_0_CTRL); + +- while (!(readl(base + MXC_CSPIINT) & MXC_CSPISTAT_RR)); ++ while (!(readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR)); + +- return readl(base + MXC_CSPIRXDATA); ++ return readl(base + CSPI_0_0_RXDATA); + } + +-static void mxc_spi_chipselect(struct spi_device *spi, int is_active) ++static void cspi_0_0_chipselect(struct spi_device *spi, int is_active) + { + struct spi_master *master = spi->master; + struct imx_spi *imx = container_of(master, struct imx_spi, master); +- ulong base = master->dev->map_base; ++ void __iomem *base = imx->regs; + unsigned int cs = 0; +- int gpio = imx->chipselect[spi->chip_select]; ++ int gpio = imx->cs_array[spi->chip_select]; + u32 ctrl_reg; + + if (spi->mode & SPI_CS_HIGH) +@@ -111,35 +170,156 @@ static void mxc_spi_chipselect(struct spi_device *spi, int is_active) + return; + } + +- ctrl_reg = MXC_CSPICTRL_BITCOUNT(spi->bits_per_word - 1) +- | MXC_CSPICTRL_DATARATE(7) /* FIXME: calculate data rate */ +- | MXC_CSPICTRL_ENABLE +- | MXC_CSPICTRL_MASTER; ++ ctrl_reg = CSPI_0_0_CTRL_BITCOUNT(spi->bits_per_word - 1) ++ | CSPI_0_0_CTRL_DATARATE(7) /* FIXME: calculate data rate */ ++ | CSPI_0_0_CTRL_ENABLE ++ | CSPI_0_0_CTRL_MASTER; + + if (gpio < 0) { +- ctrl_reg |= MXC_CSPICTRL_CS(gpio + 32); ++ ctrl_reg |= CSPI_0_0_CTRL_CS(gpio + 32); + } + + if (spi->mode & SPI_CPHA) +- ctrl_reg |= MXC_CSPICTRL_PHA; ++ ctrl_reg |= CSPI_0_0_CTRL_PHA; + if (spi->mode & SPI_CPOL) +- ctrl_reg |= MXC_CSPICTRL_LOWPOL; ++ ctrl_reg |= CSPI_0_0_CTRL_LOWPOL; + if (spi->mode & SPI_CS_HIGH) +- ctrl_reg |= MXC_CSPICTRL_HIGHSSPOL; ++ ctrl_reg |= CSPI_0_0_CTRL_HIGHSSPOL; + +- writel(ctrl_reg, base + MXC_CSPICTRL); ++ writel(ctrl_reg, base + CSPI_0_0_CTRL); + + if (gpio >= 0) + gpio_set_value(gpio, cs); + } + ++static void cspi_0_0_init(struct imx_spi *imx) ++{ ++ void __iomem *base = imx->regs; ++ ++ writel(CSPI_0_0_CTRL_ENABLE | CSPI_0_0_CTRL_MASTER, ++ base + CSPI_0_0_CTRL); ++ writel(CSPI_0_0_PERIOD_32KHZ, ++ base + CSPI_0_0_PERIOD); ++ while (readl(base + CSPI_0_0_INT) & CSPI_0_0_STAT_RR) ++ readl(base + CSPI_0_0_RXDATA); ++ writel(0, base + CSPI_0_0_INT); ++} ++#endif ++ ++#ifdef CONFIG_DRIVER_SPI_IMX_2_3 ++static unsigned int cspi_2_3_xchg_single(struct imx_spi *imx, unsigned int data) ++{ ++ void __iomem *base = imx->regs; ++ ++ unsigned int cfg_reg = readl(base + CSPI_2_3_CTRL); ++ ++ writel(data, base + CSPI_2_3_TXDATA); ++ ++ cfg_reg |= CSPI_2_3_CTRL_XCH; ++ ++ writel(cfg_reg, base + CSPI_2_3_CTRL); ++ ++ while (!(readl(base + CSPI_2_3_STAT) & CSPI_2_3_STAT_RR)); ++ ++ return readl(base + CSPI_2_3_RXDATA); ++} ++ ++/* FIXME: include/linux/kernel.h */ ++#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) ++ ++static unsigned int cspi_2_3_clkdiv(unsigned int fin, unsigned int fspi) ++{ ++ /* ++ * there are two 4-bit dividers, the pre-divider divides by ++ * $pre, the post-divider by 2^$post ++ */ ++ unsigned int pre, post; ++ ++ if (unlikely(fspi > fin)) ++ return 0; ++ ++ post = fls(fin) - fls(fspi); ++ if (fin > fspi << post) ++ post++; ++ ++ /* now we have: (fin <= fspi << post) with post being minimal */ ++ ++ post = max(4U, post) - 4; ++ if (unlikely(post > 0xf)) { ++ pr_err("%s: cannot set clock freq: %u (base freq: %u)\n", ++ __func__, fspi, fin); ++ return 0xff; ++ } ++ ++ pre = DIV_ROUND_UP(fin, fspi << post) - 1; ++ ++ pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n", ++ __func__, fin, fspi, post, pre); ++ return (pre << CSPI_2_3_CTRL_PREDIV_OFFSET) | ++ (post << CSPI_2_3_CTRL_POSTDIV_OFFSET); ++} ++ ++static void cspi_2_3_chipselect(struct spi_device *spi, int is_active) ++{ ++ struct spi_master *master = spi->master; ++ struct imx_spi *imx = container_of(master, struct imx_spi, master); ++ void __iomem *base = imx->regs; ++ unsigned int cs = spi->chip_select, gpio_cs = 0; ++ int gpio = imx->cs_array[spi->chip_select]; ++ u32 ctrl, cfg = 0; ++ ++ if (spi->mode & SPI_CS_HIGH) ++ gpio_cs = 1; ++ ++ if (!is_active) { ++ if (gpio >= 0) ++ gpio_set_value(gpio, !gpio_cs); ++ return; ++ } ++ ++ ctrl = CSPI_2_3_CTRL_ENABLE; ++ ++ /* set master mode */ ++ ctrl |= CSPI_2_3_CTRL_MODE(cs); ++ ++ /* set clock speed */ ++ ctrl |= cspi_2_3_clkdiv(166000000, spi->max_speed_hz); ++ ++ /* set chip select to use */ ++ ctrl |= CSPI_2_3_CTRL_CS(cs); ++ ++ ctrl |= (spi->bits_per_word - 1) << CSPI_2_3_CTRL_BL_OFFSET; ++ ++ cfg |= CSPI_2_3_CONFIG_SBBCTRL(cs); ++ ++ if (spi->mode & SPI_CPHA) ++ cfg |= CSPI_2_3_CONFIG_SCLKPHA(cs); ++ ++ if (spi->mode & SPI_CPOL) ++ cfg |= CSPI_2_3_CONFIG_SCLKPOL(cs); ++ ++ if (spi->mode & SPI_CS_HIGH) ++ cfg |= CSPI_2_3_CONFIG_SSBPOL(cs); ++ ++ writel(ctrl, base + CSPI_2_3_CTRL); ++ writel(cfg, base + CSPI_2_3_CONFIG); ++ ++ if (gpio >= 0) ++ gpio_set_value(gpio, gpio_cs); ++} ++ ++static void cspi_2_3_init(struct imx_spi *imx) ++{ ++} ++#endif ++ + static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg) + { + struct spi_master *master = spi->master; +- ulong base = master->dev->map_base; ++ struct imx_spi *imx = container_of(master, struct imx_spi, master); + struct spi_transfer *t = NULL; + +- mxc_spi_chipselect(spi, 1); ++ imx->chipselect(spi, 1); + + list_for_each_entry (t, &mesg->transfers, transfer_list) { + const u32 *txbuf = t->tx_buf; +@@ -147,21 +327,39 @@ static int imx_spi_transfer(struct spi_device *spi, struct spi_message *mesg) + int i = 0; + + while(i < t->len >> 2) { +- rxbuf[i] = spi_xchg_single(base, txbuf[i]); ++ rxbuf[i] = imx->xchg_single(imx, txbuf[i]); + i++; + } + } + +- mxc_spi_chipselect(spi, 0); ++ imx->chipselect(spi, 0); + + return 0; + } + ++static struct spi_imx_devtype_data spi_imx_devtype_data[] = { ++#ifdef CONFIG_DRIVER_SPI_IMX_0_0 ++ [SPI_IMX_VER_0_0] = { ++ .chipselect = cspi_0_0_chipselect, ++ .xchg_single = cspi_0_0_xchg_single, ++ .init = cspi_0_0_init, ++ }, ++#endif ++#ifdef CONFIG_DRIVER_SPI_IMX_2_3 ++ [SPI_IMX_VER_2_3] = { ++ .chipselect = cspi_2_3_chipselect, ++ .xchg_single = cspi_2_3_xchg_single, ++ .init = cspi_2_3_init, ++ }, ++#endif ++}; ++ + static int imx_spi_probe(struct device_d *dev) + { + struct spi_master *master; + struct imx_spi *imx; + struct spi_imx_master *pdata = dev->platform_data; ++ enum imx_spi_devtype version; + + imx = xzalloc(sizeof(*imx)); + +@@ -171,15 +369,22 @@ static int imx_spi_probe(struct device_d *dev) + master->setup = imx_spi_setup; + master->transfer = imx_spi_transfer; + master->num_chipselect = pdata->num_chipselect; +- imx->chipselect = pdata->chipselect; +- +- writel(MXC_CSPICTRL_ENABLE | MXC_CSPICTRL_MASTER, +- dev->map_base + MXC_CSPICTRL); +- writel(MXC_CSPIPERIOD_32KHZ, +- dev->map_base + MXC_CSPIPERIOD); +- while (readl(dev->map_base + MXC_CSPIINT) & MXC_CSPISTAT_RR) +- readl(dev->map_base + MXC_CSPIRXDATA); +- writel(0, dev->map_base + MXC_CSPIINT); ++ imx->cs_array = pdata->chipselect; ++ ++#ifdef CONFIG_DRIVER_SPI_IMX_0_0 ++ if (cpu_is_mx27()) ++ version = SPI_IMX_VER_0_0; ++#endif ++#ifdef CONFIG_DRIVER_SPI_IMX_2_3 ++ if (cpu_is_mx51()) ++ version = SPI_IMX_VER_2_3; ++#endif ++ imx->chipselect = spi_imx_devtype_data[version].chipselect; ++ imx->xchg_single = spi_imx_devtype_data[version].xchg_single; ++ imx->init = spi_imx_devtype_data[version].init; ++ imx->regs = (void __iomem *)dev->map_base; ++ ++ imx->init(imx); + + spi_register_master(master); + +diff --git a/drivers/spi/mc13783.c b/drivers/spi/mc13783.c +deleted file mode 100644 +index 19e2780..0000000 +--- a/drivers/spi/mc13783.c ++++ /dev/null +@@ -1,237 +0,0 @@ +-/* +- * Copyright (C) 2007 Sascha Hauer, Pengutronix +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- * +- */ +- +-#include <common.h> +-#include <init.h> +-#include <driver.h> +-#include <spi/spi.h> +-#include <xfuncs.h> +-#include <errno.h> +-#include <mach/pmic.h> +- +-#define REG_INTERRUPT_STATUS_0 0x0 +-#define REG_INTERRUPT_MASK 0x1 +-#define REG_INTERRUPT_SENSE_0 0x2 +-#define REG_INTERRUPT_STATUS_1 0x3 +-#define REG_INTERRUPT_MASK_1 0x4 +-#define REG_INTERRUPT_SENSE_1 0x5 +-#define REG_POWER_UP_MODE_SENSE 0x6 +-#define REG_REVISION 0x7 +-#define REG_SEMAPHORE 0x8 +-#define REG_ARBITRATION_PERIPHERAL_AUDIO 0x9 +-#define REG_ARBITRATION_SWITCHERS 0xa +-#define REG_ARBITRATION_REGULATORS(x) (0xb + (x)) /* 0 .. 1 */ +-#define REG_POWER_CONTROL(x) (0xd + (x)) /* 0 .. 2 */ +-#define REG_REGEN_ASSIGNMENT 0x10 +-#define REG_CONTROL_SPARE 0x11 +-#define REG_MEMORY_A 0x12 +-#define REG_MEMORY_B 0x13 +-#define REG_RTC_TIME 0x14 +-#define REG_RTC_ALARM 0x15 +-#define REG_RTC_DAY 0x16 +-#define REG_RTC_DAY_ALARM 0x17 +-#define REG_SWITCHERS(x) (0x18 + (x)) /* 0 .. 5 */ +-#define REG_REGULATOR_SETTING(x) (0x1e + (x)) /* 0 .. 1 */ +-#define REG_REGULATOR_MODE(x) (0x20 + (x)) /* 0 .. 1 */ +-#define REG_POWER_MISCELLANEOUS 0x22 +-#define REG_POWER_SPARE 0x23 +-#define REG_AUDIO_RX_0 0x24 +-#define REG_AUDIO_RX_1 0x25 +-#define REG_AUDIO_TX 0x26 +-#define REG_AUDIO_SSI_NETWORK 0x27 +-#define REG_AUDIO_CODEC 0x28 +-#define REG_AUDIO_STEREO_DAC 0x29 +-#define REG_AUDIO_SPARE 0x2a +-#define REG_ADC(x) (0x2b + (x)) /* 0 .. 4 */ +-#define REG_CHARGER 0x30 +-#define REG_USB 0x31 +-#define REG_CHARGE_USB_SPARE 0x32 +-#define REG_LED_CONTROL(x) (0x33 + (x)) /* 0 .. 5 */ +-#define REG_SPARE 0x39 +-#define REG_TRIM(x) (0x3a + (x)) /* 0 .. 1 */ +-#define REG_TEST(x) (0x3c + (x)) /* 0 .. 3 */ +- +-#define MXC_PMIC_REG_NUM(reg) (((reg) & 0x3f) << 25) +-#define MXC_PMIC_WRITE (1 << 31) +- +-#define SWX_VOLTAGE(x) ((x) & 0x3f) +-#define SWX_VOLTAGE_DVS(x) (((x) & 0x3f) << 6) +-#define SWX_VOLTAGE_STANDBY(x) (((x) & 0x3f) << 12) +-#define SWX_VOLTAGE_1_450 0x16 +- +-#define SWX_MODE_OFF 0 +-#define SWX_MODE_NO_PULSE_SKIP 1 +-#define SWX_MODE_PULSE_SKIP 2 +-#define SWX_MODE_LOW_POWER_PFM 3 +- +-#define SW1A_MODE(x) (((x) & 0x3) << 0) +-#define SW1A_MODE_STANDBY(x) (((x) & 0x3) << 2) +-#define SW1B_MODE(x) (((x) & 0x3) << 10) +-#define SW1B_MODE_STANDBY(x) (((x) & 0x3) << 12) +-#define SW1A_SOFTSTART (1 << 9) +-#define SW1B_SOFTSTART (1 << 17) +-#define SW_PLL_FACTOR(x) (((x) - 28) << 19) +- +-struct pmic_priv { +- struct cdev cdev; +- struct spi_device *spi; +-}; +- +-static int spi_rw(struct spi_device *spi, void * buf, size_t len) +-{ +- int ret; +- +- struct spi_transfer t = { +- .tx_buf = (const void *)buf, +- .rx_buf = buf, +- .len = len, +- .cs_change = 0, +- .delay_usecs = 0, +- }; +- struct spi_message m; +- +- spi_message_init(&m); +- spi_message_add_tail(&t, &m); +- if ((ret = spi_sync(spi, &m))) +- return ret; +- return 0; +-} +- +-static uint32_t pmic_read_reg(struct pmic_priv *pmic, int reg) +-{ +- uint32_t buf; +- +- buf = MXC_PMIC_REG_NUM(reg); +- +- spi_rw(pmic->spi, &buf, 4); +- +- return buf; +-} +- +-static void pmic_write_reg(struct pmic_priv *pmic, int reg, uint32_t val) +-{ +- uint32_t buf = MXC_PMIC_REG_NUM(reg) | MXC_PMIC_WRITE | (val & 0xffffff); +- +- spi_rw(pmic->spi, &buf, 4); +-} +- +-static struct pmic_priv *pmic_device; +- +-int pmic_power(void) +-{ +- if(!pmic_device) { +- printf("%s: no pmic device available\n", __FUNCTION__); +- return -ENODEV; +- } +- +- pmic_write_reg(pmic_device, REG_SWITCHERS(0), +- SWX_VOLTAGE(SWX_VOLTAGE_1_450) | +- SWX_VOLTAGE_DVS(SWX_VOLTAGE_1_450) | +- SWX_VOLTAGE_STANDBY(SWX_VOLTAGE_1_450)); +- +- pmic_write_reg(pmic_device, REG_SWITCHERS(4), +- SW1A_MODE(SWX_MODE_NO_PULSE_SKIP) | +- SW1A_MODE_STANDBY(SWX_MODE_NO_PULSE_SKIP)| +- SW1A_SOFTSTART | +- SW1B_MODE(SWX_MODE_NO_PULSE_SKIP) | +- SW1B_MODE_STANDBY(SWX_MODE_NO_PULSE_SKIP) | +- SW1B_SOFTSTART | +- SW_PLL_FACTOR(32) +- ); +- +- return 0; +-} +- +-ssize_t pmic_read(struct cdev *cdev, void *_buf, size_t count, ulong offset, ulong flags) +-{ +- int i = count >> 2; +- uint32_t *buf = _buf; +- +- offset >>= 2; +- +- while (i) { +- *buf = pmic_read_reg(pmic_device, offset); +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-ssize_t pmic_write(struct cdev *cdev, const void *_buf, size_t count, ulong offset, ulong flags) +-{ +- int i = count >> 2; +- const uint32_t *buf = _buf; +- +- offset >>= 2; +- +- while (i) { +- pmic_write_reg(pmic_device, offset, *buf); +- buf++; +- i--; +- offset++; +- } +- +- return count; +-} +- +-static struct file_operations pmic_fops = { +- .lseek = dev_lseek_default, +- .read = pmic_read, +- .write = pmic_write, +-}; +- +-static int pmic_probe(struct device_d *dev) +-{ +- struct spi_device *spi = (struct spi_device *)dev->type_data; +- +- if (pmic_device) +- return -EBUSY; +- +- pmic_device = xzalloc(sizeof(*pmic_device)); +- +- pmic_device->cdev.name = "pmic"; +- pmic_device->cdev.size = 256; +- pmic_device->cdev.dev = dev; +- pmic_device->cdev.ops = &pmic_fops; +- +- spi->mode = SPI_MODE_0 | SPI_CS_HIGH; +- spi->bits_per_word = 32; +- pmic_device->spi = spi; +- +- devfs_create(&pmic_device->cdev); +- +- return 0; +-} +- +-static struct driver_d pmic_driver = { +- .name = "mc13783", +- .probe = pmic_probe, +-}; +- +-static int pmic_init(void) +-{ +- register_driver(&pmic_driver); +- return 0; +-} +- +-device_initcall(pmic_init); +- +diff --git a/drivers/usb/gadget/fsl_udc.c b/drivers/usb/gadget/fsl_udc.c +index 119afcb..48fd0b5 100644 +--- a/drivers/usb/gadget/fsl_udc.c ++++ b/drivers/usb/gadget/fsl_udc.c +@@ -563,7 +563,8 @@ static void done(struct fsl_ep *ep, struct fsl_req *req, int status) + dma_free_coherent(curr_td); + } + +- dma_inv_range(req->req.buf, req->req.buf + req->req.length); ++ dma_inv_range((unsigned long)req->req.buf, ++ (unsigned long)(req->req.buf + req->req.length)); + + if (status && (status != -ESHUTDOWN)) + VDBG("complete %s req %p stat %d len %u/%u", +diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c +index 0c30c52..05f1628 100644 +--- a/drivers/usb/host/ehci-omap.c ++++ b/drivers/usb/host/ehci-omap.c +@@ -11,7 +11,7 @@ + + /*-------------------------------------------------------------------------*/ + +-#include <i2c/twl4030.h> ++#include <mfd/twl4030.h> + #include <usb/twl4030.h> + #include <mach/ehci.h> + #include <common.h> +diff --git a/drivers/usb/otg/twl4030.c b/drivers/usb/otg/twl4030.c +index 72edf25..4077169 100644 +--- a/drivers/usb/otg/twl4030.c ++++ b/drivers/usb/otg/twl4030.c +@@ -37,7 +37,7 @@ + * MA 02111-1307 USA + */ + +-#include <i2c/twl4030.h> ++#include <mfd/twl4030.h> + #include <usb/twl4030.h> + #include <clock.h> + +diff --git a/drivers/video/fb.c b/drivers/video/fb.c +index f9a425e..ab2c5eb 100644 +--- a/drivers/video/fb.c ++++ b/drivers/video/fb.c +@@ -80,6 +80,7 @@ int register_framebuffer(struct fb_info *info) + + dev = &info->dev; + dev->priv = info; ++ dev->id = id; + + sprintf(dev->name, "fb"); + +diff --git a/drivers/video/imx-ipu-fb.c b/drivers/video/imx-ipu-fb.c +index 2c25b81..c38082d 100644 +--- a/drivers/video/imx-ipu-fb.c ++++ b/drivers/video/imx-ipu-fb.c +@@ -722,55 +722,11 @@ static void sdc_enable_channel(struct ipu_fb_info *fbi, void *fbmem) + mdelay(2); + } + +-/* +- * mx3fb_set_par() - set framebuffer parameters and change the operating mode. +- * @return: 0 on success or negative error code on failure. +- */ +-static int mx3fb_set_par(struct fb_info *info) +-{ +- struct ipu_fb_info *fbi = info->priv; +- struct imx_ipu_fb_rgb *rgb; +- struct fb_videomode *mode = info->mode; +- int ret; +- +- ret = sdc_init_panel(info, IPU_PIX_FMT_RGB666); +- if (ret < 0) +- return ret; +- +- reg_write(fbi, (mode->left_margin << 16) | mode->upper_margin, +- SDC_BG_POS); +- +- switch (info->bits_per_pixel) { +- case 32: +- rgb = &def_rgb_32; +- break; +- case 24: +- rgb = &def_rgb_24; +- break; +- case 16: +- default: +- rgb = &def_rgb_16; +- break; +- } +- +- /* +- * Copy the RGB parameters for this display +- * from the machine specific parameters. +- */ +- info->red = rgb->red; +- info->green = rgb->green; +- info->blue = rgb->blue; +- info->transp = rgb->transp; +- +- +- return 0; +-} +- + /* References in this function refer to respective Linux kernel sources */ + static void ipu_fb_enable(struct fb_info *info) + { + struct ipu_fb_info *fbi = info->priv; +- ++ struct fb_videomode *mode = info->mode; + u32 reg; + + /* pcm037.c::mxc_board_init() */ +@@ -823,7 +779,10 @@ static void ipu_fb_enable(struct fb_info *info) + ~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G); + reg_write(fbi, reg, SDC_COM_CONF); + +- mx3fb_set_par(info); ++ sdc_init_panel(info, IPU_PIX_FMT_RGB666); ++ ++ reg_write(fbi, (mode->left_margin << 16) | mode->upper_margin, ++ SDC_BG_POS); + + sdc_enable_channel(fbi, info->screen_base); + +@@ -840,8 +799,6 @@ static void ipu_fb_disable(struct fb_info *info) + struct ipu_fb_info *fbi = info->priv; + u32 reg; + +- printf("%s\n", __func__); +- + if (fbi->enable) + fbi->enable(0); + +@@ -855,6 +812,39 @@ static struct fb_ops imxfb_ops = { + .fb_disable = ipu_fb_disable, + }; + ++static void imxfb_init_info(struct fb_info *info, struct fb_videomode *mode, ++ int bpp) ++{ ++ struct imx_ipu_fb_rgb *rgb; ++ ++ info->mode = mode; ++ info->xres = mode->xres; ++ info->yres = mode->yres; ++ info->bits_per_pixel = bpp; ++ ++ switch (info->bits_per_pixel) { ++ case 32: ++ rgb = &def_rgb_32; ++ break; ++ case 24: ++ rgb = &def_rgb_24; ++ break; ++ case 16: ++ default: ++ rgb = &def_rgb_16; ++ break; ++ } ++ ++ /* ++ * Copy the RGB parameters for this display ++ * from the machine specific parameters. ++ */ ++ info->red = rgb->red; ++ info->green = rgb->green; ++ info->blue = rgb->blue; ++ info->transp = rgb->transp; ++} ++ + static int imxfb_probe(struct device_d *dev) + { + struct ipu_fb_info *fbi; +@@ -871,13 +861,11 @@ static int imxfb_probe(struct device_d *dev) + fbi->regs = (void *)dev->map_base; + fbi->dev = dev; + info->priv = fbi; +- info->mode = pdata->mode; +- info->xres = pdata->mode->xres; +- info->yres = pdata->mode->yres; +- info->bits_per_pixel = pdata->bpp; + info->fbops = &imxfb_ops; + fbi->enable = pdata->enable; + ++ imxfb_init_info(info, pdata->mode, pdata->bpp); ++ + dev_info(dev, "i.MX Framebuffer driver\n"); + + /* +diff --git a/fs/fs.c b/fs/fs.c +index 3b5f284..7d8dea7 100644 +--- a/fs/fs.c ++++ b/fs/fs.c +@@ -754,7 +754,7 @@ int mount(const char *device, const char *fsname, const char *_path) + } + + fsdev = xzalloc(sizeof(struct fs_device_d)); +- if (!fs_drv->flags & FS_DRIVER_NO_DEV) { ++ if (!(fs_drv->flags & FS_DRIVER_NO_DEV)) { + fsdev->backingstore = strdup(device); + if (!device) { + printf("need a device for driver %s\n", fsname); +diff --git a/fs/ramfs.c b/fs/ramfs.c +index 9ecb824..6222550 100644 +--- a/fs/ramfs.c ++++ b/fs/ramfs.c +@@ -420,7 +420,7 @@ static int ramfs_truncate(struct device_d *dev, FILE *f, ulong size) + + if (newchunks < oldchunks) { + if (!newchunks) +- node->data = 0; ++ node->data = NULL; + while (newchunks--) + data = data->next; + while (data) { +diff --git a/include/asm-generic/barebox.lds.h b/include/asm-generic/barebox.lds.h +index 1d3f4f7..fc141a4 100644 +--- a/include/asm-generic/barebox.lds.h ++++ b/include/asm-generic/barebox.lds.h +@@ -1,5 +1,5 @@ + +-#if defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX35 ++#if defined CONFIG_ARCH_IMX25 || defined CONFIG_ARCH_IMX35 || defined CONFIG_ARCH_IMX51 + #include <mach/barebox.lds.h> + #endif + +diff --git a/include/cache.h b/include/cache.h +index 5968da9..23841dc 100644 +--- a/include/cache.h ++++ b/include/cache.h +@@ -1,7 +1,6 @@ + #ifndef __CACHE_H + #define __CACHE_H + +-void flush_cache (unsigned long, unsigned long); + int icache_status (void); + void icache_enable (void); + void icache_disable(void); +diff --git a/include/command.h b/include/command.h +index 4a4d9cf..e221546 100644 +--- a/include/command.h ++++ b/include/command.h +@@ -76,22 +76,36 @@ void barebox_cmd_usage(struct command *cmdtp); + + #endif /* __ASSEMBLY__ */ + ++#ifndef DOXYGEN_SHOULD_SKIP_THIS ++ + #define Struct_Section __attribute__ ((unused,section (".barebox_cmd"))) + +-#define BAREBOX_CMD_START(_name) \ +-const struct command __barebox_cmd_##_name \ +- __attribute__ ((unused,section (".barebox_cmd_" __stringify(_name)))) = { \ ++#define BAREBOX_CMD_START(_name) \ ++extern const struct command __barebox_cmd_##_name; \ ++const struct command __barebox_cmd_##_name \ ++ __attribute__ ((unused,section (".barebox_cmd_" __stringify(_name)))) = { \ + .name = #_name, + + #define BAREBOX_CMD_END \ + }; + ++#define BAREBOX_CMD_HELP_START(_name) \ ++static const __maybe_unused char cmd_##_name##_help[] = ++ ++#define BAREBOX_CMD_HELP_USAGE(_name) "Usage: " _name ++#define BAREBOX_CMD_HELP_SHORT(_text) _text ++#define BAREBOX_CMD_HELP_OPT(_opt, _desc) _opt "\t" _desc ++#define BAREBOX_CMD_HELP_TEXT(_text) ++#define BAREBOX_CMD_HELP_END ; ++ + #ifdef CONFIG_LONGHELP + #define BAREBOX_CMD_HELP(text) .help = text, + #else + #define BAREBOX_CMD_HELP(text) + #endif + ++#endif /* DOXYGEN_SHOULD_SKIP_THIS */ ++ + int register_command(struct command *); + + #endif /* __COMMAND_H */ +diff --git a/include/common.h b/include/common.h +index 64f49db..a14bfc1 100644 +--- a/include/common.h ++++ b/include/common.h +@@ -216,4 +216,10 @@ int run_shell(void); + + #define PAGE_SIZE 4096 + ++int memory_display(char *addr, ulong offs, ulong nbytes, int size); ++ ++extern const char version_string[]; ++ ++#define IOMEM(addr) ((void __force __iomem *)(addr)) ++ + #endif /* __COMMON_H_ */ +diff --git a/include/i2c/lp3972.h b/include/i2c/lp3972.h +deleted file mode 100644 +index edb5801..0000000 +--- a/include/i2c/lp3972.h ++++ /dev/null +@@ -1,7 +0,0 @@ +-#ifndef __ASM_ARCH_LP3972_H +-#define __ASM_ARCH_LP3972_H +- +-extern struct i2c_client *lp3972_get_client(void); +- +-#endif /* __ASM_ARCH_LP3972_H */ +- +diff --git a/include/i2c/mc13892.h b/include/i2c/mc13892.h +deleted file mode 100644 +index 112d05b..0000000 +--- a/include/i2c/mc13892.h ++++ /dev/null +@@ -1,93 +0,0 @@ +-/* +- * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> +- * +- * This file is released under the GPLv2 +- * +- * Derived from: +- * - arch-mxc/pmic_external.h -- contains interface of the PMIC protocol driver +- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. +- * +- */ +- +-#ifndef __ASM_ARCH_MC13892_H +-#define __ASM_ARCH_MC13892_H +- +-enum mc13892_reg { +- MC13892_REG_INT_STATUS0 = 0x00, +- MC13892_REG_INT_MASK0 = 0x01, +- MC13892_REG_INT_SENSE0 = 0x02, +- MC13892_REG_INT_STATUS1 = 0x03, +- MC13892_REG_INT_MASK1 = 0x04, +- MC13892_REG_INT_SENSE1 = 0x05, +- MC13892_REG_PU_MODE_S = 0x06, +- MC13892_REG_IDENTIFICATION = 0x07, +- MC13892_REG_UNUSED0 = 0x08, +- MC13892_REG_ACC0 = 0x09, +- MC13892_REG_ACC1 = 0x0a, +- MC13892_REG_UNUSED1 = 0x0b, +- MC13892_REG_UNUSED2 = 0x0c, +- MC13892_REG_POWER_CTL0 = 0x0d, +- MC13892_REG_POWER_CTL1 = 0x0e, +- MC13892_REG_POWER_CTL2 = 0x0f, +- MC13892_REG_REGEN_ASSIGN = 0x10, +- MC13892_REG_UNUSED3 = 0x11, +- MC13892_REG_MEM_A = 0x12, +- MC13892_REG_MEM_B = 0x13, +- MC13892_REG_RTC_TIME = 0x14, +- MC13892_REG_RTC_ALARM = 0x15, +- MC13892_REG_RTC_DAY = 0x16, +- MC13892_REG_RTC_DAY_ALARM = 0x17, +- MC13892_REG_SW_0 = 0x18, +- MC13892_REG_SW_1 = 0x19, +- MC13892_REG_SW_2 = 0x1a, +- MC13892_REG_SW_3 = 0x1b, +- MC13892_REG_SW_4 = 0x1c, +- MC13892_REG_SW_5 = 0x1d, +- MC13892_REG_SETTING_0 = 0x1e, +- MC13892_REG_SETTING_1 = 0x1f, +- MC13892_REG_MODE_0 = 0x20, +- MC13892_REG_MODE_1 = 0x21, +- MC13892_REG_POWER_MISC = 0x22, +- MC13892_REG_UNUSED4 = 0x23, +- MC13892_REG_UNUSED5 = 0x24, +- MC13892_REG_UNUSED6 = 0x25, +- MC13892_REG_UNUSED7 = 0x26, +- MC13892_REG_UNUSED8 = 0x27, +- MC13892_REG_UNUSED9 = 0x28, +- MC13892_REG_UNUSED10 = 0x29, +- MC13892_REG_UNUSED11 = 0x2a, +- MC13892_REG_ADC0 = 0x2b, +- MC13892_REG_ADC1 = 0x2c, +- MC13892_REG_ADC2 = 0x2d, +- MC13892_REG_ADC3 = 0x2e, +- MC13892_REG_ADC4 = 0x2f, +- MC13892_REG_CHARGE = 0x30, +- MC13892_REG_USB0 = 0x31, +- MC13892_REG_USB1 = 0x32, +- MC13892_REG_LED_CTL0 = 0x33, +- MC13892_REG_LED_CTL1 = 0x34, +- MC13892_REG_LED_CTL2 = 0x35, +- MC13892_REG_LED_CTL3 = 0x36, +- MC13892_REG_UNUSED12 = 0x37, +- MC13892_REG_UNUSED13 = 0x38, +- MC13892_REG_TRIM0 = 0x39, +- MC13892_REG_TRIM1 = 0x3a, +- MC13892_REG_TEST0 = 0x3b, +- MC13892_REG_TEST1 = 0x3c, +- MC13892_REG_TEST2 = 0x3d, +- MC13892_REG_TEST3 = 0x3e, +- MC13892_REG_TEST4 = 0x3f, +-}; +- +-struct mc13892 { +- struct cdev cdev; +- struct i2c_client *client; +-}; +- +-extern struct mc13892 *mc13892_get(void); +- +-extern int mc13892_reg_read(struct mc13892 *mc13892, enum mc13892_reg reg, u32 *val); +-extern int mc13892_reg_write(struct mc13892 *mc13892, enum mc13892_reg reg, u32 val); +-extern int mc13892_set_bits(struct mc13892 *mc13892, enum mc13892_reg reg, u32 mask, u32 val); +- +-#endif /* __ASM_ARCH_MC13892_H */ +diff --git a/include/i2c/mc34704.h b/include/i2c/mc34704.h +deleted file mode 100644 +index a3723d7..0000000 +--- a/include/i2c/mc34704.h ++++ /dev/null +@@ -1,26 +0,0 @@ +-/* +- * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> +- * Copyright (C) 2010 Baruch Siach <baruch@tkos.co.il> +- * +- * This file is released under the GPLv2 +- * +- * Derived from: +- * - arch-mxc/pmic_external.h -- contains interface of the PMIC protocol driver +- * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. +- * +- */ +- +-#ifndef __I2C_MC34704_H +-#define __I2C_MC34704_H +- +-struct mc34704 { +- struct cdev cdev; +- struct i2c_client *client; +-}; +- +-extern struct mc34704 *mc34704_get(void); +- +-extern int mc34704_reg_read(struct mc34704 *mc34704, u8 reg, u8 *val); +-extern int mc34704_reg_write(struct mc34704 *mc34704, u8 reg, u8 val); +- +-#endif /* __I2C_MC34704_H */ +diff --git a/include/i2c/mc9sdz60.h b/include/i2c/mc9sdz60.h +deleted file mode 100644 +index 3882cea..0000000 +--- a/include/i2c/mc9sdz60.h ++++ /dev/null +@@ -1,78 +0,0 @@ +-/* +- * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> +- * +- * This file is released under the GPLv2 +- * +- * Derived from: +- * - mcu_max8660-bus.h -- contains interface of the mc9sdz60 and max8660 +- * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. +- * +- */ +- +-#ifndef __ASM_ARCH_MC9SDZ60_H +-#define __ASM_ARCH_MC9SDZ60_H +- +-/** +- * Register addresses for the MC9SDZ60 +- * +- * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h +- * but not include/linux/mfd/mc9s08dz60/pmic.h +- * +- */ +-enum mc9sdz60_reg { +- MC9SDZ60_REG_VERSION = 0x00, +- /* reserved 0x01 */ +- MC9SDZ60_REG_SECS = 0x02, +- MC9SDZ60_REG_MINS = 0x03, +- MC9SDZ60_REG_HRS = 0x04, +- MC9SDZ60_REG_DAY = 0x05, +- MC9SDZ60_REG_DATE = 0x06, +- MC9SDZ60_REG_MONTH = 0x07, +- MC9SDZ60_REG_YEAR = 0x08, +- MC9SDZ60_REG_ALARM_SECS = 0x09, +- MC9SDZ60_REG_ALARM_MINS = 0x0a, +- MC9SDZ60_REG_ALARM_HRS = 0x0b, +- /* reserved 0x0c */ +- /* reserved 0x0d */ +- MC9SDZ60_REG_TS_CONTROL = 0x0e, +- MC9SDZ60_REG_X_LOW = 0x0f, +- MC9SDZ60_REG_Y_LOW = 0x10, +- MC9SDZ60_REG_XY_HIGH = 0x11, +- MC9SDZ60_REG_X_LEFT_LOW = 0x12, +- MC9SDZ60_REG_X_LEFT_HIGH = 0x13, +- MC9SDZ60_REG_X_RIGHT = 0x14, +- MC9SDZ60_REG_Y_TOP_LOW = 0x15, +- MC9SDZ60_REG_Y_TOP_HIGH = 0x16, +- MC9SDZ60_REG_Y_BOTTOM = 0x17, +- /* reserved 0x18 */ +- /* reserved 0x19 */ +- MC9SDZ60_REG_RESET_1 = 0x1a, +- MC9SDZ60_REG_RESET_2 = 0x1b, +- MC9SDZ60_REG_POWER_CTL = 0x1c, +- MC9SDZ60_REG_DELAY_CONFIG = 0x1d, +- /* reserved 0x1e */ +- /* reserved 0x1f */ +- MC9SDZ60_REG_GPIO_1 = 0x20, +- MC9SDZ60_REG_GPIO_2 = 0x21, +- MC9SDZ60_REG_KPD_1 = 0x22, +- MC9SDZ60_REG_KPD_2 = 0x23, +- MC9SDZ60_REG_KPD_CONTROL = 0x24, +- MC9SDZ60_REG_INT_ENABLE_1 = 0x25, +- MC9SDZ60_REG_INT_ENABLE_2 = 0x26, +- MC9SDZ60_REG_INT_FLAG_1 = 0x27, +- MC9SDZ60_REG_INT_FLAG_2 = 0x28, +- MC9SDZ60_REG_DES_FLAG = 0x29, +-}; +- +-struct mc9sdz60 { +- struct cdev cdev; +- struct i2c_client *client; +-}; +- +-extern struct mc9sdz60 *mc9sdz60_get(void); +- +-extern int mc9sdz60_reg_read(struct mc9sdz60 *priv, enum mc9sdz60_reg reg, u8 *val); +-extern int mc9sdz60_reg_write(struct mc9sdz60 *priv, enum mc9sdz60_reg reg, u8 val); +-extern int mc9sdz60_set_bits(struct mc9sdz60 *priv, enum mc9sdz60_reg reg, u8 mask, u8 val); +- +-#endif /* __ASM_ARCH_MC9SDZ60_H */ +diff --git a/include/i2c/twl4030.h b/include/i2c/twl4030.h +deleted file mode 100644 +index 3fef4d9..0000000 +--- a/include/i2c/twl4030.h ++++ /dev/null +@@ -1,461 +0,0 @@ +-/* +- * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de> +- * Copyright (C) 2010 Sascha Hauer <sha@pengutronix.de> +- * +- * This file is released under the GPLv2 +- * +- */ +- +-#ifndef __I2C_TWL4030_H +-#define __I2C_TWL4030_H +- +-#include <common.h> +-#include <i2c/i2c.h> +-#include <linux/err.h> +- +-/* LED */ +-#define TWL4030_LED_LEDEN_LEDAON (1 << 0) +-#define TWL4030_LED_LEDEN_LEDBON (1 << 1) +-#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4) +-#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5) +- +-/* KEYPAD */ +-#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6) +-#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5) +-#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4) +-#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3) +-#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2) +-#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1) +-#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0) +- +-/* P[1-3]_SW_EVENTS */ +-#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6) +-#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5) +-#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4) +-#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3) +-#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2) +-#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1) +-#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0) +- +- +-enum twl4030_reg { +- /* Register base addresses */ +- /* USB */ +- TWL4030_BASEADD_USB = 0x0000, +- /* AUD */ +- TWL4030_BASEADD_AUDIO_VOICE = 0x0100, +- TWL4030_BASEADD_GPIO = 0x0198, +- TWL4030_BASEADD_INTBR = 0x0185, +- TWL4030_BASEADD_PIH = 0x0180, +- TWL4030_BASEADD_TEST = 0x014C, +- /* AUX */ +- TWL4030_BASEADD_INTERRUPTS = 0x02B9, +- TWL4030_BASEADD_LED = 0x02EE, +- TWL4030_BASEADD_MADC = 0x0200, +- TWL4030_BASEADD_MAIN_CHARGE = 0x0274, +- TWL4030_BASEADD_PRECHARGE = 0x02AA, +- TWL4030_BASEADD_PWM0 = 0x02F8, +- TWL4030_BASEADD_PWM1 = 0x02FB, +- TWL4030_BASEADD_PWMA = 0x02EF, +- TWL4030_BASEADD_PWMB = 0x02F1, +- TWL4030_BASEADD_KEYPAD = 0x02D2, +- /* POWER */ +- TWL4030_BASEADD_BACKUP = 0x0314, +- TWL4030_BASEADD_INT = 0x032E, +- TWL4030_BASEADD_PM_MASTER = 0x0336, +- TWL4030_BASEADD_PM_RECIEVER = 0x035B, +- TWL4030_BASEADD_RTC = 0x031C, +- TWL4030_BASEADD_SECURED_REG = 0x0300, +- +- /* LED */ +- TWL4030_LED_LEDEN = 0x02EE, +- +- /* +- * Voltage Selection in PM Receiver Module +- */ +- TWL4030_PM_RECEIVER_VAUX2_VSEL_18 = 0x05, +- TWL4030_PM_RECEIVER_VAUX3_VSEL_28 = 0x03, +- TWL4030_PM_RECEIVER_VPLL2_VSEL_18 = 0x05, +- TWL4030_PM_RECEIVER_VDAC_VSEL_18 = 0x03, +- TWL4030_PM_RECEIVER_VMMC1_VSEL_30 = 0x02, +- +- /* +- * Device Selection in PM Receiver Module +- */ +- TWL4030_PM_RECEIVER_DEV_GRP_P1 = 0x20, +- TWL4030_PM_RECEIVER_DEV_GRP_ALL = 0xE0, +- +- /* +- * Power Management Master +- */ +- TWL4030_PM_MASTER_CFG_P1_TRANSITION = 0x0336, +- TWL4030_PM_MASTER_CFG_P2_TRANSITION = 0x0337, +- TWL4030_PM_MASTER_CFG_P3_TRANSITION = 0x0338, +- TWL4030_PM_MASTER_CFG_P123_TRANSITION = 0x0339, +- TWL4030_PM_MASTER_STS_BOOT = 0x033A, +- TWL4030_PM_MASTER_CFG_BOOT = 0x033B, +- TWL4030_PM_MASTER_SHUNDAN = 0x033C, +- TWL4030_PM_MASTER_BOOT_BCI = 0x033D, +- TWL4030_PM_MASTER_CFG_PWRANA1 = 0x033E, +- TWL4030_PM_MASTER_CFG_PWRANA2 = 0x033F, +- TWL4030_PM_MASTER_BGAP_TRIM = 0x0340, +- TWL4030_PM_MASTER_BACKUP_MISC_STS = 0x0341, +- TWL4030_PM_MASTER_BACKUP_MISC_CFG = 0x0342, +- TWL4030_PM_MASTER_BACKUP_MISC_TST = 0x0343, +- TWL4030_PM_MASTER_PROTECT_KEY = 0x0344, +- TWL4030_PM_MASTER_STS_HW_CONDITIONS = 0x0345, +- TWL4030_PM_MASTER_P1_SW_EVENTS = 0x0346, +- TWL4030_PM_MASTER_P2_SW_EVENTS = 0x0347, +- TWL4030_PM_MASTER_P3_SW_EVENTS = 0x0348, +- TWL4030_PM_MASTER_STS_P123_STATE = 0x0349, +- TWL4030_PM_MASTER_PB_CFG = 0x034A, +- TWL4030_PM_MASTER_PB_WORD_MSB = 0x034B, +- TWL4030_PM_MASTER_PB_WORD_LSB = 0x034C, +- TWL4030_PM_MASTER_SEQ_ADD_W2P = 0x0352, +- TWL4030_PM_MASTER_SEQ_ADD_P2A = 0x0353, +- TWL4030_PM_MASTER_SEQ_ADD_A2W = 0x0354, +- TWL4030_PM_MASTER_SEQ_ADD_A2S = 0x0355, +- TWL4030_PM_MASTER_SEQ_ADD_S2A12 = 0x0356, +- TWL4030_PM_MASTER_SEQ_ADD_S2A3 = 0x0357, +- TWL4030_PM_MASTER_SEQ_ADD_WARM = 0x0358, +- TWL4030_PM_MASTER_MEMORY_ADDRESS = 0x0359, +- TWL4030_PM_MASTER_MEMORY_DATA = 0x035A, +- TWL4030_PM_MASTER_SC_CONFIG = 0x035B, +- TWL4030_PM_MASTER_SC_DETECT1 = 0x035C, +- TWL4030_PM_MASTER_SC_DETECT2 = 0x035D, +- TWL4030_PM_MASTER_WATCHDOG_CFG = 0x035E, +- TWL4030_PM_MASTER_IT_CHECK_CFG = 0x035F, +- TWL4030_PM_MASTER_VIBRATOR_CFG = 0x0360, +- TWL4030_PM_MASTER_DCDC_GLOBAL_CFG = 0x0361, +- TWL4030_PM_MASTER_VDD1_TRIM1 = 0x0362, +- TWL4030_PM_MASTER_VDD1_TRIM2 = 0x0363, +- TWL4030_PM_MASTER_VDD2_TRIM1 = 0x0364, +- TWL4030_PM_MASTER_VDD2_TRIM2 = 0x0365, +- TWL4030_PM_MASTER_VIO_TRIM1 = 0x0366, +- TWL4030_PM_MASTER_VIO_TRIM2 = 0x0367, +- TWL4030_PM_MASTER_MISC_CFG = 0x0368, +- TWL4030_PM_MASTER_LS_TST_A = 0x0369, +- TWL4030_PM_MASTER_LS_TST_B = 0x036A, +- TWL4030_PM_MASTER_LS_TST_C = 0x036B, +- TWL4030_PM_MASTER_LS_TST_D = 0x036C, +- TWL4030_PM_MASTER_BB_CFG = 0x036D, +- TWL4030_PM_MASTER_MISC_TST = 0x036E, +- TWL4030_PM_MASTER_TRIM1 = 0x036F, +- +- /* Power Managment Receiver */ +- TWL4030_PM_RECEIVER_SC_CONFIG = 0x035B, +- TWL4030_PM_RECEIVER_SC_DETECT1 = 0x035C, +- TWL4030_PM_RECEIVER_SC_DETECT2 = 0x035D, +- TWL4030_PM_RECEIVER_WATCHDOG_CFG = 0x035E, +- TWL4030_PM_RECEIVER_IT_CHECK_CFG = 0x035F, +- TWL4030_PM_RECEIVER_VIBRATOR_CFG = 0x035F, +- TWL4030_PM_RECEIVER_DC_TO_DC_CFG = 0x0361, +- TWL4030_PM_RECEIVER_VDD1_TRIM1 = 0x0362, +- TWL4030_PM_RECEIVER_VDD1_TRIM2 = 0x0363, +- TWL4030_PM_RECEIVER_VDD2_TRIM1 = 0x0364, +- TWL4030_PM_RECEIVER_VDD2_TRIM2 = 0x0365, +- TWL4030_PM_RECEIVER_VIO_TRIM1 = 0x0366, +- TWL4030_PM_RECEIVER_VIO_TRIM2 = 0x0367, +- TWL4030_PM_RECEIVER_MISC_CFG = 0x0368, +- TWL4030_PM_RECEIVER_LS_TST_A = 0x0369, +- TWL4030_PM_RECEIVER_LS_TST_B = 0x036A, +- TWL4030_PM_RECEIVER_LS_TST_C = 0x036B, +- TWL4030_PM_RECEIVER_LS_TST_D = 0x036C, +- TWL4030_PM_RECEIVER_BB_CFG = 0x036D, +- TWL4030_PM_RECEIVER_MISC_TST = 0x036E, +- TWL4030_PM_RECEIVER_TRIM1 = 0x036F, +- TWL4030_PM_RECEIVER_TRIM2 = 0x0370, +- TWL4030_PM_RECEIVER_DC_DC_TIMEOUT = 0x0371, +- TWL4030_PM_RECEIVER_VAUX1_DEV_GRP = 0x0372, +- TWL4030_PM_RECEIVER_VAUX1_TYPE = 0x0373, +- TWL4030_PM_RECEIVER_VAUX1_REMAP = 0x0374, +- TWL4030_PM_RECEIVER_VAUX1_DEDICATED = 0x0375, +- TWL4030_PM_RECEIVER_VAUX2_DEV_GRP = 0x0376, +- TWL4030_PM_RECEIVER_VAUX2_TYPE = 0x0377, +- TWL4030_PM_RECEIVER_VAUX2_REMAP = 0x0378, +- TWL4030_PM_RECEIVER_VAUX2_DEDICATED = 0x0379, +- TWL4030_PM_RECEIVER_VAUX3_DEV_GRP = 0x037A, +- TWL4030_PM_RECEIVER_VAUX3_TYPE = 0x037B, +- TWL4030_PM_RECEIVER_VAUX3_REMAP = 0x037C, +- TWL4030_PM_RECEIVER_VAUX3_DEDICATED = 0x037D, +- TWL4030_PM_RECEIVER_VAUX4_DEV_GRP = 0x037E, +- TWL4030_PM_RECEIVER_VAUX4_TYPE = 0x037F, +- TWL4030_PM_RECEIVER_VAUX4_REMAP = 0x0380, +- TWL4030_PM_RECEIVER_VAUX4_DEDICATED = 0x0381, +- TWL4030_PM_RECEIVER_VMMC1_DEV_GRP = 0x0382, +- TWL4030_PM_RECEIVER_VMMC1_TYPE = 0x0383, +- TWL4030_PM_RECEIVER_VMMC1_REMAP = 0x0384, +- TWL4030_PM_RECEIVER_VMMC1_DEDICATED = 0x0385, +- TWL4030_PM_RECEIVER_VMMC2_DEV_GRP = 0x0386, +- TWL4030_PM_RECEIVER_VMMC2_TYPE = 0x0387, +- TWL4030_PM_RECEIVER_VMMC2_REMAP = 0x0388, +- TWL4030_PM_RECEIVER_VMMC2_DEDICATED = 0x0389, +- TWL4030_PM_RECEIVER_VPLL1_DEV_GRP = 0x038A, +- TWL4030_PM_RECEIVER_VPLL1_TYPE = 0x038B, +- TWL4030_PM_RECEIVER_VPLL1_REMAP = 0x038C, +- TWL4030_PM_RECEIVER_VPLL1_DEDICATED = 0x038D, +- TWL4030_PM_RECEIVER_VPLL2_DEV_GRP = 0x038E, +- TWL4030_PM_RECEIVER_VPLL2_TYPE = 0x038F, +- TWL4030_PM_RECEIVER_VPLL2_REMAP = 0x0390, +- TWL4030_PM_RECEIVER_VPLL2_DEDICATED = 0x0391, +- TWL4030_PM_RECEIVER_VSIM_DEV_GRP = 0x0392, +- TWL4030_PM_RECEIVER_VSIM_TYPE = 0x0393, +- TWL4030_PM_RECEIVER_VSIM_REMAP = 0x0394, +- TWL4030_PM_RECEIVER_VSIM_DEDICATED = 0x0395, +- TWL4030_PM_RECEIVER_VDAC_DEV_GRP = 0x0396, +- TWL4030_PM_RECEIVER_VDAC_TYPE = 0x0397, +- TWL4030_PM_RECEIVER_VDAC_REMAP = 0x0398, +- TWL4030_PM_RECEIVER_VDAC_DEDICATED = 0x0399, +- TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP = 0x039A, +- TWL4030_PM_RECEIVER_VINTANA1_TYP = 0x039B, +- TWL4030_PM_RECEIVER_VINTANA1_REMAP = 0x039C, +- TWL4030_PM_RECEIVER_VINTANA1_DEDICATED = 0x039D, +- TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP = 0x039E, +- TWL4030_PM_RECEIVER_VINTANA2_TYPE = 0x039F, +- TWL4030_PM_RECEIVER_VINTANA2_REMAP = 0x03A0, +- TWL4030_PM_RECEIVER_VINTANA2_DEDICATED = 0x03A1, +- TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP = 0x03A2, +- TWL4030_PM_RECEIVER_VINTDIG_TYPE = 0x03A3, +- TWL4030_PM_RECEIVER_VINTDIG_REMAP = 0x03A4, +- TWL4030_PM_RECEIVER_VINTDIG_DEDICATED = 0x03A5, +- TWL4030_PM_RECEIVER_VIO_DEV_GRP = 0x03A6, +- TWL4030_PM_RECEIVER_VIO_TYPE = 0x03A7, +- TWL4030_PM_RECEIVER_VIO_REMAP = 0x03A8, +- TWL4030_PM_RECEIVER_VIO_CFG = 0x03A9, +- TWL4030_PM_RECEIVER_VIO_MISC_CFG = 0x03AA, +- TWL4030_PM_RECEIVER_VIO_TEST1 = 0x03AB, +- TWL4030_PM_RECEIVER_VIO_TEST2 = 0x03AC, +- TWL4030_PM_RECEIVER_VIO_OSC = 0x03AD, +- TWL4030_PM_RECEIVER_VIO_RESERVED = 0x03AE, +- TWL4030_PM_RECEIVER_VIO_VSEL = 0x03AF, +- TWL4030_PM_RECEIVER_VDD1_DEV_GRP = 0x03B0, +- TWL4030_PM_RECEIVER_VDD1_TYPE = 0x03B1, +- TWL4030_PM_RECEIVER_VDD1_REMAP = 0x03B2, +- TWL4030_PM_RECEIVER_VDD1_CFG = 0x03B3, +- TWL4030_PM_RECEIVER_VDD1_MISC_CFG = 0x03B4, +- TWL4030_PM_RECEIVER_VDD1_TEST1 = 0x03B5, +- TWL4030_PM_RECEIVER_VDD1_TEST2 = 0x03B6, +- TWL4030_PM_RECEIVER_VDD1_OSC = 0x03B7, +- TWL4030_PM_RECEIVER_VDD1_RESERVED = 0x03B8, +- TWL4030_PM_RECEIVER_VDD1_VSEL = 0x03B9, +- TWL4030_PM_RECEIVER_VDD1_VMODE_CFG = 0x03BA, +- TWL4030_PM_RECEIVER_VDD1_VFLOOR = 0x03BB, +- TWL4030_PM_RECEIVER_VDD1_VROOF = 0x03BC, +- TWL4030_PM_RECEIVER_VDD1_STEP = 0x03BD, +- TWL4030_PM_RECEIVER_VDD2_DEV_GRP = 0x03BE, +- TWL4030_PM_RECEIVER_VDD2_TYPE = 0x03BF, +- TWL4030_PM_RECEIVER_VDD2_REMAP = 0x03C0, +- TWL4030_PM_RECEIVER_VDD2_CFG = 0x03C1, +- TWL4030_PM_RECEIVER_VDD2_MISC_CFG = 0x03C2, +- TWL4030_PM_RECEIVER_VDD2_TEST1 = 0x03C3, +- TWL4030_PM_RECEIVER_VDD2_TEST2 = 0x03C4, +- TWL4030_PM_RECEIVER_VDD2_OSC = 0x03C5, +- TWL4030_PM_RECEIVER_VDD2_RESERVED = 0x03C6, +- TWL4030_PM_RECEIVER_VDD2_VSEL = 0x03C7, +- TWL4030_PM_RECEIVER_VDD2_VMODE_CFG = 0x03C8, +- TWL4030_PM_RECEIVER_VDD2_VFLOOR = 0x03C9, +- TWL4030_PM_RECEIVER_VDD2_VROOF = 0x03CA, +- TWL4030_PM_RECEIVER_VDD2_STEP = 0x03CB, +- TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP = 0x03CC, +- TWL4030_PM_RECEIVER_VUSB1V5_TYPE = 0x03CD, +- TWL4030_PM_RECEIVER_VUSB1V5_REMAP = 0x03CE, +- TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP = 0x03CF, +- TWL4030_PM_RECEIVER_VUSB1V8_TYPE = 0x03D0, +- TWL4030_PM_RECEIVER_VUSB1V8_REMAP = 0x03D1, +- TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP = 0x03D2, +- TWL4030_PM_RECEIVER_VUSB3V1_TYPE = 0x03D3, +- TWL4030_PM_RECEIVER_VUSB3V1_REMAP = 0x03D4, +- TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP = 0x03D5, +- TWL4030_PM_RECEIVER_VUSBCP_TYPE = 0x03D6, +- TWL4030_PM_RECEIVER_VUSBCP_REMAP = 0x03D7, +- TWL4030_PM_RECEIVER_VUSB_DEDICATED1 = 0x03D8, +- TWL4030_PM_RECEIVER_VUSB_DEDICATED2 = 0x03D9, +- TWL4030_PM_RECEIVER_REGEN_DEV_GRP = 0x03DA, +- TWL4030_PM_RECEIVER_REGEN_TYPE = 0x03DB, +- TWL4030_PM_RECEIVER_REGEN_REMAP = 0x03DC, +- TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP = 0x03DD, +- TWL4030_PM_RECEIVER_NRESPWRON_TYPE = 0x03DE, +- TWL4030_PM_RECEIVER_NRESPWRON_REMAP = 0x03DF, +- TWL4030_PM_RECEIVER_CLKEN_DEV_GRP = 0x03E0, +- TWL4030_PM_RECEIVER_CLKEN_TYPE = 0x03E1, +- TWL4030_PM_RECEIVER_CLKEN_REMAP = 0x03E2, +- TWL4030_PM_RECEIVER_SYSEN_DEV_GRP = 0x03E3, +- TWL4030_PM_RECEIVER_SYSEN_TYPE = 0x03E4, +- TWL4030_PM_RECEIVER_SYSEN_REMAP = 0x03E5, +- TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP = 0x03E6, +- TWL4030_PM_RECEIVER_HFCLKOUT_TYPE = 0x03E7, +- TWL4030_PM_RECEIVER_HFCLKOUT_REMAP = 0x03E8, +- TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP = 0x03E9, +- TWL4030_PM_RECEIVER_32KCLKOUT_TYPE = 0x03EA, +- TWL4030_PM_RECEIVER_32KCLKOUT_REMAP = 0x03EB, +- TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GR = 0x03EC, +- TWL4030_PM_RECEIVER_TRITON_RESET_TYPE = 0x03ED, +- TWL4030_PM_RECEIVER_TRITON_RESET_REMAP = 0x03EE, +- TWL4030_PM_RECEIVER_MAINREF_DEV_GRP = 0x03EF, +- TWL4030_PM_RECEIVER_MAINREF_TYPE = 0x03F0, +- TWL4030_PM_RECEIVER_MAINREF_REMAP = 0x03F1, +- +- /* Keypad */ +- TWL4030_KEYPAD_KEYP_CTRL_REG = 0x02D2, +- TWL4030_KEYPAD_KEY_DEB_REG = 0x02D3, +- TWL4030_KEYPAD_LONG_KEY_REG1 = 0x02D4, +- TWL4030_KEYPAD_LK_PTV_REG = 0x02D5, +- TWL4030_KEYPAD_TIME_OUT_REG1 = 0x02D6, +- TWL4030_KEYPAD_TIME_OUT_REG2 = 0x02D7, +- TWL4030_KEYPAD_KBC_REG = 0x02D8, +- TWL4030_KEYPAD_KBR_REG = 0x02D9, +- TWL4030_KEYPAD_KEYP_SMS = 0x02DA, +- TWL4030_KEYPAD_FULL_CODE_7_0 = 0x02DB, +- TWL4030_KEYPAD_FULL_CODE_15_8 = 0x02DC, +- TWL4030_KEYPAD_FULL_CODE_23_16 = 0x02DD, +- TWL4030_KEYPAD_FULL_CODE_31_24 = 0x02DE, +- TWL4030_KEYPAD_FULL_CODE_39_32 = 0x02DF, +- TWL4030_KEYPAD_FULL_CODE_47_40 = 0x02E0, +- TWL4030_KEYPAD_FULL_CODE_55_48 = 0x02E1, +- TWL4030_KEYPAD_FULL_CODE_63_56 = 0x02E2, +- TWL4030_KEYPAD_KEYP_ISR1 = 0x02E3, +- TWL4030_KEYPAD_KEYP_IMR1 = 0x02E4, +- TWL4030_KEYPAD_KEYP_ISR2 = 0x02E5, +- TWL4030_KEYPAD_KEYP_IMR2 = 0x02E6, +- TWL4030_KEYPAD_KEYP_SIR = 0x02E7, +- TWL4030_KEYPAD_KEYP_EDR = 0x02E8, +- TWL4030_KEYPAD_KEYP_SIH_CTRL = 0x02E9, +- +- /* USB */ +- TWL4030_USB_VENDOR_ID_LO = 0x0000, +- TWL4030_USB_VENDOR_ID_HI = 0x0001, +- TWL4030_USB_PRODUCT_ID_LO = 0x0002, +- TWL4030_USB_PRODUCT_ID_HI = 0x0003, +- TWL4030_USB_FUNC_CTRL = 0x0004, +- TWL4030_USB_FUNC_CTRL_SET = 0x0005, +- TWL4030_USB_FUNC_CTRL_CLR = 0x0006, +- TWL4030_USB_IFC_CTRL = 0x0007, +- TWL4030_USB_IFC_CTRL_SET = 0x0008, +- TWL4030_USB_IFC_CTRL_CLR = 0x0009, +- TWL4030_USB_OTG_CTRL = 0x000A, +- TWL4030_USB_OTG_CTRL_SET = 0x000B, +- TWL4030_USB_OTG_CTRL_CLR = 0x000C, +- TWL4030_USB_USB_INT_EN_RISE = 0x000D, +- TWL4030_USB_USB_INT_EN_RISE_SET = 0x000E, +- TWL4030_USB_USB_INT_EN_RISE_CLR = 0x000F, +- TWL4030_USB_USB_INT_EN_FALL = 0x0010, +- TWL4030_USB_USB_INT_EN_FALL_SET = 0x0011, +- TWL4030_USB_USB_INT_EN_FALL_CLR = 0x0012, +- TWL4030_USB_USB_INT_STS = 0x0013, +- TWL4030_USB_USB_INT_LATCH = 0x0014, +- TWL4030_USB_DEBUG = 0x0015, +- TWL4030_USB_SCRATCH_REG = 0x0016, +- TWL4030_USB_SCRATCH_REG_SET = 0x0017, +- TWL4030_USB_SCRATCH_REG_CLR = 0x0018, +- TWL4030_USB_CARKIT_CTRL = 0x0019, +- TWL4030_USB_CARKIT_CTRL_SET = 0x001A, +- TWL4030_USB_CARKIT_CTRL_CLR = 0x001B, +- TWL4030_USB_CARKIT_INT_DELAY = 0x001C, +- TWL4030_USB_CARKIT_INT_EN = 0x001D, +- TWL4030_USB_CARKIT_INT_EN_SET = 0x001E, +- TWL4030_USB_CARKIT_INT_EN_CLR = 0x001F, +- TWL4030_USB_CARKIT_INT_STS = 0x0020, +- TWL4030_USB_CARKIT_INT_LATCH = 0x0021, +- TWL4030_USB_CARKIT_PLS_CTRL = 0x0022, +- TWL4030_USB_CARKIT_PLS_CTRL_SET = 0x0023, +- TWL4030_USB_CARKIT_PLS_CTRL_CLR = 0x0024, +- TWL4030_USB_TRANS_POS_WIDTH = 0x0025, +- TWL4030_USB_TRANS_NEG_WIDTH = 0x0026, +- TWL4030_USB_RCV_PLTY_RECOVERY = 0x0027, +- TWL4030_USB_MCPC_CTRL = 0x0030, +- TWL4030_USB_MCPC_CTRL_SET = 0x0031, +- TWL4030_USB_MCPC_CTRL_CLR = 0x0032, +- TWL4030_USB_MCPC_IO_CTRL = 0x0033, +- TWL4030_USB_MCPC_IO_CTRL_SET = 0x0034, +- TWL4030_USB_MCPC_IO_CTRL_CLR = 0x0035, +- TWL4030_USB_MCPC_CTRL2 = 0x0036, +- TWL4030_USB_MCPC_CTRL2_SET = 0x0037, +- TWL4030_USB_MCPC_CTRL2_CLR = 0x0038, +- TWL4030_USB_OTHER_FUNC_CTRL = 0x0080, +- TWL4030_USB_OTHER_FUNC_CTRL_SET = 0x0081, +- TWL4030_USB_OTHER_FUNC_CTRL_CLR = 0x0082, +- TWL4030_USB_OTHER_IFC_CTRL = 0x0083, +- TWL4030_USB_OTHER_IFC_CTRL_SET = 0x0084, +- TWL4030_USB_OTHER_IFC_CTRL_CLR = 0x0085, +- TWL4030_USB_OTHER_INT_EN_RISE_SET = 0x0087, +- TWL4030_USB_OTHER_INT_EN_RISE_CLR = 0x0088, +- TWL4030_USB_OTHER_INT_EN_FALL = 0x0089, +- TWL4030_USB_OTHER_INT_EN_FALL_SET = 0x008A, +- TWL4030_USB_OTHER_INT_EN_FALL_CLR = 0x008B, +- TWL4030_USB_OTHER_INT_STS = 0x008C, +- TWL4030_USB_OTHER_INT_LATCH = 0x008D, +- TWL4030_USB_ID_STATUS = 0x0096, +- TWL4030_USB_CARKIT_SM_1_INT_EN = 0x0097, +- TWL4030_USB_CARKIT_SM_1_INT_EN_SET = 0x0098, +- TWL4030_USB_CARKIT_SM_1_INT_EN_CLR = 0x0099, +- TWL4030_USB_CARKIT_SM_1_INT_STS = 0x009A, +- TWL4030_USB_CARKIT_SM_1_INT_LATCH = 0x009B, +- TWL4030_USB_CARKIT_SM_2_INT_EN = 0x009C, +- TWL4030_USB_CARKIT_SM_2_INT_EN_SET = 0x009D, +- TWL4030_USB_CARKIT_SM_2_INT_EN_CLR = 0x009E, +- TWL4030_USB_CARKIT_SM_2_INT_STS = 0x009F, +- TWL4030_USB_CARKIT_SM_2_INT_LATCH = 0x00A0, +- TWL4030_USB_CARKIT_SM_CTRL = 0x00A1, +- TWL4030_USB_CARKIT_SM_CTRL_SET = 0x00A2, +- TWL4030_USB_CARKIT_SM_CTRL_CLR = 0x00A3, +- TWL4030_USB_CARKIT_SM_CMD = 0x00A4, +- TWL4030_USB_CARKIT_SM_CMD_SET = 0x00A5, +- TWL4030_USB_CARKIT_SM_CMD_CLR = 0x00A6, +- TWL4030_USB_CARKIT_SM_CMD_STS = 0x00A7, +- TWL4030_USB_CARKIT_SM_STATUS = 0x00A8, +- TWL4030_USB_CARKIT_SM_ERR_STATUS = 0x00AA, +- TWL4030_USB_CARKIT_SM_CTRL_STATE = 0x00AB, +- TWL4030_USB_POWER_CTRL = 0x00AC, +- TWL4030_USB_POWER_CTRL_SET = 0x00AD, +- TWL4030_USB_POWER_CTRL_CLR = 0x00AE, +- TWL4030_USB_OTHER_IFC_CTRL2 = 0x00AF, +- TWL4030_USB_OTHER_IFC_CTRL2_SET = 0x00B0, +- TWL4030_USB_OTHER_IFC_CTRL2_CLR = 0x00B1, +- TWL4030_USB_REG_CTRL_EN = 0x00B2, +- TWL4030_USB_REG_CTRL_EN_SET = 0x00B3, +- TWL4030_USB_REG_CTRL_EN_CLR = 0x00B4, +- TWL4030_USB_REG_CTRL_ERROR = 0x00B5, +- TWL4030_USB_OTHER_FUNC_CTRL2 = 0x00B8, +- TWL4030_USB_OTHER_FUNC_CTRL2_SET = 0x00B9, +- TWL4030_USB_OTHER_FUNC_CTRL2_CLR = 0x00BA, +- TWL4030_USB_CARKIT_ANA_CTRL = 0x00BB, +- TWL4030_USB_CARKIT_ANA_CTRL_SET = 0x00BC, +- TWL4030_USB_CARKIT_ANA_CTRL_CLR = 0x00BD, +- TWL4030_USB_VBUS_DEBOUNCE = 0x00C0, +- TWL4030_USB_ID_DEBOUNCE = 0x00C1, +- TWL4030_USB_TPH_DP_CON_MIN = 0x00C2, +- TWL4030_USB_TPH_DP_CON_MAX = 0x00C3, +- TWL4030_USB_TCR_DP_CON_MIN = 0x00C4, +- TWL4030_USB_TCR_DP_CON_MAX = 0x00C5, +- TWL4030_USB_TPH_DP_PD_SHORT = 0x00C6, +- TWL4030_USB_TPH_CMD_DLY = 0x00C7, +- TWL4030_USB_TPH_DET_RST = 0x00C8, +- TWL4030_USB_TPH_AUD_BIAS = 0x00C9, +- TWL4030_USB_TCR_UART_DET_MIN = 0x00CA, +- TWL4030_USB_TCR_UART_DET_MAX = 0x00CB, +- TWL4030_USB_TPH_ID_INT_PW = 0x00CD, +- TWL4030_USB_TACC_ID_INT_WAIT = 0x00CE, +- TWL4030_USB_TACC_ID_INT_PW = 0x00CF, +- TWL4030_USB_TPH_CMD_WAIT = 0x00D0, +- TWL4030_USB_TPH_ACK_WAIT = 0x00D1, +- TWL4030_USB_TPH_DP_DISC_DET = 0x00D2, +- TWL4030_USB_VBAT_TIMER = 0x00D3, +- TWL4030_USB_CARKIT_4W_DEBUG = 0x00E0, +- TWL4030_USB_CARKIT_5W_DEBUG = 0x00E1, +- TWL4030_USB_PHY_PWR_CTRL = 0x00FD, +- TWL4030_USB_PHY_CLK_CTRL = 0x00FE, +- TWL4030_USB_PHY_CLK_CTRL_STS = 0x00FF, +-}; +- +-struct twl4030 { +- struct cdev cdev; +- struct i2c_client *client; +-}; +- +-extern struct twl4030 *twl4030_get(void); +- +-extern int twl4030_reg_read(struct twl4030 *twl4030, u16 reg, u8 *val); +-extern int twl4030_reg_write(struct twl4030 *twl4030, u16 reg, u8 val); +-extern int twl4030_set_bits(struct twl4030 *twl4030, enum twl4030_reg reg, u8 mask, u8 val); +- +-#endif /* __I2C_TWL4030_H */ +diff --git a/include/image.h b/include/image.h +index 2c5956d..8932947 100644 +--- a/include/image.h ++++ b/include/image.h +@@ -320,61 +320,6 @@ static inline void image_set_name(image_header_t *hdr, const char *name) + strncpy(image_get_name(hdr), name, IH_NMLEN); + } + +-static inline int image_check_magic(const image_header_t *hdr) +-{ +- return (image_get_magic(hdr) == IH_MAGIC); +-} +-static inline int image_check_type(const image_header_t *hdr, uint8_t type) +-{ +- return (image_get_type(hdr) == type); +-} +-static inline int image_check_arch(const image_header_t *hdr, uint8_t arch) +-{ +- return (image_get_arch(hdr) == arch); +-} +-static inline int image_check_os(const image_header_t *hdr, uint8_t os) +-{ +- return (image_get_os(hdr) == os); +-} +- +-#ifdef __BAREBOX__ +-static inline int image_check_target_arch(const image_header_t *hdr) +-{ +-#if defined(__ARM__) +- if (!image_check_arch(hdr, IH_ARCH_ARM)) +-#elif defined(__avr32__) +- if (!image_check_arch(hdr, IH_ARCH_AVR32)) +-#elif defined(__bfin__) +- if (!image_check_arch(hdr, IH_ARCH_BLACKFIN)) +-#elif defined(__I386__) +- if (!image_check_arch(hdr, IH_ARCH_I386)) +-#elif defined(__m68k__) +- if (!image_check_arch(hdr, IH_ARCH_M68K)) +-#elif defined(__microblaze__) +- if (!image_check_arch(hdr, IH_ARCH_MICROBLAZE)) +-#elif defined(__mips__) +- if (!image_check_arch(hdr, IH_ARCH_MIPS)) +-#elif defined(__nios__) +- if (!image_check_arch(hdr, IH_ARCH_NIOS)) +-#elif defined(__nios2__) +- if (!image_check_arch(hdr, IH_ARCH_NIOS2)) +-#elif defined(__PPC__) +- if (!image_check_arch(hdr, IH_ARCH_PPC)) +-#elif defined(__sh__) +- if (!image_check_arch(hdr, IH_ARCH_SH)) +-#elif defined(__sparc__) +- if (!image_check_arch(hdr, IH_ARCH_SPARC)) +-#elif defined(CONFIG_LINUX) +- if (!image_check_arch(hdr, IH_ARCH_LINUX)) +-#else +-# error Unknown CPU type +-#endif +- return 0; +- +- return 1; +-} +-#endif +- + ulong image_multi_count(const image_header_t *hdr); + void image_multi_getimg(const image_header_t *hdr, ulong idx, + ulong *data, ulong *len); +@@ -391,6 +336,7 @@ void print_image_hdr (image_header_t *hdr); + * image. + */ + struct image_handle *map_image(const char *filename, int verify); ++void unmap_image(struct image_handle *handle); + + /* + * Relocate an image to load_address by uncompressing +diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h +index cb35fd2..6671a72 100644 +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -359,10 +359,10 @@ struct nand_buffers { + * (determine if errors are correctable) + * @write_page: [REPLACEABLE] High-level page write function + */ +- + struct nand_chip { +- void *IO_ADDR_R; +- void *IO_ADDR_W; ++ ++ void __iomem *IO_ADDR_R; ++ void __iomem *IO_ADDR_W; + + uint8_t (*read_byte)(struct mtd_info *mtd); + u16 (*read_word)(struct mtd_info *mtd); +diff --git a/include/mci.h b/include/mci.h +new file mode 100644 +index 0000000..8c669ca +--- /dev/null ++++ b/include/mci.h +@@ -0,0 +1,239 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert, Pengutronix ++ * ++ * This code is partially based on u-boot code: ++ * ++ * Copyright 2008, Freescale Semiconductor, Inc ++ * Andy Fleming ++ * ++ * Based (loosely) on the Linux code ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef _MCI_H_ ++#define _MCI_H_ ++ ++#include <linux/list.h> ++ ++/* Firmware revisions for SD cards */ ++#define SD_VERSION_SD 0x20000 ++#define SD_VERSION_2 (SD_VERSION_SD | 0x20) ++#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10) ++#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a) ++ ++/* Firmware revisions for MMC cards */ ++#define MMC_VERSION_MMC 0x10000 ++#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) ++#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12) ++#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14) ++#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22) ++#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30) ++#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40) ++ ++#define MMC_MODE_HS 0x001 ++#define MMC_MODE_HS_52MHz 0x010 ++#define MMC_MODE_4BIT 0x100 ++#define MMC_MODE_8BIT 0x200 ++ ++#define SD_DATA_4BIT 0x00040000 ++ ++#define IS_SD(x) (x->version & SD_VERSION_SD) ++ ++#define MMC_DATA_READ 1 ++#define MMC_DATA_WRITE 2 ++ ++/* command list */ ++#define MMC_CMD_GO_IDLE_STATE 0 ++#define MMC_CMD_SEND_OP_COND 1 ++#define MMC_CMD_ALL_SEND_CID 2 ++#define MMC_CMD_SET_RELATIVE_ADDR 3 ++#define MMC_CMD_SET_DSR 4 ++#define MMC_CMD_SWITCH 6 ++#define MMC_CMD_SELECT_CARD 7 ++#define MMC_CMD_SEND_EXT_CSD 8 ++#define MMC_CMD_SEND_CSD 9 ++#define MMC_CMD_SEND_CID 10 ++#define MMC_CMD_STOP_TRANSMISSION 12 ++#define MMC_CMD_SEND_STATUS 13 ++#define MMC_CMD_SET_BLOCKLEN 16 ++#define MMC_CMD_READ_SINGLE_BLOCK 17 ++#define MMC_CMD_READ_MULTIPLE_BLOCK 18 ++#define MMC_CMD_WRITE_SINGLE_BLOCK 24 ++#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 ++#define MMC_CMD_APP_CMD 55 ++ ++#define SD_CMD_SEND_RELATIVE_ADDR 3 ++#define SD_CMD_SWITCH_FUNC 6 ++#define SD_CMD_SEND_IF_COND 8 ++ ++#define SD_CMD_APP_SET_BUS_WIDTH 6 ++#define SD_CMD_APP_SEND_OP_COND 41 ++#define SD_CMD_APP_SEND_SCR 51 ++ ++/* SCR definitions in different words */ ++#define SD_HIGHSPEED_BUSY 0x00020000 ++#define SD_HIGHSPEED_SUPPORTED 0x00020000 ++ ++#define MMC_HS_TIMING 0x00000100 ++#define MMC_HS_52MHZ 0x2 ++ ++#define OCR_BUSY 0x80000000 ++/** card's response in its OCR if it is a high capacity card */ ++#define OCR_HCS 0x40000000 ++ ++#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ ++#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ ++#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ ++#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ ++#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ ++#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ ++#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ ++#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ ++#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ ++#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ ++#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ ++#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ ++#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ ++#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ ++#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ ++#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ ++#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ ++ ++#define MMC_SWITCH_MODE_CMD_SET 0x00 /** Change the command set */ ++ /** Set bits in EXT_CSD byte addressed by index which are 1 in value field */ ++#define MMC_SWITCH_MODE_SET_BITS 0x01 ++ /** Clear bits in EXT_CSD byte addressed by index, which are 1 in value field */ ++#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 ++ /** Set target byte to value */ ++#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 ++ ++#define SD_SWITCH_CHECK 0 ++#define SD_SWITCH_SWITCH 1 ++ ++/* ++ * EXT_CSD fields ++ */ ++ ++#define EXT_CSD_BUS_WIDTH 183 /* R/W */ ++#define EXT_CSD_HS_TIMING 185 /* R/W */ ++#define EXT_CSD_CARD_TYPE 196 /* RO */ ++#define EXT_CSD_REV 192 /* RO */ ++#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ ++ ++/* ++ * EXT_CSD field definitions ++ */ ++ ++#define EXT_CSD_CMD_SET_NORMAL (1<<0) ++#define EXT_CSD_CMD_SET_SECURE (1<<1) ++#define EXT_CSD_CMD_SET_CPSECURE (1<<2) ++ ++#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ ++#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ ++ ++#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ ++#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ ++#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ ++ ++#define R1_ILLEGAL_COMMAND (1 << 22) ++#define R1_APP_CMD (1 << 5) ++ ++/* response types */ ++#define MMC_RSP_PRESENT (1 << 0) ++#define MMC_RSP_136 (1 << 1) /* 136 bit response */ ++#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ ++#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ ++#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ ++ ++#define MMC_RSP_NONE (0) ++#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) ++#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) ++#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) ++#define MMC_RSP_R3 (MMC_RSP_PRESENT) ++#define MMC_RSP_R4 (MMC_RSP_PRESENT) ++#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) ++#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) ++#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) ++ ++/** command information to be sent to the SD/MMC card */ ++struct mci_cmd { ++ unsigned cmdidx; /**< Command to be sent to the SD/MMC card */ ++ unsigned resp_type; /**< Type of expected response, refer MMC_RSP_* macros */ ++ unsigned cmdarg; /**< Command's arguments */ ++ unsigned response[4]; /**< card's response */ ++}; ++ ++/** data information to be used with some SD/MMC commands */ ++struct mci_data { ++ union { ++ uint8_t *dest; ++ const uint8_t *src; /**< src buffers don't get written to */ ++ }; ++ unsigned flags; /**< refer MMC_DATA_* to define direction */ ++ unsigned blocks; /**< block count to handle in this command */ ++ unsigned blocksize; /**< block size in bytes (mostly 512) */ ++}; ++ ++/** host information */ ++struct mci_host { ++ struct device_d *hw_dev; /**< the host MCI hardware device */ ++ unsigned voltages; ++ unsigned host_caps; /**< Host's interface capabilities, refer MMC_VDD_* */ ++ unsigned f_min; /**< host interface lower limit */ ++ unsigned f_max; /**< host interface upper limit */ ++ unsigned clock; /**< Current clock used to talk to the card */ ++ unsigned bus_width; /**< used data bus width to the card */ ++ ++ /** init the host interface */ ++ int (*init)(struct mci_host*, struct device_d*); ++ /** change host interface settings */ ++ void (*set_ios)(struct mci_host*, struct device_d*, unsigned, unsigned); ++ /** handle a command */ ++ int (*send_cmd)(struct mci_host*, struct mci_cmd*, struct mci_data*); ++}; ++ ++/** MMC/SD and interface instance information */ ++struct mci { ++ unsigned version; ++ /** != 0 when a high capacity card is connected (OCR -> OCR_HCS) */ ++ int high_capacity; ++ unsigned card_caps; /**< Card's capabilities */ ++ unsigned ocr; /**< card's "operation condition register" */ ++ unsigned scr[2]; ++ unsigned csd[4]; /**< card's "card specific data register" */ ++ unsigned cid[4]; /**< card's "card identification register" */ ++ unsigned short rca; /* FIXME */ ++ unsigned tran_speed; /**< not yet used */ ++ /** currently used data block length for read accesses */ ++ unsigned read_bl_len; ++ /** currently used data block length for write accesses */ ++ unsigned write_bl_len; ++ uint64_t capacity; /**< Card's data capacity in bytes */ ++ int ready_for_use; /** true if already probed */ ++}; ++ ++int mci_register(struct mci_host*); ++ ++#define GET_HOST_DATA(x) (x->priv) ++#define GET_HOST_PDATA(x) (x->platform_data) ++#define GET_MCI_DATA(x) (x->priv) ++#define GET_MCI_PDATA(x) (x->platform_data) ++ ++#endif /* _MCI_H_ */ +diff --git a/include/mfd/lp3972.h b/include/mfd/lp3972.h +new file mode 100644 +index 0000000..edb5801 +--- /dev/null ++++ b/include/mfd/lp3972.h +@@ -0,0 +1,7 @@ ++#ifndef __ASM_ARCH_LP3972_H ++#define __ASM_ARCH_LP3972_H ++ ++extern struct i2c_client *lp3972_get_client(void); ++ ++#endif /* __ASM_ARCH_LP3972_H */ ++ +diff --git a/include/mfd/mc13892.h b/include/mfd/mc13892.h +new file mode 100644 +index 0000000..78a42e9 +--- /dev/null ++++ b/include/mfd/mc13892.h +@@ -0,0 +1,121 @@ ++/* ++ * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> ++ * ++ * This file is released under the GPLv2 ++ * ++ * Derived from: ++ * - arch-mxc/pmic_external.h -- contains interface of the PMIC protocol driver ++ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ */ ++ ++#ifndef __ASM_ARCH_MC13892_H ++#define __ASM_ARCH_MC13892_H ++ ++enum mc13892_reg { ++ MC13892_REG_INT_STATUS0 = 0x00, ++ MC13892_REG_INT_MASK0 = 0x01, ++ MC13892_REG_INT_SENSE0 = 0x02, ++ MC13892_REG_INT_STATUS1 = 0x03, ++ MC13892_REG_INT_MASK1 = 0x04, ++ MC13892_REG_INT_SENSE1 = 0x05, ++ MC13892_REG_PU_MODE_S = 0x06, ++ MC13892_REG_IDENTIFICATION = 0x07, ++ MC13892_REG_UNUSED0 = 0x08, ++ MC13892_REG_ACC0 = 0x09, ++ MC13892_REG_ACC1 = 0x0a, ++ MC13892_REG_UNUSED1 = 0x0b, ++ MC13892_REG_UNUSED2 = 0x0c, ++ MC13892_REG_POWER_CTL0 = 0x0d, ++ MC13892_REG_POWER_CTL1 = 0x0e, ++ MC13892_REG_POWER_CTL2 = 0x0f, ++ MC13892_REG_REGEN_ASSIGN = 0x10, ++ MC13892_REG_UNUSED3 = 0x11, ++ MC13892_REG_MEM_A = 0x12, ++ MC13892_REG_MEM_B = 0x13, ++ MC13892_REG_RTC_TIME = 0x14, ++ MC13892_REG_RTC_ALARM = 0x15, ++ MC13892_REG_RTC_DAY = 0x16, ++ MC13892_REG_RTC_DAY_ALARM = 0x17, ++ MC13892_REG_SW_0 = 0x18, ++ MC13892_REG_SW_1 = 0x19, ++ MC13892_REG_SW_2 = 0x1a, ++ MC13892_REG_SW_3 = 0x1b, ++ MC13892_REG_SW_4 = 0x1c, ++ MC13892_REG_SW_5 = 0x1d, ++ MC13892_REG_SETTING_0 = 0x1e, ++ MC13892_REG_SETTING_1 = 0x1f, ++ MC13892_REG_MODE_0 = 0x20, ++ MC13892_REG_MODE_1 = 0x21, ++ MC13892_REG_POWER_MISC = 0x22, ++ MC13892_REG_UNUSED4 = 0x23, ++ MC13892_REG_UNUSED5 = 0x24, ++ MC13892_REG_UNUSED6 = 0x25, ++ MC13892_REG_UNUSED7 = 0x26, ++ MC13892_REG_UNUSED8 = 0x27, ++ MC13892_REG_UNUSED9 = 0x28, ++ MC13892_REG_UNUSED10 = 0x29, ++ MC13892_REG_UNUSED11 = 0x2a, ++ MC13892_REG_ADC0 = 0x2b, ++ MC13892_REG_ADC1 = 0x2c, ++ MC13892_REG_ADC2 = 0x2d, ++ MC13892_REG_ADC3 = 0x2e, ++ MC13892_REG_ADC4 = 0x2f, ++ MC13892_REG_CHARGE = 0x30, ++ MC13892_REG_USB0 = 0x31, ++ MC13892_REG_USB1 = 0x32, ++ MC13892_REG_LED_CTL0 = 0x33, ++ MC13892_REG_LED_CTL1 = 0x34, ++ MC13892_REG_LED_CTL2 = 0x35, ++ MC13892_REG_LED_CTL3 = 0x36, ++ MC13892_REG_UNUSED12 = 0x37, ++ MC13892_REG_UNUSED13 = 0x38, ++ MC13892_REG_TRIM0 = 0x39, ++ MC13892_REG_TRIM1 = 0x3a, ++ MC13892_REG_TEST0 = 0x3b, ++ MC13892_REG_TEST1 = 0x3c, ++ MC13892_REG_TEST2 = 0x3d, ++ MC13892_REG_TEST3 = 0x3e, ++ MC13892_REG_TEST4 = 0x3f, ++}; ++ ++enum mc13892_revision { ++ MC13892_REVISION_1_0, ++ MC13892_REVISION_1_1, ++ MC13892_REVISION_1_2, ++ MC13892_REVISION_2_0, ++ MC13892_REVISION_2_0a, ++ MC13892_REVISION_2_1, ++ MC13892_REVISION_3_0, ++ MC13892_REVISION_3_1, ++ MC13892_REVISION_3_2, ++ MC13892_REVISION_3_2a, ++ MC13892_REVISION_3_3, ++ MC13892_REVISION_3_5, ++}; ++ ++enum mc13892_mode { ++ MC13892_MODE_I2C, ++ MC13892_MODE_SPI, ++}; ++ ++struct mc13892 { ++ struct cdev cdev; ++ struct i2c_client *client; ++ struct spi_device *spi; ++ enum mc13892_mode mode; ++ enum mc13892_revision revision; ++}; ++ ++extern struct mc13892 *mc13892_get(void); ++ ++extern int mc13892_reg_read(struct mc13892 *mc13892, enum mc13892_reg reg, u32 *val); ++extern int mc13892_reg_write(struct mc13892 *mc13892, enum mc13892_reg reg, u32 val); ++extern int mc13892_set_bits(struct mc13892 *mc13892, enum mc13892_reg reg, u32 mask, u32 val); ++ ++static inline enum mc13892_revision mc13892_get_revision(struct mc13892 *mc13892) ++{ ++ return mc13892->revision; ++} ++ ++#endif /* __ASM_ARCH_MC13892_H */ +diff --git a/include/mfd/mc34704.h b/include/mfd/mc34704.h +new file mode 100644 +index 0000000..a3723d7 +--- /dev/null ++++ b/include/mfd/mc34704.h +@@ -0,0 +1,26 @@ ++/* ++ * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> ++ * Copyright (C) 2010 Baruch Siach <baruch@tkos.co.il> ++ * ++ * This file is released under the GPLv2 ++ * ++ * Derived from: ++ * - arch-mxc/pmic_external.h -- contains interface of the PMIC protocol driver ++ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ */ ++ ++#ifndef __I2C_MC34704_H ++#define __I2C_MC34704_H ++ ++struct mc34704 { ++ struct cdev cdev; ++ struct i2c_client *client; ++}; ++ ++extern struct mc34704 *mc34704_get(void); ++ ++extern int mc34704_reg_read(struct mc34704 *mc34704, u8 reg, u8 *val); ++extern int mc34704_reg_write(struct mc34704 *mc34704, u8 reg, u8 val); ++ ++#endif /* __I2C_MC34704_H */ +diff --git a/include/mfd/mc9sdz60.h b/include/mfd/mc9sdz60.h +new file mode 100644 +index 0000000..3882cea +--- /dev/null ++++ b/include/mfd/mc9sdz60.h +@@ -0,0 +1,78 @@ ++/* ++ * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> ++ * ++ * This file is released under the GPLv2 ++ * ++ * Derived from: ++ * - mcu_max8660-bus.h -- contains interface of the mc9sdz60 and max8660 ++ * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. ++ * ++ */ ++ ++#ifndef __ASM_ARCH_MC9SDZ60_H ++#define __ASM_ARCH_MC9SDZ60_H ++ ++/** ++ * Register addresses for the MC9SDZ60 ++ * ++ * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h ++ * but not include/linux/mfd/mc9s08dz60/pmic.h ++ * ++ */ ++enum mc9sdz60_reg { ++ MC9SDZ60_REG_VERSION = 0x00, ++ /* reserved 0x01 */ ++ MC9SDZ60_REG_SECS = 0x02, ++ MC9SDZ60_REG_MINS = 0x03, ++ MC9SDZ60_REG_HRS = 0x04, ++ MC9SDZ60_REG_DAY = 0x05, ++ MC9SDZ60_REG_DATE = 0x06, ++ MC9SDZ60_REG_MONTH = 0x07, ++ MC9SDZ60_REG_YEAR = 0x08, ++ MC9SDZ60_REG_ALARM_SECS = 0x09, ++ MC9SDZ60_REG_ALARM_MINS = 0x0a, ++ MC9SDZ60_REG_ALARM_HRS = 0x0b, ++ /* reserved 0x0c */ ++ /* reserved 0x0d */ ++ MC9SDZ60_REG_TS_CONTROL = 0x0e, ++ MC9SDZ60_REG_X_LOW = 0x0f, ++ MC9SDZ60_REG_Y_LOW = 0x10, ++ MC9SDZ60_REG_XY_HIGH = 0x11, ++ MC9SDZ60_REG_X_LEFT_LOW = 0x12, ++ MC9SDZ60_REG_X_LEFT_HIGH = 0x13, ++ MC9SDZ60_REG_X_RIGHT = 0x14, ++ MC9SDZ60_REG_Y_TOP_LOW = 0x15, ++ MC9SDZ60_REG_Y_TOP_HIGH = 0x16, ++ MC9SDZ60_REG_Y_BOTTOM = 0x17, ++ /* reserved 0x18 */ ++ /* reserved 0x19 */ ++ MC9SDZ60_REG_RESET_1 = 0x1a, ++ MC9SDZ60_REG_RESET_2 = 0x1b, ++ MC9SDZ60_REG_POWER_CTL = 0x1c, ++ MC9SDZ60_REG_DELAY_CONFIG = 0x1d, ++ /* reserved 0x1e */ ++ /* reserved 0x1f */ ++ MC9SDZ60_REG_GPIO_1 = 0x20, ++ MC9SDZ60_REG_GPIO_2 = 0x21, ++ MC9SDZ60_REG_KPD_1 = 0x22, ++ MC9SDZ60_REG_KPD_2 = 0x23, ++ MC9SDZ60_REG_KPD_CONTROL = 0x24, ++ MC9SDZ60_REG_INT_ENABLE_1 = 0x25, ++ MC9SDZ60_REG_INT_ENABLE_2 = 0x26, ++ MC9SDZ60_REG_INT_FLAG_1 = 0x27, ++ MC9SDZ60_REG_INT_FLAG_2 = 0x28, ++ MC9SDZ60_REG_DES_FLAG = 0x29, ++}; ++ ++struct mc9sdz60 { ++ struct cdev cdev; ++ struct i2c_client *client; ++}; ++ ++extern struct mc9sdz60 *mc9sdz60_get(void); ++ ++extern int mc9sdz60_reg_read(struct mc9sdz60 *priv, enum mc9sdz60_reg reg, u8 *val); ++extern int mc9sdz60_reg_write(struct mc9sdz60 *priv, enum mc9sdz60_reg reg, u8 val); ++extern int mc9sdz60_set_bits(struct mc9sdz60 *priv, enum mc9sdz60_reg reg, u8 mask, u8 val); ++ ++#endif /* __ASM_ARCH_MC9SDZ60_H */ +diff --git a/include/mfd/twl4030.h b/include/mfd/twl4030.h +new file mode 100644 +index 0000000..3fef4d9 +--- /dev/null ++++ b/include/mfd/twl4030.h +@@ -0,0 +1,461 @@ ++/* ++ * Copyright (C) 2010 Michael Grzeschik <mgr@pengutronix.de> ++ * Copyright (C) 2010 Sascha Hauer <sha@pengutronix.de> ++ * ++ * This file is released under the GPLv2 ++ * ++ */ ++ ++#ifndef __I2C_TWL4030_H ++#define __I2C_TWL4030_H ++ ++#include <common.h> ++#include <i2c/i2c.h> ++#include <linux/err.h> ++ ++/* LED */ ++#define TWL4030_LED_LEDEN_LEDAON (1 << 0) ++#define TWL4030_LED_LEDEN_LEDBON (1 << 1) ++#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4) ++#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5) ++ ++/* KEYPAD */ ++#define TWL4030_KEYPAD_CTRL_KBD_ON (1 << 6) ++#define TWL4030_KEYPAD_CTRL_RP_EN (1 << 5) ++#define TWL4030_KEYPAD_CTRL_TOLE_EN (1 << 4) ++#define TWL4030_KEYPAD_CTRL_TOE_EN (1 << 3) ++#define TWL4030_KEYPAD_CTRL_LK_EN (1 << 2) ++#define TWL4030_KEYPAD_CTRL_SOFTMODEN (1 << 1) ++#define TWL4030_KEYPAD_CTRL_SOFT_NRST (1 << 0) ++ ++/* P[1-3]_SW_EVENTS */ ++#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON (1 << 6) ++#define TWL4030_PM_MASTER_SW_EVENTS_STOPON_SYSEN (1 << 5) ++#define TWL4030_PM_MASTER_SW_EVENTS_ENABLE_WARMRESET (1 << 4) ++#define TWL4030_PM_MASTER_SW_EVENTS_LVL_WAKEUP (1 << 3) ++#define TWL4030_PM_MASTER_SW_EVENTS_DEVACT (1 << 2) ++#define TWL4030_PM_MASTER_SW_EVENTS_DEVSLP (1 << 1) ++#define TWL4030_PM_MASTER_SW_EVENTS_DEVOFF (1 << 0) ++ ++ ++enum twl4030_reg { ++ /* Register base addresses */ ++ /* USB */ ++ TWL4030_BASEADD_USB = 0x0000, ++ /* AUD */ ++ TWL4030_BASEADD_AUDIO_VOICE = 0x0100, ++ TWL4030_BASEADD_GPIO = 0x0198, ++ TWL4030_BASEADD_INTBR = 0x0185, ++ TWL4030_BASEADD_PIH = 0x0180, ++ TWL4030_BASEADD_TEST = 0x014C, ++ /* AUX */ ++ TWL4030_BASEADD_INTERRUPTS = 0x02B9, ++ TWL4030_BASEADD_LED = 0x02EE, ++ TWL4030_BASEADD_MADC = 0x0200, ++ TWL4030_BASEADD_MAIN_CHARGE = 0x0274, ++ TWL4030_BASEADD_PRECHARGE = 0x02AA, ++ TWL4030_BASEADD_PWM0 = 0x02F8, ++ TWL4030_BASEADD_PWM1 = 0x02FB, ++ TWL4030_BASEADD_PWMA = 0x02EF, ++ TWL4030_BASEADD_PWMB = 0x02F1, ++ TWL4030_BASEADD_KEYPAD = 0x02D2, ++ /* POWER */ ++ TWL4030_BASEADD_BACKUP = 0x0314, ++ TWL4030_BASEADD_INT = 0x032E, ++ TWL4030_BASEADD_PM_MASTER = 0x0336, ++ TWL4030_BASEADD_PM_RECIEVER = 0x035B, ++ TWL4030_BASEADD_RTC = 0x031C, ++ TWL4030_BASEADD_SECURED_REG = 0x0300, ++ ++ /* LED */ ++ TWL4030_LED_LEDEN = 0x02EE, ++ ++ /* ++ * Voltage Selection in PM Receiver Module ++ */ ++ TWL4030_PM_RECEIVER_VAUX2_VSEL_18 = 0x05, ++ TWL4030_PM_RECEIVER_VAUX3_VSEL_28 = 0x03, ++ TWL4030_PM_RECEIVER_VPLL2_VSEL_18 = 0x05, ++ TWL4030_PM_RECEIVER_VDAC_VSEL_18 = 0x03, ++ TWL4030_PM_RECEIVER_VMMC1_VSEL_30 = 0x02, ++ ++ /* ++ * Device Selection in PM Receiver Module ++ */ ++ TWL4030_PM_RECEIVER_DEV_GRP_P1 = 0x20, ++ TWL4030_PM_RECEIVER_DEV_GRP_ALL = 0xE0, ++ ++ /* ++ * Power Management Master ++ */ ++ TWL4030_PM_MASTER_CFG_P1_TRANSITION = 0x0336, ++ TWL4030_PM_MASTER_CFG_P2_TRANSITION = 0x0337, ++ TWL4030_PM_MASTER_CFG_P3_TRANSITION = 0x0338, ++ TWL4030_PM_MASTER_CFG_P123_TRANSITION = 0x0339, ++ TWL4030_PM_MASTER_STS_BOOT = 0x033A, ++ TWL4030_PM_MASTER_CFG_BOOT = 0x033B, ++ TWL4030_PM_MASTER_SHUNDAN = 0x033C, ++ TWL4030_PM_MASTER_BOOT_BCI = 0x033D, ++ TWL4030_PM_MASTER_CFG_PWRANA1 = 0x033E, ++ TWL4030_PM_MASTER_CFG_PWRANA2 = 0x033F, ++ TWL4030_PM_MASTER_BGAP_TRIM = 0x0340, ++ TWL4030_PM_MASTER_BACKUP_MISC_STS = 0x0341, ++ TWL4030_PM_MASTER_BACKUP_MISC_CFG = 0x0342, ++ TWL4030_PM_MASTER_BACKUP_MISC_TST = 0x0343, ++ TWL4030_PM_MASTER_PROTECT_KEY = 0x0344, ++ TWL4030_PM_MASTER_STS_HW_CONDITIONS = 0x0345, ++ TWL4030_PM_MASTER_P1_SW_EVENTS = 0x0346, ++ TWL4030_PM_MASTER_P2_SW_EVENTS = 0x0347, ++ TWL4030_PM_MASTER_P3_SW_EVENTS = 0x0348, ++ TWL4030_PM_MASTER_STS_P123_STATE = 0x0349, ++ TWL4030_PM_MASTER_PB_CFG = 0x034A, ++ TWL4030_PM_MASTER_PB_WORD_MSB = 0x034B, ++ TWL4030_PM_MASTER_PB_WORD_LSB = 0x034C, ++ TWL4030_PM_MASTER_SEQ_ADD_W2P = 0x0352, ++ TWL4030_PM_MASTER_SEQ_ADD_P2A = 0x0353, ++ TWL4030_PM_MASTER_SEQ_ADD_A2W = 0x0354, ++ TWL4030_PM_MASTER_SEQ_ADD_A2S = 0x0355, ++ TWL4030_PM_MASTER_SEQ_ADD_S2A12 = 0x0356, ++ TWL4030_PM_MASTER_SEQ_ADD_S2A3 = 0x0357, ++ TWL4030_PM_MASTER_SEQ_ADD_WARM = 0x0358, ++ TWL4030_PM_MASTER_MEMORY_ADDRESS = 0x0359, ++ TWL4030_PM_MASTER_MEMORY_DATA = 0x035A, ++ TWL4030_PM_MASTER_SC_CONFIG = 0x035B, ++ TWL4030_PM_MASTER_SC_DETECT1 = 0x035C, ++ TWL4030_PM_MASTER_SC_DETECT2 = 0x035D, ++ TWL4030_PM_MASTER_WATCHDOG_CFG = 0x035E, ++ TWL4030_PM_MASTER_IT_CHECK_CFG = 0x035F, ++ TWL4030_PM_MASTER_VIBRATOR_CFG = 0x0360, ++ TWL4030_PM_MASTER_DCDC_GLOBAL_CFG = 0x0361, ++ TWL4030_PM_MASTER_VDD1_TRIM1 = 0x0362, ++ TWL4030_PM_MASTER_VDD1_TRIM2 = 0x0363, ++ TWL4030_PM_MASTER_VDD2_TRIM1 = 0x0364, ++ TWL4030_PM_MASTER_VDD2_TRIM2 = 0x0365, ++ TWL4030_PM_MASTER_VIO_TRIM1 = 0x0366, ++ TWL4030_PM_MASTER_VIO_TRIM2 = 0x0367, ++ TWL4030_PM_MASTER_MISC_CFG = 0x0368, ++ TWL4030_PM_MASTER_LS_TST_A = 0x0369, ++ TWL4030_PM_MASTER_LS_TST_B = 0x036A, ++ TWL4030_PM_MASTER_LS_TST_C = 0x036B, ++ TWL4030_PM_MASTER_LS_TST_D = 0x036C, ++ TWL4030_PM_MASTER_BB_CFG = 0x036D, ++ TWL4030_PM_MASTER_MISC_TST = 0x036E, ++ TWL4030_PM_MASTER_TRIM1 = 0x036F, ++ ++ /* Power Managment Receiver */ ++ TWL4030_PM_RECEIVER_SC_CONFIG = 0x035B, ++ TWL4030_PM_RECEIVER_SC_DETECT1 = 0x035C, ++ TWL4030_PM_RECEIVER_SC_DETECT2 = 0x035D, ++ TWL4030_PM_RECEIVER_WATCHDOG_CFG = 0x035E, ++ TWL4030_PM_RECEIVER_IT_CHECK_CFG = 0x035F, ++ TWL4030_PM_RECEIVER_VIBRATOR_CFG = 0x035F, ++ TWL4030_PM_RECEIVER_DC_TO_DC_CFG = 0x0361, ++ TWL4030_PM_RECEIVER_VDD1_TRIM1 = 0x0362, ++ TWL4030_PM_RECEIVER_VDD1_TRIM2 = 0x0363, ++ TWL4030_PM_RECEIVER_VDD2_TRIM1 = 0x0364, ++ TWL4030_PM_RECEIVER_VDD2_TRIM2 = 0x0365, ++ TWL4030_PM_RECEIVER_VIO_TRIM1 = 0x0366, ++ TWL4030_PM_RECEIVER_VIO_TRIM2 = 0x0367, ++ TWL4030_PM_RECEIVER_MISC_CFG = 0x0368, ++ TWL4030_PM_RECEIVER_LS_TST_A = 0x0369, ++ TWL4030_PM_RECEIVER_LS_TST_B = 0x036A, ++ TWL4030_PM_RECEIVER_LS_TST_C = 0x036B, ++ TWL4030_PM_RECEIVER_LS_TST_D = 0x036C, ++ TWL4030_PM_RECEIVER_BB_CFG = 0x036D, ++ TWL4030_PM_RECEIVER_MISC_TST = 0x036E, ++ TWL4030_PM_RECEIVER_TRIM1 = 0x036F, ++ TWL4030_PM_RECEIVER_TRIM2 = 0x0370, ++ TWL4030_PM_RECEIVER_DC_DC_TIMEOUT = 0x0371, ++ TWL4030_PM_RECEIVER_VAUX1_DEV_GRP = 0x0372, ++ TWL4030_PM_RECEIVER_VAUX1_TYPE = 0x0373, ++ TWL4030_PM_RECEIVER_VAUX1_REMAP = 0x0374, ++ TWL4030_PM_RECEIVER_VAUX1_DEDICATED = 0x0375, ++ TWL4030_PM_RECEIVER_VAUX2_DEV_GRP = 0x0376, ++ TWL4030_PM_RECEIVER_VAUX2_TYPE = 0x0377, ++ TWL4030_PM_RECEIVER_VAUX2_REMAP = 0x0378, ++ TWL4030_PM_RECEIVER_VAUX2_DEDICATED = 0x0379, ++ TWL4030_PM_RECEIVER_VAUX3_DEV_GRP = 0x037A, ++ TWL4030_PM_RECEIVER_VAUX3_TYPE = 0x037B, ++ TWL4030_PM_RECEIVER_VAUX3_REMAP = 0x037C, ++ TWL4030_PM_RECEIVER_VAUX3_DEDICATED = 0x037D, ++ TWL4030_PM_RECEIVER_VAUX4_DEV_GRP = 0x037E, ++ TWL4030_PM_RECEIVER_VAUX4_TYPE = 0x037F, ++ TWL4030_PM_RECEIVER_VAUX4_REMAP = 0x0380, ++ TWL4030_PM_RECEIVER_VAUX4_DEDICATED = 0x0381, ++ TWL4030_PM_RECEIVER_VMMC1_DEV_GRP = 0x0382, ++ TWL4030_PM_RECEIVER_VMMC1_TYPE = 0x0383, ++ TWL4030_PM_RECEIVER_VMMC1_REMAP = 0x0384, ++ TWL4030_PM_RECEIVER_VMMC1_DEDICATED = 0x0385, ++ TWL4030_PM_RECEIVER_VMMC2_DEV_GRP = 0x0386, ++ TWL4030_PM_RECEIVER_VMMC2_TYPE = 0x0387, ++ TWL4030_PM_RECEIVER_VMMC2_REMAP = 0x0388, ++ TWL4030_PM_RECEIVER_VMMC2_DEDICATED = 0x0389, ++ TWL4030_PM_RECEIVER_VPLL1_DEV_GRP = 0x038A, ++ TWL4030_PM_RECEIVER_VPLL1_TYPE = 0x038B, ++ TWL4030_PM_RECEIVER_VPLL1_REMAP = 0x038C, ++ TWL4030_PM_RECEIVER_VPLL1_DEDICATED = 0x038D, ++ TWL4030_PM_RECEIVER_VPLL2_DEV_GRP = 0x038E, ++ TWL4030_PM_RECEIVER_VPLL2_TYPE = 0x038F, ++ TWL4030_PM_RECEIVER_VPLL2_REMAP = 0x0390, ++ TWL4030_PM_RECEIVER_VPLL2_DEDICATED = 0x0391, ++ TWL4030_PM_RECEIVER_VSIM_DEV_GRP = 0x0392, ++ TWL4030_PM_RECEIVER_VSIM_TYPE = 0x0393, ++ TWL4030_PM_RECEIVER_VSIM_REMAP = 0x0394, ++ TWL4030_PM_RECEIVER_VSIM_DEDICATED = 0x0395, ++ TWL4030_PM_RECEIVER_VDAC_DEV_GRP = 0x0396, ++ TWL4030_PM_RECEIVER_VDAC_TYPE = 0x0397, ++ TWL4030_PM_RECEIVER_VDAC_REMAP = 0x0398, ++ TWL4030_PM_RECEIVER_VDAC_DEDICATED = 0x0399, ++ TWL4030_PM_RECEIVER_VINTANA1_DEV_GRP = 0x039A, ++ TWL4030_PM_RECEIVER_VINTANA1_TYP = 0x039B, ++ TWL4030_PM_RECEIVER_VINTANA1_REMAP = 0x039C, ++ TWL4030_PM_RECEIVER_VINTANA1_DEDICATED = 0x039D, ++ TWL4030_PM_RECEIVER_VINTANA2_DEV_GRP = 0x039E, ++ TWL4030_PM_RECEIVER_VINTANA2_TYPE = 0x039F, ++ TWL4030_PM_RECEIVER_VINTANA2_REMAP = 0x03A0, ++ TWL4030_PM_RECEIVER_VINTANA2_DEDICATED = 0x03A1, ++ TWL4030_PM_RECEIVER_VINTDIG_DEV_GRP = 0x03A2, ++ TWL4030_PM_RECEIVER_VINTDIG_TYPE = 0x03A3, ++ TWL4030_PM_RECEIVER_VINTDIG_REMAP = 0x03A4, ++ TWL4030_PM_RECEIVER_VINTDIG_DEDICATED = 0x03A5, ++ TWL4030_PM_RECEIVER_VIO_DEV_GRP = 0x03A6, ++ TWL4030_PM_RECEIVER_VIO_TYPE = 0x03A7, ++ TWL4030_PM_RECEIVER_VIO_REMAP = 0x03A8, ++ TWL4030_PM_RECEIVER_VIO_CFG = 0x03A9, ++ TWL4030_PM_RECEIVER_VIO_MISC_CFG = 0x03AA, ++ TWL4030_PM_RECEIVER_VIO_TEST1 = 0x03AB, ++ TWL4030_PM_RECEIVER_VIO_TEST2 = 0x03AC, ++ TWL4030_PM_RECEIVER_VIO_OSC = 0x03AD, ++ TWL4030_PM_RECEIVER_VIO_RESERVED = 0x03AE, ++ TWL4030_PM_RECEIVER_VIO_VSEL = 0x03AF, ++ TWL4030_PM_RECEIVER_VDD1_DEV_GRP = 0x03B0, ++ TWL4030_PM_RECEIVER_VDD1_TYPE = 0x03B1, ++ TWL4030_PM_RECEIVER_VDD1_REMAP = 0x03B2, ++ TWL4030_PM_RECEIVER_VDD1_CFG = 0x03B3, ++ TWL4030_PM_RECEIVER_VDD1_MISC_CFG = 0x03B4, ++ TWL4030_PM_RECEIVER_VDD1_TEST1 = 0x03B5, ++ TWL4030_PM_RECEIVER_VDD1_TEST2 = 0x03B6, ++ TWL4030_PM_RECEIVER_VDD1_OSC = 0x03B7, ++ TWL4030_PM_RECEIVER_VDD1_RESERVED = 0x03B8, ++ TWL4030_PM_RECEIVER_VDD1_VSEL = 0x03B9, ++ TWL4030_PM_RECEIVER_VDD1_VMODE_CFG = 0x03BA, ++ TWL4030_PM_RECEIVER_VDD1_VFLOOR = 0x03BB, ++ TWL4030_PM_RECEIVER_VDD1_VROOF = 0x03BC, ++ TWL4030_PM_RECEIVER_VDD1_STEP = 0x03BD, ++ TWL4030_PM_RECEIVER_VDD2_DEV_GRP = 0x03BE, ++ TWL4030_PM_RECEIVER_VDD2_TYPE = 0x03BF, ++ TWL4030_PM_RECEIVER_VDD2_REMAP = 0x03C0, ++ TWL4030_PM_RECEIVER_VDD2_CFG = 0x03C1, ++ TWL4030_PM_RECEIVER_VDD2_MISC_CFG = 0x03C2, ++ TWL4030_PM_RECEIVER_VDD2_TEST1 = 0x03C3, ++ TWL4030_PM_RECEIVER_VDD2_TEST2 = 0x03C4, ++ TWL4030_PM_RECEIVER_VDD2_OSC = 0x03C5, ++ TWL4030_PM_RECEIVER_VDD2_RESERVED = 0x03C6, ++ TWL4030_PM_RECEIVER_VDD2_VSEL = 0x03C7, ++ TWL4030_PM_RECEIVER_VDD2_VMODE_CFG = 0x03C8, ++ TWL4030_PM_RECEIVER_VDD2_VFLOOR = 0x03C9, ++ TWL4030_PM_RECEIVER_VDD2_VROOF = 0x03CA, ++ TWL4030_PM_RECEIVER_VDD2_STEP = 0x03CB, ++ TWL4030_PM_RECEIVER_VUSB1V5_DEV_GRP = 0x03CC, ++ TWL4030_PM_RECEIVER_VUSB1V5_TYPE = 0x03CD, ++ TWL4030_PM_RECEIVER_VUSB1V5_REMAP = 0x03CE, ++ TWL4030_PM_RECEIVER_VUSB1V8_DEV_GRP = 0x03CF, ++ TWL4030_PM_RECEIVER_VUSB1V8_TYPE = 0x03D0, ++ TWL4030_PM_RECEIVER_VUSB1V8_REMAP = 0x03D1, ++ TWL4030_PM_RECEIVER_VUSB3V1_DEV_GRP = 0x03D2, ++ TWL4030_PM_RECEIVER_VUSB3V1_TYPE = 0x03D3, ++ TWL4030_PM_RECEIVER_VUSB3V1_REMAP = 0x03D4, ++ TWL4030_PM_RECEIVER_VUSBCP_DEV_GRP = 0x03D5, ++ TWL4030_PM_RECEIVER_VUSBCP_TYPE = 0x03D6, ++ TWL4030_PM_RECEIVER_VUSBCP_REMAP = 0x03D7, ++ TWL4030_PM_RECEIVER_VUSB_DEDICATED1 = 0x03D8, ++ TWL4030_PM_RECEIVER_VUSB_DEDICATED2 = 0x03D9, ++ TWL4030_PM_RECEIVER_REGEN_DEV_GRP = 0x03DA, ++ TWL4030_PM_RECEIVER_REGEN_TYPE = 0x03DB, ++ TWL4030_PM_RECEIVER_REGEN_REMAP = 0x03DC, ++ TWL4030_PM_RECEIVER_NRESPWRON_DEV_GRP = 0x03DD, ++ TWL4030_PM_RECEIVER_NRESPWRON_TYPE = 0x03DE, ++ TWL4030_PM_RECEIVER_NRESPWRON_REMAP = 0x03DF, ++ TWL4030_PM_RECEIVER_CLKEN_DEV_GRP = 0x03E0, ++ TWL4030_PM_RECEIVER_CLKEN_TYPE = 0x03E1, ++ TWL4030_PM_RECEIVER_CLKEN_REMAP = 0x03E2, ++ TWL4030_PM_RECEIVER_SYSEN_DEV_GRP = 0x03E3, ++ TWL4030_PM_RECEIVER_SYSEN_TYPE = 0x03E4, ++ TWL4030_PM_RECEIVER_SYSEN_REMAP = 0x03E5, ++ TWL4030_PM_RECEIVER_HFCLKOUT_DEV_GRP = 0x03E6, ++ TWL4030_PM_RECEIVER_HFCLKOUT_TYPE = 0x03E7, ++ TWL4030_PM_RECEIVER_HFCLKOUT_REMAP = 0x03E8, ++ TWL4030_PM_RECEIVER_32KCLKOUT_DEV_GRP = 0x03E9, ++ TWL4030_PM_RECEIVER_32KCLKOUT_TYPE = 0x03EA, ++ TWL4030_PM_RECEIVER_32KCLKOUT_REMAP = 0x03EB, ++ TWL4030_PM_RECEIVER_TRITON_RESET_DEV_GR = 0x03EC, ++ TWL4030_PM_RECEIVER_TRITON_RESET_TYPE = 0x03ED, ++ TWL4030_PM_RECEIVER_TRITON_RESET_REMAP = 0x03EE, ++ TWL4030_PM_RECEIVER_MAINREF_DEV_GRP = 0x03EF, ++ TWL4030_PM_RECEIVER_MAINREF_TYPE = 0x03F0, ++ TWL4030_PM_RECEIVER_MAINREF_REMAP = 0x03F1, ++ ++ /* Keypad */ ++ TWL4030_KEYPAD_KEYP_CTRL_REG = 0x02D2, ++ TWL4030_KEYPAD_KEY_DEB_REG = 0x02D3, ++ TWL4030_KEYPAD_LONG_KEY_REG1 = 0x02D4, ++ TWL4030_KEYPAD_LK_PTV_REG = 0x02D5, ++ TWL4030_KEYPAD_TIME_OUT_REG1 = 0x02D6, ++ TWL4030_KEYPAD_TIME_OUT_REG2 = 0x02D7, ++ TWL4030_KEYPAD_KBC_REG = 0x02D8, ++ TWL4030_KEYPAD_KBR_REG = 0x02D9, ++ TWL4030_KEYPAD_KEYP_SMS = 0x02DA, ++ TWL4030_KEYPAD_FULL_CODE_7_0 = 0x02DB, ++ TWL4030_KEYPAD_FULL_CODE_15_8 = 0x02DC, ++ TWL4030_KEYPAD_FULL_CODE_23_16 = 0x02DD, ++ TWL4030_KEYPAD_FULL_CODE_31_24 = 0x02DE, ++ TWL4030_KEYPAD_FULL_CODE_39_32 = 0x02DF, ++ TWL4030_KEYPAD_FULL_CODE_47_40 = 0x02E0, ++ TWL4030_KEYPAD_FULL_CODE_55_48 = 0x02E1, ++ TWL4030_KEYPAD_FULL_CODE_63_56 = 0x02E2, ++ TWL4030_KEYPAD_KEYP_ISR1 = 0x02E3, ++ TWL4030_KEYPAD_KEYP_IMR1 = 0x02E4, ++ TWL4030_KEYPAD_KEYP_ISR2 = 0x02E5, ++ TWL4030_KEYPAD_KEYP_IMR2 = 0x02E6, ++ TWL4030_KEYPAD_KEYP_SIR = 0x02E7, ++ TWL4030_KEYPAD_KEYP_EDR = 0x02E8, ++ TWL4030_KEYPAD_KEYP_SIH_CTRL = 0x02E9, ++ ++ /* USB */ ++ TWL4030_USB_VENDOR_ID_LO = 0x0000, ++ TWL4030_USB_VENDOR_ID_HI = 0x0001, ++ TWL4030_USB_PRODUCT_ID_LO = 0x0002, ++ TWL4030_USB_PRODUCT_ID_HI = 0x0003, ++ TWL4030_USB_FUNC_CTRL = 0x0004, ++ TWL4030_USB_FUNC_CTRL_SET = 0x0005, ++ TWL4030_USB_FUNC_CTRL_CLR = 0x0006, ++ TWL4030_USB_IFC_CTRL = 0x0007, ++ TWL4030_USB_IFC_CTRL_SET = 0x0008, ++ TWL4030_USB_IFC_CTRL_CLR = 0x0009, ++ TWL4030_USB_OTG_CTRL = 0x000A, ++ TWL4030_USB_OTG_CTRL_SET = 0x000B, ++ TWL4030_USB_OTG_CTRL_CLR = 0x000C, ++ TWL4030_USB_USB_INT_EN_RISE = 0x000D, ++ TWL4030_USB_USB_INT_EN_RISE_SET = 0x000E, ++ TWL4030_USB_USB_INT_EN_RISE_CLR = 0x000F, ++ TWL4030_USB_USB_INT_EN_FALL = 0x0010, ++ TWL4030_USB_USB_INT_EN_FALL_SET = 0x0011, ++ TWL4030_USB_USB_INT_EN_FALL_CLR = 0x0012, ++ TWL4030_USB_USB_INT_STS = 0x0013, ++ TWL4030_USB_USB_INT_LATCH = 0x0014, ++ TWL4030_USB_DEBUG = 0x0015, ++ TWL4030_USB_SCRATCH_REG = 0x0016, ++ TWL4030_USB_SCRATCH_REG_SET = 0x0017, ++ TWL4030_USB_SCRATCH_REG_CLR = 0x0018, ++ TWL4030_USB_CARKIT_CTRL = 0x0019, ++ TWL4030_USB_CARKIT_CTRL_SET = 0x001A, ++ TWL4030_USB_CARKIT_CTRL_CLR = 0x001B, ++ TWL4030_USB_CARKIT_INT_DELAY = 0x001C, ++ TWL4030_USB_CARKIT_INT_EN = 0x001D, ++ TWL4030_USB_CARKIT_INT_EN_SET = 0x001E, ++ TWL4030_USB_CARKIT_INT_EN_CLR = 0x001F, ++ TWL4030_USB_CARKIT_INT_STS = 0x0020, ++ TWL4030_USB_CARKIT_INT_LATCH = 0x0021, ++ TWL4030_USB_CARKIT_PLS_CTRL = 0x0022, ++ TWL4030_USB_CARKIT_PLS_CTRL_SET = 0x0023, ++ TWL4030_USB_CARKIT_PLS_CTRL_CLR = 0x0024, ++ TWL4030_USB_TRANS_POS_WIDTH = 0x0025, ++ TWL4030_USB_TRANS_NEG_WIDTH = 0x0026, ++ TWL4030_USB_RCV_PLTY_RECOVERY = 0x0027, ++ TWL4030_USB_MCPC_CTRL = 0x0030, ++ TWL4030_USB_MCPC_CTRL_SET = 0x0031, ++ TWL4030_USB_MCPC_CTRL_CLR = 0x0032, ++ TWL4030_USB_MCPC_IO_CTRL = 0x0033, ++ TWL4030_USB_MCPC_IO_CTRL_SET = 0x0034, ++ TWL4030_USB_MCPC_IO_CTRL_CLR = 0x0035, ++ TWL4030_USB_MCPC_CTRL2 = 0x0036, ++ TWL4030_USB_MCPC_CTRL2_SET = 0x0037, ++ TWL4030_USB_MCPC_CTRL2_CLR = 0x0038, ++ TWL4030_USB_OTHER_FUNC_CTRL = 0x0080, ++ TWL4030_USB_OTHER_FUNC_CTRL_SET = 0x0081, ++ TWL4030_USB_OTHER_FUNC_CTRL_CLR = 0x0082, ++ TWL4030_USB_OTHER_IFC_CTRL = 0x0083, ++ TWL4030_USB_OTHER_IFC_CTRL_SET = 0x0084, ++ TWL4030_USB_OTHER_IFC_CTRL_CLR = 0x0085, ++ TWL4030_USB_OTHER_INT_EN_RISE_SET = 0x0087, ++ TWL4030_USB_OTHER_INT_EN_RISE_CLR = 0x0088, ++ TWL4030_USB_OTHER_INT_EN_FALL = 0x0089, ++ TWL4030_USB_OTHER_INT_EN_FALL_SET = 0x008A, ++ TWL4030_USB_OTHER_INT_EN_FALL_CLR = 0x008B, ++ TWL4030_USB_OTHER_INT_STS = 0x008C, ++ TWL4030_USB_OTHER_INT_LATCH = 0x008D, ++ TWL4030_USB_ID_STATUS = 0x0096, ++ TWL4030_USB_CARKIT_SM_1_INT_EN = 0x0097, ++ TWL4030_USB_CARKIT_SM_1_INT_EN_SET = 0x0098, ++ TWL4030_USB_CARKIT_SM_1_INT_EN_CLR = 0x0099, ++ TWL4030_USB_CARKIT_SM_1_INT_STS = 0x009A, ++ TWL4030_USB_CARKIT_SM_1_INT_LATCH = 0x009B, ++ TWL4030_USB_CARKIT_SM_2_INT_EN = 0x009C, ++ TWL4030_USB_CARKIT_SM_2_INT_EN_SET = 0x009D, ++ TWL4030_USB_CARKIT_SM_2_INT_EN_CLR = 0x009E, ++ TWL4030_USB_CARKIT_SM_2_INT_STS = 0x009F, ++ TWL4030_USB_CARKIT_SM_2_INT_LATCH = 0x00A0, ++ TWL4030_USB_CARKIT_SM_CTRL = 0x00A1, ++ TWL4030_USB_CARKIT_SM_CTRL_SET = 0x00A2, ++ TWL4030_USB_CARKIT_SM_CTRL_CLR = 0x00A3, ++ TWL4030_USB_CARKIT_SM_CMD = 0x00A4, ++ TWL4030_USB_CARKIT_SM_CMD_SET = 0x00A5, ++ TWL4030_USB_CARKIT_SM_CMD_CLR = 0x00A6, ++ TWL4030_USB_CARKIT_SM_CMD_STS = 0x00A7, ++ TWL4030_USB_CARKIT_SM_STATUS = 0x00A8, ++ TWL4030_USB_CARKIT_SM_ERR_STATUS = 0x00AA, ++ TWL4030_USB_CARKIT_SM_CTRL_STATE = 0x00AB, ++ TWL4030_USB_POWER_CTRL = 0x00AC, ++ TWL4030_USB_POWER_CTRL_SET = 0x00AD, ++ TWL4030_USB_POWER_CTRL_CLR = 0x00AE, ++ TWL4030_USB_OTHER_IFC_CTRL2 = 0x00AF, ++ TWL4030_USB_OTHER_IFC_CTRL2_SET = 0x00B0, ++ TWL4030_USB_OTHER_IFC_CTRL2_CLR = 0x00B1, ++ TWL4030_USB_REG_CTRL_EN = 0x00B2, ++ TWL4030_USB_REG_CTRL_EN_SET = 0x00B3, ++ TWL4030_USB_REG_CTRL_EN_CLR = 0x00B4, ++ TWL4030_USB_REG_CTRL_ERROR = 0x00B5, ++ TWL4030_USB_OTHER_FUNC_CTRL2 = 0x00B8, ++ TWL4030_USB_OTHER_FUNC_CTRL2_SET = 0x00B9, ++ TWL4030_USB_OTHER_FUNC_CTRL2_CLR = 0x00BA, ++ TWL4030_USB_CARKIT_ANA_CTRL = 0x00BB, ++ TWL4030_USB_CARKIT_ANA_CTRL_SET = 0x00BC, ++ TWL4030_USB_CARKIT_ANA_CTRL_CLR = 0x00BD, ++ TWL4030_USB_VBUS_DEBOUNCE = 0x00C0, ++ TWL4030_USB_ID_DEBOUNCE = 0x00C1, ++ TWL4030_USB_TPH_DP_CON_MIN = 0x00C2, ++ TWL4030_USB_TPH_DP_CON_MAX = 0x00C3, ++ TWL4030_USB_TCR_DP_CON_MIN = 0x00C4, ++ TWL4030_USB_TCR_DP_CON_MAX = 0x00C5, ++ TWL4030_USB_TPH_DP_PD_SHORT = 0x00C6, ++ TWL4030_USB_TPH_CMD_DLY = 0x00C7, ++ TWL4030_USB_TPH_DET_RST = 0x00C8, ++ TWL4030_USB_TPH_AUD_BIAS = 0x00C9, ++ TWL4030_USB_TCR_UART_DET_MIN = 0x00CA, ++ TWL4030_USB_TCR_UART_DET_MAX = 0x00CB, ++ TWL4030_USB_TPH_ID_INT_PW = 0x00CD, ++ TWL4030_USB_TACC_ID_INT_WAIT = 0x00CE, ++ TWL4030_USB_TACC_ID_INT_PW = 0x00CF, ++ TWL4030_USB_TPH_CMD_WAIT = 0x00D0, ++ TWL4030_USB_TPH_ACK_WAIT = 0x00D1, ++ TWL4030_USB_TPH_DP_DISC_DET = 0x00D2, ++ TWL4030_USB_VBAT_TIMER = 0x00D3, ++ TWL4030_USB_CARKIT_4W_DEBUG = 0x00E0, ++ TWL4030_USB_CARKIT_5W_DEBUG = 0x00E1, ++ TWL4030_USB_PHY_PWR_CTRL = 0x00FD, ++ TWL4030_USB_PHY_CLK_CTRL = 0x00FE, ++ TWL4030_USB_PHY_CLK_CTRL_STS = 0x00FF, ++}; ++ ++struct twl4030 { ++ struct cdev cdev; ++ struct i2c_client *client; ++}; ++ ++extern struct twl4030 *twl4030_get(void); ++ ++extern int twl4030_reg_read(struct twl4030 *twl4030, u16 reg, u8 *val); ++extern int twl4030_reg_write(struct twl4030 *twl4030, u16 reg, u8 val); ++extern int twl4030_set_bits(struct twl4030 *twl4030, enum twl4030_reg reg, u8 mask, u8 val); ++ ++#endif /* __I2C_TWL4030_H */ +diff --git a/include/notifier.h b/include/notifier.h +index 878b17e..cb2be5f 100644 +--- a/include/notifier.h ++++ b/include/notifier.h +@@ -15,6 +15,7 @@ struct notifier_head { + }; + + int notifier_chain_register(struct notifier_head *nh, struct notifier_block *n); ++int notifier_chain_unregister(struct notifier_head *nh, struct notifier_block *n); + + int notifier_call_chain(struct notifier_head *nh, unsigned long val, void *v); + +diff --git a/lib/Kconfig b/lib/Kconfig +index 9eca161..ad2b3cf 100644 +--- a/lib/Kconfig ++++ b/lib/Kconfig +@@ -11,7 +11,7 @@ config CRC16 + bool + + menuconfig DIGEST +- bool "Digest" ++ bool "Digest " + + if DIGEST + +diff --git a/lib/Makefile b/lib/Makefile +index 0c62917..8b986d2 100644 +--- a/lib/Makefile ++++ b/lib/Makefile +@@ -1,7 +1,6 @@ + obj-y += ctype.o + obj-y += rbtree.o + obj-y += display_options.o +-obj-y += ldiv.o + obj-y += string.o + obj-y += vsprintf.o + obj-y += div64.o +diff --git a/lib/copy_file.c b/lib/copy_file.c +index 0ff0435..7083531 100644 +--- a/lib/copy_file.c ++++ b/lib/copy_file.c +@@ -3,6 +3,8 @@ + #include <fcntl.h> + #include <errno.h> + #include <malloc.h> ++#include <libbb.h> ++ + #define RW_BUF_SIZE (ulong)4096 + + /** +diff --git a/lib/crc32.c b/lib/crc32.c +index 3481782..275edb4 100644 +--- a/lib/crc32.c ++++ b/lib/crc32.c +@@ -42,7 +42,7 @@ static void make_crc_table(void); + the information needed to generate CRC's on data a byte at a time for all + combinations of CRC register values and incoming bytes. + */ +-static void make_crc_table() ++static void make_crc_table(void) + { + ulong c; + int n, k; +diff --git a/lib/driver.c b/lib/driver.c +index 66d8fee..ff92e44 100644 +--- a/lib/driver.c ++++ b/lib/driver.c +@@ -54,7 +54,7 @@ struct device_d *get_device_by_name(const char *name) + return NULL; + } + +-struct device_d *get_device_by_name_id(const char *name, int id) ++static struct device_d *get_device_by_name_id(const char *name, int id) + { + struct device_d *dev; + +@@ -244,6 +244,26 @@ int dummy_probe(struct device_d *dev) + } + EXPORT_SYMBOL(dummy_probe); + ++const char *dev_id(const struct device_d *dev) ++{ ++ static char buf[sizeof(unsigned long) * 2]; ++ ++ sprintf(buf, FORMAT_DRIVER_MANE_ID, dev->name, dev->id); ++ ++ return buf; ++} ++ ++void devices_shutdown(void) ++{ ++ struct device_d *dev; ++ ++ list_for_each_entry(dev, &active, active) { ++ if (dev->driver->remove) ++ dev->driver->remove(dev); ++ } ++} ++ ++#ifdef CONFIG_CMD_DEVINFO + static int do_devinfo_subtree(struct device_d *dev, int depth, char edge) + { + struct device_d *child; +@@ -276,27 +296,6 @@ static int do_devinfo_subtree(struct device_d *dev, int depth, char edge) + return 0; + } + +-const char *dev_id(const struct device_d *dev) +-{ +- static char buf[sizeof(unsigned long) * 2]; +- +- sprintf(buf, FORMAT_DRIVER_MANE_ID, dev->name, dev->id); +- +- return buf; +-} +- +-void devices_shutdown(void) +-{ +- struct device_d *dev; +- +- list_for_each_entry(dev, &active, active) { +- if (dev->driver->remove) +- dev->driver->remove(dev); +- } +-} +- +-#ifdef CONFIG_CMD_DEVINFO +- + static int do_devinfo(struct command *cmdtp, int argc, char *argv[]) + { + struct device_d *dev; +@@ -315,7 +314,7 @@ static int do_devinfo(struct command *cmdtp, int argc, char *argv[]) + for_each_driver(drv) + printf("%10s\n",drv->name); + } else { +- struct device_d *dev = get_device_by_name(argv[1]); ++ dev = get_device_by_name(argv[1]); + + if (!dev) { + printf("no such device: %s\n",argv[1]); +@@ -340,30 +339,22 @@ static int do_devinfo(struct command *cmdtp, int argc, char *argv[]) + return 0; + } + +-static const __maybe_unused char cmd_devinfo_help[] = +-"Usage: devinfo [DEVICE]\n" +-"If called without arguments devinfo shows a summary about known devices and\n" +-"drivers. If called with a device path as argument devinfo shows more detailed\n" +-"information about this device and its parameters.\n"; ++BAREBOX_CMD_HELP_START(devinfo) ++BAREBOX_CMD_HELP_USAGE("devinfo [DEVICE]\n") ++BAREBOX_CMD_HELP_SHORT("Output device information.\n") ++BAREBOX_CMD_HELP_END + +-BAREBOX_CMD_START(devinfo) +- .cmd = do_devinfo, +- .usage = "display info about devices and drivers", +- BAREBOX_CMD_HELP(cmd_devinfo_help) +-BAREBOX_CMD_END ++/** ++ * @page devinfo_command + +-#endif ++If called without arguments, devinfo shows a summary of the known ++devices and drivers. ++ ++If called with a device path being the argument, devinfo shows more ++default information about this device and its parameters. ++ ++Example from an MPC5200 based system: + +-/** +- * @page devinfo_command devinfo +- * +- * Usage is: devinfo /dev/\<device> +- * +- * If called without arguments devinfo shows a summary about known devices and +- * drivers. If called with a device path as argument devinfo shows more +- * detailed information about this device and its parameters. +- * +- * Example from an MPC5200 based system: + @verbatim + barebox:/ devinfo /dev/eth0 + base : 0x1002b000 +@@ -378,5 +369,12 @@ BAREBOX_CMD_END + netmask = 255.255.255.0 + serverip = 192.168.23.2 + @endverbatim +- * + */ ++ ++BAREBOX_CMD_START(devinfo) ++ .cmd = do_devinfo, ++ .usage = "Show information about devices and drivers.", ++ BAREBOX_CMD_HELP(cmd_devinfo_help) ++BAREBOX_CMD_END ++#endif ++ +diff --git a/lib/fnmatch.c b/lib/fnmatch.c +index 223b9d3..1a5e8d0 100644 +--- a/lib/fnmatch.c ++++ b/lib/fnmatch.c +@@ -48,10 +48,7 @@ extern int errno; + + /* Match STRING against the filename pattern PATTERN, returning zero if + it matches, nonzero if not. */ +-int fnmatch(pattern, string, flags) +-const char *pattern; +-const char *string; +-int flags; ++int fnmatch(const char *pattern, const char *string, int flags) + { + register const char *p = pattern, *n = string; + register char c; +diff --git a/lib/glob.c b/lib/glob.c +index a5e3d1d..43d2f67 100644 +--- a/lib/glob.c ++++ b/lib/glob.c +@@ -100,11 +100,8 @@ const __ptr_t b; + `glob' returns GLOB_ABEND; if it returns zero, the error is ignored. + If memory cannot be allocated for PGLOB, GLOB_NOSPACE is returned. + Otherwise, `glob' returns zero. */ +-int glob(pattern, flags, errfunc, pglob) +-const char *pattern; +-int flags; +-int (*errfunc) __P((const char *, int)); +-glob_t *pglob; ++int glob(const char *pattern, int flags, ++ int (*errfunc) __P((const char *, int)), glob_t *pglob) + { + const char *filename; + char *dirname = NULL; +@@ -171,7 +168,7 @@ glob_t *pglob; + For each name we found, call glob_in_dir on it and FILENAME, + appending the results to PGLOB. */ + for (i = 0; i < dirs.gl_pathc; ++i) { +- int oldcount; ++ int oldcount1; + + #ifdef SHELL + { +@@ -186,7 +183,7 @@ glob_t *pglob; + } + #endif /* SHELL. */ + +- oldcount = pglob->gl_pathc; ++ oldcount1 = pglob->gl_pathc; + status = glob_in_dir(filename, dirs.gl_pathv[i], + (flags | GLOB_APPEND) & + ~GLOB_NOCHECK, errfunc, pglob); +@@ -202,8 +199,8 @@ glob_t *pglob; + + /* Stick the directory on the front of each name. */ + prefix_array(dirs.gl_pathv[i], +- &pglob->gl_pathv[oldcount], +- pglob->gl_pathc - oldcount, ++ &pglob->gl_pathv[oldcount1], ++ pglob->gl_pathc - oldcount1, + flags & GLOB_MARK); + } + +@@ -286,11 +283,8 @@ out: + unless DIRNAME is just "/". Each old element of ARRAY is freed. + If ADD_SLASH is non-zero, allocate one character more than + necessary, so that a slash can be appended later. */ +-static int prefix_array(dirname, array, n, add_slash) +-const char *dirname; +-char **array; +-size_t n; +-int add_slash; ++static int prefix_array(const char *dirname, char **array, size_t n, ++ int add_slash) + { + register size_t i; + size_t dirlen = strlen(dirname); +@@ -319,12 +313,8 @@ int add_slash; + and matches are searched for in DIRECTORY. + The GLOB_NOSORT bit in FLAGS is ignored. No sorting is ever done. + The GLOB_APPEND flag is assumed to be set (always appends). */ +-static int glob_in_dir(pattern, directory, flags, errfunc, pglob) +-const char *pattern; +-const char *directory; +-int flags; +-int (*errfunc) __P((const char *, int)); +-glob_t *pglob; ++static int glob_in_dir(const char *pattern, const char *directory, ++ int flags, int (*errfunc) __P((const char *, int)), glob_t *pglob) + { + __ptr_t stream; + +@@ -457,12 +447,10 @@ glob_t *pglob; + #endif /* CONFIG_FAKE_GLOB */ + + /* Free storage allocated in PGLOB by a previous `glob' call. */ +-void globfree(pglob) +-register glob_t *pglob; ++void globfree(glob_t *pglob) + { + if (pglob->gl_pathv != NULL) { +- register int i = +- pglob->gl_flags & GLOB_DOOFFS ? pglob->gl_offs : 0; ++ int i = pglob->gl_flags & GLOB_DOOFFS ? pglob->gl_offs : 0; + for (; i < pglob->gl_pathc; ++i) + if (pglob->gl_pathv[i] != NULL) + free((__ptr_t) pglob->gl_pathv[i]); +diff --git a/lib/ldiv.c b/lib/ldiv.c +deleted file mode 100644 +index 5d231a2..0000000 +--- a/lib/ldiv.c ++++ /dev/null +@@ -1,55 +0,0 @@ +-/* Copyright (C) 1992, 1997 Free Software Foundation, Inc. +- This file is part of the GNU C Library. +- +- The GNU C Library is free software; you can redistribute it and/or +- modify it under the terms of the GNU Library General Public License as +- published by the Free Software Foundation; either version 2 of the +- License, or (at your option) any later version. +- +- The GNU C Library is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- Library General Public License for more details. +- +- You should have received a copy of the GNU Library General Public +- License along with the GNU C Library; see the file COPYING.LIB. If not, +- write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +- Boston, MA 02111-1307, USA. */ +- +-typedef struct { +- long quot; +- long rem; +-} ldiv_t; +-/* Return the `ldiv_t' representation of NUMER over DENOM. */ +-ldiv_t +-ldiv (long int numer, long int denom) +-{ +- ldiv_t result; +- +- result.quot = numer / denom; +- result.rem = numer % denom; +- +- /* The ANSI standard says that |QUOT| <= |NUMER / DENOM|, where +- NUMER / DENOM is to be computed in infinite precision. In +- other words, we should always truncate the quotient towards +- zero, never -infinity. Machine division and remainer may +- work either way when one or both of NUMER or DENOM is +- negative. If only one is negative and QUOT has been +- truncated towards -infinity, REM will have the same sign as +- DENOM and the opposite sign of NUMER; if both are negative +- and QUOT has been truncated towards -infinity, REM will be +- positive (will have the opposite sign of NUMER). These are +- considered `wrong'. If both are NUM and DENOM are positive, +- RESULT will always be positive. This all boils down to: if +- NUMER >= 0, but REM < 0, we got the wrong answer. In that +- case, to get the right answer, add 1 to QUOT and subtract +- DENOM from REM. */ +- +- if (numer >= 0 && result.rem < 0) +- { +- ++result.quot; +- result.rem -= denom; +- } +- +- return result; +-} +diff --git a/lib/libbb.c b/lib/libbb.c +index ee91fec..4d532f6 100644 +--- a/lib/libbb.c ++++ b/lib/libbb.c +@@ -29,7 +29,7 @@ char *concat_path_file(const char *path, const char *filename) + while (*filename == '/') + filename++; + +- str = xmalloc(strlen(path) + (lc==0 ? 1 : 0) + strlen(filename) + 1); ++ str = xmalloc(strlen(path) + (lc==NULL ? 1 : 0) + strlen(filename) + 1); + sprintf(str, "%s%s%s", path, (lc==NULL ? "/" : ""), filename); + + return str; +diff --git a/lib/parameter.c b/lib/parameter.c +index 0aa4193..379a057 100644 +--- a/lib/parameter.c ++++ b/lib/parameter.c +@@ -86,7 +86,7 @@ int dev_set_param_ip(struct device_d *dev, char *name, IPaddr_t ip) + * dev_set_param - set a parameter of a device to a new value + * @param dev The device + * @param name The name of the parameter +- * @param value The new value of the parameter ++ * @param val The new value of the parameter + */ + int dev_set_param(struct device_d *dev, const char *name, const char *val) + { +diff --git a/lib/process_escape_sequence.c b/lib/process_escape_sequence.c +index 546edaa..e3431d4 100644 +--- a/lib/process_escape_sequence.c ++++ b/lib/process_escape_sequence.c +@@ -21,6 +21,7 @@ + */ + #include <common.h> + #include <fs.h> ++#include <libbb.h> + + int process_escape_sequence(const char *source, char *dest, int destlen) + { +diff --git a/lib/readline.c b/lib/readline.c +index b82150e..b90de77 100644 +--- a/lib/readline.c ++++ b/lib/readline.c +@@ -120,10 +120,10 @@ static char* hist_next(void) + + #define ERASE_TO_EOL() { \ + if (num < eol_num) { \ +- int tmp; \ +- for (tmp = num; tmp < eol_num; tmp++) \ ++ int t; \ ++ for (t = num; t < eol_num; t++) \ + getcmd_putch(' '); \ +- while (tmp-- > num) \ ++ while (t-- > num) \ + getcmd_putch(CTL_BACKSPACE); \ + eol_num = num; \ + } \ +diff --git a/net/net.c b/net/net.c +index 8d99595..a613d1d 100644 +--- a/net/net.c ++++ b/net/net.c +@@ -209,7 +209,7 @@ static void arp_handler(struct arprequest *arp) + } + } + +-int arp_request(IPaddr_t dest, unsigned char *ether) ++static int arp_request(IPaddr_t dest, unsigned char *ether) + { + char *pkt; + struct arprequest *arp; +@@ -437,7 +437,7 @@ void net_unregister(struct net_connection *con) + free(con); + } + +-int net_ip_send(struct net_connection *con, int len) ++static int net_ip_send(struct net_connection *con, int len) + { + con->ip->tot_len = htons(sizeof(struct iphdr) + len); + con->ip->id = htons(net_ip_id++);; +diff --git a/net/ping.c b/net/ping.c +index 440e229..d414784 100644 +--- a/net/ping.c ++++ b/net/ping.c +@@ -40,7 +40,7 @@ static int ping_send(void) + return net_icmp_send(ping_con, 9); + } + +-void ping_handler(char *pkt, unsigned len) ++static void ping_handler(char *pkt, unsigned len) + { + IPaddr_t tmp; + struct iphdr *ip = net_eth_to_iphdr(pkt); +@@ -52,7 +52,7 @@ void ping_handler(char *pkt, unsigned len) + ping_state = PING_STATE_SUCCESS; + } + +-int do_ping(struct command *cmdtp, int argc, char *argv[]) ++static int do_ping(struct command *cmdtp, int argc, char *argv[]) + { + int ret; + uint64_t ping_start = 0; +diff --git a/net/tftp.c b/net/tftp.c +index 6345a72..6be8b8f 100644 +--- a/net/tftp.c ++++ b/net/tftp.c +@@ -364,15 +364,29 @@ out_close: + return tftp_err == 0 ? 0 : 1; + } + +-static const __maybe_unused char cmd_tftp_help[] = +-"Usage: tftp <remotefile> [localfile]\n" +-"Load a file from a TFTP server.\n" ++BAREBOX_CMD_HELP_START(tftp) + #ifdef CONFIG_NET_TFTP_PUSH +-"or\n" +-" tftp -p <localfile> [remotefile]\n" +-"Upload a file to a TFTP server\n" ++BAREBOX_CMD_HELP_USAGE("tftp <remotefile> [localfile], tftp -p <localfile> [remotefile]\n") ++BAREBOX_CMD_HELP_SHORT("Load a file from or upload to TFTP server.\n") ++BAREBOX_CMD_HELP_END ++#else ++BAREBOX_CMD_HELP_USAGE("tftp <remotefile> [localfile]\n") ++BAREBOX_CMD_HELP_SHORT("Load a file from a TFTP server.\n") ++BAREBOX_CMD_HELP_END + #endif +-; ++ ++/** ++ * @page tftp_command ++ ++The second file argument can be skipped in which case the first filename ++is used (without the directory part). ++ ++\<localfile> can be the local filename or a device file under /dev. ++This also works for flash memory. Refer to \ref erase_command and \ref ++unprotect_command for flash preparation. ++ ++\note This command is available only if enabled in menuconfig. ++ */ + + BAREBOX_CMD_START(tftp) + .cmd = do_tftpb, +@@ -384,24 +398,3 @@ BAREBOX_CMD_START(tftp) + BAREBOX_CMD_HELP(cmd_tftp_help) + BAREBOX_CMD_END + +-/** +- * @page tftp_command tftp +- * +- * Usage: +- * tftp \<remotefilename\> [\<localfilename\>] +- * +- * or +- * +- * tftp -p \<localfilename\> [\<remotefilename\>] +- * +- * Load a file from a tftp server or upload a file to a tftp server if +- * the -p option is given. The second file argument can be skipped in +- * which case the first filename is used (without the directory part). +- * +- * \<localfile> can be the local filename or a device file under /dev. +- * This also works for flash memory. Refer to \b erase, \b unprotect for +- * flash preparation. +- * +- * Note: This command is available only if enabled in menuconfig. +- */ +- +diff --git a/scripts/doxy_filter.awk b/scripts/doxy_filter.awk +new file mode 100644 +index 0000000..5ec0406 +--- /dev/null ++++ b/scripts/doxy_filter.awk +@@ -0,0 +1,103 @@ ++#!/usr/bin/awk ++ ++/BAREBOX_CMD_HELP_START[[:space:]]*\((.*)\)/ { ++ ++ this_opt = 0; ++ my_usage = ""; ++ my_short = ""; ++ my_cmd = gensub("BAREBOX_CMD_HELP_START[[:space:]]*\\((.*)\\)", "\\1", "g"); ++ this_text = 0; ++ delete(my_text); ++ delete(my_opts); ++ next; ++} ++ ++/BAREBOX_CMD_HELP_USAGE[[:space:]]*\((.*)\)/ { ++ ++ $0 = gensub("<", "\\<", "g"); ++ $0 = gensub(">", "\\>", "g"); ++ $0 = gensub("BAREBOX_CMD_HELP_USAGE[[:space:]]*\\((.*)\\)", "\\1", "g"); ++ $0 = gensub("\\\\n", "", "g"); ++ my_usage = gensub("\"", "", "g"); ++ next; ++ ++} ++ ++/BAREBOX_CMD_HELP_SHORT[[:space:]]*\((.*)\)/ { ++ ++ $0 = gensub("<", "\\<", "g"); ++ $0 = gensub(">", "\\>", "g"); ++ $0 = gensub("BAREBOX_CMD_HELP_SHORT[[:space:]]*\\((.*)\\)", "\\1", "g"); ++ $0 = gensub("\\\\n", "", "g"); ++ my_short = gensub("\"", "", "g"); ++ next; ++ ++} ++ ++/BAREBOX_CMD_HELP_OPT[[:space:]]*\([[:space:]]*(.*)[[:space:]]*,[[:space:]]*(.*)[[:space:]]*\)/ { ++ ++ $0 = gensub("<", "\\<", "g"); ++ $0 = gensub(">", "\\>", "g"); ++ $0 = gensub("@", "\\\\@", "g"); ++ $0 = gensub("BAREBOX_CMD_HELP_OPT[[:space:]]*\\([[:space:]]*\"*(.*)\"[[:space:]]*,[[:space:]]*\"(.*)\"[[:space:]]*\\)", \ ++ "<tr><td><tt> \\1 </tt></td><td>\\ \\ \\ </td><td> \\2 </td></tr>", "g"); ++ $0 = gensub("\\\\n", "", "g"); ++ my_opts[this_opt] = gensub("\"", "", "g"); ++ this_opt ++; ++ next; ++} ++ ++/BAREBOX_CMD_HELP_TEXT[[:space:]]*\((.*)\)/ { ++ ++ $0 = gensub("<", "\\<", "g"); ++ $0 = gensub(">", "\\>", "g"); ++ $0 = gensub("BAREBOX_CMD_HELP_TEXT[[:space:]]*\\((.*)\\)", "\\1", "g"); ++ $0 = gensub("\\\\n", "<br>", "g"); ++ my_text[this_text] = gensub("\"", "", "g"); ++ this_text ++; ++ next; ++} ++ ++/BAREBOX_CMD_HELP_END/ { ++ ++ printf "/**\n"; ++ printf " * @page " my_cmd "_command " my_cmd "\n"; ++ printf " *\n"; ++ printf " * \\par Usage:\n"; ++ printf " * " my_usage "\n"; ++ printf " *\n"; ++ ++ if (this_opt != 0) { ++ printf " * \\par Options:\n"; ++ printf " *\n"; ++ printf " * <table border=\"0\" cellpadding=\"0\">\n"; ++ n = asorti(my_opts, my_opts_sorted); ++ for (i=1; i<=n; i++) { ++ printf " * " my_opts[my_opts_sorted[i]] "\n"; ++ } ++ printf " * </table>\n"; ++ printf " *\n"; ++ } ++ ++ printf " * " my_short "\n"; ++ printf " *\n"; ++ ++ n = asorti(my_text, my_text_sorted); ++ if (n > 0) { ++ for (i=1; i<=n; i++) { ++ printf " * " my_text[my_text_sorted[i]] "\n"; ++ } ++ printf " *\n"; ++ } ++ ++ printf " */\n"; ++ ++ next; ++} ++ ++/^.*$/ { ++ ++ print $0; ++ ++} ++ +diff --git a/scripts/mkimage.c b/scripts/mkimage.c +index f6cbb1c..40a3483 100644 +--- a/scripts/mkimage.c ++++ b/scripts/mkimage.c +@@ -224,7 +224,7 @@ NXTARG: ; + */ + memcpy (hdr, ptr, sizeof(image_header_t)); + +- if (image_check_magic(hdr)) { ++ if (image_get_magic(hdr) != IH_MAGIC) { + fprintf (stderr, + "%s: Bad Magic Number: \"%s\" is no valid image\n", + cmdname, imagefile); +diff --git a/scripts/setupmbr/setupmbr.c b/scripts/setupmbr/setupmbr.c +index 3cfec97..dd7f38c 100644 +--- a/scripts/setupmbr/setupmbr.c ++++ b/scripts/setupmbr/setupmbr.c +@@ -42,8 +42,8 @@ + #include <assert.h> + + /* include the info from this barebox release */ +-#include "include/generated/utsrelease.h" +-#include "arch/x86/include/asm/barebox.lds.h" ++#include "../../include/generated/utsrelease.h" ++#include "../../arch/x86/include/asm/barebox.lds.h" + + /** define to disable integrity tests and debug messages */ + #define NDEBUG diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/adapt_fec_driver.diff b/configs/platform-chumby/patches/barebox-2010.11.0/adapt_fec_driver.diff new file mode 100644 index 0000000..f24d7e7 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/adapt_fec_driver.diff @@ -0,0 +1,246 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: FEC/ENET driver: Add i.MX28 incarnation + +The i.MX28 SoC comes with a ENET/FEC. But to make the current driver work +on this new harware a few adpations are requirend. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + drivers/net/fec_imx.c | 83 +++++++++++++++++++++++++++++++++++++++----------- + drivers/net/fec_imx.h | 34 ++++++++++++++++---- + 2 files changed, 92 insertions(+), 25 deletions(-) + +Index: barebox-2010.10.0/drivers/net/fec_imx.c +=================================================================== +--- barebox-2010.10.0.orig/drivers/net/fec_imx.c ++++ barebox-2010.10.0/drivers/net/fec_imx.c +@@ -30,6 +30,7 @@ + + #include <asm/mmu.h> + #include <asm/io.h> ++#include <mach/generic.h> + #include <mach/imx-regs.h> + #include <clock.h> + #include <mach/clock.h> +@@ -151,6 +152,19 @@ static int fec_tx_task_disable(struct fe + } + + /** ++ * Swap endianess for i.MX28 implementation ++ * @param buf guess what (must be 4 byte aligned!) ++ * @param len size in bytes ++ */ ++static void imx28_fix_endianess(uint32_t *buf, unsigned len) ++{ ++ unsigned u; ++ ++ for (u = 0; u < (len >> 2); u++, buf++) ++ *buf = __swab32(*buf); ++} ++ ++/** + * Initialize receive task's buffer descriptors + * @param[in] fec all we know about the device yet + * @param[in] count receive buffer count to be allocated +@@ -270,12 +284,13 @@ static int fec_init(struct eth_device *d + /* + * Frame length=1518; 7-wire mode + */ +- writel((1518 << 16), fec->regs + FEC_R_CNTRL); ++ writel(FEC_R_CNTRL_MAX_FL(1518), fec->regs + FEC_R_CNTRL); + } else { + /* + * Frame length=1518; MII mode; + */ +- writel((1518 << 16) | (1 << 2), fec->regs + FEC_R_CNTRL); ++ writel(FEC_R_CNTRL_MAX_FL(1518) | FEC_R_CNTRL_MII_MODE, ++ fec->regs + FEC_R_CNTRL); + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. +@@ -285,16 +300,26 @@ static int fec_init(struct eth_device *d + } + + if (fec->xcv_type == RMII) { +- /* disable the gasket and wait */ +- writel(0, fec->regs + FEC_MIIGSK_ENR); +- while (readl(fec->regs + FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) +- udelay(1); ++ if (cpu_is_mx28()) { ++ /* just another way to enable RMII */ ++ uint32_t reg = readl(fec->regs + FEC_R_CNTRL); ++ writel(reg | FEC_R_CNTRL_RMII_MODE ++ /* the linux driver add these bits, why not we? */ ++ /* | FEC_R_CNTRL_FCE | */ ++ /* FEC_R_CNTRL_NO_LGTH_CHECK */, ++ fec->regs + FEC_R_CNTRL); ++ } else { ++ /* disable the gasket and wait */ ++ writel(0, fec->regs + FEC_MIIGSK_ENR); ++ while (readl(fec->regs + FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY) ++ udelay(1); + +- /* configure the gasket for RMII, 50 MHz, no loopback, no echo */ +- writel(FEC_MIIGSK_CFGR_IF_MODE_RMII, fec->regs + FEC_MIIGSK_CFGR); ++ /* configure the gasket for RMII, 50 MHz, no loopback, no echo */ ++ writel(FEC_MIIGSK_CFGR_IF_MODE_RMII, fec->regs + FEC_MIIGSK_CFGR); + +- /* re-enable the gasket */ +- writel(FEC_MIIGSK_ENR_EN, fec->regs + FEC_MIIGSK_ENR); ++ /* re-enable the gasket */ ++ writel(FEC_MIIGSK_ENR_EN, fec->regs + FEC_MIIGSK_ENR); ++ } + } + + /* +@@ -419,11 +444,19 @@ static int fec_send(struct eth_device *d + * Note: We are always using the first buffer for transmission, + * the second will be empty and only used to stop the DMA engine + */ ++ if (cpu_is_mx28()) ++ imx28_fix_endianess(eth_data, (data_length + 3) & ~0x3); ++ + writew(data_length, &fec->tbd_base[fec->tbd_index].data_length); + + writel((uint32_t)(eth_data), &fec->tbd_base[fec->tbd_index].data_pointer); +- dma_flush_range((unsigned long)eth_data, +- (unsigned long)(eth_data + data_length)); ++ if (cpu_is_mx28()) ++ dma_flush_range((unsigned long)eth_data, ++ (unsigned long)(eth_data + ((data_length + 3) & ~0x3))); ++ else ++ dma_flush_range((unsigned long)eth_data, ++ (unsigned long)(eth_data + data_length)); ++ + /* + * update BD's status now + * This block: +@@ -447,6 +480,13 @@ static int fec_send(struct eth_device *d + } + } + ++ /* ++ * Some network commands seems to continue using the buffer content ++ * So, swab them back, otherwise they do not work anymore ++ */ ++ if (cpu_is_mx28()) ++ imx28_fix_endianess(eth_data, (data_length + 3) & ~0x3); ++ + /* for next transmission use the other buffer */ + if (fec->tbd_index) + fec->tbd_index = 0; +@@ -476,18 +516,20 @@ static int fec_recv(struct eth_device *d + ievent = readl(fec->regs + FEC_IEVENT); + writel(ievent, fec->regs + FEC_IEVENT); + +- if (ievent & (FEC_IEVENT_BABT | FEC_IEVENT_XFIFO_ERROR | +- FEC_IEVENT_RFIFO_ERROR)) { ++ if (ievent & (FEC_IEVENT_BABT /* | FEC_IEVENT_XFIFO_ERROR | ++ FEC_IEVENT_RFIFO_ERROR*/)) { + /* BABT, Rx/Tx FIFO errors */ + fec_halt(dev); + fec_init(dev); + printf("some error: 0x%08x\n", ievent); + return 0; + } +- if (ievent & FEC_IEVENT_HBERR) { +- /* Heartbeat error */ +- writel(readl(fec->regs + FEC_X_CNTRL) | 0x1, +- fec->regs + FEC_X_CNTRL); ++ if (!cpu_is_mx28()) { ++ if (ievent & FEC_IEVENT_HBERR) { ++ /* Heartbeat error */ ++ writel(readl(fec->regs + FEC_X_CNTRL) | 0x1, ++ fec->regs + FEC_X_CNTRL); ++ } + } + if (ievent & FEC_IEVENT_GRA) { + /* Graceful stop complete */ +@@ -507,6 +549,11 @@ static int fec_recv(struct eth_device *d + if (!(bd_status & FEC_RBD_EMPTY)) { + if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && + ((readw(&rbd->data_length) - 4) > 14)) { ++ ++ if (cpu_is_mx28()) ++ imx28_fix_endianess((void*)readl(&rbd->data_pointer), ++ (readw(&rbd->data_length) + 3) & ~0x3); ++ + /* + * Get buffer address and size + */ +Index: barebox-2010.10.0/drivers/net/fec_imx.h +=================================================================== +--- barebox-2010.10.0.orig/drivers/net/fec_imx.h ++++ barebox-2010.10.0/drivers/net/fec_imx.h +@@ -38,8 +38,8 @@ + #define FEC_R_CNTRL 0x084 + #define FEC_X_CNTRL 0x0c4 + #define FEC_PADDR1 0x0e4 +-#define FEC_OP_PAUSE 0x0ec + #define FEC_PADDR2 0x0e8 ++#define FEC_OP_PAUSE 0x0ec + #define FEC_IADDR1 0x118 + #define FEC_IADDR2 0x11c + #define FEC_GADDR1 0x120 +@@ -63,8 +63,19 @@ + #define FEC_MIIGSK_ENR_READY (1 << 2) + #define FEC_MIIGSK_ENR_EN (1 << 1) + ++#define FEC_R_CNTRL_GRS (1 << 31) ++#define FEC_R_CNTRL_NO_LGTH_CHECK (1 << 30) ++#ifdef CONFIG_ARCH_IMX28 ++# define FEC_R_CNTRL_MAX_FL(x) (((x) & 0x3fff) << 16) ++#else ++# define FEC_R_CNTRL_MAX_FL(x) (((x) & 0x7ff) << 16) ++#endif ++#define FEC_R_CNTRL_RMII_10T (1 << 9) /* i.MX28 specific */ ++#define FEC_R_CNTRL_RMII_MODE (1 << 8) /* i.MX28 specific */ ++#define FEC_R_CNTRL_FCE (1 << 5) ++#define FEC_R_CNTRL_MII_MODE (1 << 2) + +-#define FEC_IEVENT_HBERR 0x80000000 ++#define FEC_IEVENT_HBERR 0x80000000 /* Note: Not on i.MX28 */ + #define FEC_IEVENT_BABR 0x40000000 + #define FEC_IEVENT_BABT 0x20000000 + #define FEC_IEVENT_GRA 0x10000000 +@@ -73,10 +84,14 @@ + #define FEC_IEVENT_LATE_COL 0x00200000 + #define FEC_IEVENT_COL_RETRY_LIM 0x00100000 + #define FEC_IEVENT_XFIFO_UN 0x00080000 +-#define FEC_IEVENT_XFIFO_ERROR 0x00040000 +-#define FEC_IEVENT_RFIFO_ERROR 0x00020000 ++#ifdef CONFIG_ARCH_IMX28 ++# define FEC_IEVENT_WAKEUP (1 << 17) ++# define FEC_IEVENT_TS_AVAIL (1 << 16) ++# define FEC_IEVENT_TS_TIMER (1 << 15) ++#endif + +-#define FEC_IMASK_HBERR 0x80000000 ++ ++#define FEC_IMASK_HBERR 0x80000000 /* Note: Not on i.MX28 */ + #define FEC_IMASK_BABR 0x40000000 + #define FEC_IMASK_BABT 0x20000000 + #define FEC_IMASK_GRA 0x10000000 +@@ -84,8 +99,11 @@ + #define FEC_IMASK_LATE_COL 0x00200000 + #define FEC_IMASK_COL_RETRY_LIM 0x00100000 + #define FEC_IMASK_XFIFO_UN 0x00080000 +-#define FEC_IMASK_XFIFO_ERROR 0x00040000 +-#define FEC_IMASK_RFIFO_ERROR 0x00020000 ++#ifdef CONFIG_ARCH_IMX28 ++# define FEC_IMASK_WAKEUP (1 << 17) ++# define FEC_IMASK_TS_AVAIL (1 << 16) ++# define FEC_IMASK_TS_TIMER (1 << 15) ++#endif + + #define FEC_RCNTRL_MAX_FL_SHIFT 16 + #define FEC_RCNTRL_LOOP 0x01 +@@ -124,6 +142,8 @@ + * @brief Receive & Transmit Buffer Descriptor definitions + * + * Note: The first BD must be aligned (see DB_ALIGNMENT) ++ * ++ * BTW: Don't trust the i.MX27 and i.MX28 data sheet + */ + struct buffer_descriptor { + uint16_t data_length; /**< payload's length in bytes */ diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_chumby.diff b/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_chumby.diff new file mode 100644 index 0000000..4f32cdf --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_chumby.diff @@ -0,0 +1,125 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: i.MX23/Chumby: Add framebuffer support + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/boards/chumby_falconwing/falconwing.c | 81 +++++++++++++++++-------- + 1 file changed, 58 insertions(+), 23 deletions(-) + +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/falconwing.c +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/falconwing.c ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/falconwing.c +@@ -28,6 +28,7 @@ + #include <mach/imx-regs.h> + #include <mach/clock.h> + #include <mach/mci.h> ++#include <mach/fb.h> + + static struct memory_platform_data ram_pdata = { + .name = "ram0", +@@ -54,6 +55,38 @@ static struct device_d mci_dev = { + .platform_data = &mci_pdata, + }; + ++static struct fb_videomode falconwing_vmode = { ++ .name = "NMA35", ++ .refresh = 60, ++ .xres = 320, ++ .yres = 240, /* active area 70.08 mm x 52.56 mm */ ++ .pixclock = KHZ2PICOS(6250), /* max 10 MHz */ ++ .left_margin = 28, ++ .hsync_len = 24, ++ .right_margin = 28, /* = 64 µs */ ++ .upper_margin = 8, ++ .vsync_len = 4, ++ .lower_margin = 8, /* = 60 Hz */ ++ /* low active DE signal, VSYNC and HSYNC are high active */ ++ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, ++ .vmode = FB_VMODE_NONINTERLACED, ++ .flag = 0, ++}; ++ ++static struct imx_fb_videomode fb_mode = { ++ .mode_list = &falconwing_vmode, ++ .mode_count = 1, ++ /* 24 bit display, but only 18 bit connected */ ++ .ld_intf_width = STMLCDIF_18BIT, ++}; ++ ++static struct device_d ldcif_dev = { ++ .name = "stmfb", ++ .map_base = IMX_FB_BASE, ++ .size = 4096, ++ .platform_data = &fb_mode, ++}; ++ + static const uint32_t pad_setup[] = { + /* may be not required as already done by the bootlet code */ + #if 0 +@@ -114,33 +147,34 @@ static const uint32_t pad_setup[] = { + PWM0_DUART_RX | STRENGTH(S4MA), /* strength is TBD */ + + /* lcd */ +- LCD_VSYNC, /* kernel tries with 12 mA for all LCD related pins */ +- LCD_HSYNC, +- LCD_ENABE, +- LCD_DOTCLOCK, +- LCD_D17, +- LCD_D16, +- LCD_D15, +- LCD_D14, +- LCD_D13, +- LCD_D12, +- LCD_D11, +- LCD_D10, +- LCD_D9, +- LCD_D8, +- LCD_D7, +- LCD_D6, +- LCD_D5, +- LCD_D4, +- LCD_D3, +- LCD_D2, +- LCD_D1, +- LCD_D0, ++ LCD_VSYNC | STRENGTH(S12MA), ++ LCD_HSYNC | STRENGTH(S12MA), ++ LCD_ENABE | STRENGTH(S12MA), ++ LCD_DOTCLOCK | STRENGTH(S12MA), ++ LCD_D17 | STRENGTH(S12MA), ++ LCD_D16 | STRENGTH(S12MA), ++ LCD_D15 | STRENGTH(S12MA), ++ LCD_D14 | STRENGTH(S12MA), ++ LCD_D13 | STRENGTH(S12MA), ++ LCD_D12 | STRENGTH(S12MA), ++ LCD_D11 | STRENGTH(S12MA), ++ LCD_D10 | STRENGTH(S12MA), ++ LCD_D9 | STRENGTH(S12MA), ++ LCD_D8 | STRENGTH(S12MA), ++ LCD_D7 | STRENGTH(S12MA), ++ LCD_D6 | STRENGTH(S12MA), ++ LCD_D5 | STRENGTH(S12MA), ++ LCD_D4 | STRENGTH(S12MA), ++ LCD_D3 | STRENGTH(S12MA), ++ LCD_D2 | STRENGTH(S12MA), ++ LCD_D1 | STRENGTH(S12MA), ++ LCD_D0 | STRENGTH(S12MA), + + /* LCD usage currently unknown */ + LCD_CS, /* used as SPI SS */ + LCD_RS, /* used as SPI CLK */ +- LCD_RESET, ++ /* keep the display in reset state */ ++ LCD_RESET_GPIO | STRENGTH(S4MA) | GPIO_OUT | GPIO_VALUE(0), + LCD_WR, /* used as SPI MOSI */ + + /* I2C to the MMA7455L, KXTE9, AT24C08 (DCID), AT24C128B (ID EEPROM) and QN8005B */ +@@ -271,6 +305,7 @@ static int falconwing_devices_init(void) + /* run the SSP unit clock at 100,000 kHz */ + imx_set_sspclk(0, 100U * 1000U, 1); + register_device(&mci_dev); ++ register_device(&ldcif_dev); + + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100)); diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_iMX23.diff b/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_iMX23.diff new file mode 100644 index 0000000..55877a7 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_iMX23.diff @@ -0,0 +1,20 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: i.MX23: Add framebuffer device support + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/mach-stm/include/mach/imx23-regs.h | 1 + + 1 file changed, 1 insertion(+) + +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/imx23-regs.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/include/mach/imx23-regs.h ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/imx23-regs.h +@@ -36,6 +36,7 @@ + #define IMX_CCM_BASE 0x80040000 + #define IMX_I2C1_BASE 0x80058000 + #define IMX_SSP1_BASE 0x80010000 ++#define IMX_FB_BASE 0x80030000 + #define IMX_SSP2_BASE 0x80034000 + + #endif /* __ASM_ARCH_MX23_REGS_H */ diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_init.diff b/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_init.diff new file mode 100644 index 0000000..dc29400 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/add_fb_support_to_init.diff @@ -0,0 +1,47 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Runtime activation of Chumby's LCD + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/boards/chumby_falconwing/env/bin/init | 15 +++++++++++++++ + arch/arm/boards/chumby_falconwing/env/config | 3 +++ + 2 files changed, 18 insertions(+) + +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/bin/init +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/env/bin/init ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/bin/init +@@ -5,6 +5,21 @@ export PATH + + . /env/config + ++# enable the display on demand ++if [ -e /dev/fb0 ]; then ++ # setup the mode to be used ++ framebuffer0.mode=NMA35 ++ if [ -e "$splash_image" ]; then ++ bmp -f /dev/fb0 $splash_image ++ fi ++ # set its RESET# pin to high (activate the glass) ++ gpio_set_value 50 1 ++ # enable the video signals ++ framebuffer0.enable=1 ++ # activate the backlight (low is full brightness, high is off) ++ gpio_set_value 60 1 ++fi ++ + echo + echo -n "Hit any key to stop autoboot: " + timeout -a $autoboot_timeout +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/config +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/env/config ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/config +@@ -34,3 +34,6 @@ kernel_part=disk0.2 + bootargs="console=ttyAM0,115200 quiet ro lcd_panel=lms350 ssp1=mmc line=1 sysrq_always_enabled rotary=1" + + autoboot_timeout=2 ++ ++# what splash image should be used ++splash_image=/env/splash.bmp diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/add_fec_to_i.MX28.diff b/configs/platform-chumby/patches/barebox-2010.11.0/add_fec_to_i.MX28.diff new file mode 100644 index 0000000..cdf785c --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/add_fec_to_i.MX28.diff @@ -0,0 +1,202 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Share the iim header file between i.MX and STM architecture + +The i.MX28 SoC comes with a ENET/FEC device known from the i.MX family. To +be able to share the header files between both architectures move it to the +ordinary include path. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/mach-imx/iim.c | 2 - + arch/arm/mach-imx/imx25.c | 2 - + arch/arm/mach-imx/imx35.c | 2 - + arch/arm/mach-imx/include/mach/iim.h | 57 ----------------------------------- + drivers/net/fec_imx.c | 2 - + include/imx_iim.h | 57 +++++++++++++++++++++++++++++++++++ + 6 files changed, 61 insertions(+), 61 deletions(-) + +Index: barebox-2010.10.0/arch/arm/mach-imx/include/mach/iim.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-imx/include/mach/iim.h ++++ /dev/null +@@ -1,57 +0,0 @@ +-/* +- * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> +- * +- * See file CREDITS for list of people who contributed to this +- * project. +- * +- * This program is free software; you can redistribute it and/or +- * modify it under the terms of the GNU General Public License as +- * published by the Free Software Foundation; either version 2 of +- * the License, or (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, +- * MA 02111-1307 USA +- */ +- +-#ifndef __MACH_IMX_IIM_H +-#define __MACH_IMX_IIM_H +- +-#include <errno.h> +- +-#define IIM_STAT 0x0000 +-#define IIM_STATM 0x0004 +-#define IIM_ERR 0x0008 +-#define IIM_EMASK 0x000C +-#define IIM_FCTL 0x0010 +-#define IIM_UA 0x0014 +-#define IIM_LA 0x0018 +-#define IIM_SDAT 0x001C +-#define IIM_PREV 0x0020 +-#define IIM_SREV 0x0024 +-#define IIM_PREG_P 0x0028 +-#define IIM_SCS0 0x002C +-#define IIM_SCS1 0x0030 +-#define IIM_SCS2 0x0034 +-#define IIM_SCS3 0x0038 +- +-struct imx_iim_platform_data { +- unsigned long mac_addr_base; +-}; +- +-#ifdef CONFIG_IMX_IIM +-int imx_iim_get_mac(unsigned char *mac); +-#else +-static inline int imx_iim_get_mac(unsigned char *mac) +-{ +- return -EINVAL; +-} +-#endif /* CONFIG_IMX_IIM */ +- +-#endif /* __MACH_IMX_IIM_H */ +Index: barebox-2010.10.0/include/imx_iim.h +=================================================================== +--- /dev/null ++++ barebox-2010.10.0/include/imx_iim.h +@@ -0,0 +1,57 @@ ++/* ++ * (c) 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> ++ * ++ * See file CREDITS for list of people who contributed to this ++ * project. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef __MACH_IMX_IIM_H ++#define __MACH_IMX_IIM_H ++ ++#include <errno.h> ++ ++#define IIM_STAT 0x0000 ++#define IIM_STATM 0x0004 ++#define IIM_ERR 0x0008 ++#define IIM_EMASK 0x000C ++#define IIM_FCTL 0x0010 ++#define IIM_UA 0x0014 ++#define IIM_LA 0x0018 ++#define IIM_SDAT 0x001C ++#define IIM_PREV 0x0020 ++#define IIM_SREV 0x0024 ++#define IIM_PREG_P 0x0028 ++#define IIM_SCS0 0x002C ++#define IIM_SCS1 0x0030 ++#define IIM_SCS2 0x0034 ++#define IIM_SCS3 0x0038 ++ ++struct imx_iim_platform_data { ++ unsigned long mac_addr_base; ++}; ++ ++#ifdef CONFIG_IMX_IIM ++int imx_iim_get_mac(unsigned char *mac); ++#else ++static inline int imx_iim_get_mac(unsigned char *mac) ++{ ++ return -EINVAL; ++} ++#endif /* CONFIG_IMX_IIM */ ++ ++#endif /* __MACH_IMX_IIM_H */ +Index: barebox-2010.10.0/drivers/net/fec_imx.c +=================================================================== +--- barebox-2010.10.0.orig/drivers/net/fec_imx.c ++++ barebox-2010.10.0/drivers/net/fec_imx.c +@@ -23,6 +23,7 @@ + #include <net.h> + #include <init.h> + #include <miidev.h> ++#include <imx_iim.h> + #include <driver.h> + #include <miidev.h> + #include <fec.h> +@@ -32,7 +33,6 @@ + #include <mach/imx-regs.h> + #include <clock.h> + #include <mach/clock.h> +-#include <mach/iim.h> + #include <xfuncs.h> + + #include "fec_imx.h" +Index: barebox-2010.10.0/arch/arm/mach-imx/iim.c +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-imx/iim.c ++++ barebox-2010.10.0/arch/arm/mach-imx/iim.c +@@ -25,7 +25,7 @@ + + #include <asm/io.h> + +-#include <mach/iim.h> ++#include <imx_iim.h> + + #define DRIVERNAME "imx_iim" + +Index: barebox-2010.10.0/arch/arm/mach-imx/imx25.c +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-imx/imx25.c ++++ barebox-2010.10.0/arch/arm/mach-imx/imx25.c +@@ -17,8 +17,8 @@ + + #include <common.h> + #include <init.h> ++#include <imx_iim.h> + #include <mach/imx-regs.h> +-#include <mach/iim.h> + #include <asm/io.h> + + #include "gpio.h" +Index: barebox-2010.10.0/arch/arm/mach-imx/imx35.c +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-imx/imx35.c ++++ barebox-2010.10.0/arch/arm/mach-imx/imx35.c +@@ -17,8 +17,8 @@ + + #include <common.h> + #include <asm/io.h> ++#include <imx_iim.h> + #include <mach/imx-regs.h> +-#include <mach/iim.h> + #include <mach/generic.h> + + #include "gpio.h" diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/add_gpio_commands_to_imx23.diff b/configs/platform-chumby/patches/barebox-2010.11.0/add_gpio_commands_to_imx23.diff new file mode 100644 index 0000000..b9db9d4 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/add_gpio_commands_to_imx23.diff @@ -0,0 +1,61 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: i.MX23: Add support for the gpio commands + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/mach-stm/iomux-imx23.c | 37 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 37 insertions(+) + +Index: barebox-2010.10.0/arch/arm/mach-stm/iomux-imx23.c +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/iomux-imx23.c ++++ barebox-2010.10.0/arch/arm/mach-stm/iomux-imx23.c +@@ -20,6 +20,7 @@ + #include <common.h> + #include <init.h> + #include <gpio.h> ++#include <errno.h> + #include <asm/io.h> + #include <mach/imx-regs.h> + +@@ -124,3 +125,39 @@ void imx_gpio_mode(uint32_t m) + } + } + } ++ ++void gpio_set_value(unsigned gpio, int val) ++{ ++ unsigned reg_offset; ++ ++ reg_offset = calc_output_reg(gpio); ++ pr_debug("%u: Accessing %X+%X with value %X\n", gpio, IMX_IOMUXC_BASE, ++ reg_offset, 0x1 << (gpio % 32)); ++ writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + (val != 0 ? 4 : 8)); ++} ++ ++int gpio_direction_input(unsigned gpio) ++{ ++ pr_err("Not yet supported\n"); ++ return -EINVAL; ++} ++ ++int gpio_direction_output(unsigned gpio, int val) ++{ ++ pr_err("Not yet supported\n"); ++ return -EINVAL; ++} ++ ++int gpio_get_value(unsigned gpio) ++{ ++ uint32_t reg; ++ unsigned reg_offset; ++ ++ reg_offset = calc_input_reg(gpio); ++ reg = readl(IMX_IOMUXC_BASE + reg_offset); ++ pr_debug("%u: Accessing %X+%X with value %X->%X\n", gpio, IMX_IOMUXC_BASE, ++ reg_offset, 0x1 << (gpio % 32), reg & (0x1 << (gpio % 32))); ++ if (reg & (0x1 << (gpio % 32))) ++ return 1; ++ return 0; ++} diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/add_imx28_architecture.diff b/configs/platform-chumby/patches/barebox-2010.11.0/add_imx28_architecture.diff new file mode 100644 index 0000000..e01cfc4 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/add_imx28_architecture.diff @@ -0,0 +1,1616 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: STM378x: Add i.MX28 architecture + +The i.MX28 is mostly the same than the i.MX23. But only mostly. It slightly +differs in many ways. So, some files must be added beside the i.MX23 +related ones to support both CPUs. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/mach-imx/include/mach/generic.h | 2 + arch/arm/mach-stm/Kconfig | 14 + arch/arm/mach-stm/Makefile | 1 + arch/arm/mach-stm/clocksource-imx28.c | 84 ++++ + arch/arm/mach-stm/include/mach/clock-imx28.h | 36 + + arch/arm/mach-stm/include/mach/clock.h | 3 + arch/arm/mach-stm/include/mach/generic.h | 6 + arch/arm/mach-stm/include/mach/gpio.h | 9 + arch/arm/mach-stm/include/mach/imx-regs.h | 4 + arch/arm/mach-stm/include/mach/imx28-regs.h | 59 ++ + arch/arm/mach-stm/include/mach/iomux-imx28.h | 552 +++++++++++++++++++++++++++ + arch/arm/mach-stm/iomux-imx23.c | 13 + arch/arm/mach-stm/iomux-imx28.c | 172 ++++++++ + arch/arm/mach-stm/speed-imx28.c | 518 +++++++++++++++++++++++++ + 14 files changed, 1471 insertions(+), 2 deletions(-) + +Index: barebox-2010.10.0/arch/arm/mach-stm/Kconfig +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/Kconfig ++++ barebox-2010.10.0/arch/arm/mach-stm/Kconfig +@@ -18,6 +18,11 @@ config ARCH_IMX23 + bool "i.MX23" + select CPU_ARM926T + ++config ARCH_IMX28 ++ bool "i.MX28" ++ select CPU_ARM926T ++ select ARCH_HAS_FEC_IMX ++ + endchoice + + if ARCH_IMX23 +@@ -41,6 +46,15 @@ endchoice + + endif + ++if ARCH_IMX28 ++ ++choice ++ prompt "i.MX28 Board Type" ++ ++endchoice ++ ++endif ++ + menu "Board specific settings " + + endmenu +Index: barebox-2010.10.0/arch/arm/mach-stm/Makefile +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/Makefile ++++ barebox-2010.10.0/arch/arm/mach-stm/Makefile +@@ -1,2 +1,3 @@ + obj-$(CONFIG_ARCH_IMX23) += speed-imx23.o imx23.o iomux-imx23.o clocksource-imx23.o reset-imx23.o ++obj-$(CONFIG_ARCH_IMX28) += speed-imx28.o imx23.o iomux-imx23.o clocksource-imx28.o reset-imx23.o + +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/include/mach/clock.h ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock.h +@@ -21,5 +21,8 @@ + #if defined CONFIG_ARCH_IMX23 + # include <mach/clock-imx23.h> + #endif ++#if defined CONFIG_ARCH_IMX28 ++# include <mach/clock-imx28.h> ++#endif + + #endif /* __ASM_MACH_CLOCK_H */ +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/generic.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/include/mach/generic.h ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/generic.h +@@ -22,3 +22,9 @@ + #else + # define cpu_is_mx23() (0) + #endif ++ ++#ifdef CONFIG_ARCH_IMX28 ++# define cpu_is_mx28() (1) ++#else ++# define cpu_is_mx28() (0) ++#endif +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/gpio.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/include/mach/gpio.h ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/gpio.h +@@ -23,7 +23,14 @@ + #if defined CONFIG_ARCH_IMX23 + # include <mach/iomux-imx23.h> + #endif ++#if defined CONFIG_ARCH_IMX28 ++# include <mach/iomux-imx28.h> ++#endif + +-void imx_gpio_mode(unsigned); ++void gpio_set_value(unsigned, int); ++int gpio_direction_input(unsigned); ++int gpio_direction_output(unsigned, int); ++int gpio_get_value(unsigned); ++void imx_gpio_mode(uint32_t); + + #endif /* __ASM_MACH_GPIO_H */ +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/imx-regs.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/include/mach/imx-regs.h ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/imx-regs.h +@@ -24,4 +24,8 @@ + # include <mach/imx23-regs.h> + #endif + ++#if defined CONFIG_ARCH_IMX28 ++# include <mach/imx28-regs.h> ++#endif ++ + #endif /* _IMX_REGS_H */ +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/imx28-regs.h +=================================================================== +--- /dev/null ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/imx28-regs.h +@@ -0,0 +1,59 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, ++ * MA 02110-1301, USA. ++ */ ++ ++#ifndef __ASM_ARCH_MX28_REGS_H ++#define __ASM_ARCH_MX28_REGS_H ++ ++/* ++ * sanity check ++ */ ++#ifndef _IMX_REGS_H ++# error "Please do not include directly. Use imx-regs.h instead." ++#endif ++ ++#define IMX_SRAM_BASE 0x00000000 ++#define IMX_MEMORY_BASE 0x40000000 ++ ++#define IMX_NFC_BASE 0x8000C000 ++#define IMX_SSP0_BASE 0x80010000 ++#define IMX_SSP1_BASE 0x80012000 ++#define IMX_SSP2_BASE 0x80014000 ++#define IMX_SSP3_BASE 0x80016000 ++#define IMX_IOMUXC_BASE 0x80018000 ++#define IMX_FB_BASE 0x80030000 ++#define IMX_CCM_BASE 0x80040000 ++#define IMX_WDT_BASE 0x80056000 ++#define IMX_I2C0_BASE 0x80058000 ++#define IMX_I2C1_BASE 0x8005a000 ++#define IMX_TIM1_BASE 0x80068000 ++#define IMX_UART0_BASE 0x8006a000 ++#define IMX_UART1_BASE 0x8006c000 ++#define IMX_UART2_BASE 0x8006e000 ++#define IMX_UART3_BASE 0x80070000 ++#define IMX_UART4_BASE 0x80072000 ++#define IMX_DBGUART_BASE 0x80074000 ++#define IMX_FEC0_BASE 0x800F0000 ++#define IMX_FEC1_BASE 0x800F4000 ++ ++// #define IMX_MAX_BASE 0x43F04000 ++// #define IMX_ESD_BASE 0xb8001000 ++// #define IMX_AIPS1_BASE 0x43F00000 ++// #define IMX_AIPS2_BASE 0x53F00000 ++// #define IMX_IIM_BASE 0x53FF0000 ++// #define IMX_OTG_BASE 0x53FF4000 ++// #define IMX_M3IF_BASE 0xB8003000 ++ ++#endif /* __ASM_ARCH_MX28_REGS_H */ +Index: barebox-2010.10.0/arch/arm/mach-stm/speed-imx28.c +=================================================================== +--- /dev/null ++++ barebox-2010.10.0/arch/arm/mach-stm/speed-imx28.c +@@ -0,0 +1,518 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This code is based partially on code of: ++ * ++ * (c) 2008 Embedded Alley Solutions, Inc. ++ * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* #define DEBUG */ ++ ++#include <common.h> ++#include <init.h> ++#include <asm/io.h> ++#include <mach/imx-regs.h> ++#include <mach/generic.h> ++#include <mach/clock.h> ++ ++/* Note: all clock frequencies are returned in kHz */ ++ ++#define HW_CLKCTRL_PLL0CTRL0 0x000 ++#define HW_CLKCTRL_PLL0CTRL1 0x010 ++#define HW_CLKCTRL_PLL1CTRL0 0x020 ++#define HW_CLKCTRL_PLL1CTRL1 0x030 ++#define HW_CLKCTRL_PLL2CTRL0 0x040 ++# define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) ++# define CLKCTRL_PLL2CTRL0_POWER (1 << 23) ++#define HW_CLKCTRL_CPU 0x50 ++# define GET_CPU_XTAL_DIV(x) (((x) >> 16) & 0x3ff) ++# define GET_CPU_PLL_DIV(x) ((x) & 0x3f) ++#define HW_CLKCTRL_HBUS 0x60 ++#define HW_CLKCTRL_XBUS 0x70 ++#define HW_CLKCTRL_XTAL 0x080 ++#define HW_CLKCTRL_SSP0 0x090 ++#define HW_CLKCTRL_SSP1 0x0a0 ++#define HW_CLKCTRL_SSP2 0x0b0 ++#define HW_CLKCTRL_SSP3 0x0c0 ++/* note: no set/clear register! */ ++# define CLKCTRL_SSP_CLKGATE (1 << 31) ++# define CLKCTRL_SSP_BUSY (1 << 29) ++# define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) ++# define CLKCTRL_SSP_DIV_MASK 0x1ff ++# define GET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) ++# define SET_SSP_DIV(x) ((x) & CLKCTRL_SSP_DIV_MASK) ++#define HW_CLKCTRL_GPMI 0x0d0 ++/* note: no set/clear register! */ ++#define HW_CLKCTRL_SPDIF 0x0e0 ++/* note: no set/clear register! */ ++#define HW_CLKCTRL_EMI 0xf0 ++/* note: no set/clear register! */ ++# define CLKCTRL_EMI_CLKGATE (1 << 31) ++# define GET_EMI_XTAL_DIV(x) (((x) >> 8) & 0xf) ++# define GET_EMI_PLL_DIV(x) ((x) & 0x3f) ++#define HW_CLKCTRL_SAIF0 0x100 ++#define HW_CLKCTRL_SAIF1 0x110 ++#define HW_CLKCTRL_DIS_LCDIF 0x120 ++# define CLKCTRL_DIS_LCDIF_GATE (1 << 31) ++# define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) ++# define SET_DIS_LCDIF_DIV(x) ((x) & 0x1fff) ++# define GET_DIS_LCDIF_DIV(x) ((x) & 0x1fff) ++#define HW_CLKCTRL_ETM 0x130 ++#define HW_CLKCTRL_ENET 0x140 ++# define SET_CLKCTRL_ENET_DIV(x) (((x) & 0x3f) << 21) ++# define SET_CLKCTRL_ENET_SEL(x) (((x) & 0x3) << 19) ++# define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) ++#define HW_CLKCTRL_HSADC 0x150 ++#define HW_CLKCTRL_FLEXCAN 0x160 ++#define HW_CLKCTRL_FRAC0 0x1b0 ++# define CLKCTRL_FRAC_CLKGATEIO0 (1 << 31) ++# define GET_IO0FRAC(x) (((x) >> 24) & 0x3f) ++# define SET_IO0FRAC(x) (((x) & 0x3f) << 24) ++# define CLKCTRL_FRAC_CLKGATEIO1 (1 << 23) ++# define GET_IO1FRAC(x) (((x) >> 16) & 0x3f) ++# define SET_IO1FRAC(x) (((x) & 0x3f) << 16) ++# define CLKCTRL_FRAC_CLKGATEEMI (1 << 15) ++# define GET_EMIFRAC(x) (((x) >> 8) & 0x3f) ++# define CLKCTRL_FRAC_CLKGATECPU (1 << 7) ++# define GET_CPUFRAC(x) ((x) & 0x3f) ++#define HW_CLKCTRL_FRAC1 0x1c0 ++# define CLKCTRL_FRAC_CLKGATEGPMI (1 << 23) ++# define GET_GPMIFRAC(x) (((x) >> 16) & 0x3f) ++# define CLKCTRL_FRAC_CLKGATEHSADC (1 << 15) ++# define GET_HSADCFRAC(x) (((x) >> 8) & 0x3f) ++# define CLKCTRL_FRAC_CLKGATEPIX (1 << 7) ++# define GET_PIXFRAC(x) ((x) & 0x3f) ++# define SET_PIXFRAC(x) ((x) & 0x3f) ++#define HW_CLKCTRL_CLKSEQ 0x1d0 ++# define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) ++# define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) ++# define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) ++# define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) ++# define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) ++# define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) ++# define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) ++# define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) ++# define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) ++# define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) ++# define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) ++#define HW_CLKCTRL_RESET 0x1e0 ++#define HW_CLKCTRL_STATUS 0x1f0 ++#define HW_CLKCTRL_VERSION 0x200 ++ ++unsigned imx_get_mpllclk(void) ++{ ++ /* the main PLL runs at 480 MHz */ ++ return 480U * 1000U; ++} ++ ++unsigned imx_get_xtalclk(void) ++{ ++ /* the external reference runs at 24 MHz */ ++ return 24U * 1000U; ++} ++ ++/** @return FEC's input clock in [Hz] (_not_ [kHz]!) */ ++unsigned imx_get_fecclk(void) ++{ ++ /* this PLL always runs at 50 MHz */ ++ return 50U * 1000U * 1000U; ++} ++ ++ ++/* used for the SDRAM controller FIXME */ ++unsigned imx_get_emiclk(void) ++{ ++ uint32_t reg; ++ unsigned rate; ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_EMI) & CLKCTRL_EMI_CLKGATE) ++ return 0U; /* clock is off */ ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_EMI) ++ return imx_get_xtalclk() / GET_EMI_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)); ++ ++ rate = imx_get_mpllclk(); ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0); ++ if (!(reg & CLKCTRL_FRAC_CLKGATEEMI)) { ++ rate *= 18U; ++ rate /= GET_EMIFRAC(reg); ++ } ++ ++ return rate / GET_EMI_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)); ++} ++ ++/* ++ * Source of ssp, gpmi, ir ??? FIXME ++ * @param index 0 or 1 for ioclk0 or ioclock1 ++ */ ++unsigned imx_get_ioclk(unsigned index) ++{ ++ uint32_t reg; ++ unsigned rate = imx_get_mpllclk(); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0); ++ switch (index) { ++ case 0: ++ if (reg & CLKCTRL_FRAC_CLKGATEIO0) ++ return 0U; /* clock is off */ ++ ++ rate *= 18U; ++ rate /= GET_IO0FRAC(reg); ++ break; ++ case 1: ++ if (reg & CLKCTRL_FRAC_CLKGATEIO1) ++ return 0U; /* clock is off */ ++ ++ rate *= 18U; ++ rate /= GET_IO1FRAC(reg); ++ break; ++ } ++ return rate; ++} ++ ++/** ++ * Setup a new frequency to the IOCLK domain. ++ * @param index 0 or 1 for ioclk0 or ioclock1 ++ * @param nc New frequency in [kHz] ++ * ++ * The FRAC divider for the IOCLK must be between 18 (* 18/18) and 35 (* 18/35) ++ * ++ * ioclock0 is the shared clock source of SSP0/SSP1, ioclock1 the shared clock ++ * source of SSP2/SSP3 ++ */ ++unsigned imx_set_ioclk(unsigned index, unsigned nc) ++{ ++ uint32_t reg; ++ unsigned div; ++ ++ div = imx_get_mpllclk(); ++ div *= 18U; ++ div += nc >> 1; ++ div /= nc; ++ if (div > 0x3f) ++ div = 0x3f; ++ ++ switch (index) { ++ case 0: ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0) & ~(SET_IO0FRAC(0x3f)); ++ /* mask the current settings */ ++ writel(reg | SET_IO0FRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC0); ++ /* enable the IO clock at its new frequency */ ++ writel(CLKCTRL_FRAC_CLKGATEIO0, IMX_CCM_BASE + HW_CLKCTRL_FRAC0 + 8); ++ break; ++ case 1: ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0) & ~(SET_IO1FRAC(0x3f)); ++ /* mask the current settings */ ++ writel(reg | SET_IO1FRAC(div), IMX_CCM_BASE + HW_CLKCTRL_FRAC0); ++ /* enable the IO clock at its new frequency */ ++ writel(CLKCTRL_FRAC_CLKGATEIO1, IMX_CCM_BASE + HW_CLKCTRL_FRAC0 + 8); ++ break; ++ } ++ ++ return imx_get_ioclk(index); ++} ++ ++/* this is CPU core clock */ ++unsigned imx_get_armclk(void) ++{ ++ uint32_t reg; ++ unsigned rate; ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & CLKCTRL_CLKSEQ_BYPASS_CPU) ++ return imx_get_xtalclk() / GET_CPU_XTAL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0); ++ if (reg & CLKCTRL_FRAC_CLKGATECPU) ++ return 0U; /* should not possible, shouldn't it? */ ++ ++ rate = imx_get_mpllclk(); ++ rate *= 18U; ++ rate /= GET_CPUFRAC(reg); ++ ++ return rate / GET_CPU_PLL_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)); ++} ++ ++/* this is the AHB and APBH bus clock */ ++unsigned imx_get_hclk(void) ++{ ++ unsigned rate = imx_get_armclk(); ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x20) { ++ rate *= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; ++ rate >>= 5U; /* / 32 */ ++ } else ++ rate /= readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS) & 0x1f; ++ return rate; ++} ++ ++/* ++ * Source of UART, debug UART, audio, PWM, dri, timer, digctl ++ */ ++unsigned imx_get_xclk(void) ++{ ++ unsigned rate = imx_get_xtalclk(); /* runs from the 24 MHz crystal reference */ ++ ++ return rate / (readl(IMX_CCM_BASE + HW_CLKCTRL_XBUS) & 0x3ff); ++} ++ ++/** ++ * @param index The SSP unit (0...3) ++ */ ++unsigned imx_get_sspclk(unsigned index) ++{ ++ unsigned rate, offset, shift, ioclk_index; ++ ++ if (index > 3) { ++ pr_debug("Unknown SSP unit: %u\n", index); ++ return 0U; ++ } ++ ++ ioclk_index = index >> 1; ++ ++ offset = HW_CLKCTRL_SSP0 + (0x10 * index); ++ shift = CLKCTRL_CLKSEQ_BYPASS_SSP0 << index; ++ ++ if (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_CLKGATE) ++ return 0U; /* clock is off */ ++ ++ if (readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ) & shift) ++ rate = imx_get_xtalclk(); ++ else ++ rate = imx_get_ioclk(ioclk_index); ++ ++ return rate / GET_SSP_DIV(readl(IMX_CCM_BASE + offset)); ++} ++ ++/** ++ * @param index The SSP unit (0...3) ++ * @param nc New frequency in [kHz] ++ * @param high != 0 if ioclk should be the source ++ * @return The new possible frequency ++ * ++ * FIXME add SSP interface index! ++ */ ++unsigned imx_set_sspclk(unsigned index, unsigned nc, int high) ++{ ++ uint32_t reg; ++ unsigned ssp_div, offset, shift, ioclk_index; ++ ++ if (index > 3) { ++ pr_debug("Unknown SSP unit: %u\n", index); ++ return 0U; ++ } ++ ++ ioclk_index = index >> 1; ++ ++ offset = HW_CLKCTRL_SSP0 + (0x10 * index); ++ shift = CLKCTRL_CLKSEQ_BYPASS_SSP0 << index; ++ ++ reg = readl(IMX_CCM_BASE + offset) & ~CLKCTRL_SSP_CLKGATE; ++ /* Datasheet says: Do not change the DIV setting if the clock is off */ ++ writel(reg, IMX_CCM_BASE + offset); ++ /* Wait while clock is gated */ ++ while (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_CLKGATE) ++ ; ++ ++ if (high) ++ ssp_div = imx_get_ioclk(ioclk_index); ++ else ++ ssp_div = imx_get_xtalclk(); ++ ++ if (nc > ssp_div) { ++ printf("Cannot setup SSP unit clock to %u Hz, base clock is only %u Hz\n", nc, ssp_div); ++ ssp_div = 1U; ++ } else { ++ ssp_div += nc - 1U; ++ ssp_div /= nc; ++ if (ssp_div > CLKCTRL_SSP_DIV_MASK) ++ ssp_div = CLKCTRL_SSP_DIV_MASK; ++ } ++ ++ /* Set new divider value */ ++ reg = readl(IMX_CCM_BASE + offset) & ~CLKCTRL_SSP_DIV_MASK; ++ writel(reg | SET_SSP_DIV(ssp_div), IMX_CCM_BASE + offset); ++ ++ /* Wait until new divider value is set */ ++ while (readl(IMX_CCM_BASE + offset) & CLKCTRL_SSP_BUSY) ++ ; ++ ++ if (high) ++ /* switch to ioclock */ ++ writel(shift, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 8); ++ else ++ /* switch to 24 MHz crystal */ ++ writel(shift, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 4); ++ ++ return imx_get_sspclk(index); ++} ++ ++unsigned imx_get_lcdifclk(void) ++{ ++ unsigned rate = imx_get_mpllclk() * 18U; ++ unsigned div; ++ ++ div = GET_PIXFRAC(readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC1)); ++ if (div != 0U) { ++ rate /= div; ++ div = GET_DIS_LCDIF_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF)); ++ if (div != 0U) ++ rate /= div; ++ else ++ pr_debug("LCDIF clock has divisor 0!\n"); ++ } else ++ pr_debug("LCDIF clock has frac divisor 0!\n"); ++ ++ return rate; ++} ++ ++/** ++ * @param nc Pixel clock in [kHz] ++ * ++ * Calculate the best settings for the fractional and integer divider to match ++ * the requested pixel clock as close as possible. ++ * ++ * pixel clock = 480 MHz * 18 / frac_div / int_div ++ */ ++unsigned imx_set_lcdifclk(unsigned nc) ++{ ++ unsigned frac, best_frac = 0, div, best_div = 0, result; ++ int delta, best_delta = 0xffffff; ++ unsigned i, parent_rate = imx_get_mpllclk(); ++ uint32_t reg; ++ ++#define DIV(NOM, DEN) (((NOM) + (DEN) / 2) / (DEN)) ++#define SH_DIV(NOM, DEN, LSH) ((((NOM) / (DEN)) << (LSH)) + DIV(((NOM) % (DEN)) << (LSH), DEN)) ++#define ABS(x) (((x) < 0) ? (-(x)) : (x)) ++#define SHIFT 4 ++ ++ nc <<= SHIFT; ++ ++ for (frac = 18; frac <= 35; ++frac) { ++ for (div = 1; div <= 255; ++div) { ++ result = DIV(parent_rate * SH_DIV(18U, frac, SHIFT), div); ++ delta = nc - result; ++ if (ABS(delta) < ABS(best_delta)) { ++ best_delta = delta; ++ best_frac = frac; ++ best_div = div; ++ } ++ } ++ } ++ ++ if (best_delta == 0xffffff) { ++ pr_debug("Unable to match the pixelclock\n"); ++ return 0; ++ } ++ ++ pr_debug("Programming PFD=%u,DIV=%u ref_pix=%u MHz PIXCLK=%u MHz\n", ++ best_frac, best_div, 480 * 18 / best_frac, ++ 480 * 18 / best_frac / best_div); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC1) & ~0x3f; ++ reg |= SET_PIXFRAC(best_frac); ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_FRAC1); ++ writel(reg & ~CLKCTRL_FRAC_CLKGATEPIX, IMX_CCM_BASE + HW_CLKCTRL_FRAC1); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF) & ~0x1fff; ++ reg &= ~CLKCTRL_DIS_LCDIF_GATE; ++ reg |= SET_DIS_LCDIF_DIV(best_div); ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF); ++ ++ /* Wait for divider update */ ++ for (i = 0; i < 10000; i++) { ++ if (!(readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF) & CLKCTRL_DIS_LCDIF_BUSY)) ++ break; ++ } ++ ++ if (i >= 10000) { ++ pr_debug("Setting LCD clock failed\n"); ++ return 0; ++ } ++ ++ writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 8); ++ ++ return imx_get_lcdifclk(); ++} ++ ++void imx_enable_enetclk(void) ++{ ++ uint32_t reg; ++ ++ /* wake up main enet PLL */ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0); ++ if (!(reg & CLKCTRL_PLL2CTRL0_POWER)) { ++ reg |= CLKCTRL_PLL2CTRL0_POWER; ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0); ++ udelay(50); /* wait until this PLL locks */ ++ } ++ reg &= ~CLKCTRL_PLL2CTRL0_CLKGATE; ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0); ++ ++ writel(SET_CLKCTRL_ENET_DIV(1) | SET_CLKCTRL_ENET_SEL(0) | ++ CLKCTRL_ENET_CLK_OUT_EN, /* FIXME may be platform specific */ ++ IMX_CCM_BASE + HW_CLKCTRL_ENET); ++} ++ ++void imx_dump_clocks(void) ++{ ++ printf("mpll: %10u kHz\n", imx_get_mpllclk()); ++ printf("arm: %10u kHz\n", imx_get_armclk()); ++ printf("ioclk0: %10u kHz\n", imx_get_ioclk(0)); ++ printf("ioclk1: %10u kHz\n", imx_get_ioclk(1)); ++ printf("emiclk: %10u kHz\n", imx_get_emiclk()); ++ printf("hclk: %10u kHz\n", imx_get_hclk()); ++ printf("xclk: %10u kHz\n", imx_get_xclk()); ++ printf("ssp0: %10u kHz\n", imx_get_sspclk(0)); ++ printf("ssp1: %10u kHz\n", imx_get_sspclk(1)); ++ printf("ssp2: %10u kHz\n", imx_get_sspclk(2)); ++ printf("ssp3: %10u kHz\n", imx_get_sspclk(3)); ++#ifdef DEBUG ++ printf("-------------------------------------------\n"); ++ printf("CLKCTRL_PLL0CTRL0: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_PLL0CTRL0)); ++ printf("CLKCTRL_PLL0CTRL1: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_PLL0CTRL1)); ++ printf("CLKCTRL_PLL1CTRL0: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_PLL1CTRL0)); ++ printf("CLKCTRL_PLL1CTRL1: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_PLL1CTRL1)); ++ printf("CLKCTRL_PLL2CTRL0: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_PLL2CTRL0)); ++ printf("CLKCTRL_CPU: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_CPU)); ++ printf("CLKCTRL_HBUS: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_HBUS)); ++ printf("CLKCTRL_XBUS: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_XBUS)); ++ printf("CLKCTRL_XTAL: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_XTAL)); ++ printf("CLKCTRL_SSP0: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_SSP0)); ++ printf("CLKCTRL_SSP1: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_SSP1)); ++ printf("CLKCTRL_SSP2: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_SSP2)); ++ printf("CLKCTRL_SSP3: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_SSP3)); ++ printf("CLKCTRL_GPMI: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_GPMI)); ++ printf("CLKCTRL_SPDIF: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_SPDIF)); ++ printf("CLKCTRL_ENET: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_ENET)); ++ printf("CLKCTRL_HSADC: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_HSADC)); ++ printf("CLKCTRL_FLEXCAN: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_FLEXCAN)); ++ printf("CLKCTRL_EMI: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_EMI)); ++ printf("CLKCTRL_SAIF0: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_SAIF0)); ++ printf("CLKCTRL_SAIF1: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_SAIF1)); ++ printf("CLKCTRL_LCDIF: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF)); ++ printf("CLKCTRL_ETM: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_ETM)); ++ printf("CLKCTRL_FRAC0: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC0)); ++ printf("CLKCTRL_FRAC1: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC1)); ++ printf("CLKCTRL_CLKSEQ: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ)); ++ printf("CLKCTRL_RESET: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_RESET)); ++ printf("CLKCTRL_STATUS: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_STATUS)); ++ printf("CLKCTRL_VERSION: 0x%08X\n", readl(IMX_CCM_BASE + HW_CLKCTRL_VERSION)); ++ printf("-------------------------------------------\n"); ++#endif ++} +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock-imx28.h +=================================================================== +--- /dev/null ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock-imx28.h +@@ -0,0 +1,36 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef ASM_ARCH_CLOCK_IMX28_H ++#define ASM_ARCH_CLOCK_IMX28_H ++ ++unsigned imx_get_mpllclk(void); ++unsigned imx_get_emiclk(void); ++unsigned imx_get_ioclk(unsigned); ++unsigned imx_get_armclk(void); ++unsigned imx_get_hclk(void); ++unsigned imx_get_xclk(void); ++unsigned imx_get_sspclk(unsigned); ++unsigned imx_set_sspclk(unsigned, unsigned, int); ++unsigned imx_set_ioclk(unsigned, unsigned); ++unsigned imx_get_fecclk(void); ++unsigned imx_set_lcdifclk(unsigned); ++unsigned imx_get_lcdifclk(void); ++void imx_enable_enetclk(void); ++ ++#endif /* ASM_ARCH_CLOCK_IMX28_H */ ++ +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/iomux-imx28.h +=================================================================== +--- /dev/null ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/iomux-imx28.h +@@ -0,0 +1,552 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, ++ * MA 02110-1301, USA. ++ */ ++ ++/* 3322222222221111111111 ++ * 10987654321098765432109876543210 ++ * ^^^^^_ Bit offset ++ * ^^^______ Register Number ++ * ^^_________ Function ++ * ^___________ Drive strength feature present ++ * ^____________ Pull up / bit keeper present ++ * ^^_____________ Drive strength setting ++ * ^_______________ Pull up / bit keeper setting ++ * ^________________ Voltage select present ++ * ^_________________ Voltage selection ++ * ^_____________________ direction if enabled as GPIO (1 = output) ++ * ^______________________ initial output value if enabled as GPIO and configured as output ++ */ ++#ifndef __MACH_IOMUX_IMX28_H ++#define __MACH_IOMUX_IMX28_H ++ ++/* control pad's function */ ++#define FBANK_SHIFT (5) ++#define PORTF(bank,bit) (((bank) << FBANK_SHIFT) | (bit)) ++#define GET_GPIO_NO(x) ((x) & 0xff) ++#define FUNC_SHIFT 8 ++#define FUNC(x) ((x) << FUNC_SHIFT) ++#define GET_FUNC(x) (((x) >> FUNC_SHIFT) & 3) ++#define IS_GPIO (3) ++ ++/* control pad's GPIO feature if enabled */ ++#define GPIO_OUT (1 << 20) ++#define GPIO_VALUE(x) ((x) << 21) ++#define GPIO_IN (0 << 20) ++#define GET_GPIODIR(x) (!!((x) & (1 << 20))) ++#define GET_GPIOVAL(x) (!!((x) & (1 << 21))) ++ ++/* control pad's drive strength */ ++#define SE (1 << 10) ++#define SE_PRESENT(x) (!!((x) & SE)) ++#define STRENGTH(x) ((x) << 12) ++#define S4MA 0 /* used to define a 4 mA drive strength */ ++#define S8MA 1 /* used to define a 8 mA drive strength */ ++#define S12MA 2 /* used to define a 12 mA drive strength */ ++#define S16MA 3 /* used to define a 16 mA drive strength, not all pads can drive this current! */ ++#define GET_STRENGTH(x) (((x) >> 12) & 0x3) ++ ++/* control pad's pull up / bit keeper feature */ ++#define PE (1 << 11) ++#define BK (1 << 11) /* FIXME */ ++#define PE_PRESENT(x) (!!((x) & PE)) ++#define BK_PRESENT(x) (!!((x) & BK)) ++#define PULLUP(x) ((x) << 14) ++#define BITKEEPER(x) ((x) << 14) ++#define GET_PULLUP(x) (!!((x) & (1 << 14))) ++#define GET_BITKEEPER(x) (!!((x) & (1 << 14))) ++ ++/* control pad's voltage feature */ ++#define VE (1 << 15) ++#define VE_PRESENT(x) (!!((x) & VE)) ++#define VE_1_8V (0 << 16) ++#define VE_3_3V (1 << 16) ++#define GET_VOLTAGE(x) (!!((x) & (1 << 16))) ++ ++/* Bank 0, GPIO pins 0 ... 31 */ ++#define GPMI_RESETN (FUNC(0) | PORTF(0, 28) | SE | VE | PE) ++#define GPMI_RESETN_SSP3_CMD (FUNC(1) | PORTF(0, 28) | SE | VE | PE) ++#define GPMI_RESETN_GPIO (FUNC(3) | PORTF(0, 28) | SE | VE | PE) ++#define GPMI_CLE (FUNC(0) | PORTF(0, 27) | SE | VE | PE) ++#define GPMI_CLE_SSP3_D2 (FUNC(1) | PORTF(0, 27) | SE | VE | PE) ++#define GPMI_CLE_SSP3_D5 (FUNC(2) | PORTF(0, 27) | SE | VE | PE) ++#define GPMI_CLE_GPIO (FUNC(3) | PORTF(0, 27) | SE | VE | PE) ++#define GPMI_ALE (FUNC(0) | PORTF(0, 26) | SE | VE | PE) ++#define GPMI_ALE_SSP3_D1 (FUNC(1) | PORTF(0, 26) | SE | VE | PE) ++#define GPMI_ALE_SSP3_D4 (FUNC(2) | PORTF(0, 26) | SE | VE | PE) ++#define GPMI_ALE_GPIO (FUNC(3) | PORTF(0, 26) | SE | VE | PE) ++#define GPMI_WRN (FUNC(0) | PORTF(0, 25) | SE | VE | BK) ++#define GPMI_WRN_SSP1_SCK (FUNC(1) | PORTF(0, 25) | SE | VE | BK) ++#define GPMI_WRN_GPIO (FUNC(3) | PORTF(0, 25) | SE | VE | BK) ++#define GPMI_RDN (FUNC(0) | PORTF(0, 24) | SE | VE | PE) ++#define GPMI_RDN_SSP3_SCK (FUNC(1) | PORTF(0, 24) | SE | VE | PE) ++#define GPMI_RDN_GPIO (FUNC(3) | PORTF(0, 24) | SE | VE | PE) ++#define GPMI_READY3 (FUNC(0) | PORTF(0, 23) | SE | VE | PE) ++#define GPMI_READY3_CAN0_RX (FUNC(1) | PORTF(0, 23) | SE | VE | PE) ++#define GPMI_READY3_HSDAC_TRIG (FUNC(2) | PORTF(0, 23) | SE | VE | PE) ++#define GPMI_READY3_GPIO (FUNC(3) | PORTF(0, 23) | SE | VE | PE) ++#define GPMI_READY2 (FUNC(0) | PORTF(0, 22) | SE | VE | PE) ++#define GPMI_READY2_CAN0_TX (FUNC(1) | PORTF(0, 22) | SE | VE | PE) ++#define GPMI_READY2_ENET0_TX_ER (FUNC(2) | PORTF(0, 22) | SE | VE | PE) ++#define GPMI_READY2_GPIO (FUNC(3) | PORTF(0, 22) | SE | VE | PE) ++#define GPMI_READY1 (FUNC(0) | PORTF(0, 21) | SE | VE | PE) ++#define GPMI_READY1_SSP1_CMD (FUNC(1) | PORTF(0, 21) | SE | VE | PE) ++#define GPMI_READY1_GPIO (FUNC(3) | PORTF(0, 21) | SE | VE | PE) ++#define GPMI_READY0 (FUNC(0) | PORTF(0, 20) | SE | VE | PE) ++#define GPMI_READY0_SSP1_CD (FUNC(1) | PORTF(0, 20) | SE | VE | PE) ++#define GPMI_READY0_USB0_ID (FUNC(2) | PORTF(0, 20) | SE | VE | PE) ++#define GPMI_READY0_GPIO (FUNC(3) | PORTF(0, 20) | SE | VE | PE) ++#define GPMI_CE3N (FUNC(0) | PORTF(0, 19) | SE | VE | PE) ++#define GPMI_CE3N_CAN1_RX (FUNC(1) | PORTF(0, 19) | SE | VE | PE) ++#define GPMI_CE3N_SAIF1_MCLK (FUNC(2) | PORTF(0, 19) | SE | VE | PE) ++#define GPMI_CE3N_GPIO (FUNC(3) | PORTF(0, 19) | SE | VE | PE) ++#define GPMI_CE2N (FUNC(0) | PORTF(0, 18) | SE | VE | PE) ++#define GPMI_CE2N_CAN1_TX (FUNC(1) | PORTF(0, 18) | SE | VE | PE) ++#define GPMI_CE2N_ENET0_RX_ER (FUNC(2) | PORTF(0, 18) | SE | VE | PE) ++#define GPMI_CE2N_GPIO (FUNC(3) | PORTF(0, 18) | SE | VE | PE) ++#define GPMI_CE1N (FUNC(0) | PORTF(0, 17) | SE | VE | PE) ++#define GPMI_CE1N_SSP3_D3 (FUNC(1) | PORTF(0, 17) | SE | VE | PE) ++#define GPMI_CE1N_GPIO (FUNC(3) | PORTF(0, 17) | SE | VE | PE) ++#define GPMI_CE0N (FUNC(0) | PORTF(0, 16) | SE | VE | PE) ++#define GPMI_CE0N_SSP3_D0 (FUNC(1) | PORTF(0, 16) | SE | VE | PE) ++#define GPMI_CE0N_GPIO (FUNC(3) | PORTF(0, 16) | SE | VE | PE) ++#define GPMI_D7 (FUNC(0) | PORTF(0, 7) | SE | VE | PE) ++#define GPMI_D7_SSP1_D7 (FUNC(1) | PORTF(0, 7) | SE | VE | PE) ++#define GPMI_D7_GPIO (FUNC(3) | PORTF(0, 7) | SE | VE | PE) ++#define GPMI_D6 (FUNC(0) | PORTF(0, 6) | SE | VE | PE) ++#define GPMI_D6_SSP1_D6 (FUNC(1) | PORTF(0, 6) | SE | VE | PE) ++#define GPMI_D6_GPIO (FUNC(3) | PORTF(0, 6) | SE | VE | PE) ++#define GPMI_D5 (FUNC(0) | PORTF(0, 5) | SE | VE | PE) ++#define GPMI_D5_SSP1_D5 (FUNC(1) | PORTF(0, 5) | SE | VE | PE) ++#define GPMI_D5_GPIO (FUNC(3) | PORTF(0, 5) | SE | VE | PE) ++#define GPMI_D4 (FUNC(0) | PORTF(0, 4) | SE | VE | PE) ++#define GPMI_D4_SSP1_D4 (FUNC(1) | PORTF(0, 4) | SE | VE | PE) ++#define GPMI_D4_GPIO (FUNC(3) | PORTF(0, 4) | SE | VE | PE) ++#define GPMI_D3 (FUNC(0) | PORTF(0, 3) | SE | VE | PE) ++#define GPMI_D3_SSP1_D3 (FUNC(1) | PORTF(0, 3) | SE | VE | PE) ++#define GPMI_D3_GPIO (FUNC(3) | PORTF(0, 3) | SE | VE | PE) ++#define GPMI_D2 (FUNC(0) | PORTF(0, 2) | SE | VE | PE) ++#define GPMI_D2_SSP1_D2 (FUNC(1) | PORTF(0, 2) | SE | VE | PE) ++#define GPMI_D2_GPIO (FUNC(3) | PORTF(0, 2) | SE | VE | PE) ++#define GPMI_D1 (FUNC(0) | PORTF(0, 1) | SE | VE | PE) ++#define GPMI_D1_SSP1_D1 (FUNC(1) | PORTF(0, 1) | SE | VE | PE) ++#define GPMI_D1_GPIO (FUNC(3) | PORTF(0, 1) | SE | VE | PE) ++#define GPMI_D0 (FUNC(0) | PORTF(0, 0) | SE | VE | PE) ++#define GPMI_D0_SSP1_D0 (FUNC(1) | PORTF(0, 0) | SE | VE | PE) ++#define GPMI_D0_GPIO (FUNC(3) | PORTF(0, 0) | SE | VE | PE) ++ ++/* Bank 1, GPIO pins 32 ... 63 */ ++ ++#define LCD_ENABLE (FUNC(0) | PORTF(1, 31) | SE | VE | BK) ++#define LCD_ENABLE_GPIO (FUNC(3) | PORTF(1, 31) | SE | VE | BK) ++ ++#define LCD_DOTCLK (FUNC(0) | PORTF(1, 30) | SE | VE | BK) ++ ++#define LCD_HSYNC (FUNC(0) | PORTF(1, 29) | SE | VE | BK) ++ ++#define LCD_VSYNC (FUNC(0) | PORTF(1, 28) | SE | VE | BK) ++ ++#define LCD_CS (FUNC(0) | PORTF(1, 27) | SE | VE | BK) ++#define LCD_CS_LCD_ENABLE (FUNC(1) | PORTF(1, 27) | SE | VE | BK) ++#define LCD_CS_GPIO (FUNC(3) | PORTF(1, 27) | SE | VE | BK) ++ ++#define LCD_RS (FUNC(0) | PORTF(1, 26) | SE | VE | BK) ++#define LCD_RS_LCD_DOTCLK (FUNC(1) | PORTF(1, 26) | SE | VE | BK) ++#define LCD_RS_GPIO (FUNC(3) | PORTF(1, 26) | SE | VE | BK) ++#define LCD_WR_RWN (FUNC(0) | PORTF(1, 25) | SE | VE | BK) ++#define LCD_WR_RWN_LCD_HSYNC (FUNC(1) | PORTF(1, 25) | SE | VE | BK) ++#define LCD_WR_RWN_ETM_TCLK (FUNC(2) | PORTF(1, 25) | SE | VE | BK) ++#define LCD_WR_RWN_GPIO (FUNC(3) | PORTF(1, 25) | SE | VE | BK) ++#define LCD_RD_E (FUNC(0) | PORTF(1, 24) | SE | VE | BK) ++#define LCD_RD_E_LCD_VSYNC (FUNC(1) | PORTF(1, 24) | SE | VE | BK) ++#define LCD_RD_E_ETM_TCTL (FUNC(2) | PORTF(1, 24) | SE | VE | BK) ++#define LCD_RD_E_GPIO (FUNC(3) | PORTF(1, 24) | SE | VE | BK) ++ ++#define LCD_D23 (FUNC(0) | PORTF(1, 23) | SE | VE | BK) ++ ++#define LCD_D22 (FUNC(0) | PORTF(1, 22) | SE | VE | BK) ++ ++#define LCD_D21 (FUNC(0) | PORTF(1, 21) | SE | VE | BK) ++ ++#define LCD_D20 (FUNC(0) | PORTF(1, 20) | SE | VE | BK) ++ ++#define LCD_D19 (FUNC(0) | PORTF(1, 19) | SE | VE | BK) ++ ++#define LCD_D18 (FUNC(0) | PORTF(1, 18) | SE | VE | BK) ++ ++#define LCD_D17 (FUNC(0) | PORTF(1, 17) | SE | VE | BK) ++ ++#define LCD_D16 (FUNC(0) | PORTF(1, 16) | SE | VE | BK) ++ ++#define LCD_D15 (FUNC(0) | PORTF(1, 15) | SE | VE | BK) ++#define LCD_D15_ETM_DA15 (FUNC(2) | PORTF(1, 15) | SE | VE | BK) ++#define LCD_D15_GPIO (FUNC(3) | PORTF(1, 15) | SE | VE | BK) ++#define LCD_D14 (FUNC(0) | PORTF(1, 14) | SE | VE | BK) ++#define LCD_D14_ETM_DA14 (FUNC(2) | PORTF(1, 14) | SE | VE | BK) ++#define LCD_D14_GPIO (FUNC(3) | PORTF(1, 14) | SE | VE | BK) ++#define LCD_D13 (FUNC(0) | PORTF(1, 13) | SE | VE | BK) ++#define LCD_D13_ETM_DA13 (FUNC(2) | PORTF(1, 13) | SE | VE | BK) ++#define LCD_D13_GPIO (FUNC(3) | PORTF(1, 13) | SE | VE | BK) ++#define LCD_D12 (FUNC(0) | PORTF(1, 12) | SE | VE | BK) ++#define LCD_D12_ETM_DA12 (FUNC(2) | PORTF(1, 12) | SE | VE | BK) ++#define LCD_D12_GPIO (FUNC(3) | PORTF(1, 12) | SE | VE | BK) ++#define LCD_D11 (FUNC(0) | PORTF(1, 11) | SE | VE | BK) ++#define LCD_D11_ETM_DA11 (FUNC(2) | PORTF(1, 11) | SE | VE | BK) ++#define LCD_D11_GPIO (FUNC(3) | PORTF(1, 11) | SE | VE | BK) ++#define LCD_D10 (FUNC(0) | PORTF(1, 10) | SE | VE | BK) ++#define LCD_D10_ETM_DA10 (FUNC(2) | PORTF(1, 10) | SE | VE | BK) ++#define LCD_D10_GPIO (FUNC(3) | PORTF(1, 10) | SE | VE | BK) ++#define LCD_D9 (FUNC(0) | PORTF(1, 9) | SE | VE | BK) ++#define LCD_D9_ETM_DA4 (FUNC(1) | PORTF(1, 9) | SE | VE | BK) ++#define LCD_D9_ETM_DA9 (FUNC(2) | PORTF(1, 9) | SE | VE | BK) ++#define LCD_D9_GPIO (FUNC(3) | PORTF(1, 9) | SE | VE | BK) ++#define LCD_D8 (FUNC(0) | PORTF(1, 8) | SE | VE | BK) ++#define LCD_D8_ETM_DA3 (FUNC(1) | PORTF(1, 8) | SE | VE | BK) ++#define LCD_D8_ETM_DA8 (FUNC(2) | PORTF(1, 8) | SE | VE | BK) ++#define LCD_D8_GPIO (FUNC(3) | PORTF(1, 8) | SE | VE | BK) ++#define LCD_D7 (FUNC(0) | PORTF(1, 7) | SE | VE | BK) ++#define LCD_D7_ETM_DA7 (FUNC(2) | PORTF(1, 7) | SE | VE | BK) ++#define LCD_D7_GPIO (FUNC(3) | PORTF(1, 7) | SE | VE | BK) ++#define LCD_D6 (FUNC(0) | PORTF(1, 6) | SE | VE | BK) ++#define LCD_D6_ETM_DA6 (FUNC(2) | PORTF(1, 6) | SE | VE | BK) ++#define LCD_D6_GPIO (FUNC(3) | PORTF(1, 6) | SE | VE | BK) ++#define LCD_D5 (FUNC(0) | PORTF(1, 5) | SE | VE | BK) ++#define LCD_D5_ETM_DA5 (FUNC(2) | PORTF(1, 5) | SE | VE | BK) ++#define LCD_D5_GPIO (FUNC(3) | PORTF(1, 5) | SE | VE | BK) ++#define LCD_D4 (FUNC(0) | PORTF(1, 4) | SE | VE | BK) ++#define LCD_D4_ETM_DA9 (FUNC(1) | PORTF(1, 4) | SE | VE | BK) ++#define LCD_D4_ETM_DA4 (FUNC(2) | PORTF(1, 4) | SE | VE | BK) ++#define LCD_D4_GPIO (FUNC(3) | PORTF(1, 4) | SE | VE | BK) ++#define LCD_D3 (FUNC(0) | PORTF(1, 3) | SE | VE | BK) ++#define LCD_D3_ETM_DA8 (FUNC(1) | PORTF(1, 3) | SE | VE | BK) ++#define LCD_D3_ETM_DA3 (FUNC(2) | PORTF(1, 3) | SE | VE | BK) ++#define LCD_D3_GPIO (FUNC(3) | PORTF(1, 3) | SE | VE | BK) ++#define LCD_D2 (FUNC(0) | PORTF(1, 2) | SE | VE | BK) ++#define LCD_D2_ETM_DA2 (FUNC(2) | PORTF(1, 2) | SE | VE | BK) ++#define LCD_D2_GPIO (FUNC(3) | PORTF(1, 2) | SE | VE | BK) ++#define LCD_D1 (FUNC(0) | PORTF(1, 1) | SE | VE | BK) ++#define LCD_D1_ETM_DA1 (FUNC(2) | PORTF(1, 1) | SE | VE | BK) ++#define LCD_D1_GPIO (FUNC(3) | PORTF(1, 1) | SE | VE | BK) ++#define LCD_D0 (FUNC(0) | PORTF(1, 0) | SE | VE | BK) ++#define LCD_D0_ETM_DA0 (FUNC(2) | PORTF(1, 0) | SE | VE | BK) ++#define LCD_D0_GPIO (FUNC(3) | PORTF(1, 0) | SE | VE | BK) ++ ++/* TODO */ ++ ++/* Bank 2, GPIO pins 64 ... 95 */ ++ ++/* TODO */ ++ ++#define SSP1_D3 (FUNC(0) | PORTF(2, 15) | SE | VE | PE) ++#define SSP1_D3_SSP2_D7 (FUNC(1) | PORTF(2, 15) | SE | VE | PE) ++#define SSP1_D3_ENET_1588_EVENT3_IN (FUNC(2) | PORTF(4, 15) | SE | VE | PE) ++#define SSP1_D3_GPIO (FUNC(3) | PORTF(2, 15) | SE | VE | PE) ++#define SSP1_D0 (FUNC(0) | PORTF(2, 14) | SE | VE | PE) ++#define SSP1_D0_SSP2_D6 (FUNC(1) | PORTF(2, 14) | SE | VE | PE) ++#define SSP1_D0_ENET_1588_EVENT3_OUT (FUNC(2) | PORTF(2, 14) | SE | VE | PE) ++#define SSP1_D0_GPIO (FUNC(3) | PORTF(2, 14) | SE | VE | PE) ++#define SSP1_CMD (FUNC(0) | PORTF(2, 13) | SE | VE | PE) ++#define SSP1_CMD_SSP2_D2 (FUNC(1) | PORTF(2, 13) | SE | VE | PE) ++#define SSP1_CMD_ENET_1588_EVENT2_IN (FUNC(2) | PORTF(2, 13) | SE | VE | PE) ++#define SSP1_CMD_GPIO (FUNC(3) | PORTF(2, 13) | SE | VE | PE) ++#define SSP1_SCK (FUNC(0) | PORTF(2, 12) | SE | VE | PE) ++#define SSP1_SCK_SSP2_D1 (FUNC(1) | PORTF(2, 12) | SE | VE | PE) ++#define SSP1_SCK_ENET_1588_EVENT2_OUT (FUNC(2) | PORTF(2, 12) | SE | VE | PE) ++#define SSP1_SCK_GPIO (FUNC(3) | PORTF(2, 12) | SE | VE | PE) ++#define SSP0_SCK (FUNC(0) | PORTF(2, 10) | SE | VE | BK) ++#define SSP0_SCK_GPIO (FUNC(3) | PORTF(2, 10) | SE | VE | BK) ++#define SSP0_CD (FUNC(0) | PORTF(2, 9) | SE | VE | PE) ++#define SSP0_CD_GPIO (FUNC(3) | PORTF(2, 9) | SE | VE | PE) ++#define SSP0_CMD (FUNC(0) | PORTF(2, 8) | SE | VE | PE) ++#define SSP0_CMD_GPIO (FUNC(3) | PORTF(2, 8) | SE | VE | PE) ++#define SSP0_D7 (FUNC(0) | PORTF(2, 7) | SE | VE | PE) ++#define SSP0_D7_SSP2_SCK (FUNC(1) | PORTF(2, 7) | SE | VE | PE) ++#define SSP0_D7_GPIO (FUNC(3) | PORTF(2, 7) | SE | VE | PE) ++#define SSP0_D6 (FUNC(0) | PORTF(2, 6) | SE | VE | PE) ++#define SSP0_D6_SSP2_CMD (FUNC(1) | PORTF(2, 6) | SE | VE | PE) ++#define SSP0_D6_GPIO (FUNC(3) | PORTF(2, 6) | SE | VE | PE) ++#define SSP0_D5 (FUNC(0) | PORTF(2, 5) | SE | VE | PE) ++#define SSP0_D5_SSP2_D3 (FUNC(1) | PORTF(2, 5) | SE | VE | PE) ++#define SSP0_D5_GPIO (FUNC(3) | PORTF(2, 5) | SE | VE | PE) ++#define SSP0_D4 (FUNC(0) | PORTF(2, 4) | SE | VE | PE) ++#define SSP0_D4_SSP2_D0 (FUNC(1) | PORTF(2, 4) | SE | VE | PE) ++#define SSP0_D4_GPIO (FUNC(3) | PORTF(2, 4) | SE | VE | PE) ++#define SSP0_D3 (FUNC(0) | PORTF(2, 3) | SE | VE | PE) ++#define SSP0_D3_GPIO (FUNC(3) | PORTF(2, 3) | SE | VE | PE) ++#define SSP0_D2 (FUNC(0) | PORTF(2, 2) | SE | VE | PE) ++#define SSP0_D2_GPIO (FUNC(3) | PORTF(2, 2) | SE | VE | PE) ++#define SSP0_D1 (FUNC(0) | PORTF(2, 1) | SE | VE | PE) ++#define SSP0_D1_GPIO (FUNC(3) | PORTF(2, 1) | SE | VE | PE) ++#define SSP0_D0 (FUNC(0) | PORTF(2, 0) | SE | VE | PE) ++#define SSP0_D0_GPIO (FUNC(3) | PORTF(2, 0) | SE | VE | PE) ++ ++/* Bank 3, GPIO pins 95 ... 127 */ ++ ++#define LCD_RESET (FUNC(0) | PORTF(3, 30)) ++#define LCD_RESET_LCD_VSYNC (FUNC(1) | PORTF(3, 30)) ++#define LCD_RESET_GPIO (FUNC(3) | PORTF(3, 30)) ++#define PWM4 (FUNC(0) | PORTF(3, 29)) ++#define PWM4_GPIO (FUNC(3) | PORTF(3, 29)) ++#define PWM3 (FUNC(0) | PORTF(3 28)) ++#define PWM3_GPIO (FUNC(3) | PORTF(3, 28)) ++ ++#define PWM2 (FUNC(0) | PORTF(3, 18)) ++ ++#define PWM1 (FUNC(0) | PORTF(3, 17)) ++ ++#define PWM0 (FUNC(0) | PORTF(3, 16)) ++ ++#define AUART3_RTS (FUNC(0) | PORTF(3, 15) | SE | VE | BK) ++#define AUART3_RTS_CAN1_RX (FUNC(1) | PORTF(3, 15) | SE | VE | BK) ++#define AUART3_RTS_ENET0_1588_EVENT1_IN (FUNC(2) | PORTF(3, 15) | SE | VE | BK) ++#define AUART3_RTS_GPIO (FUNC(3) | PORTF(3, 15) | SE | VE | BK) ++#define AUART3_CTS (FUNC(0) | PORTF(3, 14) | SE | VE | BK | BK) ++#define AUART3_CTS_CAN1_TX (FUNC(1) | PORTF(3, 14) | SE | VE | BK) ++#define AUART3_CTS_ENET0_1588_EVENT1_OUT (FUNC(2) | PORTF(3, 14) | SE | VE | BK) ++#define AUART3_CTS_GPIO (FUNC(3) | PORTF(3, 14) | SE | VE | BK) ++#define AUART3_TX (FUNC(0) | PORTF(3, 13) | SE | VE | BK) ++#define AUART3_TX_CAN0_RX (FUNC(1) | PORTF(3, 13) | SE | VE | BK) ++#define AUART3_TX_ENET0_1588_EVENT0_IN (FUNC(2) | PORTF(3, 13) | SE | VE | BK) ++#define AUART3_TX_GPIO (FUNC(3) | PORTF(3, 13) | SE | VE | BK) ++#define AUART3_RX (FUNC(0) | PORTF(3, 12) | SE | VE | BK) ++#define AUART3_RX_CAN0_TX (FUNC(1) | PORTF(3, 12) | SE | VE | BK) ++#define AUART3_RX_ENET0_1588_EVENT0_OUT (FUNC(2) | PORTF(3, 12) | SE | VE | BK) ++#define AUART3_RX_GPIO (FUNC(3) | PORTF(3, 12) | SE | VE | BK) ++#define AUART2_RTS (FUNC(0) | PORTF(3, 11) | SE | VE | BK) ++#define AUART2_RTS_I2C1_SDA (FUNC(1) | PORTF(3, 11) | SE | VE | BK) ++#define AUART2_RTS_SAIF1_IRCLK (FUNC(2) | PORTF(3, 11) | SE | VE | BK) ++#define AUART2_RTS_GPIO (FUNC(3) | PORTF(3, 11) | SE | VE | BK) ++#define AUART2_CTS (FUNC(0) | PORTF(3, 10) | SE | VE | BK) ++#define AUART2_CTS_I2C1_SCL (FUNC(1) | PORTF(3, 10) | SE | VE | BK) ++#define AUART2_CTS_SAIF1_BITCLK (FUNC(2) | PORTF(3, 10) | SE | VE | BK) ++#define AUART2_CTS_GPIO (FUNC(3) | PORTF(3, 10) | SE | VE | BK) ++#define AUART2_TX (FUNC(0) | PORTF(3, 9) | SE | VE | PE) ++#define AUART2_TX_SSP3_D2 (FUNC(1) | PORTF(3, 9) | SE | VE | PE) ++#define AUART2_TX_SSP3_D5 (FUNC(2) | PORTF(3, 9) | SE | VE | PE) ++#define AUART2_TX_GPIO (FUNC(3) | PORTF(3, 9) | SE | VE | PE) ++#define AUART2_RX (FUNC(0) | PORTF(3, 8) | SE | VE | PE) ++#define AUART2_RX_SSP3_D1 (FUNC(1) | PORTF(3, 8) | SE | VE | PE) ++#define AUART2_RX_SSP3_D4 (FUNC(2) | PORTF(3, 8) | SE | VE | PE) ++#define AUART2_RX_GPIO (FUNC(3) | PORTF(3, 8) | SE | VE | PE) ++#define AUART1_RTS (FUNC(0) | PORTF(3, 7) | SE | VE | PE) ++#define AUART1_RTS_USB0_ID (FUNC(1) | PORTF(3, 7) | SE | VE | PE) ++#define AUART1_RTS_ROTARYB (FUNC(2) | PORTF(3, 7) | SE | VE | PE) ++#define AUART1_RTS_GPIO (FUNC(3) | PORTF(3, 7) | SE | VE | PE) ++#define AUART1_CTS (FUNC(0) | PORTF(3, 6) | SE | VE | PE) ++#define AUART1_CTS_USB0_OC (FUNC(1) | PORTF(3, 6) | SE | VE | PE) ++#define AUART1_CTS_ROTARYA (FUNC(2) | PORTF(3, 6) | SE | VE | PE) ++#define AUART1_CTS_GPIO (FUNC(3) | PORTF(3, 6) | SE | VE | PE) ++#define AUART1_TX (FUNC(0) | PORTF(3, 5) | SE | VE | BK) ++#define AUART1_TX_SSP3_CD (FUNC(1) | PORTF(3, 5) | SE | VE | BK) ++#define AUART1_TX_PWM1 (FUNC(2) | PORTF(3, 5) | SE | VE | BK) ++#define AUART1_TX_GPIO (FUNC(3) | PORTF(3, 5) | SE | VE | BK) ++#define AUART1_RX (FUNC(0) | PORTF(3, 4) | SE | VE | BK) ++#define AUART1_RX_SSP2_CD (FUNC(1) | PORTF(3, 4) | SE | VE | BK) ++#define AUART1_RX_PWM0 (FUNC(2) | PORTF(3, 4) | SE | VE | BK) ++#define AUART1_RX_GPIO (FUNC(3) | PORTF(3, 4) | SE | VE | BK) ++#define AUART0_RTS (FUNC(0) | PORTF(3, 3) | SE | VE | BK) ++#define AUART0_RTS_AUART4_TX (FUNC(1) | PORTF(3, 3) | SE | VE | BK) ++#define AUART0_RTS_DUART_TX (FUNC(2) | PORTF(3, 3) | SE | VE | BK) ++#define AUART0_RTS_GPIO (FUNC(3) | PORTF(3, 3) | SE | VE | BK) ++#define AUART0_CTS (FUNC(0) | PORTF(3, 2) | SE | VE | BK) ++#define AUART0_CTS_AUART4_RX (FUNC(1) | PORTF(3, 2) | SE | VE | BK) ++#define AUART0_CTS_DUART_RX (FUNC(2) | PORTF(3, 2) | SE | VE | BK) ++#define AUART0_CTS_GPIO (FUNC(3) | PORTF(3, 2) | SE | VE | BK) ++#define AUART0_TX (FUNC(0) | PORTF(3, 1) | SE | VE | BK) ++#define AUART0_TX_I2C0_SDA (FUNC(1) | PORTF(3, 1) | SE | VE | BK) ++#define AUART0_TX_DUART_RTS (FUNC(2) | PORTF(3, 1) | SE | VE | BK) ++#define AUART0_TX_GPIO (FUNC(3) | PORTF(3, 1) | SE | VE | BK) ++#define AUART0_RX (FUNC(0) | PORTF(3, 0) | SE | VE | BK) ++#define AUART0_RX_I2C0_SCL (FUNC(1) | PORTF(3, 0) | SE | VE | BK) ++#define AUART0_RX_DUART_CTS (FUNC(2) | PORTF(3, 0) | SE | VE | BK) ++#define AUART0_RX_GPIO (FUNC(3) | PORTF(3, 0) | SE | VE | BK) ++ ++/* Bank 4, GPIO pins 128 ... 159 */ ++ ++#define JTAG_RTCK (FUNC(0) | PORTF(4, 20) | SE | VE | BK) ++#define JTAG_RTCK_GPIO (FUNC(3) | PORTF(4, 20) | SE | VE | BK) ++#define ENET_CLK (FUNC(0) | PORTF(4, 16) | SE | VE | BK) ++#define ENET_CLK_GPIO (FUNC(3) | PORTF(4, 16) | SE | VE | BK) ++ ++#define ENET0_CRS (FUNC(0) | PORTF(4, 15) | SE | VE | BK) ++ ++#define ENET0_COL (FUNC(0) | PORTF(4, 14) | SE | VE | BK) ++ ++#define ENET0_RX_CLK (FUNC(0) | PORTF(4, 13) | SE | VE | BK) ++#define ENET0_RX_CLK_RX_ER (FUNC(1) | PORTF(4, 13) | SE | VE | BK) ++#define ENET0_RX_ENET0_1588_EVENT2_IN (FUNC(2) | PORTF(4, 13) | SE | VE | BK) ++#define ENET0_RX_CLK_GPIO (FUNC(3) | PORTF(4, 13) | SE | VE | BK) ++#define ENET0_TXD3 (FUNC(0) | PORTF(4, 12) | SE | VE | BK) ++#define ENET0_TXD3_ENET1_TXD1 (FUNC(1) | PORTF(4, 12) | SE | VE | BK) ++#define ENET0_TXD3_ENET0_1588_EVENT1_IN (FUNC(2) | PORTF(4, 12) | SE | VE | BK) ++#define ENET0_TXD3_GPIO (FUNC(3) | PORTF(4, 12) | SE | VE | BK) ++ ++#define ENET0_TXD2 (FUNC(0) | PORTF(4, 11) | SE | VE | BK) ++ ++#define ENET0_TXD2_GPIO (FUNC(3) | PORTF(4, 11) | SE | VE | BK) ++ ++#define ENET0_RXD3 (FUNC(0) | PORTF(4, 10) | SE | VE | BK) ++#define ENET0_RXD3_ENET1_RXD1 (FUNC(1) | PORTF(4, 10) | SE | VE | BK) ++#define ENET0_RXD3_ENET0_1588_EVENT0_IN (FUNC(2) | PORTF(4, 10) | SE | VE | BK) ++#define ENET0_RXD3_GPIO (FUNC(3) | PORTF(4, 10) | SE | VE | BK) ++ ++#define ENET0_RXD2 (FUNC(0) | PORTF(4, 9) | SE | VE | BK) ++ ++#define ENET0_RXD2_GPIO (FUNC(3) | PORTF(4, 9) | SE | VE | BK) ++ ++#define ENET0_TXD1 (FUNC(0) | PORTF(4, 8) | SE | VE | PE) ++ ++#define ENET0_TXD1_GPIO (FUNC(3) | PORTF(4, 8) | SE | VE | PE) ++ ++#define ENET0_TXD0 (FUNC(0) | PORTF(4, 7) | SE | VE | PE) ++ ++#define ENET0_TXD0_GPIO (FUNC(3) | PORTF(4, 7) | SE | VE | PE) ++ ++#define ENET0_TX_EN (FUNC(0) | PORTF(4, 6) | SE | VE | PE) ++ ++#define ENET0_TX_EN_GPIO (FUNC(3) | PORTF(4, 6) | SE | VE | PE) ++ ++#define ENET0_TX_CLK (FUNC(0) | PORTF(4, 5) | SE | VE | BK) ++ ++#define ENET0_TX_CLK_GPIO (FUNC(3) | PORTF(4, 5) | SE | VE | BK) ++ ++#define ENET0_RXD1 (FUNC(0) | PORTF(4, 4) | SE | VE | PE) ++#define ENET0_RXD1_GPMI_READY4 (FUNC(1) | PORTF(4, 4) | SE | VE | PE) ++#define ENET0_RXD1_GPIO (FUNC(3) | PORTF(4, 4) | SE | VE | PE) ++#define ENET0_RXD0 (FUNC(0) | PORTF(4, 3) | SE | VE | PE) ++#define ENET0_RXD0_GPMI_CE7N (FUNC(1) | PORTF(4, 3) | SE | VE | PE) ++#define ENET0_RXD0_SAIF1_SDATA2 (FUNC(2) | PORTF(4, 3) | SE | VE | PE) ++#define ENET0_RXD0_GPIO (FUNC(3) | PORTF(4, 3) | SE | VE | PE) ++#define ENET0_RX_EN (FUNC(0) | PORTF(4, 2) | SE | VE | PE) ++#define ENET0_RX_EN_GPMI_CE6N (FUNC(1) | PORTF(4, 2) | SE | VE | PE) ++#define ENET0_RX_EN_SAIF1_SDATA1 (FUNC(2) | PORTF(4, 2) | SE | VE | PE) ++#define ENET0_RX_EN_GPIO (FUNC(3) | PORTF(4, 2) | SE | VE | PE) ++#define ENET0_MDIO (FUNC(0) | PORTF(4, 1) | SE | VE | PE) ++#define ENET0_MDIO_GPMI_CE5N (FUNC(1) | PORTF(4, 1) | SE | VE | PE) ++#define ENET0_MDIO_SAIF0_SDATA2 (FUNC(2) | PORTF(4, 1) | SE | VE | PE) ++#define ENET0_MDIO_GPIO (FUNC(3) | PORTF(4, 1) | SE | VE | PE) ++#define ENET0_MDC (FUNC(0) | PORTF(4, 0) | SE | VE | PE) ++#define ENET0_MDC_GPMI_CE4N (FUNC(1) | PORTF(4, 0) | SE | VE | PE) ++#define ENET0_MDC_SAIF0_SDATA1 (FUNC(2) | PORTF(4, 0) | SE | VE | PE) ++#define ENET0_MDC_GPIO (FUNC(3) | PORTF(4, 0) | SE | VE | PE) ++ ++/* ++ * Bank 5, GPIO pins 160 ... 191 ++ * Note: These pins are disabled instead of being GPIOs ++ */ ++#define EMI_DDR_OPEN (FUNC(0) | PORTF(5, 26) | BK) ++#define EMI_DDR_OPEN_OFF (FUNC(3) | PORTF(5, 26) | BK) ++#define EMI_DSQ1 (FUNC(0) | PORTF(5, 23) | BK) ++#define EMI_DSQ1_OFF (FUNC(3) | PORTF(5, 23) | BK) ++#define EMI_DSQ0 (FUNC(0) | PORTF(5, 22) | BK) ++#define EMI_DSQ0_OFF (FUNC(3) | PORTF(5, 22) | BK) ++#define EMI_CLK (FUNC(0) | PORTF(5, 21) | BK) ++#define EMI_CLK_OFF (FUNC(3) | PORTF(5, 21) | BK) ++#define EMI_DDR_OPEN_FB (FUNC(0) | PORTF(5, 20) | BK) ++#define EMI_DDR_OPEN_FB_OFF (FUNC(3) | PORTF(5, 20) | BK) ++#define EMI_DQM1 (FUNC(0) | PORTF(5, 19) | BK) ++#define EMI_DQM1_OFF (FUNC(3) | PORTF(5, 19) | BK) ++#define EMI_ODT1 (FUNC(0) | PORTF(5, 18) | BK) ++#define EMI_ODT1_OFF (FUNC(3) | PORTF(5, 18) | BK) ++#define EMI_DQM0 (FUNC(0) | PORTF(5, 17) | BK) ++#define EMI_DQM0_OFF (FUNC(3) | PORTF(5, 17) | BK) ++#define EMI_ODT0 (FUNC(0) | PORTF(5, 16) | BK) ++#define EMI_ODT0_OFF (FUNC(3) | PORTF(5, 16) | BK) ++#define EMI_DATA15 (FUNC(0) | PORTF(5, 15) | BK) ++#define EMI_DATA15_OFF (FUNC(3) | PORTF(5, 15) | BK) ++#define EMI_DATA14 (FUNC(0) | PORTF(5, 14) | BK) ++#define EMI_DATA14_OFF (FUNC(3) | PORTF(5, 14) | BK) ++#define EMI_DATA13 (FUNC(0) | PORTF(5, 13) | BK) ++#define EMI_DATA13_OFF (FUNC(3) | PORTF(5, 13) | BK) ++#define EMI_DATA12 (FUNC(0) | PORTF(5, 12) | BK) ++#define EMI_DATA12_OFF (FUNC(3) | PORTF(5, 12) | BK) ++#define EMI_DATA11 (FUNC(0) | PORTF(5, 11) | BK) ++#define EMI_DATA10_OFF (FUNC(3) | PORTF(5, 10) | BK) ++#define EMI_DATA10 (FUNC(0) | PORTF(5, 10) | BK) ++#define EMI_DATA10_OFF (FUNC(3) | PORTF(5, 10) | BK) ++#define EMI_DATA9 (FUNC(0) | PORTF(5, 9) | BK) ++#define EMI_DATA9_OFF (FUNC(3) | PORTF(5, 9) | BK) ++#define EMI_DATA8 (FUNC(0) | PORTF(5, 8) | BK) ++#define EMI_DATA8_OFF (FUNC(3) | PORTF(5, 8) | BK) ++#define EMI_DATA7 (FUNC(0) | PORTF(5, 7) | BK) ++#define EMI_DATA7_OFF (FUNC(3) | PORTF(5, 7) | BK) ++#define EMI_DATA6 (FUNC(0) | PORTF(5, 6) | BK) ++#define EMI_DATA6_OFF (FUNC(3) | PORTF(5, 6) | BK) ++#define EMI_DATA5 (FUNC(0) | PORTF(5, 5) | BK) ++#define EMI_DATA5_OFF (FUNC(3) | PORTF(5, 5) | BK) ++#define EMI_DATA4 (FUNC(0) | PORTF(5, 4) | BK) ++#define EMI_DATA4_OFF (FUNC(3) | PORTF(5, 4) | BK) ++#define EMI_DATA3 (FUNC(0) | PORTF(5, 3) | BK) ++#define EMI_DATA3_OFF (FUNC(3) | PORTF(5, 3) | BK) ++#define EMI_DATA2 (FUNC(0) | PORTF(5, 2) | BK) ++#define EMI_DATA2_OFF (FUNC(3) | PORTF(5, 2) | BK) ++#define EMI_DATA1 (FUNC(0) | PORTF(5, 1) | BK) ++#define EMI_DATA1_OFF (FUNC(3) | PORTF(5, 1) | BK) ++#define EMI_DATA0 (FUNC(0) | PORTF(5, 0) | BK) ++#define EMI_DATA0_OFF (FUNC(3) | PORTF(5, 0) | BK) ++ ++/* ++ * Bank 6, GPIO pins 192 ... 223 ++ * Note: This pins are disabled instead of being GPIOs ++ */ ++#define EMI_CKE (FUNC(0) | PORTF(6, 24) | BK) ++#define EMI_CKE_OFF (FUNC(3) | PORTF(6, 24) | BK) ++#define EMI_CE1N (FUNC(0) | PORTF(6, 23) | BK) ++#define EMI_CE1N_OFF (FUNC(3) | PORTF(6, 23) | BK) ++#define EMI_CE0N (FUNC(0) | PORTF(6, 22) | BK) ++#define EMI_CE0N_OFF (FUNC(3) | PORTF(6, 22) | BK) ++#define EMI_WEN (FUNC(0) | PORTF(6, 21) | BK) ++#define EMI_WEN_OFF (FUNC(3) | PORTF(6, 21) | BK) ++#define EMI_RASN (FUNC(0) | PORTF(6, 20) | BK) ++#define EMI_RASN_OFF (FUNC(3) | PORTF(6, 20) | BK) ++#define EMI_CASN (FUNC(0) | PORTF(6, 19) | BK) ++#define EMI_CASN_OFF (FUNC(3) | PORTF(6, 19) | BK) ++#define EMI_BA2 (FUNC(0) | PORTF(6, 18) | BK) ++#define EMI_BA2_OFF (FUNC(3) | PORTF(6, 18) | BK) ++#define EMI_BA1 (FUNC(0) | PORTF(6, 17) | BK) ++#define EMI_BA1_OFF (FUNC(3) | PORTF(6, 17) | BK) ++#define EMI_BA0 (FUNC(0) | PORTF(6, 16) | BK) ++#define EMI_BA0_OFF (FUNC(3) | PORTF(6, 16) | BK) ++#define EMI_A14 (FUNC(0) | PORTF(6, 14) | BK) ++#define EMI_A14_OFF (FUNC(3) | PORTF(6, 14) | BK) ++#define EMI_A13 (FUNC(0) | PORTF(6, 13) | BK) ++#define EMI_A13_OFF (FUNC(3) | PORTF(6, 13) | BK) ++#define EMI_A12 (FUNC(0) | PORTF(6, 12) | BK) ++#define EMI_A12_OFF (FUNC(3) | PORTF(6, 12) | BK) ++#define EMI_A11 (FUNC(0) | PORTF(6, 11) | BK) ++#define EMI_A11_OFF (FUNC(3) | PORTF(6, 11) | BK) ++#define EMI_A10 (FUNC(0) | PORTF(6, 10) | BK) ++#define EMI_A10_OFF (FUNC(3) | PORTF(6, 10) | BK) ++#define EMI_A9 (FUNC(0) | PORTF(6, 9) | BK) ++#define EMI_A9_OFF (FUNC(3) | PORTF(6, 9) | BK) ++#define EMI_A8 (FUNC(0) | PORTF(6, 8) | BK) ++#define EMI_A8_OFF (FUNC(3) | PORTF(6, 8) | BK) ++#define EMI_A7 (FUNC(0) | PORTF(6, 7) | BK) ++#define EMI_A7_OFF (FUNC(3) | PORTF(6, 7) | BK) ++#define EMI_A6 (FUNC(0) | PORTF(6, 6) | BK) ++#define EMI_A6_OFF (FUNC(3) | PORTF(6, 6) | BK) ++#define EMI_A5 (FUNC(0) | PORTF(6, 5) | BK) ++#define EMI_A5_OFF (FUNC(3) | PORTF(6, 5) | BK) ++#define EMI_A4 (FUNC(0) | PORTF(6, 4) | BK) ++#define EMI_A4_OFF (FUNC(3) | PORTF(6, 4) | BK) ++#define EMI_A3 (FUNC(0) | PORTF(6, 3) | BK) ++#define EMI_A3_OFF (FUNC(3) | PORTF(6, 3) | BK) ++#define EMI_A2 (FUNC(0) | PORTF(6, 2) | BK) ++#define EMI_A2_OFF (FUNC(3) | PORTF(6, 2) | BK) ++#define EMI_A1 (FUNC(0) | PORTF(6, 1) | BK) ++#define EMI_A1_OFF (FUNC(3) | PORTF(6, 1) | BK) ++#define EMI_A0 (FUNC(0) | PORTF(6, 0) | BK) ++#define EMI_A0_OFF (FUNC(3) | PORTF(6, 0) | BK) ++ ++#endif /* __MACH_IOMUX_IMX28_H */ +Index: barebox-2010.10.0/arch/arm/mach-stm/iomux-imx28.c +=================================================================== +--- /dev/null ++++ barebox-2010.10.0/arch/arm/mach-stm/iomux-imx28.c +@@ -0,0 +1,172 @@ ++/* ++ * Copyright (C) 2010 Juergen Beisert, Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++/* NOTE: this file is just for reference. Can be removed when this is forwarded to mainline */ ++ ++#include <common.h> ++#include <init.h> ++#include <gpio.h> ++#include <errno.h> ++#include <asm/io.h> ++#include <mach/imx-regs.h> ++ ++#define HW_PINCTRL_CTRL 0x000 ++#define HW_PINCTRL_MUXSEL0 0x100 ++#define HW_PINCTRL_DRIVE0 0x300 ++#define HW_PINCTRL_PULL0 0x600 ++#define HW_PINCTRL_DOUT0 0x700 ++#define HW_PINCTRL_DIN0 0x900 ++#define HW_PINCTRL_DOE0 0xb00 ++ ++#define MAX_GPIO_NO 159 ++ ++static unsigned calc_mux_reg(unsigned no) ++{ ++ /* each register controls 16 pads */ ++ return ((no >> 4) << 4) + HW_PINCTRL_MUXSEL0; ++} ++ ++static unsigned calc_strength_reg(unsigned no) ++{ ++ /* each register controls 8 pads */ ++ return ((no >> 3) << 4) + HW_PINCTRL_DRIVE0; ++} ++ ++static unsigned calc_pullup_reg(unsigned no) ++{ ++ /* each register controls 32 pads */ ++ return ((no >> 5) << 4) + HW_PINCTRL_PULL0; ++} ++ ++static unsigned calc_output_enable_reg(unsigned no) ++{ ++ /* each register controls 32 pads */ ++ return ((no >> 5) << 4) + HW_PINCTRL_DOE0; ++} ++ ++static unsigned calc_output_reg(unsigned no) ++{ ++ /* each register controls 32 pads */ ++ return ((no >> 5) << 4) + HW_PINCTRL_DOUT0; ++} ++ ++static unsigned calc_input_reg(unsigned no) ++{ ++ /* each register controls 32 pads */ ++ return ((no >> 5) << 4) + HW_PINCTRL_DIN0; ++} ++ ++/** ++ * @param[in] m One of the defines from iomux-mx23.h to configure *one* pin ++ */ ++void imx_gpio_mode(uint32_t m) ++{ ++ uint32_t reg; ++ unsigned gpio_pin, reg_offset; ++ ++ gpio_pin = GET_GPIO_NO(m); ++ ++ /* configure the pad to its function (always) */ ++ reg_offset = calc_mux_reg(gpio_pin); ++ reg = readl(IMX_IOMUXC_BASE + reg_offset) & ~(0x3 << ((gpio_pin % 16) << 1)); ++ reg |= GET_FUNC(m) << ((gpio_pin % 16) << 1); ++ writel(reg, IMX_IOMUXC_BASE + reg_offset); ++ ++ /* some pins are disabled when configured for GPIO */ ++ if ((gpio_pin > MAX_GPIO_NO) && (GET_FUNC(m) == IS_GPIO)) { ++ printf("Cannot configure pad %d to GPIO\n", gpio_pin); ++ return; ++ } ++ ++ if (SE_PRESENT(m)) { ++ reg_offset = calc_strength_reg(gpio_pin); ++ reg = readl(IMX_IOMUXC_BASE + reg_offset) & ~(0x3 << ((gpio_pin % 8) << 2)); ++ reg |= GET_STRENGTH(m) << ((gpio_pin % 8) << 2); ++ writel(reg, IMX_IOMUXC_BASE + reg_offset); ++ } ++ ++ if (VE_PRESENT(m)) { ++ reg_offset = calc_strength_reg(gpio_pin); ++ if (GET_VOLTAGE(m) == 1) ++ writel(0x1 << (((gpio_pin % 8) << 2) + 2), IMX_IOMUXC_BASE + reg_offset + 4); ++ else ++ writel(0x1 << (((gpio_pin % 8) << 2) + 2), IMX_IOMUXC_BASE + reg_offset + 8); ++ } ++ ++ if (PE_PRESENT(m)) { ++ reg_offset = calc_pullup_reg(gpio_pin); ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + (GET_PULLUP(m) == 1 ? 4 : 8)); ++ } ++ ++#if 0 ++ /* TODO Do we need a separate bit keeper handling? */ ++ if (BK_PRESENT(m)) { ++ reg_offset = calc_pullup_reg(gpio_pin); ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + (GET_BITKEEPER(m) == 1 ? 4 : 8)); ++ } ++#endif ++ if (GET_FUNC(m) == IS_GPIO) { ++ if (GET_GPIODIR(m) == 1) { ++ /* first set the output value */ ++ reg_offset = calc_output_reg(gpio_pin); ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + (GET_GPIOVAL(m) == 1 ? 4 : 8)); ++ /* then the direction */ ++ reg_offset = calc_output_enable_reg(gpio_pin); ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + 4); ++ } else { ++ writel(0x1 << (gpio_pin % 32), IMX_IOMUXC_BASE + reg_offset + 8); ++ } ++ } ++} ++ ++void gpio_set_value(unsigned gpio, int val) ++{ ++ unsigned reg_offset; ++ ++ reg_offset = calc_output_reg(gpio); ++ pr_debug("%u: Accessing %X+%X with value %X\n", gpio, IMX_IOMUXC_BASE, ++ reg_offset, 0x1 << (gpio % 32)); ++ writel(0x1 << (gpio % 32), IMX_IOMUXC_BASE + reg_offset + (val != 0 ? 4 : 8)); ++} ++ ++int gpio_direction_input(unsigned gpio) ++{ ++ pr_err("Not yet supported\n"); ++ return -EINVAL; ++} ++ ++int gpio_direction_output(unsigned gpio, int val) ++{ ++ pr_err("Not yet supported\n"); ++ return -EINVAL; ++} ++ ++int gpio_get_value(unsigned gpio) ++{ ++ uint32_t reg; ++ unsigned reg_offset; ++ ++ reg_offset = calc_input_reg(gpio); ++ reg = readl(IMX_IOMUXC_BASE + reg_offset); ++ pr_debug("%u: Accessing %X+%X with value %X->%X\n", gpio, IMX_IOMUXC_BASE, ++ reg_offset, 0x1 << (gpio % 32), reg & (0x1 << (gpio % 32))); ++ if (reg & (0x1 << (gpio % 32))) ++ return 1; ++ return 0; ++} +Index: barebox-2010.10.0/arch/arm/mach-stm/clocksource-imx28.c +=================================================================== +--- /dev/null ++++ barebox-2010.10.0/arch/arm/mach-stm/clocksource-imx28.c +@@ -0,0 +1,84 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#include <common.h> ++#include <init.h> ++#include <clock.h> ++#include <notifier.h> ++#include <mach/imx-regs.h> ++#include <mach/clock.h> ++#include <asm/io.h> ++ ++#define TIMROTCTRL 0x00 ++ ++#define TIMCTRL1 0x60 ++#define TIMCTRL1_SET 0x64 ++#define TIMCTRL1_CLR 0x68 ++#define TIMCTRL1_TOG 0x6c ++# define TIMCTRL_RELOAD (1 << 6) ++# define TIMCTRL_UPDATE (1 << 7) ++# define TIMCTRL_PRESCALE(x) ((x & 0x3) << 4) ++# define TIMCTRL_SELECT(x) (x & 0xf) ++#define TIMCOUNT1 0x70 ++#define TIMFIX1 0x80 ++ ++static const unsigned long timer_base = IMX_TIM1_BASE; ++ ++/* we are using the 32 kHz reference */ ++#define CLOCK_TICK_RATE (32000) ++ ++static uint64_t imx23_clocksource_read(void) ++{ ++ return ~(readl(timer_base + TIMCOUNT1)); ++} ++ ++static struct clocksource cs = { ++ .read = imx23_clocksource_read, ++ .mask = 0xffffffff, ++ .shift = 10, ++}; ++ ++static int imx23_clocksource_clock_change(struct notifier_block *nb, unsigned long event, void *data) ++{ ++ cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cs.shift); ++ return 0; ++} ++ ++static struct notifier_block imx23_clock_notifier = { ++ .notifier_call = imx23_clocksource_clock_change, ++}; ++ ++static int clocksource_init(void) ++{ ++ /* enable the whole timer block */ ++ writel(0x3e000000, timer_base + TIMROTCTRL); ++ /* setup general purpose timer 1 */ ++ writel(0x00000000, timer_base + TIMCTRL1); ++ writel(TIMCTRL_UPDATE, timer_base + TIMCTRL1); ++ writel(0xffffffff, timer_base + TIMFIX1); ++ ++ writel(TIMCTRL_UPDATE | TIMCTRL_RELOAD | TIMCTRL_PRESCALE(0) | TIMCTRL_SELECT(0xb), timer_base + TIMCTRL1); ++ cs.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cs.shift); ++ init_clock(&cs); ++ ++ clock_register_client(&imx23_clock_notifier); ++ return 0; ++} ++ ++core_initcall(clocksource_init); +Index: barebox-2010.10.0/arch/arm/mach-imx/include/mach/generic.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-imx/include/mach/generic.h ++++ barebox-2010.10.0/arch/arm/mach-imx/include/mach/generic.h +@@ -51,3 +51,5 @@ u64 imx_uid(void); + #define cpu_is_mx51() (0) + #endif + ++#define cpu_is_mx23() (0) ++#define cpu_is_mx28() (0) +Index: barebox-2010.10.0/arch/arm/mach-stm/iomux-imx23.c +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/iomux-imx23.c ++++ barebox-2010.10.0/arch/arm/mach-stm/iomux-imx23.c +@@ -26,13 +26,24 @@ + + #define HW_PINCTRL_CTRL 0x000 + #define HW_PINCTRL_MUXSEL0 0x100 ++ ++#ifdef CONFIG_ARCH_IMX23 + #define HW_PINCTRL_DRIVE0 0x200 + #define HW_PINCTRL_PULL0 0x400 + #define HW_PINCTRL_DOUT0 0x500 + #define HW_PINCTRL_DIN0 0x600 + #define HW_PINCTRL_DOE0 0x700 +- + #define MAX_GPIO_NO 95 ++#endif ++ ++#ifdef CONFIG_ARCH_IMX28 ++#define HW_PINCTRL_DRIVE0 0x300 ++#define HW_PINCTRL_PULL0 0x600 ++#define HW_PINCTRL_DOUT0 0x700 ++#define HW_PINCTRL_DIN0 0x900 ++#define HW_PINCTRL_DOE0 0xb00 ++#define MAX_GPIO_NO 159 ++#endif + + static unsigned calc_mux_reg(unsigned no) + { diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/add_lcdclock_to_iMX23.diff b/configs/platform-chumby/patches/barebox-2010.11.0/add_lcdclock_to_iMX23.diff new file mode 100644 index 0000000..7d83f24 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/add_lcdclock_to_iMX23.diff @@ -0,0 +1,156 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: i.MX23: Add pixel clock calculation routine for framebuffer support + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + arch/arm/mach-stm/include/mach/clock.h | 2 + arch/arm/mach-stm/speed-imx23.c | 97 ++++++++++++++++++++++++++++++++- + 2 files changed, 98 insertions(+), 1 deletion(-) + +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/include/mach/clock.h ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock.h +@@ -29,6 +29,8 @@ unsigned imx_get_xclk(void); + unsigned imx_get_sspclk(unsigned); + unsigned imx_set_sspclk(unsigned, unsigned, int); + unsigned imx_set_ioclk(unsigned); ++unsigned imx_set_lcdifclk(unsigned); ++unsigned imx_get_lcdifclk(void); + + #endif /* ASM_ARCH_CLOCK_IMX23_H */ + +Index: barebox-2010.10.0/arch/arm/mach-stm/speed-imx23.c +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/speed-imx23.c ++++ barebox-2010.10.0/arch/arm/mach-stm/speed-imx23.c +@@ -39,7 +39,11 @@ + #define HW_CLKCTRL_HBUS 0x30 + #define HW_CLKCTRL_XBUS 0x40 + #define HW_CLKCTRL_XTAL 0x050 +-#define HW_CLKCTRL_PIX 0x060 ++#define HW_CLKCTRL_DIS_LCDIF 0x060 ++# define CLKCTRL_DIS_LCDIF_GATE (1 << 31) ++# define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) ++# define SET_DIS_LCDIF_DIV(x) ((x) & 0xfff) ++# define GET_DIS_LCDIF_DIV(x) ((x) & 0xfff) + /* note: no set/clear register! */ + #define HW_CLKCTRL_SSP 0x070 + /* note: no set/clear register! */ +@@ -66,6 +70,7 @@ + # define SET_IOFRAC(x) (((x) & 0x3f) << 24) + # define CLKCTRL_FRAC_CLKGATEPIX (1 << 23) + # define GET_PIXFRAC(x) (((x) >> 16) & 0x3f) ++# define SET_PIXFRAC(x) (((x) & 0x3f) << 16) + # define CLKCTRL_FRAC_CLKGATEEMI (1 << 15) + # define GET_EMIFRAC(x) (((x) >> 8) & 0x3f) + # define CLKCTRL_FRAC_CLKGATECPU (1 << 7) +@@ -77,6 +82,7 @@ + # define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) + # define CLKCTRL_CLKSEQ_BYPASS_SSP (1 << 5) + # define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) ++# define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 1) + #define HW_CLKCTRL_RESET 0x120 + #define HW_CLKCTRL_STATUS 0x130 + #define HW_CLKCTRL_VERSION 0x140 +@@ -268,6 +274,94 @@ unsigned imx_set_sspclk(unsigned index, + return imx_get_sspclk(index); + } + ++unsigned imx_get_lcdifclk(void) ++{ ++ unsigned rate = imx_get_mpllclk() * 18U; ++ unsigned div; ++ ++ div = GET_PIXFRAC(readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC)); ++ if (div != 0U) { ++ rate /= div; ++ div = GET_DIS_LCDIF_DIV(readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF)); ++ if (div != 0U) ++ rate /= div; ++ else ++ pr_debug("LCDIF clock has divisor 0!\n"); ++ } else ++ pr_debug("LCDIF clock has frac divisor 0!\n"); ++ ++ return rate; ++} ++ ++/** ++ * @param nc Pixel clock in [kHz] ++ * ++ * Calculate the best settings for the fractional and integer divider to match ++ * the requested pixel clock as close as possible. ++ * ++ * pixel clock = 480 MHz * 18 / frac_div / int_div ++ */ ++unsigned imx_set_lcdifclk(unsigned nc) ++{ ++ unsigned frac, best_frac = 0, div, best_div = 0, result; ++ int delta, best_delta = 0xffffff; ++ unsigned i, parent_rate = imx_get_mpllclk(); ++ uint32_t reg; ++ ++#define DIV(NOM, DEN) (((NOM) + (DEN) / 2) / (DEN)) ++#define SH_DIV(NOM, DEN, LSH) ((((NOM) / (DEN)) << (LSH)) + DIV(((NOM) % (DEN)) << (LSH), DEN)) ++#define ABS(x) (((x) < 0) ? (-(x)) : (x)) ++#define SHIFT 4 ++ ++ nc <<= SHIFT; ++ ++ for (frac = 18; frac <= 35; ++frac) { ++ for (div = 1; div <= 255; ++div) { ++ result = DIV(parent_rate * SH_DIV(18U, frac, SHIFT), div); ++ delta = nc - result; ++ if (ABS(delta) < ABS(best_delta)) { ++ best_delta = delta; ++ best_frac = frac; ++ best_div = div; ++ } ++ } ++ } ++ ++ if (best_delta == 0xffffff) { ++ pr_debug("Unable to match the pixelclock\n"); ++ return 0; ++ } ++ ++ pr_debug("Programming PFD=%u,DIV=%u ref_pix=%u MHz PIXCLK=%u MHz\n", ++ best_frac, best_div, 480 * 18 / best_frac, ++ 480 * 18 / best_frac / best_div); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_FRAC) & ~0x003f0000; ++ reg |= SET_PIXFRAC(best_frac); ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_FRAC); ++ writel(reg & ~CLKCTRL_FRAC_CLKGATEPIX, IMX_CCM_BASE + HW_CLKCTRL_FRAC); ++ ++ reg = readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF) & ~0x1fff; ++ reg &= ~CLKCTRL_DIS_LCDIF_GATE; ++ reg |= SET_DIS_LCDIF_DIV(best_div); ++ writel(reg, IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF); ++ ++ /* Wait for divider update */ ++ for (i = 0; i < 10000; i++) { ++ if (!(readl(IMX_CCM_BASE + HW_CLKCTRL_DIS_LCDIF) & CLKCTRL_DIS_LCDIF_BUSY)) ++ break; ++ } ++ ++ if (i >= 10000) { ++ pr_debug("Setting LCD clock failed\n"); ++ return 0; ++ } ++ ++ writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, IMX_CCM_BASE + HW_CLKCTRL_CLKSEQ + 8); ++ ++ return imx_get_lcdifclk(); ++} ++ + void imx_dump_clocks(void) + { + printf("mpll: %10u kHz\n", imx_get_mpllclk()); +@@ -277,4 +371,5 @@ void imx_dump_clocks(void) + printf("hclk: %10u kHz\n", imx_get_hclk()); + printf("xclk: %10u kHz\n", imx_get_xclk()); + printf("ssp: %10u kHz\n", imx_get_sspclk(0)); ++ printf("lcdif: %10u kHz\n", imx_get_lcdifclk()); + } diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/add_mci_doc.diff b/configs/platform-chumby/patches/barebox-2010.11.0/add_mci_doc.diff new file mode 100644 index 0000000..cea2229 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/add_mci_doc.diff @@ -0,0 +1,160 @@ +From: Juergen Beisert <juergen@kreuzholzen.de> +Subject: [PATCH] MCI: Add some doc how to handle MCI cards + +Signed-off-by: Juergen Beisert <juergen@kreuzholzen.de> + +--- + Documentation/developers_manual.dox | 1 + Documentation/users_manual.dox | 1 + drivers/mci/mci-core.c | 117 ++++++++++++++++++++++++++++++++++++ + 3 files changed, 119 insertions(+) + +Index: barebox-2010.11.0/Documentation/developers_manual.dox +=================================================================== +--- barebox-2010.11.0.orig/Documentation/developers_manual.dox ++++ barebox-2010.11.0/Documentation/developers_manual.dox +@@ -18,6 +18,7 @@ This part of the documentation is intend + @li @subpage how_mount_works + @li @subpage boot_preparation + @li @subpage barebox_simul ++@li @subpage mci_for_developers + @li @subpage io_access_functions + @li @subpage mcfv4e_MCDlib + +Index: barebox-2010.11.0/Documentation/users_manual.dox +=================================================================== +--- barebox-2010.11.0.orig/Documentation/users_manual.dox ++++ barebox-2010.11.0/Documentation/users_manual.dox +@@ -8,6 +8,7 @@ you find a lot of nice tricks on these p + @li @subpage first_steps + @li @subpage command_reference + @li @subpage gpio_for_users ++@li @subpage mci_for_users + + \todo Rework the following sections + @li @subpage shell_notes +Index: barebox-2010.11.0/drivers/mci/mci-core.c +=================================================================== +--- barebox-2010.11.0.orig/drivers/mci/mci-core.c ++++ barebox-2010.11.0/drivers/mci/mci-core.c +@@ -1358,3 +1358,120 @@ int mci_register(struct mci_host *host) + + return register_device(mci_dev); + } ++ ++/** ++ * @page mci_for_developers MCI information for developers ++ * ++ * Pay attention ++ * - Provide a MCI clock to let the card do its reset ++ * - Provide power supply to the socket. There is no callback in the generic ++ * driver to do so ++ * ++ * If your MCI host hardware is slow, you should avoid the card probing at system ++ * startup. Do it on demand only in this case. This can be achieved by disabling ++ * the MCI_STARTUP menu entry. ++ */ ++ ++/** ++@page mci_for_users MCI cards for users ++ ++MCI cards are handled like regular disks in @b barebox. When a card is detected, ++access gets added to the system as @b /dev/disk0. If @b barebox detects a partition ++table in the first sector, it also adds these partitions as @b /dev/disk0.0, ++@b dev/disk0.1 and so on. ++ ++All these disk devices can be used with the command @b md, @b mw, @b cp, ++@b bootm in a regular manner. ++ ++@verbatim ++barebox:/ devinfo ++devices: ++|----s3c24x0_serial0 ++|----cs0 ++|----ramfs0 ++|----devfs0 ++|----mem0 (defaultenv) ++|----mem1 (mem) ++|----s3c_mci0 ++|----disk0 (disk0, disk0.0) ++|----s3cfb0 ++|----framebuffer0 (fb0) ++|----s3c24x0_nand0 ++|----nand0 (nand0, nand_oob0, self_raw, env_raw, nand0.uboot, nand0.ubootenv, nand0.kernel, nand0.root) ++|----mem2 (ram0) ++|----cs89000 ++|----eth0 ++ ++drivers: ++s3c24x0_serial ++ ramfs ++ devfs ++ cs8900 ++s3c24x0_nand ++ disk ++framebuffer ++ s3cfb ++ s3c_mci ++ mem ++@endverbatim ++ ++The device in question is the @b mci0. Run the @b devinfo command again on this device. ++ ++@verbatim ++barebox:/ devinfo mci0 ++base : 0x00000000 ++size : 0x3d600000 ++driver: mci ++ ++ Card: ++ Attached is an SD Card (Version: 2.0) ++ Capacity: 982 MiB ++ CID: 1C535653-44432020-10000000-1800849F ++ CSD: 005E0032-5F5983D5-EDB7FF9F-964000C1 ++ Max. transfer speed: 25000000 Hz ++ Manufacturer ID: 1C ++ OEM/Application ID: 5356 ++ Product name: 'SDC ' ++ Product revision: 1.0 ++ Serial no: 24 ++ Manufacturing date: 4.2008 ++no parameters available ++@endverbatim ++ ++In this case probing the MCI card has successfully happen at system startup. Probing ++at this early point of time can be necessary for systems that depends on data from ++this kind of storage (for example if the persistant environment is stored on the ++MCI card). ++ ++As probing an MCI card may take some seconds, it could be useful to do this ++on demand only (if not otherwise required). In this case the @b devinfo ++shows different information about the MCI card prior probing: ++ ++@verbatim ++barebox:/ devinfo mci0 ++base : 0x00000000 ++size : 0x00000000 ++driver: mci ++ ++ Card: ++ Not probed yet. ++ ++parameters ++ probe = 0 ++@endverbatim ++ ++@note The MCI card should already be inserted when powering the system, as ++@b barebox does not support runtime power supply switching. ++ ++To do the MCI card probing right now, just enter: ++@verbatim ++barebox:/ mci0.probe=1 ++@endverbatim ++ ++@note @b barebox currently cannot really cope with hot plug (its a bootloader only, ++not an operating system...). So, unplugging the already probed card and replacing ++it by another one and also probing this new card may crash your system (and might ++also destroy the MCI card, as unplugging and plugging happens while the socket is ++"hot"). ++ ++*/ diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/fix_baudrate_setting.diff b/configs/platform-chumby/patches/barebox-2010.11.0/fix_baudrate_setting.diff new file mode 100644 index 0000000..f9bc11b --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/fix_baudrate_setting.diff @@ -0,0 +1,33 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Fix baudrate setting + +The menu entry to set CONFIG_BAUDRATE makes no sense, if its content is not +used. This patch makes barebox using the setting again. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + common/console.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +Index: barebox-2010.10.0/common/console.c +=================================================================== +--- barebox-2010.10.0.orig/common/console.c ++++ barebox-2010.10.0/common/console.c +@@ -34,6 +34,7 @@ + #include <clock.h> + #include <kfifo.h> + #include <module.h> ++#include <linux/stringify.h> + #include <linux/list.h> + + LIST_HEAD(console_list); +@@ -140,7 +141,7 @@ int console_register(struct console_devi + + if (newcdev->setbrg) { + dev_add_param(dev, "baudrate", console_baudrate_set, NULL, 0); +- dev_set_param(dev, "baudrate", "115200"); ++ dev_set_param(dev, "baudrate", __stringify(CONFIG_BAUDRATE)); + } + + dev_add_param(dev, "active", console_std_set, NULL, 0); diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/fix_lcd_flickering.diff b/configs/platform-chumby/patches/barebox-2010.11.0/fix_lcd_flickering.diff new file mode 100644 index 0000000..4cbde1b --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/fix_lcd_flickering.diff @@ -0,0 +1,39 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Avoid image and backlight flickering while startup + +It seems the display needs a few more frame periods to sync into the data +stream. So, we must enable the video signals earlier in time, and give it more +syncs and time by writing the image into the framebuffer after enabling the +video signals and prior switching on the backlight. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/boards/chumby_falconwing/env/bin/init | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +Index: barebox-2010.10.0/arch/arm/boards/chumby_falconwing/env/bin/init +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/boards/chumby_falconwing/env/bin/init ++++ barebox-2010.10.0/arch/arm/boards/chumby_falconwing/env/bin/init +@@ -7,15 +7,16 @@ export PATH + + # enable the display on demand + if [ -e /dev/fb0 ]; then ++ # set its RESET# pin to high (activate the glass) ++ gpio_set_value 50 1 + # setup the mode to be used + framebuffer0.mode=NMA35 ++ # enable the video signals ++ framebuffer0.enable=1 ++ + if [ -e "$splash_image" ]; then + bmp -f /dev/fb0 $splash_image + fi +- # set its RESET# pin to high (activate the glass) +- gpio_set_value 50 1 +- # enable the video signals +- framebuffer0.enable=1 + # activate the backlight (low is full brightness, high is off) + gpio_set_value 60 1 + fi diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/fix_machine_type.diff b/configs/platform-chumby/patches/barebox-2010.11.0/fix_machine_type.diff new file mode 100644 index 0000000..446d4bf --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/fix_machine_type.diff @@ -0,0 +1,25 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Fix machine type, als long the chumby kernel misuses the STMP378X one + +TODO: Chumby Industries should register theirs own machine type number for the +'ChumbyOne'. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/boards/chumby_falconwing/env/bin/boot | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/bin/boot +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/env/bin/boot ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/bin/boot +@@ -27,7 +27,7 @@ elif [ x$rootfs_loc = xinitrd ]; then + fi + + if [ x$kernelimage_type = xuimage ]; then +- bootm /dev/$kernel_part ++ bootm -a 0x000006c5 /dev/$kernel_part + elif [ x$kernelimage_type = xzimage ]; then + bootz /dev/$kernel_part + else diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/fix_sdram_id.diff b/configs/platform-chumby/patches/barebox-2010.11.0/fix_sdram_id.diff new file mode 100644 index 0000000..f8142f0 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/fix_sdram_id.diff @@ -0,0 +1,21 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: i.MX23/Chumby: Device ID handling was changed + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/boards/chumby_falconwing/falconwing.c | 1 + + 1 file changed, 1 insertion(+) + +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/falconwing.c +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/falconwing.c ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/falconwing.c +@@ -35,6 +35,7 @@ static struct memory_platform_data ram_p + }; + + static struct device_d sdram_dev = { ++ .id = -1, + .name = "mem", + .map_base = IMX_MEMORY_BASE, + .size = 64 * 1024 * 1024, diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/generalize_mci_driver.diff b/configs/platform-chumby/patches/barebox-2010.11.0/generalize_mci_driver.diff new file mode 100644 index 0000000..e9343d9 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/generalize_mci_driver.diff @@ -0,0 +1,263 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: STM378x: Adapt the MCI driver to support i.MX23 and i.MX28 + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + drivers/mci/Kconfig | 4 - + drivers/mci/stm378x.c | 141 +++++++++++++++++++++++++++++++++++++++++++------- + 2 files changed, 125 insertions(+), 20 deletions(-) + +Index: barebox-2010.10.0/drivers/mci/stm378x.c +=================================================================== +--- barebox-2010.10.0.orig/drivers/mci/stm378x.c ++++ barebox-2010.10.0/drivers/mci/stm378x.c +@@ -52,7 +52,7 @@ + # define SSP_CTRL0_SFTRST (1 << 31) + # define SSP_CTRL0_CLKGATE (1 << 30) + # define SSP_CTRL0_RUN (1 << 29) +-# define SSP_CTRL0_LOCK_CS (1 << 29) ++# define SSP_CTRL0_LOCK_CS (1 << 27) + # define SSP_CTRL0_READ (1 << 25) + # define SSP_CTRL0_IGNORE_CRC (1 << 26) + # define SSP_CTRL0_DATA_XFER (1 << 24) +@@ -61,37 +61,77 @@ + # define SSP_CTRL0_LONG_RESP (1 << 19) + # define SSP_CTRL0_GET_RESP (1 << 17) + # define SSP_CTRL0_ENABLE (1 << 16) ++#ifdef CONFIG_ARCH_IMX23 + # define SSP_CTRL0_XFER_COUNT(x) ((x) & 0xffff) ++#endif + + #define HW_SSP_CMD0 0x010 + # define SSP_CMD0_SLOW_CLK (1 << 22) + # define SSP_CMD0_CONT_CLK (1 << 21) + # define SSP_CMD0_APPEND_8CYC (1 << 20) ++#ifdef CONFIG_ARCH_IMX23 + # define SSP_CMD0_BLOCK_SIZE(x) (((x) & 0xf) << 16) + # define SSP_CMD0_BLOCK_COUNT(x) (((x) & 0xff) << 8) ++#endif + # define SSP_CMD0_CMD(x) ((x) & 0xff) + + #define HW_SSP_CMD1 0x020 +-#define HW_SSP_COMPREF 0x030 +-#define HW_SSP_COMPMASK 0x040 +-#define HW_SSP_TIMING 0x050 ++ ++#ifdef CONFIG_ARCH_IMX23 ++# define HW_SSP_COMPREF 0x030 ++# define HW_SSP_COMPMASK 0x040 ++# define HW_SSP_TIMING 0x050 ++# define HW_SSP_CTRL1 0x060 ++# define HW_SSP_DATA 0x070 ++#endif ++#ifdef CONFIG_ARCH_IMX28 ++# define HW_SSP_XFER_COUNT 0x30 ++# define HW_SSP_BLOCK_SIZE 0x40 ++# define SSP_BLOCK_SIZE(x) ((x) & 0xf) ++# define SSP_BLOCK_COUNT(x) (((x) & 0xffffff) << 4) ++# define HW_SSP_COMPREF 0x050 ++# define HW_SSP_COMPMASK 0x060 ++# define HW_SSP_TIMING 0x070 ++# define HW_SSP_CTRL1 0x080 ++# define HW_SSP_DATA 0x090 ++#endif ++/* bit definition for register HW_SSP_TIMING */ + # define SSP_TIMING_TIMEOUT_MASK (0xffff0000) + # define SSP_TIMING_TIMEOUT(x) ((x) << 16) + # define SSP_TIMING_CLOCK_DIVIDE(x) (((x) & 0xff) << 8) + # define SSP_TIMING_CLOCK_RATE(x) ((x) & 0xff) + +-#define HW_SSP_CTRL1 0x060 ++/* bit definition for register HW_SSP_CTRL1 */ + # define SSP_CTRL1_POLARITY (1 << 9) + # define SSP_CTRL1_WORD_LENGTH(x) (((x) & 0xf) << 4) + # define SSP_CTRL1_SSP_MODE(x) ((x) & 0xf) + +-#define HW_SSP_DATA 0x070 +-#define HW_SSP_SDRESP0 0x080 +-#define HW_SSP_SDRESP1 0x090 +-#define HW_SSP_SDRESP2 0x0A0 +-#define HW_SSP_SDRESP3 0x0B0 ++#ifdef CONFIG_ARCH_IMX23 ++# define HW_SSP_SDRESP0 0x080 ++# define HW_SSP_SDRESP1 0x090 ++# define HW_SSP_SDRESP2 0x0A0 ++# define HW_SSP_SDRESP3 0x0B0 ++#endif ++#ifdef CONFIG_ARCH_IMX28 ++# define HW_SSP_SDRESP0 0x0A0 ++# define HW_SSP_SDRESP1 0x0B0 ++# define HW_SSP_SDRESP2 0x0C0 ++# define HW_SSP_SDRESP3 0x0D0 ++#endif ++ ++#ifdef CONFIG_ARCH_IMX28 ++# define HW_SSP_DDR_CTRL 0x0E0 ++# define HW_SSP_DLL_CTRL 0x0F0 ++#endif ++ ++#ifdef CONFIG_ARCH_IMX23 ++# define HW_SSP_STATUS 0x0C0 ++#endif ++#ifdef CONFIG_ARCH_IMX28 ++# define HW_SSP_STATUS 0x100 ++#endif + +-#define HW_SSP_STATUS 0x0C0 ++/* bit definition for register HW_SSP_STATUS */ + # define SSP_STATUS_PRESENT (1 << 31) + # define SSP_STATUS_SD_PRESENT (1 << 29) + # define SSP_STATUS_CARD_DETECT (1 << 28) +@@ -111,11 +151,23 @@ + SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR | \ + SSP_STATUS_RESP_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | SSP_STATUS_TIMEOUT) + +-#define HW_SSP_DEBUG 0x100 +-#define HW_SSP_VERSION 0x110 ++#ifdef CONFIG_ARCH_IMX28 ++# define HW_SSP_DLL_STS 0x110 ++#endif ++ ++#ifdef CONFIG_ARCH_IMX23 ++# define HW_SSP_DEBUG 0x100 ++# define HW_SSP_VERSION 0x110 ++#endif ++ ++#ifdef CONFIG_ARCH_IMX28 ++# define HW_SSP_DEBUG 0x120 ++# define HW_SSP_VERSION 0x130 ++#endif + + struct stm_mci_host { + unsigned clock; /* current clock speed in Hz ("0" if disabled) */ ++ unsigned index; + #ifdef CONFIG_MCI_INFO + unsigned f_min; + unsigned f_max; +@@ -124,6 +176,18 @@ struct stm_mci_host { + }; + + /** ++ * Get the SSP clock rate ++ * @param hw_dev Host interface device instance ++ * @return Unit's clock in [Hz] ++ */ ++static unsigned get_unit_clock(struct device_d *hw_dev) ++{ ++ struct stm_mci_host *host_data = GET_HOST_DATA(hw_dev); ++ ++ return imx_get_sspclk(host_data->index) * 1000; ++} ++ ++/** + * Get MCI cards response if defined for the type of command + * @param hw_dev Host interface device instance + * @param cmd Command description +@@ -417,6 +481,7 @@ static int stm_mci_adtc(struct device_d + xfer_cnt = log2blocksize = block_cnt = 0; + + /* setup command and transfer parameters */ ++#ifdef CONFIG_ARCH_IMX23 + writel(prepare_transfer_setup(cmd->resp_type, data != NULL ? data->flags : 0) | + SSP_CTRL0_BUS_WIDTH(host_data->bus_width) | + (xfer_cnt != 0 ? SSP_CTRL0_DATA_XFER : 0) | /* command plus data */ +@@ -430,6 +495,23 @@ static int stm_mci_adtc(struct device_d + SSP_CMD0_BLOCK_COUNT(block_cnt) | + (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ? SSP_CMD0_APPEND_8CYC : 0), + hw_dev->map_base + HW_SSP_CMD0); ++#endif ++#ifdef CONFIG_ARCH_IMX28 ++ writel(prepare_transfer_setup(cmd->resp_type, data != NULL ? data->flags : 0) | ++ SSP_CTRL0_BUS_WIDTH(host_data->bus_width) | ++ (xfer_cnt != 0 ? SSP_CTRL0_DATA_XFER : 0) | /* command plus data */ ++ SSP_CTRL0_ENABLE, ++ hw_dev->map_base + HW_SSP_CTRL0); ++ writel(xfer_cnt, hw_dev->map_base + HW_SSP_XFER_COUNT); ++ ++ /* prepare the command and the transfered data count */ ++ writel(SSP_CMD0_CMD(cmd->cmdidx) | ++ (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ? SSP_CMD0_APPEND_8CYC : 0), ++ hw_dev->map_base + HW_SSP_CMD0); ++ writel(SSP_BLOCK_SIZE(log2blocksize) | ++ SSP_BLOCK_COUNT(block_cnt), ++ hw_dev->map_base + HW_SSP_BLOCK_SIZE); ++#endif + + /* prepare command's arguments */ + writel(cmd->cmdarg, hw_dev->map_base + HW_SSP_CMD1); +@@ -481,7 +563,7 @@ static unsigned setup_clock_speed(struct + return 0; + } + +- ssp = imx_get_sspclk(0) * 1000; ++ ssp = get_unit_clock(hw_dev); + + for (div = 2; div < 255; div += 2) { + rate = (((ssp + (nc >> 1) ) / nc) + (div >> 1)) / div; +@@ -657,21 +739,44 @@ static int stm_mci_probe(struct device_d + host->voltages = pd->voltages; + host->host_caps = pd->caps; + ++#ifdef CONFIG_ARCH_IMX23 ++ host_data->index = 0; /* there is only one clock for all */ ++#endif ++#ifdef CONFIG_ARCH_IMX28 ++ /* one dedicated clock per unit */ ++ switch(hw_dev->map_base) { ++ case IMX_SSP0_BASE: ++ host_data->index = 0; ++ break; ++ case IMX_SSP1_BASE: ++ host_data->index = 1; ++ break; ++ case IMX_SSP2_BASE: ++ host_data->index = 2; ++ break; ++ case IMX_SSP3_BASE: ++ host_data->index = 3; ++ break; ++ default: ++ pr_debug("Unknown SSP unit at address %08X\n", hw_dev->map_base); ++ return 0; ++ } ++#endif + if (pd->f_min == 0) { +- host->f_min = imx_get_sspclk(0) / 254U / 256U * 1000U; ++ host->f_min = get_unit_clock(hw_dev) / 254U / 256U; + pr_debug("Min. frequency is %u Hz\n", host->f_min); + } else { + host->f_min = pd->f_min; + pr_debug("Min. frequency is %u Hz, could be %u Hz\n", +- host->f_min, imx_get_sspclk(0) / 254U / 256U * 1000U); ++ host->f_min, get_unit_clock(hw_dev) / 254U / 256U); + } + if (pd->f_max == 0) { +- host->f_max = imx_get_sspclk(0) / 2U / 1U * 1000U; ++ host->f_max = get_unit_clock(hw_dev) / 2U / 1U; + pr_debug("Max. frequency is %u Hz\n", host->f_max); + } else { + host->f_max = pd->f_max; + pr_debug("Max. frequency is %u Hz, could be %u Hz\n", +- host->f_max, imx_get_sspclk(0) / 2U / 1U * 1000U); ++ host->f_max, get_unit_clock(hw_dev) / 2U / 1U); + } + + #ifdef CONFIG_MCI_INFO +Index: barebox-2010.10.0/drivers/mci/Kconfig +=================================================================== +--- barebox-2010.10.0.orig/drivers/mci/Kconfig ++++ barebox-2010.10.0/drivers/mci/Kconfig +@@ -28,11 +28,11 @@ config MCI_INFO + comment "--- MCI host drivers ---" + + config MCI_STM378X +- bool "i.MX23" ++ bool "i.MX23/i.MX28" + depends on ARCH_STM + help + Enable this entry to add support to read and write SD cards on a +- i.MX23 based system. ++ i.MX23/i.MX28 based system. + + config MCI_S3C + bool "S3C" diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/generalize_serial_driver.diff b/configs/platform-chumby/patches/barebox-2010.11.0/generalize_serial_driver.diff new file mode 100644 index 0000000..68dc337 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/generalize_serial_driver.diff @@ -0,0 +1,41 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: STM378x: Adapt the serial driver to support i.MX23 and i.MX28 + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + drivers/serial/Kconfig | 2 +- + drivers/serial/stm-serial.c | 5 +++++ + 2 files changed, 6 insertions(+), 1 deletion(-) + +Index: drivers/serial/stm-serial.c +=================================================================== +--- drivers/serial/stm-serial.c.orig ++++ drivers/serial/stm-serial.c +@@ -138,9 +138,14 @@ static int stm_serial_init_port(struct c + * If the board specific file registers this console we should force + * the usage of the debug UART pins, to be able to let the user see + * the output, even if the board file forgets to configure these pins. ++ * This is valid for the i.MX23 only. Due to the pin voltage settings ++ * its impossible to do the same on the i.MX28. The platform has to ++ * ensure the correct pin settings. + */ ++#ifdef CONFIG_ARCH_IMX23 + imx_gpio_mode(PWM1_DUART_TX); + imx_gpio_mode(PWM0_DUART_RX); ++#endif + + /* Disable UART */ + writel(0, dev->map_base + UARTDBGCR); +Index: drivers/serial/Kconfig +=================================================================== +--- drivers/serial/Kconfig.orig ++++ drivers/serial/Kconfig +@@ -21,7 +21,7 @@ config DRIVER_SERIAL_IMX + config DRIVER_SERIAL_STM378X + depends on ARCH_STM + default y +- bool "i.MX23 serial driver" ++ bool "i.MX23/i.MX28 serial driver" + + config DRIVER_SERIAL_NETX + depends on ARCH_NETX diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/make_the_kernel_less_noisy.diff b/configs/platform-chumby/patches/barebox-2010.11.0/make_the_kernel_less_noisy.diff new file mode 100644 index 0000000..1ec99ee --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/make_the_kernel_less_noisy.diff @@ -0,0 +1,21 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: For faster booting, keep the kernel quiet + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/boards/chumby_falconwing/env/config | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/config +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/env/config ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/config +@@ -31,6 +31,6 @@ kernelimage_type=uimage + kernel_part=disk0.2 + + # base kernel parameter +-bootargs="console=ttyAM0,115200 debug ro lcd_panel=lms350 ssp1=mmc line=1 sysrq_always_enabled rotary=1" ++bootargs="console=ttyAM0,115200 quiet ro lcd_panel=lms350 ssp1=mmc line=1 sysrq_always_enabled rotary=1" + + autoboot_timeout=2 diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/remove_varsize_restriction_in_imx23_gpio.diff b/configs/platform-chumby/patches/barebox-2010.11.0/remove_varsize_restriction_in_imx23_gpio.diff new file mode 100644 index 0000000..8cb2a8c --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/remove_varsize_restriction_in_imx23_gpio.diff @@ -0,0 +1,74 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Remove variable size restrictions in i.MX23's gpio managing routines + +There is no really need for restricted variable types for the parameters. +Replace them by standard C types with the same behaviour. Only imx_gpio_mode() +need it, to ensure GPIO's bit settings. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/mach-stm/iomux-imx23.c | 21 ++++++++++++++------- + 1 file changed, 14 insertions(+), 7 deletions(-) + +Index: barebox-2010.10.0/arch/arm/mach-stm/iomux-imx23.c +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/iomux-imx23.c ++++ barebox-2010.10.0/arch/arm/mach-stm/iomux-imx23.c +@@ -31,42 +31,49 @@ + #define HW_PINCTRL_DIN0 0x600 + #define HW_PINCTRL_DOE0 0x700 + +-static uint32_t calc_mux_reg(uint32_t no) ++static unsigned calc_mux_reg(unsigned no) + { + /* each register controls 16 pads */ + return ((no >> 4) << 4) + HW_PINCTRL_MUXSEL0; + } + +-static uint32_t calc_strength_reg(uint32_t no) ++static unsigned calc_strength_reg(unsigned no) + { + /* each register controls 8 pads */ + return ((no >> 3) << 4) + HW_PINCTRL_DRIVE0; + } + +-static uint32_t calc_pullup_reg(uint32_t no) ++static unsigned calc_pullup_reg(unsigned no) + { + /* each register controls 32 pads */ + return ((no >> 5) << 4) + HW_PINCTRL_PULL0; + } + +-static uint32_t calc_output_enable_reg(uint32_t no) ++static unsigned calc_output_enable_reg(unsigned no) + { + /* each register controls 32 pads */ + return ((no >> 5) << 4) + HW_PINCTRL_DOE0; + } + +-static uint32_t calc_output_reg(uint32_t no) ++static unsigned calc_output_reg(unsigned no) + { + /* each register controls 32 pads */ + return ((no >> 5) << 4) + HW_PINCTRL_DOUT0; + } + ++static unsigned calc_input_reg(unsigned no) ++{ ++ /* each register controls 32 pads */ ++ return ((no >> 5) << 4) + HW_PINCTRL_DIN0; ++} ++ + /** + * @param[in] m One of the defines from iomux-mx23.h to configure *one* pin + */ +-void imx_gpio_mode(unsigned m) ++void imx_gpio_mode(uint32_t m) + { +- uint32_t reg_offset, gpio_pin, reg; ++ uint32_t reg; ++ unsigned gpio_pin, reg_offset; + + gpio_pin = GET_GPIO_NO(m); + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/reserve_video_memory_chumby.diff b/configs/platform-chumby/patches/barebox-2010.11.0/reserve_video_memory_chumby.diff new file mode 100644 index 0000000..bddb3ad --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/reserve_video_memory_chumby.diff @@ -0,0 +1,69 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Provide a reserved memory area for persistant splash screen + +Note: WIP + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/boards/chumby_falconwing/env/config | 2 +- + arch/arm/boards/chumby_falconwing/falconwing.c | 9 +++++++++ + arch/arm/mach-stm/Kconfig | 12 ++++++++++++ + 3 files changed, 22 insertions(+), 1 deletion(-) + +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/falconwing.c +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/falconwing.c ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/falconwing.c +@@ -307,6 +307,15 @@ static int falconwing_devices_init(void) + register_device(&mci_dev); + register_device(&ldcif_dev); + ++#ifdef CONFIG_MACH_CHUMBY_RESERVE_VIDMEM ++#define VIDMEM_SZ (1 * 1024 * 1024) ++ ++ /* force a fixed framebuffer location */ ++ fb_mode.framebuffer = (void*)(sdram_dev.map_base + sdram_dev.size - VIDMEM_SZ); ++ fb_mode.size = VIDMEM_SZ; ++ /* reduce the size of available regular memory */ ++ sdram_dev.size -= VIDMEM_SZ; ++#endif + armlinux_add_dram(&sdram_dev); + armlinux_set_bootparams((void*)(sdram_dev.map_base + 0x100)); + armlinux_set_architecture(MACH_TYPE_CHUMBY); +Index: barebox-2010.11.0/arch/arm/mach-stm/Kconfig +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/mach-stm/Kconfig ++++ barebox-2010.11.0/arch/arm/mach-stm/Kconfig +@@ -57,6 +57,18 @@ endif + + menu "Board specific settings " + ++if MACH_CHUMBY ++ ++config MACH_CHUMBY_RESERVE_VIDMEM ++ bool "lock video memory" ++ default y ++ help ++ To support a seamless splash screen from the bootloader into userland ++ some memory must be reserved to keep the splash image. This memory ++ must be locked to be not used by the kernel as regular memory. ++ ++endif ++ + endmenu + + endif +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/config +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/env/config ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/env/config +@@ -31,7 +31,7 @@ kernelimage_type=uimage + kernel_part=disk0.2 + + # base kernel parameter +-bootargs="console=ttyAM0,115200 quiet ro lcd_panel=lms350 ssp1=mmc line=1 sysrq_always_enabled rotary=1" ++bootargs="console=ttyAM0,115200 quiet ro lcd_panel=lms350 ssp1=mmc line=1 sysrq_always_enabled rotary=1 vidmem=0x43f00000,0x100000" + + autoboot_timeout=2 + diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/separate_imx23_imx28_clocks.diff b/configs/platform-chumby/patches/barebox-2010.11.0/separate_imx23_imx28_clocks.diff new file mode 100644 index 0000000..078d7f9 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/separate_imx23_imx28_clocks.diff @@ -0,0 +1,91 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Separate i.MX23 clock handling + +Separate i.MX23 clock handling to simplify the addition of the upcoming i.MX28. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/mach-stm/include/mach/clock-imx23.h | 36 +++++++++++++++++++++++++++ + arch/arm/mach-stm/include/mach/clock.h | 23 ++++------------- + 2 files changed, 42 insertions(+), 17 deletions(-) + +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock.h +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/include/mach/clock.h ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock.h +@@ -1,6 +1,4 @@ + /* +- * (C) Copyright 2010 Juergen Beisert - Pengutronix +- * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of +@@ -17,20 +15,11 @@ + * MA 02111-1307 USA + */ + +-#ifndef ASM_ARCH_CLOCK_IMX23_H +-#define ASM_ARCH_CLOCK_IMX23_H +- +-unsigned imx_get_mpllclk(void); +-unsigned imx_get_emiclk(void); +-unsigned imx_get_ioclk(void); +-unsigned imx_get_armclk(void); +-unsigned imx_get_hclk(void); +-unsigned imx_get_xclk(void); +-unsigned imx_get_sspclk(unsigned); +-unsigned imx_set_sspclk(unsigned, unsigned, int); +-unsigned imx_set_ioclk(unsigned); +-unsigned imx_set_lcdifclk(unsigned); +-unsigned imx_get_lcdifclk(void); ++#ifndef __ASM_MACH_CLOCK_H ++#define __ASM_MACH_CLOCK_H + +-#endif /* ASM_ARCH_CLOCK_IMX23_H */ ++#if defined CONFIG_ARCH_IMX23 ++# include <mach/clock-imx23.h> ++#endif + ++#endif /* __ASM_MACH_CLOCK_H */ +Index: barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock-imx23.h +=================================================================== +--- /dev/null ++++ barebox-2010.10.0/arch/arm/mach-stm/include/mach/clock-imx23.h +@@ -0,0 +1,36 @@ ++/* ++ * (C) Copyright 2010 Juergen Beisert - Pengutronix ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ */ ++ ++#ifndef ASM_ARCH_CLOCK_IMX23_H ++#define ASM_ARCH_CLOCK_IMX23_H ++ ++unsigned imx_get_mpllclk(void); ++unsigned imx_get_emiclk(void); ++unsigned imx_get_ioclk(void); ++unsigned imx_get_armclk(void); ++unsigned imx_get_hclk(void); ++unsigned imx_get_xclk(void); ++unsigned imx_get_sspclk(unsigned); ++unsigned imx_set_sspclk(unsigned, unsigned, int); ++unsigned imx_set_ioclk(unsigned); ++unsigned imx_set_lcdifclk(unsigned); ++unsigned imx_get_lcdifclk(void); ++ ++#endif /* ASM_ARCH_CLOCK_IMX23_H */ ++ diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/series b/configs/platform-chumby/patches/barebox-2010.11.0/series new file mode 100644 index 0000000..312c8a1 --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/series @@ -0,0 +1,61 @@ +# this is the current next +# from d1209136e304faab8616f75a347bf2d02d283468 to f90e136aa22ab13a3a8a321ae00e013d489a9f81 +# +2010.11_2_next.diff +make_the_kernel_less_noisy.diff +fix_machine_type.diff +# for next (sent upstream 2010-11-22) +add_mci_doc.diff + +# for master and next +# (sent upstream 2010-11-22) +remove_varsize_restriction_in_imx23_gpio.diff +# (sent upstream 2010-11-22) +simplify_max_gpio_no_test.diff +# (sent upstream 2010-11-22) +add_gpio_commands_to_imx23.diff +# (sent upstream 2010-11-22) +add_lcdclock_to_iMX23.diff +# (sent upstream 2010-11-22) +add_fb_support_to_iMX23.diff +# (sent upstream 2010-11-22) +speed_up_mci_detection.diff + +# generic changes -> mainline (keep track of their occurrence) +# (sent upstream 2010-11-22) +fix_baudrate_setting.diff + +# +# additional work on i.MX28 +# +# (sent upstream 2010-11-22) +separate_imx23_imx28_clocks.diff +add_imx28_architecture.diff +# for mainline, as its also i.MX23 relevant +generalize_serial_driver.diff -p0 +generalize_mci_driver.diff +add_fec_to_i.MX28.diff + +# change framebuffer behaviour series +# (sent upstream 2010-11-19) +0001-Separate-framebuffer-platformdata-and-the-videomode.patch +0002-Add-more-flags-for-sync-control.patch +0003-Bring-in-dynamic-videomode-selection-at-runtime.patch +0004-Add-verbose-framebuffer-device-info.patch +0005-Adapt-the-existing-imx-fb-driver-to-support-runtime-.patch +0006-Adapt-the-existing-imx-ipu-fb-driver-to-support-runt.patch +0007-Remove-variable-size-restrictions.patch +0008-Add-doxygen-documentation-to-the-framebfuffer-code.patch +0009-Provide-more-driver-specific-data-in-a-videomode.patch +0010-Add-a-video-driver-for-S3C2440-bases-platforms.patch +0011-STM378x-Add-video-driver-for-this-platform.patch +# end of change framebuffer behaviour + +adapt_fec_driver.diff + +# some chumby fixes +fix_sdram_id.diff +add_fb_support_to_chumby.diff +add_fb_support_to_init.diff +fix_lcd_flickering.diff +reserve_video_memory_chumby.diff diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/simplify_max_gpio_no_test.diff b/configs/platform-chumby/patches/barebox-2010.11.0/simplify_max_gpio_no_test.diff new file mode 100644 index 0000000..e63a94c --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/simplify_max_gpio_no_test.diff @@ -0,0 +1,33 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Simplify test for the max. possible GPIO number. + +This is only for easier integration of the i.MX28 architecture. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/mach-stm/iomux-imx23.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +Index: barebox-2010.10.0/arch/arm/mach-stm/iomux-imx23.c +=================================================================== +--- barebox-2010.10.0.orig/arch/arm/mach-stm/iomux-imx23.c ++++ barebox-2010.10.0/arch/arm/mach-stm/iomux-imx23.c +@@ -31,6 +31,8 @@ + #define HW_PINCTRL_DIN0 0x600 + #define HW_PINCTRL_DOE0 0x700 + ++#define MAX_GPIO_NO 95 ++ + static unsigned calc_mux_reg(unsigned no) + { + /* each register controls 16 pads */ +@@ -84,7 +86,7 @@ void imx_gpio_mode(uint32_t m) + writel(reg, IMX_IOMUXC_BASE + reg_offset); + + /* some pins are disabled when configured for GPIO */ +- if ((gpio_pin > 95) && (GET_FUNC(m) == IS_GPIO)) { ++ if ((gpio_pin > MAX_GPIO_NO) && (GET_FUNC(m) == IS_GPIO)) { + printf("Cannot configure pad %d to GPIO\n", gpio_pin); + return; + } diff --git a/configs/platform-chumby/patches/barebox-2010.11.0/speed_up_mci_detection.diff b/configs/platform-chumby/patches/barebox-2010.11.0/speed_up_mci_detection.diff new file mode 100644 index 0000000..76d45ca --- /dev/null +++ b/configs/platform-chumby/patches/barebox-2010.11.0/speed_up_mci_detection.diff @@ -0,0 +1,28 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Speed up mci card detection + +Currently the framework uses the slowest possible clock speed when detecting +the card. This leads into seconds barebox waits for the data. +Maybe the framework should use 400 kHz as the slowest clock speed instead if +the archives the specs. + +Until then, we force the usage of 400 kHz locally. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/boards/chumby_falconwing/falconwing.c | 1 + + 1 file changed, 1 insertion(+) + +Index: barebox-2010.11.0/arch/arm/boards/chumby_falconwing/falconwing.c +=================================================================== +--- barebox-2010.11.0.orig/arch/arm/boards/chumby_falconwing/falconwing.c ++++ barebox-2010.11.0/arch/arm/boards/chumby_falconwing/falconwing.c +@@ -44,6 +44,7 @@ static struct device_d sdram_dev = { + static struct stm_mci_platform_data mci_pdata = { + .caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz, + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, /* fixed to 3.3 V */ ++ .f_min = 400U * 1000U, + }; + + static struct device_d mci_dev = { diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/add_debug_on_demand_only.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/add_debug_on_demand_only.diff new file mode 100644 index 0000000..df781e1 --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/add_debug_on_demand_only.diff @@ -0,0 +1,117 @@ +From: Lothar Wassmann <LW@karo-electronics.de> +Subject: Add debug code on demand only + +Shrink the binaries if no debug output is required. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + boot_prep/Makefile | 9 ++++++++- + boot_prep/debug.h | 14 +++++++++++++- + mach-mx28/drivers/power/src/ddi_power.c | 1 - + power_prep/Makefile | 7 ++++++- + power_prep/debug.h | 14 +++++++++++++- + 5 files changed, 40 insertions(+), 5 deletions(-) + +Index: imx-bootlets-src-10.07.11/boot_prep/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/boot_prep/Makefile ++++ imx-bootlets-src-10.07.11/boot_prep/Makefile +@@ -24,7 +24,14 @@ CFLAGS = -g -Wall -I$(INCLUDEDIR) -I$(I + LDFLAGS = -static -nostdlib -T $(BOOT_LAYOUT) -Map=$@.map --cref + + # Generic code +-CORE_OBJS = init-$(ARCH).o debug.o ++CORE_OBJS = init-$(ARCH).o ++# TODO ++# CORE_OBJS = startup.o init-$(ARCH).o eabi.o ++ ++ifneq ($(DEBUG),) ++CFLAGS += -D_DEBUG ++CORE_OBJS += debug.o ++endif + + all: boot_prep + +Index: imx-bootlets-src-10.07.11/boot_prep/debug.h +=================================================================== +--- imx-bootlets-src-10.07.11.orig/boot_prep/debug.h ++++ imx-bootlets-src-10.07.11/boot_prep/debug.h +@@ -19,8 +19,20 @@ + */ + + #ifndef _DEBUG_H_ +-#define _DEBUG_H_ ++# define _DEBUG_H_ ++# ifdef _DEBUG + void putc(char ch); + void printhex(int data); + void printf(char *fmt, ...); ++# else ++static inline void putc(char ch) ++{ ++} ++static inline void printhex(int data) ++{ ++} ++static inline void printf(const char *fmt, ...) ++{ ++} ++# endif + #endif +Index: imx-bootlets-src-10.07.11/mach-mx28/drivers/power/src/ddi_power.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/mach-mx28/drivers/power/src/ddi_power.c ++++ imx-bootlets-src-10.07.11/mach-mx28/drivers/power/src/ddi_power.c +@@ -11,7 +11,6 @@ + * http://www.gnu.org/copyleft/gpl.html + */ + +- + // Includes and external references + //////////////////////////////////////////////////////////////////////////////// + #include "types.h" +Index: imx-bootlets-src-10.07.11/power_prep/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/Makefile ++++ imx-bootlets-src-10.07.11/power_prep/Makefile +@@ -48,7 +48,12 @@ ddi_libs += $(COMMONSRCDIR)/drivers/powe + POWER_PREP_OBJS = power_prep.o eabi.o + + # Generic code +-CORE_OBJS = debug.o ++CORE_OBJS = ++ ++ifneq ($(DEBUG),) ++CFLAGS += -D_DEBUG ++CORE_OBJS += debug.o ++endif + + # Default goal + .PHONY: all +Index: imx-bootlets-src-10.07.11/power_prep/debug.h +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/debug.h ++++ imx-bootlets-src-10.07.11/power_prep/debug.h +@@ -19,8 +19,20 @@ + */ + + #ifndef _DEBUG_H_ +-#define _DEBUG_H_ ++# define _DEBUG_H_ ++# ifdef _DEBUG + void putc(char ch); + void printhex(int data); + void printf(char *fmt, ...); ++# else ++static inline void putc(char ch) ++{ ++} ++static inline void printhex(int data) ++{ ++} ++static inline void printf(const char *fmt, ...) ++{ ++} ++# endif + #endif diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/avoid_anything.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/avoid_anything.diff new file mode 100644 index 0000000..41e0edd --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/avoid_anything.diff @@ -0,0 +1,31 @@ +--- + power_prep/power_prep.c | 6 ++---- + 1 file changed, 2 insertions(+), 4 deletions(-) + +Index: imx-bootlets-src-10.07.11/power_prep/power_prep.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/power_prep.c ++++ imx-bootlets-src-10.07.11/power_prep/power_prep.c +@@ -206,10 +206,10 @@ int _start( void ) + { + int iRtn = SUCCESS; + #ifndef mx28 +- HW_DIGCTL_CTRL_SET(BM_DIGCTL_CTRL_USE_SERIAL_JTAG); ++// HW_DIGCTL_CTRL_SET(BM_DIGCTL_CTRL_USE_SERIAL_JTAG); + #endif + +- PowerPrep_CPUClock2XTAL(); ++ PowerPrep_CPUClock2XTAL(); /* now at 24 MHz */ + PowerPrep_ClearAutoRestart(); + + hw_power_SetPowerClkGate( false ); +@@ -1116,9 +1116,7 @@ void PowerPrep_PrintBatteryVoltage(unsig + + void PowerPrep_CPUClock2XTAL(void) + { +-#ifdef mx28 + HW_CLKCTRL_CLKSEQ_SET(BM_CLKCTRL_CLKSEQ_BYPASS_CPU); +-#endif + } + + void PowerPrep_CPUClock2PLL(void) diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_buildsystem.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_buildsystem.diff new file mode 100644 index 0000000..28b72e6 --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_buildsystem.diff @@ -0,0 +1,76 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Make the 'elftosb2' tool configurable + +The 'elftosb2' may not in the path. Give the caller of this Makefile a chance +to setup the path and the name of this propritary tool. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + Makefile | 22 ++++++++++++---------- + 1 file changed, 12 insertions(+), 10 deletions(-) + +Index: imx-bootlets-src-10.07.11/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/Makefile ++++ imx-bootlets-src-10.07.11/Makefile +@@ -2,6 +2,8 @@ export CROSS_COMPILE + MEM_TYPE ?= MEM_DDR1 + export MEM_TYPE + ++ELFTOSB := elftosb2 ++ + DFT_IMAGE=$(DEV_IMAGE)/boot/zImage + DFT_UBOOT=$(DEV_IMAGE)/boot/u-boot + +@@ -25,17 +27,17 @@ build_prep: + gen_bootstream: linux_prep boot_prep power_prep linux.db uboot.db linux_prebuilt.db uboot_prebuilt.db updater_prebuilt.db + @echo "generating linux kernel boot stream image" + ifeq "$(DFT_IMAGE)" "$(wildcard $(DFT_IMAGE))" +- @echo "by using the rootfs/boot/zImage" ++ @echo "by using the '$(DFT_IMAGE)'" + sed -i 's,[^ *]zImage.*;,\tzImage="$(DFT_IMAGE)";,' linux.db +- elftosb2 -z -c ./linux.db -o i$(ARCH)_linux.sb +- @echo "by using the rootfs/boot/u-boot" ++ $(ELFTOSB) -z -c ./linux.db -o i$(ARCH)_linux.sb ++ @echo "by using the '$(DFT_UBOOT)'" + sed -i 's,[^ *]image.*;,\timage="$(DFT_UBOOT)";,' uboot.db +- elftosb2 -z -c ./uboot.db -o i$(ARCH)_uboot.sb ++ $(ELFTOSB) -z -c ./uboot.db -o i$(ARCH)_uboot.sb + else + @echo "by using the pre-built kernel" +- elftosb2 -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb ++ $(ELFTOSB) -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb + @echo "generating U-Boot boot stream image" +- elftosb2 -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb ++ $(ELFTOSB) -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb + endif + #@echo "generating kernel bootstream file sd_mmc_bootstream.raw" + #Please use cfimager to burn xxx_linux.sb. The below way will no +@@ -62,7 +64,7 @@ boot_prep: + + updater: linux_prep boot_prep power_prep + @echo "Build updater firmware" +- elftosb2 -z -c ./updater_prebuilt.db -o updater.sb ++ $(ELFTOSB) -z -c ./updater_prebuilt.db -o updater.sb + + linux_prep: + ifneq "$(CMDLINE1)" "" +@@ -85,14 +87,14 @@ install: + + cp -f *.sb ${DESTDIR} + # to create finial mfg updater.sb +-# cp -f elftosb2 ${DESTDIR} ++# cp -f $(ELFTOSB) ${DESTDIR} + cp -f ./updater_prebuilt.db ${DESTDIR} + cp -f ./create_updater.sh ${DESTDIR} + + distclean: clean + clean: +- -rm -rf *.sb +- rm -f sd_mmc_bootstream.raw ++ -$(RM) -rf *.sb ++ $(RM) -f sd_mmc_bootstream.raw + $(MAKE) -C linux_prep clean ARCH=$(ARCH) + $(MAKE) -C boot_prep clean ARCH=$(ARCH) + $(MAKE) -C power_prep clean ARCH=$(ARCH) diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_crlf.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_crlf.diff new file mode 100644 index 0000000..68c74f2 --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_crlf.diff @@ -0,0 +1,91 @@ +--- + power_prep/power_prep.c | 38 +++++++++++++++++++------------------- + 1 file changed, 19 insertions(+), 19 deletions(-) + +Index: imx-bootlets-src-10.07.11/power_prep/power_prep.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/power_prep.c ++++ imx-bootlets-src-10.07.11/power_prep/power_prep.c +@@ -293,8 +293,8 @@ int PowerPrep_ConfigurePowerSource( void + bBatteryReady = false; + bBatteryGood = false; + +- printf("\r\nConfigured for 5v only power source.\ +- Battery powered operation disabled.\r\n"); ++ printf("\r\nConfigured for 5v only power source. " ++ "Battery powered operation disabled.\r\n"); + + /* disable automatic battery voltage measurements */ + BF_CLR(LRADC_CONVERSION, AUTOMATIC); +@@ -343,16 +343,16 @@ int PowerPrep_ConfigurePowerSource( void + * appears to be chargeable but the voltage is current + * too low to use as a reliable battery voltage source. + */ +- printf("\r\nChargeable battery detected but\ +- the voltage is too low for battery\ +- powered operation.Booting from 5V\ +- power source.\r\n"); ++ printf("\r\nChargeable battery detected but " ++ "the voltage is too low for battery " ++ "powered operation.Booting from 5V " ++ "power source.\r\n"); + else { + BF_CLR(LRADC_CONVERSION, AUTOMATIC); + BF_WR(POWER_BATTMONITOR, BATT_VAL,0); +- printf("\r\nNo battery or bad battery\ +- detected!!!.Disabling battery\ +- voltage measurements./r/n"); ++ printf("\r\nNo battery or bad battery " ++ "detected!!!.Disabling battery " ++ "voltage measurements.\r\n"); + } + iReturnValue = PowerPrep_5vBoot(); + #ifndef MXS_VBUS_CURRENT_DRAW +@@ -361,9 +361,9 @@ int PowerPrep_ConfigurePowerSource( void + } + else + { +- printf("\r\n5v source detected.Valid battery\ +- voltage detected.Booting from battery\ +- voltage source.\r\n"); ++ printf("\r\n5v source detected.Valid battery " ++ "voltage detected.Booting from battery " ++ "voltage source.\r\n"); + /*Boot from battery*/ + iReturnValue = PowerPrep_BattBoot(); + PowerPrep_CPUClock2PLL(); +@@ -655,9 +655,9 @@ void PowerPrep_Init4p2Regulator( void ) + hw_power_Enable4p2DcdcInput(false); + hw_power_EnableMaster4p2( false ); + +- printf("Enabling of DCDC failed at setting of \ +- DCDC4P2 ENABLE_DCDC. Only 5V power supply \ +- operating is the linear regulators.\n"); ++ printf("Enabling of DCDC failed at setting of " ++ "DCDC4P2 ENABLE_DCDC. Only 5V power supply " ++ "operating is the linear regulators.\n"); + return; + } + +@@ -777,8 +777,8 @@ void PowerPrep_InitDcdc4p2Source( void ) + + if(HW_POWER_DCDC4P2.B.ENABLE_DCDC == false) + { +- printf("Error: tried to enable 5VCTRL ENABLE_DCDC before\ +- enabling DCDC4P2 ENABLE_DCDC.\n"); ++ printf("Error: tried to enable 5VCTRL ENABLE_DCDC before " ++ "enabling DCDC4P2 ENABLE_DCDC.\r\n"); + return; + } + +@@ -797,8 +797,8 @@ void PowerPrep_InitDcdc4p2Source( void ) + hw_power_Enable4p2DcdcInput( false ); + hw_power_EnableMaster4p2( false ); + +- printf("Enabling of DCDC failed at setting of "\ +- "5VCTRL ENABLE_DCDC. The only 5V power supply "\ ++ printf("Enabling of DCDC failed at setting of " ++ "5VCTRL ENABLE_DCDC. The only 5V power supply " + "operating is the linear regulators.\r\n"); + return; + } diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_default_command_line.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_default_command_line.diff new file mode 100644 index 0000000..4a25d8f --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_default_command_line.diff @@ -0,0 +1,33 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Adapt the kernel command line to out needs + +Currently the only location where to define the kernel command line. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + linux_prep/board/stmp378x_dev.c | 2 +- + linux_prep/cmdlines/stmp378x_dev.txt | 4 ++-- + 2 files changed, 3 insertions(+), 3 deletions(-) + +Index: imx-bootlets-src-10.07.11/linux_prep/board/stmp378x_dev.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/linux_prep/board/stmp378x_dev.c ++++ imx-bootlets-src-10.07.11/linux_prep/board/stmp378x_dev.c +@@ -51,4 +51,4 @@ u32 magic_keys[MAGIC_KEY_NR] = { + /************************************************ + * Default command line * + ************************************************/ +-char cmdline_def[] = "console=ttyAM0,115200"; ++char cmdline_def[] = "console=ttyAM0,115200 root=/dev/mmcblk0p3 rw rootwait"; +Index: imx-bootlets-src-10.07.11/linux_prep/cmdlines/stmp378x_dev.txt +=================================================================== +--- imx-bootlets-src-10.07.11.orig/linux_prep/cmdlines/stmp378x_dev.txt ++++ imx-bootlets-src-10.07.11/linux_prep/cmdlines/stmp378x_dev.txt +@@ -1,5 +1,5 @@ +-console=ttyAM0,115200 root=/dev/mmcblk0p3 rw rootwait lcd_panel=lms430 no_console_suspend +-console=ttyAM0,115200 root=/dev/mmcblk0p3 rw rootwait lcd_panel=lms350 ++console=ttyAM0,115200 root=/dev/mmcblk0p2 rw rootwait lcd_panel=lms430 no_console_suspend ++console=ttyAM0,115200 root=/dev/mmcblk0p2 rw rootwait lcd_panel=lms350 + console=ttyAM0,115200 ssp1=spi1 ubi.mtd=2 root=ubi0:rootfs0 rootfstype=ubifs lcd_panel=lms430 + + diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_mach_number.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_mach_number.diff new file mode 100644 index 0000000..28a058a --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_mach_number.diff @@ -0,0 +1,27 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Fake the MACH number for the reference kernel + +Chumby uses the 1733 in its 2.6.28 reference kernel. Fake this number to make +it boot. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + linux_prep/include/mx23/platform.h | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +Index: imx-bootlets-src-10.07.11/linux_prep/include/mx23/platform.h +=================================================================== +--- imx-bootlets-src-10.07.11.orig/linux_prep/include/mx23/platform.h ++++ imx-bootlets-src-10.07.11/linux_prep/include/mx23/platform.h +@@ -18,7 +18,9 @@ + #define __37XX_PLATFORM_H + + #if defined (BOARD_STMP378X_DEV) +-#define MACHINE_ID 0xa45 ++/* #define MACHINE_ID 0xa45 */ ++/* Used by Chumby in its 2.6.28 reference kernel */ ++#define MACHINE_ID 1733 + #else + #error "Allocate a machine ID for your board" + #endif diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_zero_keys.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_zero_keys.diff new file mode 100644 index 0000000..5665a93 --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/fix_zero_keys.diff @@ -0,0 +1,57 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Do not use zero keys on chumby for the boot image + +Using zero keys will end up in a '0x80501006' message on the screen while +booting from SD card. The error list shows it means: + + "Key dictionary lookup failed" + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + Makefile | 13 ++++++++----- + 1 file changed, 8 insertions(+), 5 deletions(-) + +Index: imx-bootlets-src-10.07.11/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/Makefile ++++ imx-bootlets-src-10.07.11/Makefile +@@ -3,6 +3,9 @@ MEM_TYPE ?= MEM_DDR1 + export MEM_TYPE + + ELFTOSB := elftosb2 ++# define to empty variable if the stream is to be used on 'chumby one' ++# for the i.MX23 EVK keep the '-z' ++ELFTOSB_KEY_PARAM := -z + + DFT_IMAGE=$(DEV_IMAGE)/boot/zImage + DFT_UBOOT=$(DEV_IMAGE)/boot/u-boot +@@ -29,15 +32,15 @@ gen_bootstream: linux_prep boot_prep pow + ifeq "$(DFT_IMAGE)" "$(wildcard $(DFT_IMAGE))" + @echo "by using the '$(DFT_IMAGE)'" + sed -i 's,[^ *]zImage.*;,\tzImage="$(DFT_IMAGE)";,' linux.db +- $(ELFTOSB) -z -c ./linux.db -o i$(ARCH)_linux.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./linux.db -o i$(ARCH)_linux.sb + @echo "by using the '$(DFT_UBOOT)'" + sed -i 's,[^ *]image.*;,\timage="$(DFT_UBOOT)";,' uboot.db +- $(ELFTOSB) -z -c ./uboot.db -o i$(ARCH)_uboot.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./uboot.db -o i$(ARCH)_uboot.sb + else + @echo "by using the pre-built kernel" +- $(ELFTOSB) -z -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb + @echo "generating U-Boot boot stream image" +- $(ELFTOSB) -z -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb + endif + #@echo "generating kernel bootstream file sd_mmc_bootstream.raw" + #Please use cfimager to burn xxx_linux.sb. The below way will no +@@ -64,7 +67,7 @@ boot_prep: + + updater: linux_prep boot_prep power_prep + @echo "Build updater firmware" +- $(ELFTOSB) -z -c ./updater_prebuilt.db -o updater.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./updater_prebuilt.db -o updater.sb + + linux_prep: + ifneq "$(CMDLINE1)" "" diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/generate_sd_image.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/generate_sd_image.diff new file mode 100644 index 0000000..980c4ab --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/generate_sd_image.diff @@ -0,0 +1,36 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Generate an bootable image to write on an SD card + +Just create a bootable image from all generated sources. This can simply +copied on an SD card to boot the chumby with it. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + Makefile | 13 ++++++------- + 1 file changed, 6 insertions(+), 7 deletions(-) + +Index: imx-bootlets-src-10.07.11/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/Makefile ++++ imx-bootlets-src-10.07.11/Makefile +@@ -45,13 +45,12 @@ else + @echo "generating U-Boot boot stream image" + $(ELFTOSB) $(ELFTOSB_KEY_PARAM) $(ELFTOSB_VERBOSE_PARAM) -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb + endif +- #@echo "generating kernel bootstream file sd_mmc_bootstream.raw" +- #Please use cfimager to burn xxx_linux.sb. The below way will no +- #work at imx28 platform. +- #rm -f sd_mmc_bootstream.raw +- #dd if=/dev/zero of=sd_mmc_bootstream.raw bs=512 count=4 +- #dd if=imx233_linux.sb of=sd_mmc_bootstream.raw ibs=512 seek=4 \ +- #conv=sync,notrunc ++# #@echo "generating kernel bootstream file sd_mmc_bootstream.raw" ++# #Please use cfimager to burn xxx_linux.sb. The below way will no ++# #work at imx28 platform. ++ $(RM) -f sd_mmc_bootstream.raw ++ dd if=/dev/zero of=sd_mmc_bootstream.raw bs=512 count=4 ++ dd if=i$(ARCH)_linux.sb of=sd_mmc_bootstream.raw ibs=512 seek=4 conv=sync,notrunc + @echo "To install bootstream onto SD/MMC card, type: sudo dd \ + if=sd_mmc_bootstream.raw of=/dev/sdXY where X is the correct letter \ + for your sd or mmc device (to check, do a ls /dev/sd*) and Y \ diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/improve_buildsystem.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/improve_buildsystem.diff new file mode 100644 index 0000000..53e2958 --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/improve_buildsystem.diff @@ -0,0 +1,129 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Provide as much info as possible about the generated binaries + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + boot_prep/Makefile | 8 ++++++-- + boot_prep/link.lds | 6 +++--- + power_prep/Makefile | 17 ++++++++++++----- + power_prep/eabi.S | 3 +++ + power_prep/link.lds | 6 +++--- + 5 files changed, 27 insertions(+), 13 deletions(-) + +Index: imx-bootlets-src-10.07.11/boot_prep/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/boot_prep/Makefile ++++ imx-bootlets-src-10.07.11/boot_prep/Makefile +@@ -20,8 +20,8 @@ OBJDUMP = $(CROSS_COMPILE)objdump + + MEM_TYPE ?= MEM_DDR1 + +-CFLAGS = -g -Wall -I$(INCLUDEDIR) -I$(INCLUDEDIR)/mach -I./ -O -D$(MEM_TYPE) +-LDFLAGS = -static -nostdlib -T $(BOOT_LAYOUT) ++CFLAGS = -g -Wall -I$(INCLUDEDIR) -I$(INCLUDEDIR)/mach -I./ -O -D$(MEM_TYPE) -fdata-sections -ffunction-sections ++LDFLAGS = -static -gc-sections -nostdlib -T $(BOOT_LAYOUT) -Map=$@.map --cref + + # Generic code + CORE_OBJS = init-$(ARCH).o debug.o +@@ -42,10 +42,14 @@ all: boot_prep + + boot_prep: $(BOOT_LAYOUT) $(CORE_OBJS) + $(LD) -o $@ $(CORE_OBJS) $(LDFLAGS) ++ @echo "-------------------------------------------------" > $@.list ++ @echo " * Regular Text content" >> $@.list ++ @$(OBJDUMP) -j .text -S -d $@ >> $@.list + + clean: + @echo Cleaning... + @echo Files: + @echo Build output: ++ rm -f boot_prep.map + rm -rf *.o + rm -f boot_prep +Index: imx-bootlets-src-10.07.11/power_prep/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/Makefile ++++ imx-bootlets-src-10.07.11/power_prep/Makefile +@@ -29,8 +29,8 @@ ifeq ($(POWERFLAG),MXS_VBUS_CURRENT_DRAW + CFLAGS += -DMXS_VBUS_CURRENT_DRAW + endif + +-CFLAGS += -Wall $(INCLUDEDIRS) -I./ -O -DSTMP378x -D$(ARCH) +-LDFLAGS = -static -gc-sections -nostdlib -T $(BOOT_LAYOUT) ++CFLAGS += -g -Wall $(INCLUDEDIRS) -I./ -O -DSTMP378x -D$(ARCH) -fdata-sections -ffunction-sections ++LDFLAGS = -static -gc-sections -nostdlib -T $(BOOT_LAYOUT) -Map=$@.map --cref + + + #TOP_LEVEL_OBJS = power_prep.o +@@ -70,9 +70,16 @@ all: power_prep + # + .PHONY: build build_prep clean + power_prep: libs $(BOOT_LAYOUT) $(POWER_PREP_OBJS) $(CORE_OBJS) +- $(LD) -o $@ $(POWER_PREP_OBJS) $(ddi_libs) $(hw_libs) \ +- $(LDFLAGS) $(CORE_OBJS) +- @nm -n $@ > power_prep.map ++ $(LD) -o $@ $(POWER_PREP_OBJS) $(ddi_libs) $(hw_libs) $(LDFLAGS) $(CORE_OBJS) ++ @echo "-------------------------------------------------" > $@.list ++ @echo " * Regular Text content" >> $@.list ++ @$(OBJDUMP) -j .text -S -d $@ >> $@.list ++ @echo "-------------------------------------------------" >> $@.list ++ @echo " * Regular Data content" >> $@.list ++ @$(OBJDUMP) -j .data -d $@ >> $@.list ++ @echo "-------------------------------------------------" >> $@.list ++ @echo " * Regular BSS content" >> $@.list ++ @$(OBJDUMP) -j .bss -d $@ >> $@.list + + libs: + $(MAKE) -C $(COMMONSRCDIR)/hw +Index: imx-bootlets-src-10.07.11/boot_prep/link.lds +=================================================================== +--- imx-bootlets-src-10.07.11.orig/boot_prep/link.lds ++++ imx-bootlets-src-10.07.11/boot_prep/link.lds +@@ -4,9 +4,9 @@ SECTIONS + { + . = 0x00000000; + . = ALIGN(4); +- .text : { *(.text) } +- .data : { *(.data) } +- .bss : { *(.bss) } ++ .text : { *(.text) *(.text*) *(.rodata*) } ++ .data : { *(.data) *(.data*) } ++ .bss : { *(.bss) *(.bss*) } + } + + +Index: imx-bootlets-src-10.07.11/power_prep/link.lds +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/link.lds ++++ imx-bootlets-src-10.07.11/power_prep/link.lds +@@ -4,9 +4,9 @@ SECTIONS + { + . = 0x00000000; + . = ALIGN(4); +- .text : { *(.text) } +- .data : { *(.data) } +- .bss : { *(.bss) } ++ .text : { *(.text) *(.text*) *(.rodata*) } ++ .data : { *(.data) *(.data*) } ++ .bss : { *(.bss) *(.bss*) } + } + + +Index: imx-bootlets-src-10.07.11/power_prep/eabi.S +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/eabi.S ++++ imx-bootlets-src-10.07.11/power_prep/eabi.S +@@ -15,9 +15,12 @@ + * ARM EABI toolchain needs divide by zero handler to be implemented + * externally. + */ ++ .section ".text.__div0","ax" + .globl __div0 + __div0: + mov pc, lr ++ ++ .section ".text.__aeabi_unwind_cpp_pr0","ax" + .globl __aeabi_unwind_cpp_pr0 + __aeabi_unwind_cpp_pr0: + mov pc, lr diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/make_elf2sb_more_noisy_on_demand.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/make_elf2sb_more_noisy_on_demand.diff new file mode 100644 index 0000000..0f2ddd1 --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/make_elf2sb_more_noisy_on_demand.diff @@ -0,0 +1,52 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: If 'DEBUG' is enabled, let 'elf2sb' also spit out more info + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + Makefile | 13 ++++++++----- + 1 file changed, 8 insertions(+), 5 deletions(-) + +Index: imx-bootlets-src-10.07.11/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/Makefile ++++ imx-bootlets-src-10.07.11/Makefile +@@ -6,6 +6,9 @@ ELFTOSB := elftosb2 + # define to empty variable if the stream is to be used on 'chumby one' + # for the i.MX23 EVK keep the '-z' + ELFTOSB_KEY_PARAM := -z ++ifneq ($(DEBUG),) ++ELFTOSB_VERBOSE_PARAM := -V -d ++endif + + DFT_IMAGE=$(DEV_IMAGE)/boot/zImage + DFT_UBOOT=$(DEV_IMAGE)/boot/u-boot +@@ -32,15 +35,15 @@ gen_bootstream: linux_prep boot_prep pow + ifeq "$(DFT_IMAGE)" "$(wildcard $(DFT_IMAGE))" + @echo "by using the '$(DFT_IMAGE)'" + sed -i 's,[^ *]zImage.*;,\tzImage="$(DFT_IMAGE)";,' linux.db +- $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./linux.db -o i$(ARCH)_linux.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) $(ELFTOSB_VERBOSE_PARAM) -c ./linux.db -o i$(ARCH)_linux.sb + @echo "by using the '$(DFT_UBOOT)'" + sed -i 's,[^ *]image.*;,\timage="$(DFT_UBOOT)";,' uboot.db +- $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./uboot.db -o i$(ARCH)_uboot.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) $(ELFTOSB_VERBOSE_PARAM) -c ./uboot.db -o i$(ARCH)_uboot.sb + else + @echo "by using the pre-built kernel" +- $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) $(ELFTOSB_VERBOSE_PARAM) -c ./linux_prebuilt.db -o i$(ARCH)_linux.sb + @echo "generating U-Boot boot stream image" +- $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) $(ELFTOSB_VERBOSE_PARAM) -c ./uboot_prebuilt.db -o i$(ARCH)_uboot.sb + endif + #@echo "generating kernel bootstream file sd_mmc_bootstream.raw" + #Please use cfimager to burn xxx_linux.sb. The below way will no +@@ -67,7 +70,7 @@ boot_prep: + + updater: linux_prep boot_prep power_prep + @echo "Build updater firmware" +- $(ELFTOSB) $(ELFTOSB_KEY_PARAM) -c ./updater_prebuilt.db -o updater.sb ++ $(ELFTOSB) $(ELFTOSB_KEY_PARAM) $(ELFTOSB_VERBOSE_PARAM) -c ./updater_prebuilt.db -o updater.sb + + linux_prep: + ifneq "$(CMDLINE1)" "" diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/move_putc_function.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/move_putc_function.diff new file mode 100644 index 0000000..7639fa4 --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/move_putc_function.diff @@ -0,0 +1,152 @@ +From: Lothar Wassmann <LW@karo-electronics.de> and Juergen Beisert <jbe@pengutronix.de> +Subject: Move the putc() function where it belongs to + +'debug.c' seems a better place for the putc() function, as long there is no +platform specific file available. + +This patch outputs all debug info on the debug UART. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + boot_prep/debug.c | 20 ++++++++++++++++++++ + boot_prep/init-mx23.c | 13 ------------- + boot_prep/init-mx28.c | 13 ------------- + power_prep/debug.c | 20 ++++++++++++++++++++ + power_prep/power_prep.c | 13 ------------- + 5 files changed, 40 insertions(+), 39 deletions(-) + +Index: imx-bootlets-src-10.07.11/boot_prep/init-mx28.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/boot_prep/init-mx28.c ++++ imx-bootlets-src-10.07.11/boot_prep/init-mx28.c +@@ -31,19 +31,6 @@ + + #define PIN_DRIVE_12mA 2 + //#define EMI_96M +- /* Debug uart have been init by boot rom. */ +-void putc(char ch) +-{ +- int loop = 0; +- while (HW_UARTDBGFR_RD()&BM_UARTDBGFR_TXFF) { +- loop++; +- if (loop > 10000) +- break; +- }; +- +- /* if(!(HW_UARTDBGFR_RD() &BM_UARTDBGFR_TXFF)) */ +- HW_UARTDBGDR_WR(ch); +-} + void delay(unsigned int us) + { + unsigned int start , cur; +Index: imx-bootlets-src-10.07.11/boot_prep/debug.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/boot_prep/debug.c ++++ imx-bootlets-src-10.07.11/boot_prep/debug.c +@@ -19,6 +19,26 @@ + */ + + #include <stdarg.h> ++#include <stdlib.h> ++#include "regsuartdbg.h" ++#include "debug.h" ++ ++void putc(char ch) ++{ ++ int loop = 0; ++ ++ if (ch == '\n') ++ putc('\r'); ++ ++ while (HW_UARTDBGFR_RD() & BM_UARTDBGFR_TXFF) { ++ loop++; ++ if (loop > 10000) ++ break; ++ } ++ ++ HW_UARTDBGDR_WR(ch); ++} ++ + void printhex(int data) + { + int i = 0; +Index: imx-bootlets-src-10.07.11/power_prep/debug.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/debug.c ++++ imx-bootlets-src-10.07.11/power_prep/debug.c +@@ -19,6 +19,26 @@ + */ + + #include <stdarg.h> ++#include <stdlib.h> ++#include "regsuartdbg.h" ++#include "debug.h" ++ ++void putc(char ch) ++{ ++ int loop = 0; ++ ++ if (ch == '\n') ++ putc('\r'); ++ ++ while (HW_UARTDBGFR_RD() & BM_UARTDBGFR_TXFF) { ++ loop++; ++ if (loop > 10000) ++ break; ++ }; ++ ++ HW_UARTDBGDR_WR(ch); ++} ++ + void printhex(int data) + { + int i = 0; +Index: imx-bootlets-src-10.07.11/power_prep/power_prep.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/power_prep/power_prep.c ++++ imx-bootlets-src-10.07.11/power_prep/power_prep.c +@@ -1095,19 +1095,6 @@ bool PowerPrep_IsBatteryReady( void ) + return false; + } + +-void putc(char ch) +-{ +- int loop = 0; +- while (HW_UARTDBGFR_RD()&BM_UARTDBGFR_TXFF) { +- loop++; +- if (loop > 10000) +- break; +- }; +- +- /* if(!(HW_UARTDBGFR_RD() &BM_UARTDBGFR_TXFF)) */ +- HW_UARTDBGDR_WR(ch); +-} +- + void PowerPrep_PrintBatteryVoltage(unsigned int value) + { + unsigned int num[3] = {0,0,0}; +Index: imx-bootlets-src-10.07.11/boot_prep/init-mx23.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/boot_prep/init-mx23.c ++++ imx-bootlets-src-10.07.11/boot_prep/init-mx23.c +@@ -32,19 +32,6 @@ + + #define PIN_DRIVE_12mA 2 + //#define EMI_96M +- /* Debug uart have been init by boot rom. */ +-void putc(char ch) +-{ +- int loop = 0; +- while (HW_UARTDBGFR_RD()&BM_UARTDBGFR_TXFF) { +- loop++; +- if (loop > 10000) +- break; +- }; +- +- /* if(!(HW_UARTDBGFR_RD() &BM_UARTDBGFR_TXFF)) */ +- HW_UARTDBGDR_WR(ch); +-} + + static void delay(unsigned int us) + { diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/remove_unused_functions.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/remove_unused_functions.diff new file mode 100644 index 0000000..b78962d --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/remove_unused_functions.diff @@ -0,0 +1,161 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Give the compiler a chance to sort out unused functions + +Do not pollute the global namespace. By the way, give the compiler a chance +to sort out not used functions, due to different macro definition. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + boot_prep/init-mx23.c | 39 ++++++++++++++++++++++++--------------- + 1 file changed, 24 insertions(+), 15 deletions(-) + +Index: imx-bootlets-src-10.07.11/boot_prep/init-mx23.c +=================================================================== +--- imx-bootlets-src-10.07.11.orig/boot_prep/init-mx23.c ++++ imx-bootlets-src-10.07.11/boot_prep/init-mx23.c +@@ -45,7 +45,8 @@ void putc(char ch) + /* if(!(HW_UARTDBGFR_RD() &BM_UARTDBGFR_TXFF)) */ + HW_UARTDBGDR_WR(ch); + } +-void delay(unsigned int us) ++ ++static void delay(unsigned int us) + { + unsigned int start , cur; + start = cur = HW_DIGCTL_MICROSECONDS_RD(); +@@ -58,7 +59,7 @@ void delay(unsigned int us) + + } + +-void init_mddr_mt46h32m16lf_96Mhz(int ce) ++static void init_mddr_mt46h32m16lf_96Mhz(int ce) + { + HW_DRAM_CTL00_WR(0x01010001); + HW_DRAM_CTL01_WR(0x00010100); +@@ -100,7 +101,7 @@ void init_mddr_mt46h32m16lf_96Mhz(int ce + HW_DRAM_CTL08_WR(0x01010000); + } + +-void init_mddr_mt46h32m16lf_133Mhz(int ce) ++static void init_mddr_mt46h32m16lf_133Mhz(int ce) + { + HW_DRAM_CTL00_WR(0x01010001); + HW_DRAM_CTL01_WR(0x00010000); +@@ -142,7 +143,7 @@ void init_mddr_mt46h32m16lf_133Mhz(int c + HW_DRAM_CTL08_WR(0x01010000); + } + +-void init_ddr_mt46v32m16_133Mhz(int ce) ++static void init_ddr_mt46v32m16_133Mhz(int ce) + { + HW_DRAM_CTL00_WR(0x01010001); + HW_DRAM_CTL01_WR(0x00010100); +@@ -185,7 +186,7 @@ void init_ddr_mt46v32m16_133Mhz(int ce) + + } + +-void init_ddr_mt46v32m16_96Mhz(int ce) ++static void init_ddr_mt46v32m16_96Mhz(int ce) + { + HW_DRAM_CTL00_WR(0x01010001); + HW_DRAM_CTL01_WR(0x00010000); +@@ -226,11 +227,13 @@ void init_ddr_mt46v32m16_96Mhz(int ce) + HW_DRAM_CTL40_WR(0x00010000); + HW_DRAM_CTL08_WR(0x01000000); + } +-void poweron_pll() ++ ++static void poweron_pll() + { + HW_CLKCTRL_PLLCTRL0_SET(BM_CLKCTRL_PLLCTRL0_POWER); + } +-void turnon_mem_rail(int mv) ++ ++static void turnon_mem_rail(int mv) + { + unsigned int value; + HW_POWER_CTRL_CLR(BM_POWER_CTRL_CLKGATE); +@@ -246,13 +249,15 @@ void turnon_mem_rail(int mv) + BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE); + HW_POWER_VDDMEMCTRL_WR(value); + } +-void set_emi_frac(unsigned int div) ++ ++static void set_emi_frac(unsigned int div) + { + HW_CLKCTRL_FRAC_SET(BM_CLKCTRL_FRAC_EMIFRAC); + div = (~div); + HW_CLKCTRL_FRAC_CLR(BF_CLKCTRL_FRAC_EMIFRAC(div)); + } +-void init_clock() ++ ++static void init_clock() + { + HW_CLKCTRL_FRAC_SET(BM_CLKCTRL_FRAC_CLKGATEEMI); + #ifdef EMI_96M +@@ -284,7 +289,7 @@ void init_clock() + + } + +-void disable_emi_padkeepers(void) ++static void disable_emi_padkeepers(void) + { + HW_PINCTRL_CTRL_CLR(BM_PINCTRL_CTRL_SFTRST | BM_PINCTRL_CTRL_CLKGATE); + +@@ -311,7 +316,7 @@ void disable_emi_padkeepers(void) + } + + #define PIN_VOL(pin , v) ((v) ? (pin) : 0) +-void init_emi_pin(int pin_voltage, ++static void init_emi_pin(int pin_voltage, + int pin_drive + ) + { +@@ -580,7 +585,8 @@ void init_emi_pin(int pin_voltage, + BM_PINCTRL_MUXSEL7_BANK3_PIN20 | + BM_PINCTRL_MUXSEL7_BANK3_PIN21); + } +-void exit_selfrefresh() ++ ++static void exit_selfrefresh() + { + unsigned int start; + unsigned int value; +@@ -600,7 +606,7 @@ void exit_selfrefresh() + } + } + +-void set_port_priority() ++static void set_port_priority() + { + unsigned int value; + +@@ -613,7 +619,8 @@ void set_port_priority() + HW_EMI_CTRL_SET(BF_EMI_CTRL_PORT_PRIORITY_ORDER(0x2)); + + } +-void entry_auto_clock_gate() ++ ++static void entry_auto_clock_gate() + { + unsigned int value; + value = HW_DRAM_CTL16_RD(); +@@ -624,7 +631,8 @@ void entry_auto_clock_gate() + value |= 1<<11; + HW_DRAM_CTL16_WR(value); + } +-void change_cpu_freq() ++ ++static void change_cpu_freq() + { + int value = 0; + printf("power 0x%x\r\n" , HW_POWER_VDDDCTRL_RD()); +@@ -662,6 +670,7 @@ void change_cpu_freq() + printf("cpu 0x%x\r\n" , HW_CLKCTRL_CPU_RD()); + + } ++ + int _start(int arg) + { + unsigned int value; diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/separate_bootlets.diff b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/separate_bootlets.diff new file mode 100644 index 0000000..eb763a9 --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/separate_bootlets.diff @@ -0,0 +1,46 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Separate the generated boot streams + +Most of the time only one of these streams is required to make the Chumby work + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + Makefile | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +Index: imx-bootlets-src-10.07.11/Makefile +=================================================================== +--- imx-bootlets-src-10.07.11.orig/Makefile ++++ imx-bootlets-src-10.07.11/Makefile +@@ -27,6 +27,30 @@ endif + + all: build_prep gen_bootstream + ++# build the bootloader boot stream ++bootloader_stream: i$(ARCH)_uboot.sb ++ @$(RM) -f $@ ++ @dd if=/dev/zero of=$@ bs=512 count=4 ++ @dd if=$< of=$@ ibs=512 seek=4 conv=sync,notrunc ++ ++# build the kernel boot stream ++linux_stream: i$(ARCH)_linux.sb ++ @$(RM) -f $@ ++ @dd if=/dev/zero of=$@ bs=512 count=4 ++ @dd if=$< of=$@ ibs=512 seek=4 conv=sync,notrunc ++ ++# build the bootloader bootlet ++i$(ARCH)_uboot.sb: power_prep boot_prep ++ @echo "Generating bootloader boot stream image by using the '$(DFT_UBOOT)'" ++ @sed -i 's,[^ *]image.*;,\timage="$(DFT_UBOOT)";,' uboot.db ++ @$(ELFTOSB) $(ELFTOSB_KEY_PARAM) $(ELFTOSB_VERBOSE_PARAM) -c ./uboot.db -o $@ ++ ++# build the kernel bootlet ++i$(ARCH)_linux.sb: power_prep boot_prep linux_prep ++ @echo "Generating linux kernel boot stream image by using the '$(DFT_IMAGE)'" ++ @sed -i 's,[^ *]zImage.*;,\tzImage="$(DFT_IMAGE)";,' linux.db ++ @$(ELFTOSB) $(ELFTOSB_KEY_PARAM) $(ELFTOSB_VERBOSE_PARAM) -c ./linux.db -o $@ ++ + build_prep: + + diff --git a/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/series b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/series new file mode 100644 index 0000000..bc1791e --- /dev/null +++ b/configs/platform-chumby/patches/imx-bootlets-src-10.07.11/series @@ -0,0 +1,13 @@ +fix_buildsystem.diff +improve_buildsystem.diff +fix_zero_keys.diff +make_elf2sb_more_noisy_on_demand.diff +generate_sd_image.diff +separate_bootlets.diff +fix_mach_number.diff +fix_default_command_line.diff +remove_unused_functions.diff +fix_crlf.diff +add_debug_on_demand_only.diff +move_putc_function.diff +sep_funcs.diff diff --git a/configs/platform-chumby/patches/linux-2.6.28/0001-Ugly-hack-to-make-ip-config-work.patch b/configs/platform-chumby/patches/linux-2.6.28/0001-Ugly-hack-to-make-ip-config-work.patch new file mode 100644 index 0000000..4f4a0b8 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/0001-Ugly-hack-to-make-ip-config-work.patch @@ -0,0 +1,33 @@ +From aa80802bda2a70bf58d67c583bf41c170fe72763 Mon Sep 17 00:00:00 2001 +From: Sascha Hauer <s.hauer@pengutronix.de> +Date: Thu, 28 May 2009 15:04:41 +0200 +Subject: [PATCH 01/57] Ugly hack to make ip config work + +We want to use nfsroot over an usb network adapter. There is a +rootdelay kernel option which makes sure that we wait some seconds +before trying to mount the rootfs to make sure that the network +adapter appears. Unfortunately the ip autoconfig code does +not wait and thus fails. This hack increases the time to wait +before the autoconfig code runs. + +Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> +--- + net/ipv4/ipconfig.c | 2 +- + 1 files changed, 1 insertions(+), 1 deletions(-) + +diff --git a/net/ipv4/ipconfig.c b/net/ipv4/ipconfig.c +index 10a6a60..1cba476 100644 +--- a/net/ipv4/ipconfig.c ++++ b/net/ipv4/ipconfig.c +@@ -86,7 +86,7 @@ + #endif + + /* Define the friendly delay before and after opening net devices */ +-#define CONF_PRE_OPEN 500 /* Before opening: 1/2 second */ ++#define CONF_PRE_OPEN 8000 /* Before opening: 1/2 second */ + #define CONF_POST_OPEN 1 /* After opening: 1 second */ + + /* Define the timeout for waiting for a DHCP/BOOTP/RARP reply */ +-- +1.7.0 + diff --git a/configs/platform-chumby/patches/linux-2.6.28/adapt_falconwings_fb.diff b/configs/platform-chumby/patches/linux-2.6.28/adapt_falconwings_fb.diff new file mode 100644 index 0000000..4826493 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/adapt_falconwings_fb.diff @@ -0,0 +1,94 @@ +--- + arch/arm/mach-stmp3xxx/stmp378x_devb.c | 58 +++++++++++++++++++++++++++++++++ + 1 file changed, 58 insertions(+) + +Index: linux-2.6.28/arch/arm/mach-stmp3xxx/stmp378x_devb.c +=================================================================== +--- linux-2.6.28.orig/arch/arm/mach-stmp3xxx/stmp378x_devb.c ++++ linux-2.6.28/arch/arm/mach-stmp3xxx/stmp378x_devb.c +@@ -23,6 +23,7 @@ + #include <linux/mtd/mtd.h> + #include <linux/mtd/partitions.h> + #include <linux/platform_device.h> ++#include <linux/dma-mapping.h> + #include <linux/fsl_devices.h> + #include <linux/spi/spi.h> + #include <linux/i2c.h> +@@ -41,6 +42,8 @@ + #include <mach/regs-usbphy.h> + #include <mach/regs-pinctrl.h> + #include <mach/regs-pwm.h> ++#include <mach/regs-lcdif.h> ++#include <mach/fb.h> + + #define CHLOG(format, arg...) \ + printk("stmp378x_devb.c - %s():%d - " format, __func__, __LINE__, ## arg) +@@ -367,6 +370,60 @@ static struct i2c_board_info __initdata + { I2C_BOARD_INFO("stfm1000", 0xc0), .flags = I2C_M_TEN } + }; + ++static struct fb_videomode falconwing_vmode = { ++ .name = "NMA35", ++ .refresh = 60, ++ .xres = 320, ++ .yres = 240, /* active area 70.08 mm x 52.56 mm */ ++ .pixclock = KHZ2PICOS(6250), /* max 10 MHz */ ++ .left_margin = 28, ++ .hsync_len = 24, ++ .right_margin = 28, /* = 64 µs */ ++ .upper_margin = 8, ++ .vsync_len = 4, ++ .lower_margin = 8, /* = 60 Hz */ ++ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, /* low active DE */ ++ .vmode = FB_VMODE_NONINTERLACED, ++ .flag = 0, ++}; ++ ++static struct stmfb_platformdata fb_data = { ++ .mode_list = &falconwing_vmode, ++ .mode_count = 1, ++ .selected_mode = 0, ++ .max_bpp = 16, ++ .fixed_fb_start = 0, ++ .fixed_fb_size = 0, ++ .ld_intf_width = STMLCDIF_18BIT, /* FIXME or 24 bit? */ ++}; ++ ++static struct resource framebuffer_resource[] = { ++ { ++ .flags = IORESOURCE_MEM, ++ .start = REGS_LCDIF_BASE, ++ .end = REGS_LCDIF_BASE + 0x2000 - 1, ++ }, ++}; ++ ++static u64 dmamask = DMA_BIT_MASK(32); ++ ++static struct platform_device fb_dev = { ++ .name = "stmp-fb", ++ .id = 0, ++ .dev = { ++ .platform_data = &fb_data, ++ .dma_mask = &dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++ .resource = framebuffer_resource, ++ .num_resources = ARRAY_SIZE(framebuffer_resource), ++}; ++ ++static void __init devb_init_lcdif(void) ++{ ++ platform_device_register(&fb_dev); ++} ++ + static void __init stmp378x_devb_init(void) + { + struct fsl_usb2_platform_data *udata; +@@ -388,6 +445,7 @@ static void __init stmp378x_devb_init(vo + platform_add_devices(devices, ARRAY_SIZE(devices)); + if (pwm_leds_enable) + platform_device_register(&stmp378x_leds); ++ devb_init_lcdif(); + } + + MACHINE_START(STMP378X, "STMP378X") diff --git a/configs/platform-chumby/patches/linux-2.6.28/avoid_re_initializing.diff b/configs/platform-chumby/patches/linux-2.6.28/avoid_re_initializing.diff new file mode 100644 index 0000000..b40c8ff --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/avoid_re_initializing.diff @@ -0,0 +1,74 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Avoid re-initializing the controller if already done in bootloader + +If the bootloader already had intialized the LCD controller, avoid to +re-initialize it again. Instead read back bootloaders settings and continue +to use them. + +NOTE: This is WIP. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + drivers/video/stmfb.c | 20 ++++++++++++++++---- + 1 file changed, 16 insertions(+), 4 deletions(-) + +Index: linux-2.6.31/drivers/video/stmfb.c +=================================================================== +--- linux-2.6.31.orig/drivers/video/stmfb.c ++++ linux-2.6.31/drivers/video/stmfb.c +@@ -165,6 +165,7 @@ struct imxfb_host { + struct clk *clk; + void __iomem *base; /* registers */ + unsigned allocated_size; ++ unsigned char pre_init; + + unsigned transfer_count; /* CPU dependend register offset */ + unsigned cur_buf; +@@ -615,6 +616,10 @@ static int __devinit acquire_videomemory + } else { + /* dynamic framebuffer area */ + pr_debug("Going to allocate a framebuffer from generic RAM\n"); ++ if (host->pre_init != 0) { ++ dev_warn(&host->pdev->dev, "Pre-init configured but not prepared! Falling back to standard behaviour\n"); ++ host->pre_init = 0; ++ } + #ifdef DEBUG + if ((pdata->fixed_fb_start != NULL) || (pdata->fixed_fb_size != 0)) + dev_warn(&host->pdev->dev, "Only one param for fixed framebuffer set. Ignored\n"); +@@ -874,7 +879,10 @@ static int __devinit stmfb_probe(struct + + host = to_imxfb_host(fb_info); + +- /* what is its meaning? Hardware register or a separate framebuffer memory? */ ++#ifdef CONFIG_FB_PRE_INIT_FB ++ host->pre_init = 1; ++#endif ++ /* TODO what is its meaning? Hardware register or a separate framebuffer memory? */ + fb_info->fix.mmio_start = main_res->start; + fb_info->fix.mmio_len = resource_size(main_res); + +@@ -895,8 +903,11 @@ static int __devinit stmfb_probe(struct + if (ret != 0) + goto error_videomemory; + +- /* init the colour bitfields */ +- stmfb_check_var(&fb_info->var, fb_info); ++ if (host->pre_init == 0) ++ /* init the colour bitfields */ ++ stmfb_check_var(&fb_info->var, fb_info); ++ else ++ ; /* TODO read back all required info from current register settings */ + + ret = fb_alloc_cmap(&fb_info->cmap, 1 << fb_info->var.bits_per_pixel, 0); + if (ret < 0) +@@ -913,7 +924,8 @@ static int __devinit stmfb_probe(struct + * If there is no user than a userland application, force to setup a + * videomode, for the case the application forgets to do so + */ +- stmfb_set_par(fb_info); ++ if (host->pre_init == 0) ++ stmfb_set_par(fb_info); + #endif + + return 0; diff --git a/configs/platform-chumby/patches/linux-2.6.28/chumby.diff.bz2 b/configs/platform-chumby/patches/linux-2.6.28/chumby.diff.bz2 Binary files differnew file mode 100644 index 0000000..955d51e --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/chumby.diff.bz2 diff --git a/configs/platform-chumby/patches/linux-2.6.28/fb_clock_28.diff b/configs/platform-chumby/patches/linux-2.6.28/fb_clock_28.diff new file mode 100644 index 0000000..1894e57 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/fb_clock_28.diff @@ -0,0 +1,206 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Add a useable framebuffer pixel calculation routine for i.MX28 + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + arch/arm/mach-stmp3xxx/clock.c | 169 +++++++++++++++++++---------------------- + 1 file changed, 81 insertions(+), 88 deletions(-) + +Index: linux-2.6.28/arch/arm/mach-stmp3xxx/clock.c +=================================================================== +--- linux-2.6.28.orig/arch/arm/mach-stmp3xxx/clock.c ++++ linux-2.6.28/arch/arm/mach-stmp3xxx/clock.c +@@ -205,103 +205,96 @@ static long lcdif_get_rate(struct clk *c + return 0; + } + +-static int lcdif_set_rate(struct clk *clk, u32 rate) +-{ +- int ret = 0; +- /* +- * On 3700, we can get most timings exact by modifying ref_pix +- * and the divider, but keeping the phase timings at 1 (2 +- * phases per cycle). +- * +- * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz, +- * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns. +- * +- * ns_cycle >= 2*18e3/(18*480) = 25/6 +- * ns_cycle <= 2*35e3/(18*480) = 875/108 +- * +- * Multiply the ns_cycle by 'div' to lengthen it until it fits the +- * bounds. This is the divider we'll use after ref_pix. +- * +- * 6 * ns_cycle >= 25 * div +- * 108 * ns_cycle <= 875 * div +- */ +- u32 ns_cycle = 1000000 / rate; +- u32 div, reg_val; +- u32 lowest_result = (u32) -1; +- u32 lowest_div = 0, lowest_fracdiv = 0; +- +- for (div = 1; div < 256; ++div) { +- u32 fracdiv; +- u32 ps_result; +- int lower_bound = 6 * ns_cycle >= 25 * div; +- int upper_bound = 108 * ns_cycle <= 875 * div; +- if (!lower_bound) +- break; +- if (!upper_bound) +- continue; +- /* +- * Found a matching div. Calculate fractional divider needed, +- * rounded up. +- */ +- fracdiv = ((clk->parent->rate / 1000 * 18 / 2) * +- ns_cycle + 1000 * div - 1) / +- (1000 * div); +- if (fracdiv < 18 || fracdiv > 35) { +- ret = -EINVAL; +- goto out; +- } +- /* Calculate the actual cycle time this results in */ +- ps_result = 6250 * div * fracdiv / 27; +- +- /* Use the fastest result that doesn't break ns_cycle */ +- if (ps_result <= lowest_result) { +- lowest_result = ps_result; +- lowest_div = div; +- lowest_fracdiv = fracdiv; ++/* ++ * 'nc' comes in in Hz! ++ * ++ * Calculate the best settings for the fractional and integer divider to match ++ * the requested pixel clock as close as possible. ++ * ++ * pixel clock = 480 MHz * 18 / frac_div / int_div ++ */ ++int imx_set_lcdifclk(struct clk *clk, unsigned long nc) ++{ ++ unsigned frac, best_frac = 0, div, best_div = 0, result; ++ int delta, best_delta = 0xffffff; ++ unsigned i, parent_rate = 480U * 1000U; ++ uint32_t reg; ++ ++ nc /= 1000U; /* now in kHz */ ++ ++#undef SH_DIV ++#define DIV(NOM, DEN) (((NOM) + (DEN) / 2) / (DEN)) ++#define SH_DIV(NOM, DEN, LSH) ((((NOM) / (DEN)) << (LSH)) + DIV(((NOM) % (DEN)) << (LSH), DEN)) ++#define ABS(x) (((x) < 0) ? (-(x)) : (x)) ++#define SHIFT 4 ++ ++ nc <<= SHIFT; ++ ++ for (frac = 18; frac <= 35; ++frac) { ++ for (div = 1; div <= 255; ++div) { ++ result = DIV(parent_rate * SH_DIV(18U, frac, SHIFT), div); ++ delta = nc - result; ++ if (ABS(delta) < ABS(best_delta)) { ++ best_delta = delta; ++ best_frac = frac; ++ best_div = div; ++ } + } + } + +- if (div >= 256 || lowest_result == (u32) -1) { +- ret = -EINVAL; +- goto out; ++ if (best_delta == 0xffffff) { ++ pr_debug("Unable to match the pixelclock\n"); ++ return -EINVAL; + } +- pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz " +- "PIXCLK=%uMHz cycle=%u.%03uns\n", +- lowest_fracdiv, lowest_div, +- 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div, +- lowest_result / 1000, lowest_result % 1000); +- +- /* Program ref_pix phase fractional divider */ +- HW_CLKCTRL_FRAC_WR((HW_CLKCTRL_FRAC_RD() & ~BM_CLKCTRL_FRAC_PIXFRAC) | +- BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv)); +- /* Ungate PFD */ +- HW_CLKCTRL_FRAC_CLR(BM_CLKCTRL_FRAC_CLKGATEPIX); +- +- /* Program pix divider */ +- reg_val = __raw_readl(clk->scale_reg); +- reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE); +- reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div); +- __raw_writel(reg_val, clk->scale_reg); ++ ++ pr_debug("# Programming PFD=%u,DIV=%u ref_pix=%u MHz PIXCLK=%u MHz\n", ++ best_frac, best_div, 480 * 18 / best_frac, ++ 480 * 18 / best_frac / best_div); ++ ++# define SET_PIXFRAC(x) (((x) & 0x3f) << 16) ++# define CLKCTRL_FRAC_CLKGATEPIX (1 << 23) ++ ++ /* setup the pre-divider after the PLL */ ++ reg = __raw_readl(REGS_CLKCTRL_BASE + 0xf0) & ~0x003f0000; ++ reg |= SET_PIXFRAC(best_frac); ++ __raw_writel(reg, REGS_CLKCTRL_BASE + 0xf0); ++ /* enable the clock */ ++ __raw_writel(CLKCTRL_FRAC_CLKGATEPIX, REGS_CLKCTRL_BASE + 0xf8); ++ pr_debug("# FRAC1: %08X\n", __raw_readl(REGS_CLKCTRL_BASE + 0xf0)); ++ ++# define SET_DIS_LCDIF_DIV(x) ((x) & 0xfff) ++# define CLKCTRL_DIS_LCDIF_GATE (1 << 31) ++ ++ /* setup the post-divider prior the LCD unit */ ++ reg = __raw_readl(clk->scale_reg) & ~0xfff; ++ /* enable the clock */ ++ reg &= ~CLKCTRL_DIS_LCDIF_GATE; ++ reg |= SET_DIS_LCDIF_DIV(best_div); ++ __raw_writel(reg, clk->scale_reg); ++ pr_debug("# LCDIF DIV: %08X\n", __raw_readl(clk->enable_reg)); ++ ++# define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) + + /* Wait for divider update */ +- if (clk->busy_reg) { +- int i; +- for (i = 10000; i; i--) +- if (!clk_is_busy(clk)) +- break; +- if (!i) { +- ret = -ETIMEDOUT; +- goto out; +- } ++ for (i = 0; i < 10000; i++) { ++ if (!(__raw_readl(clk->busy_reg) & (1 << clk->busy_bit))) ++ break; + } + +- /* Switch to ref_pix source */ +- HW_CLKCTRL_CLKSEQ_CLR(BM_CLKCTRL_CLKSEQ_BYPASS_PIX); ++ if (i >= 10000) { ++ pr_debug("# Setting LCD clock failed\n"); ++ return -EINVAL; ++ } + +-out: +- return ret; +-} ++# define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) ++ ++ /* always switch to the PLL as clock source */ ++ clk->parent = &pll_clk; ++ __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + 8); ++ pr_debug("# BYPASS: %08X\n", __raw_readl(clk->bypass_reg)); + ++ return 0; ++} + + static int cpu_set_rate(struct clk *clk, u32 rate) + { +@@ -870,7 +863,7 @@ static struct clk lcdif_clk = { + .name = "lcdif", + .parent = &pll_clk, + .get_rate = lcdif_get_rate, +- .set_rate = lcdif_set_rate, ++ .set_rate = imx_set_lcdifclk, + .scale_reg = HW_CLKCTRL_PIX_ADDR, + .busy_reg = HW_CLKCTRL_PIX_ADDR, + .busy_bit = 29, diff --git a/configs/platform-chumby/patches/linux-2.6.28/fix_getline.diff b/configs/platform-chumby/patches/linux-2.6.28/fix_getline.diff new file mode 100644 index 0000000..efb9ab3 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/fix_getline.diff @@ -0,0 +1,41 @@ +From: Juergen Beisert <jbe@pengutronix.de> and others +Subject: Fix a compile time failure with more current host glibcs + +Local getline() collides with current host environments. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> +--- + scripts/unifdef.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +Index: linux-2.6.28/scripts/unifdef.c +=================================================================== +--- linux-2.6.28.orig/scripts/unifdef.c ++++ linux-2.6.28/scripts/unifdef.c +@@ -206,7 +206,7 @@ static void done(void); + static void error(const char *); + static int findsym(const char *); + static void flushline(bool); +-static Linetype getline(void); ++static Linetype get_line(void); + static Linetype ifeval(const char **); + static void ignoreoff(void); + static void ignoreon(void); +@@ -512,7 +512,7 @@ process(void) + + for (;;) { + linenum++; +- lineval = getline(); ++ lineval = get_line(); + trans_table[ifstate[depth]][lineval](); + debug("process %s -> %s depth %d", + linetype_name[lineval], +@@ -526,7 +526,7 @@ process(void) + * help from skipcomment(). + */ + static Linetype +-getline(void) ++get_line(void) + { + const char *cp; + int cursym; diff --git a/configs/platform-chumby/patches/linux-2.6.28/fix_mach_id.diff b/configs/platform-chumby/patches/linux-2.6.28/fix_mach_id.diff new file mode 100644 index 0000000..7e4dfcf --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/fix_mach_id.diff @@ -0,0 +1,17 @@ +--- + arch/arm/mach-stmp3xxx/stmp378x_devb.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +Index: linux-2.6.28/arch/arm/mach-stmp3xxx/stmp378x_devb.c +=================================================================== +--- linux-2.6.28.orig/arch/arm/mach-stmp3xxx/stmp378x_devb.c ++++ linux-2.6.28/arch/arm/mach-stmp3xxx/stmp378x_devb.c +@@ -448,7 +448,7 @@ static void __init stmp378x_devb_init(vo + devb_init_lcdif(); + } + +-MACHINE_START(STMP378X, "STMP378X") ++MACHINE_START(CHUMBY, "ChumbyOne") + .phys_io = 0x80000000, + .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc, + .boot_params = 0x40000100, diff --git a/configs/platform-chumby/patches/linux-2.6.28/force_video_mode_without_console.diff b/configs/platform-chumby/patches/linux-2.6.28/force_video_mode_without_console.diff new file mode 100644 index 0000000..d8b73fe --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/force_video_mode_without_console.diff @@ -0,0 +1,32 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Force a videomode if there is noone who is requested one + +If the framebuffer console is disabled, there is noone who sets up a videomode. +This will keep the display dark. So, if there is no framebuffer console enabled +force the default videomode. + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + drivers/video/stmfb.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +Index: linux-2.6.31/drivers/video/stmfb.c +=================================================================== +--- linux-2.6.31.orig/drivers/video/stmfb.c ++++ linux-2.6.31/drivers/video/stmfb.c +@@ -908,6 +908,14 @@ static int __devinit stmfb_probe(struct + goto failed_register; + } + ++#ifndef CONFIG_FRAMEBUFFER_CONSOLE ++ /* ++ * If there is no user than a userland application, force to setup a ++ * videomode, for the case the application forgets to do so ++ */ ++ stmfb_set_par(fb_info); ++#endif ++ + return 0; + + failed_register: diff --git a/configs/platform-chumby/patches/linux-2.6.28/imx23_2.6.28.fb_h.diff b/configs/platform-chumby/patches/linux-2.6.28/imx23_2.6.28.fb_h.diff new file mode 100644 index 0000000..ac184c6 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/imx23_2.6.28.fb_h.diff @@ -0,0 +1,52 @@ +Note: WIP +--- + arch/arm/mach-stmp3xxx/include/mach/fb.h | 42 +++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +Index: linux-2.6.28/arch/arm/mach-stmp3xxx/include/mach/fb.h +=================================================================== +--- /dev/null ++++ linux-2.6.28/arch/arm/mach-stmp3xxx/include/mach/fb.h +@@ -0,0 +1,42 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, ++ * MA 02110-1301, USA. ++ */ ++ ++#ifndef __MACH_FB_H ++# define __MACH_FB_H ++ ++#include <linux/fb.h> ++ ++#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */ ++#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */ ++#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */ ++#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */ ++ ++struct stmfb_platformdata { ++ struct fb_videomode *mode_list; ++ unsigned mode_count; ++ unsigned selected_mode; ++ ++ unsigned max_bpp; ++ ++ unsigned fixed_fb_start; /* force fixed framebuffer address if != NULL */ ++ unsigned fixed_fb_size; /* force fixed size if != NULL */ ++ ++ unsigned dotclk_delay; /* refer manual HW_LCDIF_VDCTRL4 register */ ++ unsigned ld_intf_width; /* refer STMLCDIF_* macros */ ++}; ++ ++#endif /* __MACH_FB_H */ ++ diff --git a/configs/platform-chumby/patches/linux-2.6.28/missuse_of_existing_flags.diff b/configs/platform-chumby/patches/linux-2.6.28/missuse_of_existing_flags.diff new file mode 100644 index 0000000..1687479 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/missuse_of_existing_flags.diff @@ -0,0 +1,24 @@ +From: Juergen Beisert <jbe@pengutronix.de> + +Adapt the display's DE signal to the used display in the ChumbyOne + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + drivers/video/stmfb.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +Index: linux-2.6.28/drivers/video/stmfb.c +=================================================================== +--- linux-2.6.28.orig/drivers/video/stmfb.c ++++ linux-2.6.28/drivers/video/stmfb.c +@@ -437,8 +437,7 @@ static int stmfb_set_par(struct fb_info + reg |= VDCTRL0_HSYNC_POL; + if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) + reg |= VDCTRL0_VSYNC_POL; +- reg |= VDCTRL0_ENABLE_POL; /* FIXME platform specific */ +-/* reg |= VDCTRL0_DOTCLK_POL; */ ++ reg &= ~VDCTRL0_ENABLE_POL; /* FIXME platform specific for Chumby! */ + + /* + * Dotclock mode: diff --git a/configs/platform-chumby/patches/linux-2.6.28/series b/configs/platform-chumby/patches/linux-2.6.28/series new file mode 100644 index 0000000..bb30621 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/series @@ -0,0 +1,20 @@ +# these are the patches to be used for the ChumbyOne within a 2.6.28 kernel +# +# This huge patch stack is for reference only. Its made from the kernel source +# archive available at the chumby homepage +# +chumby.diff.bz2 +fix_getline.diff +#fix_mach_number.diff +#0001-add-really-low-level-printk.patch +0001-Ugly-hack-to-make-ip-config-work.patch +fb_clock_28.diff +stm_fb.diff +support_imx23_28.diff +force_video_mode_without_console.diff +avoid_re_initializing.diff +imx23_2.6.28.fb_h.diff +stm_fb_menu_28.diff +adapt_falconwings_fb.diff +missuse_of_existing_flags.diff +fix_mach_id.diff diff --git a/configs/platform-chumby/patches/linux-2.6.28/stm_fb.diff b/configs/platform-chumby/patches/linux-2.6.28/stm_fb.diff new file mode 100644 index 0000000..7be3a03 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/stm_fb.diff @@ -0,0 +1,925 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Add a useable framebuffer driver for STMP37xx CPUs + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + drivers/video/stmfb.c | 911 ++++++++++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 911 insertions(+) + +Index: linux-2.6.31/drivers/video/stmfb.c +=================================================================== +--- /dev/null ++++ linux-2.6.31/drivers/video/stmfb.c +@@ -0,0 +1,911 @@ ++/* ++ * Copyright (C) 2010 Juergen Beisert, Pengutronix ++ * ++ * This code is based on: ++ * Author: Vitaly Wool <vital@embeddedalley.com> ++ * ++ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. ++ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version 2 ++ * of the License, or (at your option) any later version. ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#define STM_NAME "stmp-fb" ++ ++/** ++ * @file ++ * @brief LCDIF driver for i.MX23 and i.MX28 (i.MX23 untested yet) ++ * ++ * The LCDIF support four modes of operation ++ * - MPU interface (to drive smart displays) -> not supported yet ++ * - VSYNC interface (like MPU interface plus Vsync) -> not supported yet ++ * - Dotclock interface (to drive LC displays with RGB data and sync signals) ++ * - DVI (to drive ITU-R BT656) -> not supported yet ++ * ++ * This driver depends on a correct setup of the pins used for this purpose ++ * (platform specific). ++ * ++ * For the developer: Don't forget to set the data bus width to the display ++ * in the imx_fb_videomode structure. You will else end up with ugly colours. ++ * If you fight against jitter you can vary the clock delay. This is a feature ++ * of the i.MX28 and you can vary it between 2 ns ... 8 ns in 2 ns steps. Give ++ * the required value in the imx_fb_videomode structure. ++ */ ++ ++#define DEBUG ++ ++#include <linux/kernel.h> ++#include <linux/platform_device.h> ++ ++#include <linux/clk.h> ++#include <linux/dma-mapping.h> ++ ++#include <asm/io.h> ++#include <mach/fb.h> ++ ++#ifdef CONFIG_ARCH_MX28 ++# include <mach/mx28.h> ++#endif ++ ++#ifdef CONFIG_ARCH_STMP378X ++# include <mach/regs-lcdif.h> ++#endif ++ ++#define CTRL 0x00 ++# define CTRL_SFTRST (1 << 31) ++# define CTRL_CLKGATE (1 << 30) ++# define CTRL_BYPASS_COUNT (1 << 19) ++# define CTRL_VSYNC_MODE (1 << 18) ++# define CTRL_DOTCLK_MODE (1 << 17) ++# define CTRL_DATA_SELECT (1 << 16) ++# define SET_BUS_WIDTH(x) (((x) & 0x3) << 10) ++# define SET_WORD_LENGTH(x) (((x) & 0x3) << 8) ++# define GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) ++# define CTRL_MASTER (1 << 5) ++# define CTRL_DF16 (1 << 3) ++# define CTRL_DF18 (1 << 2) ++# define CTRL_DF24 (1 << 1) ++# define CTRL_RUN (1 << 0) ++ ++#define CTRL1 0x10 ++# define CTRL1_FIFO_CLEAR (1 << 21) ++# define SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) ++# define GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) ++ ++#define CTRL2 0x20 ++ ++#define TRANSFER_COUNT 0x30 ++# define SET_VCOUNT(x) (((x) & 0xffff) << 16) ++# define SET_HCOUNT(x) ((x) & 0xffff) ++ ++#define CUR_BUF 0x40 ++ ++#define NEXT_BUF 0x50 ++ ++#define TIMING 0x60 ++# define SET_CMD_HOLD(x) (((x) & 0xff) << 24) ++# define SET_CMD_SETUP(x) (((x) & 0xff) << 16) ++# define SET_DATA_HOLD(x) (((x) & 0xff) << 8) ++# define SET_DATA_SETUP(x) ((x) & 0xff)) ++ ++#define VDCTRL0 0x70 ++# define VDCTRL0_ENABLE_PRESENT (1 << 28) ++# define VDCTRL0_VSYNC_POL (1 << 27) /* 0 = low active, 1 = high active */ ++# define VDCTRL0_HSYNC_POL (1 << 26) /* 0 = low active, 1 = high active */ ++# define VDCTRL0_DOTCLK_POL (1 << 25) /* 0 = output at falling edge, capturing at rising edge */ ++# define VDCTRL0_ENABLE_POL (1 << 24) /* 0 = low active, 1 = high active */ ++# define VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) ++# define VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) ++# define VDCTRL0_HALF_LINE (1 << 19) ++# define VDCTRL0_HALF_LINE_MODE (1 << 18) ++# define SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) ++ ++#define VDCTRL1 0x80 ++# define MIN_YRES 120 /* FIXME */ ++# define MAX_YRES 1024 /* FIXME: 0xffffffff */ ++ ++#define VDCTRL2 0x90 ++# define SET_HSYNC_PULSE_WIDTH(x) (((x) & 0x3fff) << 18) ++# define SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) ++ ++#define VDCTRL3 0xa0 ++# define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) ++# define VDCTRL3_VSYNC_ONLY (1 << 28) ++# define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) ++# define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) ++ ++#define VDCTRL4 0xb0 ++# define SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) ++# define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) ++# define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) ++# define MIN_XRES 120 ++# define MAX_XRES 1280 /* FIXME: 0x3ffff */ ++ ++#define DVICTRL0 0xc0 ++#define DVICTRL1 0xd0 ++#define DVICTRL2 0xe0 ++#define DVICTRL3 0xf0 ++#define DVICTRL4 0x100 ++#define DATA 0x180 ++ ++#define DEBUG0 0x1d0 ++# define DEBUG_HSYNC (1 < 26) ++# define DEBUG_VSYNC (1 < 25) ++ ++#define RED 0 ++#define GREEN 1 ++#define BLUE 2 ++#define TRANSP 3 ++ ++struct imxfb_host { ++ struct fb_info fb_info; ++ struct platform_device *pdev; ++ struct clk *clk; ++ void __iomem *base; /* registers */ ++ unsigned allocated_size; ++}; ++ ++#define to_imxfb_host(x) (container_of(x, struct imxfb_host, fb_info)) ++ ++/* the RGB565 true colour mode */ ++static const struct fb_bitfield def_rgb565[] = { ++ [RED] = { ++ .offset = 11, ++ .length = 5, ++ }, ++ [GREEN] = { ++ .offset = 5, ++ .length = 6, ++ }, ++ [BLUE] = { ++ .offset = 0, ++ .length = 5, ++ }, ++ [TRANSP] = { /* no support for transparency */ ++ .length = 0, ++ } ++}; ++ ++/* the RGB666 true colour mode */ ++static const struct fb_bitfield def_rgb666[] = { ++ [RED] = { ++ .offset = 16, ++ .length = 6, ++ }, ++ [GREEN] = { ++ .offset = 8, ++ .length = 6, ++ }, ++ [BLUE] = { ++ .offset = 0, ++ .length = 6, ++ }, ++ [TRANSP] = { /* no support for transparency */ ++ .length = 0, ++ } ++}; ++ ++/* the RGB888 true colour mode */ ++static const struct fb_bitfield def_rgb888[] = { ++ [RED] = { ++ .offset = 16, ++ .length = 8, ++ }, ++ [GREEN] = { ++ .offset = 8, ++ .length = 8, ++ }, ++ [BLUE] = { ++ .offset = 0, ++ .length = 8, ++ }, ++ [TRANSP] = { /* no support for transparency */ ++ .length = 0, ++ } ++}; ++ ++static inline unsigned chan_to_field(unsigned chan, struct fb_bitfield *bf) ++{ ++ chan &= 0xffff; ++ chan >>= 16 - bf->length; ++ return chan << bf->offset; ++} ++ ++static int stmfb_set_lcdifclk(struct imxfb_host *host, unsigned nc) ++{ ++ int ret; ++ ++ ret = clk_set_rate(host->clk, nc * 1000U); ++ if (ret != 0) { ++ pr_debug("Cannot set requested pixel frequency of %u MHz\n", ++ nc / 1000); ++ } ++ ++ pr_debug("Pixel clock is running at %d Hz\n", clk_get_rate(host->clk)); ++ ++ return 0; ++} ++ ++static inline unsigned stmfb_calc_line_length(unsigned ppl, unsigned bpp) ++{ ++ if (bpp == 24) ++ bpp = 32; ++ return (ppl * bpp) >> 3; ++} ++ ++/* check if the requested videomode is supported */ ++static int stmfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb_info) ++{ ++ struct imxfb_host *host = to_imxfb_host(fb_info); ++ struct stmfb_platformdata *pdata = host->pdev->dev.platform_data; ++ const struct fb_bitfield *rgb = NULL; ++ ++ pr_debug("%s\n", __func__); ++ ++ if (var->xres < MIN_XRES) ++ var->xres = MIN_XRES; ++ if (var->yres < MIN_YRES) ++ var->yres = MIN_YRES; ++ var->xres_virtual = max(var->xres_virtual, var->xres); ++ var->yres_virtual = max(var->yres_virtual, var->yres); ++ ++ pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); ++ ++ switch (var->bits_per_pixel) { ++ case 8: ++ pr_warning("8 bpp mode not supported yet\n"); ++ break; ++ case 16: ++ pr_debug("Setting up an RGB565 mode\n"); ++ /* always expect RGB 565 */ ++ rgb = def_rgb565; ++ break; ++ case 24: ++ case 32: ++ pr_debug("Setting up an RGB888/666 mode\n"); ++ switch (pdata->ld_intf_width) { ++ case STMLCDIF_8BIT: ++ pr_debug("Unsupported LCD bus width mapping\n"); ++ break; ++ case STMLCDIF_16BIT: ++ case STMLCDIF_18BIT: ++ /* 24 bit to 18 bit mapping */ ++ rgb = def_rgb666; ++ break; ++ case STMLCDIF_24BIT: ++ /* real 24 bit */ ++ rgb = def_rgb888; ++ break; ++ } ++ break; ++ default: ++ pr_debug("Unsupported colour depth: %u\n", var->bits_per_pixel); ++ } ++ ++ if (rgb == NULL) { ++ return -EINVAL; ++ } ++ /* ++ * Copy the RGB parameters for this display ++ * from the machine specific parameters. ++ */ ++ var->red = rgb[RED]; ++ var->green = rgb[GREEN]; ++ var->blue = rgb[BLUE]; ++ var->transp = rgb[TRANSP]; ++ ++ return 0; ++} ++ ++static void stmfb_enable_controller(struct imxfb_host*); ++static void stmfb_disable_controller(struct imxfb_host*); ++ ++/* setup the requested videomode */ ++static int stmfb_set_par(struct fb_info *fb_info) ++{ ++ struct imxfb_host *host = to_imxfb_host(fb_info); ++ struct stmfb_platformdata *pdata = host->pdev->dev.platform_data; ++ uint32_t reg; ++ int ret; ++ unsigned size; ++ ++ pr_debug("%s\n", __func__); ++ ++ /* ++ * It seems, you can't re-program the controller if it is still running. ++ * This may lead into shifted pictures (FIFO issue?). ++ * So, first stop the controller and drain its FIFOs ++ */ ++ reg = readl(host->base + CTRL); ++ if (reg & CTRL_RUN) ++ stmfb_disable_controller(host); ++ ++ /* clear the FIFOs */ ++ writel(CTRL1_FIFO_CLEAR, host->base + CTRL1 + 4); ++ ++ ret = stmfb_set_lcdifclk(host, PICOS2KHZ(fb_info->var.pixclock)); ++ if (ret != 0) { ++ pr_debug("Unable to set a valid pixel clock\n"); ++ return -EINVAL; ++ } ++ ++ /* ++ * bring the controller out of reset and ++ * configure it into DOTCLOCK mode ++ */ ++ reg = CTRL_BYPASS_COUNT | /* always in DOTCLOCK mode */ ++ CTRL_DOTCLK_MODE; ++ writel(reg, host->base + CTRL); ++ ++ /* master mode only */ ++ reg |= CTRL_MASTER; ++ ++ /* ++ * Configure videomode and interface mode ++ */ ++ reg |= SET_BUS_WIDTH(pdata->ld_intf_width); ++ switch (fb_info->var.bits_per_pixel) { ++ case 8: ++ reg |= SET_WORD_LENGTH(1); ++ /* TODO refer manual page 2046 */ ++ pr_warning("8 bpp mode not supported yet\n"); ++ fb_info->fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ break; ++ case 16: ++ pr_debug("Setting up an RGB565 mode\n"); ++ reg |= SET_WORD_LENGTH(0); ++ reg &= ~CTRL_DF16; /* we assume RGB565 */ ++ writel(SET_BYTE_PACKAGING(0xf), host->base + CTRL1); ++ fb_info->fix.visual = FB_VISUAL_TRUECOLOR; ++ break; ++ case 24: ++ case 32: ++ pr_debug("Setting up an RGB888/666 mode\n"); ++ reg |= SET_WORD_LENGTH(3); ++ switch (pdata->ld_intf_width) { ++ case STMLCDIF_8BIT: ++ pr_debug("Unsupported LCD bus width mapping\n"); ++ break; ++ case STMLCDIF_16BIT: ++ case STMLCDIF_18BIT: ++ /* 24 bit to 18 bit mapping */ ++ reg |= CTRL_DF24; /* ignore the upper 2 bits in each colour component */ ++ break; ++ case STMLCDIF_24BIT: ++ /* real 24 bit */ ++ break; ++ } ++ /* do not use packed pixels = one pixel per word instead */ ++ writel(SET_BYTE_PACKAGING(0x7), host->base + CTRL1); ++ fb_info->fix.visual = FB_VISUAL_TRUECOLOR; ++ break; ++ default: ++ pr_debug("Unhandled colour depth of %u\n", fb_info->var.bits_per_pixel); ++ return -EINVAL; ++ } ++ writel(reg, host->base + CTRL); ++ pr_debug("Setting up CTRL to %08X\n", reg); ++ ++ writel(SET_VCOUNT(fb_info->var.yres) | ++ SET_HCOUNT(fb_info->var.xres), host->base + TRANSFER_COUNT); ++ ++ reg = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ ++ VDCTRL0_VSYNC_PERIOD_UNIT | ++ VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; ++ if (fb_info->var.sync & FB_SYNC_HOR_HIGH_ACT) ++ reg |= VDCTRL0_HSYNC_POL; ++ if (fb_info->var.sync & FB_SYNC_VERT_HIGH_ACT) ++ reg |= VDCTRL0_VSYNC_POL; ++ reg |= VDCTRL0_ENABLE_POL; /* FIXME platform specific */ ++/* reg |= VDCTRL0_DOTCLK_POL; */ ++ ++/* ++ * Dotclock mode: ++ * One line of pixels or one frame in the i.MX28 is defined to: ++ * ++ * |<---------------------- one line period -------------------------------->| ++ * |<- HSync length ->| ++ * |<----- Start of line --->| ++ * |<-------- active line data ------>| ++ * ++ * |<------------------------ frame period --------------------------------->| ++ * |<- VSync length ->| ++ * |<--- Start of 1. line -->| ++ * |<---------- active lines -------->| ++ * ++ * Based on the values from struct fb_videomode: ++ * - "one line period" = left_margin + xres + right_margin + hsync_len ++ * - "HSync length" = hsync_len ++ * - "Start of line" = hsync_len + left_margin ++ * - "active line data" = xres ++ */ ++ ++ reg |= SET_VSYNC_PULSE_WIDTH(fb_info->var.vsync_len); ++ writel(reg, host->base + VDCTRL0); ++ ++ /* frame length in lines */ ++ writel(fb_info->var.upper_margin + fb_info->var.vsync_len + ++ fb_info->var.lower_margin + fb_info->var.yres, ++ host->base + VDCTRL1); ++ ++ /* line length in units of clocks or pixels */ ++ writel(SET_HSYNC_PULSE_WIDTH(fb_info->var.hsync_len) | ++ SET_HSYNC_PERIOD(fb_info->var.left_margin + ++ fb_info->var.hsync_len + fb_info->var.right_margin + ++ fb_info->var.xres), ++ host->base + VDCTRL2); ++ ++ writel(SET_HOR_WAIT_CNT(fb_info->var.left_margin + ++ fb_info->var.hsync_len) | ++ SET_VERT_WAIT_CNT(fb_info->var.upper_margin + ++ fb_info->var.vsync_len), ++ host->base + VDCTRL3); ++ ++ writel( ++#ifdef CONFIG_ARCH_MX28 ++ SET_DOTCLK_DLY(pdata->dotclk_delay) | ++#endif ++ SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres), ++ host->base + VDCTRL4); ++ ++ writel(fb_info->fix.smem_start, host->base + CUR_BUF); ++ /* always show one framebuffer only */ ++ writel(fb_info->fix.smem_start, host->base + NEXT_BUF); ++ ++ /* everything is ready to use now. Launch the video signals */ ++ stmfb_enable_controller(host); ++ ++ return 0; ++} ++ ++static int stmfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, u_int transp, struct fb_info *fb_info) ++{ ++ struct imxfb_host *host = to_imxfb_host(fb_info); ++ unsigned int val; ++ int ret = -EINVAL; ++ ++ /* ++ * If inverse mode was selected, invert all the colours ++ * rather than the register number. The register number ++ * is what you poke into the framebuffer to produce the ++ * colour you requested. ++ */ ++#if 0 ++ if (fbi->cmap_inverse) { ++ red = 0xffff - red; ++ green = 0xffff - green; ++ blue = 0xffff - blue; ++ } ++#endif ++ /* ++ * If greyscale is true, then we convert the RGB value ++ * to greyscale no mater what visual we are using. ++ */ ++ if (fb_info->var.grayscale) ++ red = green = blue = (19595 * red + 38470 * green + ++ 7471 * blue) >> 16; ++ ++ switch (fb_info->fix.visual) { ++ case FB_VISUAL_TRUECOLOR: ++ /* ++ * 12 or 16-bit True Colour. We encode the RGB value ++ * according to the RGB bitfield information. ++ */ ++ if (regno < 16) { ++ u32 *pal = fb_info->pseudo_palette; ++ ++ val = chan_to_field(red, &fb_info->var.red); ++ val |= chan_to_field(green, &fb_info->var.green); ++ val |= chan_to_field(blue, &fb_info->var.blue); ++ ++ pal[regno] = val; ++ ret = 0; ++ } ++ break; ++ ++ case FB_VISUAL_STATIC_PSEUDOCOLOR: ++ case FB_VISUAL_PSEUDOCOLOR: ++ pr_warning("Not yet programmed\n"); ++ break; ++ } ++ ++ return ret; ++} ++ ++static int stmfb_ioctl(struct fb_info *fb_info, unsigned int cmd, unsigned long arg) ++{ ++ /* struct imxfb_host *host = to_imxfb_host(fb_info); */ ++ ++ pr_debug("%s\n", __func__); ++ ++ return -EINVAL; ++} ++ ++static int stmfb_blank(int blank, struct fb_info *fb_info) ++{ ++ /* struct imxfb_host *host = to_imxfb_host(fb_info); */ ++ ++ pr_debug("%s\n", __func__); ++ ++ return 0; ++} ++ ++static int stmfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *fb_info) ++{ ++ /* struct imxfb_host *host = to_imxfb_host(fb_info); */ ++ ++ pr_debug("%s\n", __func__); ++ ++ return 0; ++} ++ ++static struct fb_ops stmfb_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = stmfb_check_var, ++ .fb_set_par = stmfb_set_par, ++ .fb_setcolreg = stmfb_setcolreg, ++ .fb_ioctl = stmfb_ioctl, ++ .fb_blank = stmfb_blank, ++ .fb_pan_display = stmfb_pan_display, ++ .fb_fillrect = cfb_fillrect, ++ .fb_copyarea = cfb_copyarea, ++ .fb_imageblit = cfb_imageblit, ++}; ++ ++/* FIXME shouldn'd it be done on a per videomode base? */ ++static int __devinit acquire_videomemory(struct imxfb_host *host) ++{ ++ struct stmfb_platformdata *pdata = host->pdev->dev.platform_data; ++ dma_addr_t map_dma; ++ unsigned size; ++ ++ pr_debug("%s\n", __func__); ++ ++ if ((pdata->fixed_fb_start != 0U) && (pdata->fixed_fb_size != 0)) { ++ /* fixed framebuffer area */ ++ pr_debug("Going to map area beginning at %08x with size %x\n", pdata->fixed_fb_start, pdata->fixed_fb_size); ++ size = PAGE_ALIGN(pdata->fixed_fb_size); ++ host->fb_info.screen_base = ioremap_wc(pdata->fixed_fb_start, size); ++ if (host->fb_info.screen_base == NULL) { ++ dev_err(&host->pdev->dev, "Cannot map area at %08x\n", pdata->fixed_fb_start); ++ return -ENXIO; ++ } ++ /* is this the mmio_start/mmio_len meaning? */ ++ host->fb_info.fix.smem_start = pdata->fixed_fb_start; ++ host->fb_info.fix.smem_len = size; ++ host->allocated_size = 0; ++ } else { ++ /* dynamic framebuffer area */ ++ pr_debug("Going to allocate a framebuffer from generic RAM\n"); ++#ifdef DEBUG ++ if ((pdata->fixed_fb_start != NULL) || (pdata->fixed_fb_size != 0)) ++ dev_warn(&host->pdev->dev, "Only one param for fixed framebuffer set. Ignored\n"); ++#endif ++ host->allocated_size = host->fb_info.var.xres * host->fb_info.var.yres * host->fb_info.var.bits_per_pixel; ++ host->allocated_size >>= 3; ++ host->allocated_size = PAGE_ALIGN(host->allocated_size); ++ host->fb_info.screen_base = dma_alloc_writecombine(&host->pdev->dev, host->allocated_size, &map_dma, GFP_KERNEL); ++ if (host->fb_info.screen_base == NULL) { ++ dev_err(&host->pdev->dev, "Cannot allocat framebuffer memoryX\n"); ++ return -ENXIO; ++ } ++ host->fb_info.fix.smem_start = map_dma; ++ host->fb_info.fix.smem_len = host->allocated_size; ++ pr_debug("Mapping framebuffer to virtual memory %X (%X bytes @ %X)\n", host->fb_info.screen_base, host->fb_info.fix.smem_len, host->fb_info.fix.smem_start); ++ } ++ ++ /* the used screen size */ ++ host->fb_info.screen_size = (host->fb_info.var.xres * host->fb_info.var.yres * host->fb_info.var.bits_per_pixel) >> 3; ++ host->fb_info.fix.line_length = stmfb_calc_line_length(host->fb_info.var.xres, host->fb_info.var.bits_per_pixel); ++ pr_debug("Used screen size is 0x%X bytes, line length is %d bytes\n", host->fb_info.screen_size, host->fb_info.fix.line_length); ++ ++ return 0; ++} ++ ++static void stmfb_enable_controller(struct imxfb_host *host) ++{ ++ uint32_t reg, last_reg; ++ unsigned loop, edges; ++ ++ pr_debug("%s\n", __func__); ++ ++ /* if it was disabled, re-enable the mode again */ ++ reg = readl(host->base + CTRL); ++ reg |= CTRL_DOTCLK_MODE; ++ writel(reg, host->base + CTRL); ++ ++ /* enable the SYNC signals first, then the DMA engine */ ++ reg = readl(host->base + VDCTRL4); ++ reg |= VDCTRL4_SYNC_SIGNALS_ON; ++ writel(reg, host->base + VDCTRL4); ++ ++ /* ++ * Give the attached LC display or monitor a chance to sync into ++ * our signals. ++ * Wait for at least 2 VSYNCs = four VSYNC edges ++ */ ++ edges = 4; ++ ++ while (edges != 0) { ++ loop = 800; ++ last_reg = readl(host->base + DEBUG0) & DEBUG_VSYNC; ++ do { ++ reg = readl(host->base + DEBUG0) & DEBUG_VSYNC; ++ if (reg != last_reg); ++ break; ++ last_reg = reg; ++ loop--; ++ } while (loop != 0); ++ edges--; ++ } ++ ++ reg = readl(host->base + CTRL); ++ reg |= CTRL_RUN; ++ writel(reg, host->base + CTRL); ++} ++ ++static void stmfb_disable_controller(struct imxfb_host *host) ++{ ++ unsigned loop; ++ uint32_t reg; ++ ++ pr_debug("%s\n", __func__); ++ /* ++ * Even if we disable the controller here, it will still continue ++ * until its FIFOs are running out of data ++ */ ++ reg = readl(host->base + CTRL); ++ reg &= ~CTRL_DOTCLK_MODE; ++ writel(reg, host->base + CTRL); ++ ++ loop = 1000; ++ while (loop) { ++ reg = readl(host->base + CTRL); ++ if (!(reg & CTRL_RUN)) ++ break; ++ loop--; ++ } ++ ++ reg = readl(host->base + VDCTRL4); ++ reg &= ~VDCTRL4_SYNC_SIGNALS_ON; ++ writel(reg, host->base + VDCTRL4); ++} ++ ++static void stmfb_free_videomemory(struct imxfb_host *host) ++{ ++ struct stmfb_platformdata *pdata = host->pdev->dev.platform_data; ++ ++ pr_debug("%s\n", __func__); ++ ++ if ((pdata->fixed_fb_start != NULL) && (pdata->fixed_fb_size != 0)) ++ iounmap(host->fb_info.screen_base); ++ else ++ dma_free_writecombine(&host->pdev->dev, host->allocated_size, ++ host->fb_info.screen_base, host->fb_info.fix.smem_start); ++} ++ ++static int __devinit stmfb_init_fbinfo(struct imxfb_host *host) ++{ ++ struct fb_info *fb_info = &host->fb_info; ++ struct stmfb_platformdata *pdata = host->pdev->dev.platform_data; ++ struct fb_videomode *vmode; ++ ++ pr_debug("%s\n", __func__); ++ ++ if ((pdata->mode_list == NULL) || (pdata->mode_count == 0)) { ++ dev_err(&host->pdev->dev, "No video output device defined\n"); ++ return -ENODEV; ++ } ++ ++ vmode = &pdata->mode_list[pdata->selected_mode]; ++ ++ fb_info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); ++ if (!fb_info->pseudo_palette) ++ return -ENOMEM; ++ ++ strlcpy(fb_info->fix.id, STM_NAME, sizeof(fb_info->fix.id)); ++ ++ fb_info->fix.type = FB_TYPE_PACKED_PIXELS; ++ fb_info->fix.type_aux = 0; ++ fb_info->fix.xpanstep = 0; ++ fb_info->fix.ypanstep = 0; ++ fb_info->fix.ywrapstep = 0; ++ fb_info->fix.accel = FB_ACCEL_NONE; ++ ++ fb_info->var.nonstd = 0; ++ fb_info->var.activate = FB_ACTIVATE_NOW; ++ fb_info->var.height = -1; ++ fb_info->var.width = -1; ++ fb_info->var.accel_flags = 0; ++ fb_info->var.vmode = FB_VMODE_NONINTERLACED; ++ ++ fb_info->fbops = &stmfb_ops; ++ fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; ++ ++ fb_info->var.xres = fb_info->var.xres_virtual = vmode->xres; ++ fb_info->var.yres = fb_info->var.yres_virtual = vmode->yres; ++ ++ fb_info->var.bits_per_pixel = pdata->max_bpp; ++ fb_info->var.nonstd = 0; ++ fb_info->var.pixclock = vmode->pixclock; ++ fb_info->var.hsync_len = vmode->hsync_len; ++ fb_info->var.left_margin = vmode->left_margin; ++ fb_info->var.right_margin = vmode->right_margin; ++ fb_info->var.vsync_len = vmode->vsync_len; ++ fb_info->var.upper_margin = vmode->upper_margin; ++ fb_info->var.lower_margin = vmode->lower_margin; ++ fb_info->var.sync = vmode->sync; ++ fb_info->var.grayscale = 0; /* TODO */ ++ ++ return 0; ++} ++ ++#ifdef CONFIG_ARCH_MX28 ++# define LCD_PIX_CLOCK_NAME "dis_lcdif" ++#endif ++#ifdef CONFIG_ARCH_STMP378X ++# define LCD_PIX_CLOCK_NAME "lcdif" ++#endif ++ ++static int stmfb_init_clocks(struct imxfb_host *host) ++{ ++ int ret = 0; ++ ++ pr_debug("%s\n", __func__); ++ ++ host->clk = clk_get(&host->pdev->dev, LCD_PIX_CLOCK_NAME); ++ if (IS_ERR(host->clk)) { ++ ret = PTR_ERR(host->clk); ++ goto out; ++ } ++ ++ ret = clk_enable(host->clk); ++ if (ret != 0) { ++ clk_put(host->clk); ++ goto out; ++ } ++ ++out: ++ return ret; ++} ++ ++static int __devinit stmfb_probe(struct platform_device *pdev) ++{ ++ struct stmfb_platformdata *pdata = pdev->dev.platform_data; ++ struct resource *main_res, *res; ++ struct imxfb_host *host; ++ struct fb_info *fb_info; ++ int ret; ++ ++ pr_debug("%s\n", __func__); ++ ++ if (pdata == NULL) { ++ dev_err(&pdev->dev, "No platformdata. Giving up\n"); ++ return -ENODEV; ++ } ++ ++ main_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (main_res == NULL) { ++ dev_err(&pdev->dev, "Cannot get memory IO resource\n"); ++ return -ENODEV; ++ } ++ ++ res = request_mem_region(main_res->start, resource_size(main_res), ++ STM_NAME); ++ if (res == NULL) { ++ dev_err(&pdev->dev, "Can't request memory IO area\n"); ++ return -ENXIO; ++ } ++ ++ fb_info = framebuffer_alloc(sizeof(struct imxfb_host), &pdev->dev); ++ if (fb_info == NULL) { ++ dev_err(&pdev->dev, "Failed to allocate fbdev\n"); ++ ret = -ENOMEM; ++ goto error_request; ++ } ++ ++ host = to_imxfb_host(fb_info); ++ ++ /* what is its meaning? Hardware register or a separate framebuffer memory? */ ++ fb_info->fix.mmio_start = main_res->start; ++ fb_info->fix.mmio_len = resource_size(main_res); ++ ++#ifdef CONFIG_ARCH_MX28 ++ /* FIXME: No ioremap()? */ ++ host->base = IO_ADDRESS(res->start); ++#endif ++#ifdef CONFIG_ARCH_STMP378X ++ /* FIXME: No ioremap()? */ ++ host->base = REGS_LCDIF_BASE; ++#endif ++ host->pdev = pdev; ++ platform_set_drvdata(pdev, host); ++ ++ ret = stmfb_init_clocks(host); ++ if (ret != 0) ++ goto error_getclock; ++ ++ ret = stmfb_init_fbinfo(host); ++ if (ret != 0) ++ goto error_videomemory; ++ ++ ret = acquire_videomemory(host); ++ if (ret != 0) ++ goto error_videomemory; ++ ++ /* init the colour bitfields */ ++ stmfb_check_var(&fb_info->var, fb_info); ++ ++ ret = fb_alloc_cmap(&fb_info->cmap, 1 << fb_info->var.bits_per_pixel, 0); ++ if (ret < 0) ++ goto failed_cmap; ++ ++ ret = register_framebuffer(fb_info); ++ if (ret != 0) { ++ dev_err(&pdev->dev,"Failed to register framebuffer\n"); ++ goto failed_register; ++ } ++ ++ return 0; ++ ++failed_register: ++ fb_dealloc_cmap(&fb_info->cmap); ++ ++failed_cmap: ++ stmfb_free_videomemory(host); ++ ++error_videomemory: ++ clk_put(host->clk); ++ ++error_getclock: ++ framebuffer_release(fb_info); ++ ++error_request: ++ release_mem_region(main_res->start, resource_size(main_res)); ++ ++ platform_set_drvdata(pdev, NULL); ++ return ret; ++} ++ ++static int __devexit stmfb_remove(struct platform_device *pdev) ++{ ++ /* TODO */ ++ return 0; ++} ++ ++static void stmfb_shutdown(struct platform_device *pdev) ++{ ++ struct imxfb_host *host = platform_get_drvdata(pdev); ++ ++ stmfb_disable_controller(host); ++} ++ ++static struct platform_driver stmpfbdriver = { ++ .probe = stmfb_probe, ++ .shutdown = stmfb_shutdown, ++ .remove = __devexit_p(stmfb_remove), ++ .driver = { ++ .name = STM_NAME, ++ }, ++}; ++ ++static int __init stmpfbinit(void) ++{ ++ pr_debug("%s\n", __func__); ++ return platform_driver_register(&stmpfbdriver); ++} ++ ++static void __exit stmpfbexit(void) ++{ ++ platform_driver_unregister(&stmpfbdriver); ++} ++ ++module_init(stmpfbinit); ++module_exit(stmpfbexit); diff --git a/configs/platform-chumby/patches/linux-2.6.28/stm_fb_menu_28.diff b/configs/platform-chumby/patches/linux-2.6.28/stm_fb_menu_28.diff new file mode 100644 index 0000000..976c754 --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/stm_fb_menu_28.diff @@ -0,0 +1,53 @@ +From: Juergen Beisert <jbe@pengutronix.de> +Subject: Add a i.MX23/8 framebuffer driver to a 2.6.38 kernel + +Signed-off-by: Juergen Beisert <jbe@pengutronix.de> + +--- + drivers/video/Kconfig | 13 ++++++++++++- + drivers/video/Makefile | 1 + + 2 files changed, 13 insertions(+), 1 deletion(-) + +Index: linux-2.6.28/drivers/video/Kconfig +=================================================================== +--- linux-2.6.28.orig/drivers/video/Kconfig ++++ linux-2.6.28/drivers/video/Kconfig +@@ -385,6 +385,17 @@ if ARCH_MXC + source "drivers/video/mxc/Kconfig" + endif + ++config FB_PTXSTMP ++ bool ++ prompt "PTX's STMP37XX framebuffer driver" ++ depends on FB && (ARCH_STMP378X || ARCH_MXS) ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ help ++ Enable a nice and working framebuffer driver for the STMP37XX or ++ i.MXS processor family ++ + config FB_SA1100 + bool "SA-1100 LCD support" + depends on (FB = y) && ARM && ARCH_SA1100 +@@ -2134,7 +2145,7 @@ config FB_CHUMBYFBFW + + config FB_PRE_INIT_FB + bool "Don't reinitialize, use bootloader's GDC/Display configuration" +- depends on FB_MB862XX_LIME ++ depends on FB_MB862XX_LIME || FB_PTXSTMP + ---help--- + Select this option if display contents should be inherited as set by + the bootloader. +Index: linux-2.6.28/drivers/video/Makefile +=================================================================== +--- linux-2.6.28.orig/drivers/video/Makefile ++++ linux-2.6.28/drivers/video/Makefile +@@ -120,6 +120,7 @@ obj-$(CONFIG_FB_STMP37XX) += stmp37xxf + obj-$(CONFIG_FB_IBM_GXT4500) += gxt4500.o + obj-$(CONFIG_FB_PS3) += ps3fb.o + obj-$(CONFIG_FB_SM501) += sm501fb.o ++obj-$(CONFIG_FB_PTXSTMP) += stmfb.o + obj-$(CONFIG_FB_XILINX) += xilinxfb.o + obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o + obj-$(CONFIG_FB_OMAP) += omap/ diff --git a/configs/platform-chumby/patches/linux-2.6.28/support_imx23_28.diff b/configs/platform-chumby/patches/linux-2.6.28/support_imx23_28.diff new file mode 100644 index 0000000..852f58d --- /dev/null +++ b/configs/platform-chumby/patches/linux-2.6.28/support_imx23_28.diff @@ -0,0 +1,325 @@ +Distinguish i.MX23 and i.MX28 at runtime + +Note: To be merged with the whole driver patch. Currently separate for +development only. + +--- + drivers/video/stmfb.c | 173 ++++++++++++++++++++++++++++++++------------------ + 1 file changed, 114 insertions(+), 59 deletions(-) + +Index: linux-2.6.31/drivers/video/stmfb.c +=================================================================== +--- linux-2.6.31.orig/drivers/video/stmfb.c ++++ linux-2.6.31/drivers/video/stmfb.c +@@ -49,13 +49,18 @@ + + #include <asm/io.h> + #include <mach/fb.h> ++#include <mach/hardware.h> + + #ifdef CONFIG_ARCH_MX28 + # include <mach/mx28.h> ++#define REGS_LCDIF_BASE 0 /* FIXME its from STMP */ ++# define cpu_is_stmp378x() (0) + #endif + + #ifdef CONFIG_ARCH_STMP378X + # include <mach/regs-lcdif.h> ++# include <mach/cpu.h> ++# define cpu_is_mx28() (0) + #endif + + #define CTRL 0x00 +@@ -66,6 +71,7 @@ + # define CTRL_DOTCLK_MODE (1 << 17) + # define CTRL_DATA_SELECT (1 << 16) + # define SET_BUS_WIDTH(x) (((x) & 0x3) << 10) ++# define GET_BUS_WIDTH(x) (((x) >> 10) & 0x3) + # define SET_WORD_LENGTH(x) (((x) & 0x3) << 8) + # define GET_WORD_LENGTH(x) (((x) >> 8) & 0x3) + # define CTRL_MASTER (1 << 5) +@@ -79,15 +85,18 @@ + # define SET_BYTE_PACKAGING(x) (((x) & 0xf) << 16) + # define GET_BYTE_PACKAGING(x) (((x) >> 16) & 0xf) + +-#define CTRL2 0x20 +- +-#define TRANSFER_COUNT 0x30 ++#define MX28_CTRL2 0x20 ++#define MX28_TRANSFER_COUNT 0x30 ++#define MX23_TRANSFER_COUNT 0x20 + # define SET_VCOUNT(x) (((x) & 0xffff) << 16) ++# define GET_VCOUNT(x) (((x) >> 16) & 0xffff) + # define SET_HCOUNT(x) ((x) & 0xffff) ++# define GET_HCOUNT(x) ((x) & 0xffff) + +-#define CUR_BUF 0x40 +- +-#define NEXT_BUF 0x50 ++#define MX28_CUR_BUF 0x40 ++#define MX28_NEXT_BUF 0x50 ++#define MX23_CUR_BUF 0x30 ++#define MX23_NEXT_BUF 0x40 + + #define TIMING 0x60 + # define SET_CMD_HOLD(x) (((x) & 0xff) << 24) +@@ -106,23 +115,27 @@ + # define VDCTRL0_HALF_LINE (1 << 19) + # define VDCTRL0_HALF_LINE_MODE (1 << 18) + # define SET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) ++# define GET_VSYNC_PULSE_WIDTH(x) ((x) & 0x3ffff) + + #define VDCTRL1 0x80 + # define MIN_YRES 120 /* FIXME */ + # define MAX_YRES 1024 /* FIXME: 0xffffffff */ + + #define VDCTRL2 0x90 +-# define SET_HSYNC_PULSE_WIDTH(x) (((x) & 0x3fff) << 18) + # define SET_HSYNC_PERIOD(x) ((x) & 0x3ffff) ++# define GET_HSYNC_PERIOD(x) ((x) & 0x3ffff) + + #define VDCTRL3 0xa0 + # define VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) + # define VDCTRL3_VSYNC_ONLY (1 << 28) + # define SET_HOR_WAIT_CNT(x) (((x) & 0xfff) << 16) ++# define GET_HOR_WAIT_CNT(x) (((x) >> 16) & 0xfff) + # define SET_VERT_WAIT_CNT(x) ((x) & 0xffff) ++# define GET_VERT_WAIT_CNT(x) ((x) & 0xffff) + + #define VDCTRL4 0xb0 +-# define SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) ++# define SET_DOTCLK_DLY(x) (((x) & 0x7) << 29) /* i.MX28 only */ ++# define GET_DOTCLK_DLY(x) (((x) >> 29) & 0x7) /* i.MX28 only */ + # define VDCTRL4_SYNC_SIGNALS_ON (1 << 18) + # define SET_DOTCLK_H_VALID_DATA_CNT(x) ((x) & 0x3ffff) + # define MIN_XRES 120 +@@ -133,9 +146,11 @@ + #define DVICTRL2 0xe0 + #define DVICTRL3 0xf0 + #define DVICTRL4 0x100 +-#define DATA 0x180 ++#define MX28_DATA 0x180 ++#define MX23_DATA 0x1b0 + +-#define DEBUG0 0x1d0 ++#define MX28_DEBUG0 0x1d0 ++#define MX23_DEBUG0 0x1f0 + # define DEBUG_HSYNC (1 < 26) + # define DEBUG_VSYNC (1 < 25) + +@@ -150,10 +165,28 @@ struct imxfb_host { + struct clk *clk; + void __iomem *base; /* registers */ + unsigned allocated_size; ++ ++ unsigned transfer_count; /* CPU dependend register offset */ ++ unsigned cur_buf; ++ unsigned next_buf; ++ unsigned debug0; ++ unsigned hs_wdth_mask; ++ unsigned hs_wdth_shift; + }; + + #define to_imxfb_host(x) (container_of(x, struct imxfb_host, fb_info)) + ++/* mask and shift depends on architecture */ ++static inline uint32_t set_hsync_pulse_width(struct imxfb_host *host, unsigned val) ++{ ++ return (val & host->hs_wdth_mask) << host->hs_wdth_shift; ++} ++ ++static inline uint32_t get_hsync_pulse_width(struct imxfb_host *host, unsigned val) ++{ ++ return (val >> host->hs_wdth_shift) & host->hs_wdth_mask; ++} ++ + /* the RGB565 true colour mode */ + static const struct fb_bitfield def_rgb565[] = { + [RED] = { +@@ -394,7 +427,7 @@ static int stmfb_set_par(struct fb_info + pr_debug("Setting up CTRL to %08X\n", reg); + + writel(SET_VCOUNT(fb_info->var.yres) | +- SET_HCOUNT(fb_info->var.xres), host->base + TRANSFER_COUNT); ++ SET_HCOUNT(fb_info->var.xres), host->base + host->transfer_count); + + reg = VDCTRL0_ENABLE_PRESENT | /* always in DOTCLOCK mode */ + VDCTRL0_VSYNC_PERIOD_UNIT | +@@ -436,7 +469,7 @@ static int stmfb_set_par(struct fb_info + host->base + VDCTRL1); + + /* line length in units of clocks or pixels */ +- writel(SET_HSYNC_PULSE_WIDTH(fb_info->var.hsync_len) | ++ writel(set_hsync_pulse_width(host, fb_info->var.hsync_len) | + SET_HSYNC_PERIOD(fb_info->var.left_margin + + fb_info->var.hsync_len + fb_info->var.right_margin + + fb_info->var.xres), +@@ -448,16 +481,14 @@ static int stmfb_set_par(struct fb_info + fb_info->var.vsync_len), + host->base + VDCTRL3); + +- writel( +-#ifdef CONFIG_ARCH_MX28 +- SET_DOTCLK_DLY(pdata->dotclk_delay) | +-#endif +- SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres), +- host->base + VDCTRL4); ++ reg = SET_DOTCLK_H_VALID_DATA_CNT(fb_info->var.xres); ++ if (cpu_is_mx28()) ++ reg |= SET_DOTCLK_DLY(pdata->dotclk_delay); ++ writel(reg, host->base + VDCTRL4); + +- writel(fb_info->fix.smem_start, host->base + CUR_BUF); ++ writel(fb_info->fix.smem_start, host->base + host->cur_buf); + /* always show one framebuffer only */ +- writel(fb_info->fix.smem_start, host->base + NEXT_BUF); ++ writel(fb_info->fix.smem_start, host->base + host->next_buf); + + /* everything is ready to use now. Launch the video signals */ + stmfb_enable_controller(host); +@@ -635,14 +666,15 @@ static void stmfb_enable_controller(stru + + while (edges != 0) { + loop = 800; +- last_reg = readl(host->base + DEBUG0) & DEBUG_VSYNC; ++ last_reg = readl(host->base + host->debug0) & DEBUG_VSYNC; + do { +- reg = readl(host->base + DEBUG0) & DEBUG_VSYNC; ++ reg = readl(host->base + host->debug0) & DEBUG_VSYNC; + if (reg != last_reg); + break; + last_reg = reg; + loop--; + } while (loop != 0); ++ /* FIXME really wait a whole frame! */ + edges--; + } + +@@ -678,6 +710,7 @@ static void stmfb_disable_controller(str + writel(reg, host->base + VDCTRL4); + } + ++/* to be fixed! */ + static void stmfb_free_videomemory(struct imxfb_host *host) + { + struct stmfb_platformdata *pdata = host->pdev->dev.platform_data; +@@ -691,6 +724,63 @@ static void stmfb_free_videomemory(struc + host->fb_info.screen_base, host->fb_info.fix.smem_start); + } + ++ ++#define MX28_LCD_PIX_CLOCK_NAME "dis_lcdif" ++#define MX23_LCD_PIX_CLOCK_NAME "lcdif" ++ ++static int __devinit stmfb_init_clocks(struct imxfb_host *host) ++{ ++ int ret = 0; ++ ++ pr_debug("## %s\n", __func__); ++ ++ if (cpu_is_mx28()) ++ host->clk = clk_get(&host->pdev->dev, MX28_LCD_PIX_CLOCK_NAME); ++ if (cpu_is_stmp378x()) ++ host->clk = clk_get(&host->pdev->dev, MX23_LCD_PIX_CLOCK_NAME); ++ ++ if (IS_ERR(host->clk)) { ++ ret = PTR_ERR(host->clk); ++ goto out; ++ } ++ ++ ret = clk_enable(host->clk); ++ if (ret != 0) { ++ clk_put(host->clk); ++ goto out; ++ } ++ ++out: ++ return ret; ++} ++ ++static void __devinit stmfb_init_arch(struct imxfb_host *host, struct resource *res) ++{ ++ if (cpu_is_mx28()) { ++ pr_debug("Instantiating an i.MX28 LCDIF\n"); ++ host->transfer_count = MX28_TRANSFER_COUNT; ++ host->cur_buf = MX28_CUR_BUF; ++ host->next_buf = MX28_NEXT_BUF; ++ host->debug0 = MX28_DEBUG0; ++ host->hs_wdth_mask = 0x3fff; ++ host->hs_wdth_shift = 18; ++ /* FIXME: No ioremap()? */ ++ host->base = IO_ADDRESS(res->start); ++ } ++ ++ if (cpu_is_stmp378x()) { ++ pr_debug("Instantiating an i.MX23 LCDIF\n"); ++ host->transfer_count = MX23_TRANSFER_COUNT; ++ host->cur_buf = MX23_CUR_BUF; ++ host->next_buf = MX23_NEXT_BUF; ++ host->debug0 = MX23_DEBUG0; ++ host->hs_wdth_mask = 0xff; ++ host->hs_wdth_shift = 24; ++ /* FIXME: No ioremap()? */ ++ host->base = REGS_LCDIF_BASE; ++ } ++} ++ + static int __devinit stmfb_init_fbinfo(struct imxfb_host *host) + { + struct fb_info *fb_info = &host->fb_info; +@@ -747,35 +837,6 @@ static int __devinit stmfb_init_fbinfo(s + return 0; + } + +-#ifdef CONFIG_ARCH_MX28 +-# define LCD_PIX_CLOCK_NAME "dis_lcdif" +-#endif +-#ifdef CONFIG_ARCH_STMP378X +-# define LCD_PIX_CLOCK_NAME "lcdif" +-#endif +- +-static int stmfb_init_clocks(struct imxfb_host *host) +-{ +- int ret = 0; +- +- pr_debug("%s\n", __func__); +- +- host->clk = clk_get(&host->pdev->dev, LCD_PIX_CLOCK_NAME); +- if (IS_ERR(host->clk)) { +- ret = PTR_ERR(host->clk); +- goto out; +- } +- +- ret = clk_enable(host->clk); +- if (ret != 0) { +- clk_put(host->clk); +- goto out; +- } +- +-out: +- return ret; +-} +- + static int __devinit stmfb_probe(struct platform_device *pdev) + { + struct stmfb_platformdata *pdata = pdev->dev.platform_data; +@@ -817,17 +878,11 @@ static int __devinit stmfb_probe(struct + fb_info->fix.mmio_start = main_res->start; + fb_info->fix.mmio_len = resource_size(main_res); + +-#ifdef CONFIG_ARCH_MX28 +- /* FIXME: No ioremap()? */ +- host->base = IO_ADDRESS(res->start); +-#endif +-#ifdef CONFIG_ARCH_STMP378X +- /* FIXME: No ioremap()? */ +- host->base = REGS_LCDIF_BASE; +-#endif + host->pdev = pdev; + platform_set_drvdata(pdev, host); + ++ stmfb_init_arch(host, main_res); ++ + ret = stmfb_init_clocks(host); + if (ret != 0) + goto error_getclock; diff --git a/configs/platform-chumby/platformconfig b/configs/platform-chumby/platformconfig new file mode 100644 index 0000000..da92f15 --- /dev/null +++ b/configs/platform-chumby/platformconfig @@ -0,0 +1,200 @@ +# +# Automatically generated make config: don't edit +# PTXdist 2011.06.0-00012-g6bed447-dirty +# +PTXCONF_PLATFORMCONFIG_VERSION="2011.06.0-00012-g6bed447-dirty" +PTXCONF__platformconfig_MAGIC__=y + +# +# ------------------------------------ +# + +# +# Target Platform Configuration +# + +# +# ------------------------------------ +# +PTXCONF_PLATFORM="chumby" +PTXCONF_PLATFORM_VERSION="-master" + +# +# architecture +# +# PTXCONF_ARCH_ALPHA is not set +# PTXCONF_ARCH_AVR is not set +PTXCONF_ARCH_ARM=y +# PTXCONF_ARCH_BLACKFIN is not set +# PTXCONF_ARCH_X86 is not set +# PTXCONF_ARCH_MINGW is not set +# PTXCONF_ARCH_PPC is not set +# PTXCONF_ARCH_M68K is not set +# PTXCONF_ARCH_SPARC is not set +# PTXCONF_ARCH_MICROBLAZE is not set +# PTXCONF_ARCH_MIPS is not set +# PTXCONF_ARCH_CRIS is not set +# PTXCONF_ARCH_PARISC is not set +# PTXCONF_ARCH_SH is not set +PTXCONF_ARCH_SUPPORTS_ENDIAN_BIG=y +PTXCONF_ARCH_SUPPORTS_ENDIAN_LITTLE=y +# PTXCONF_ENDIAN_BIG is not set +PTXCONF_ENDIAN_LITTLE=y +# PTXCONF_ARCH_ARM_V6 is not set +# PTXCONF_ARCH_ARM_IWMMXT is not set +# PTXCONF_HAS_HARDFLOAT is not set +PTXCONF_HAS_MMU=y +PTXCONF_SIZEOF_LONG_DOUBLE="8" +PTXCONF_ARCH_STRING="arm" + +# +# paths & directories +# +PTXCONF_SYSROOT_TARGET="${PTXDIST_PLATFORMDIR}/sysroot-target" +PTXCONF_SYSROOT_HOST="${PTXDIST_PLATFORMDIR}/sysroot-host" +PTXCONF_SYSROOT_CROSS="${PTXDIST_PLATFORMDIR}/sysroot-cross" + +# +# toolchain +# +PTXCONF_CROSSCHAIN_VENDOR="OSELAS.Toolchain-2011" +PTXCONF_CROSSCHAIN_CHECK="4.5.2" +PTXCONF_LIBC_GLIBC=y +# PTXCONF_LIBC_UCLIBC is not set +PTXCONF_GLIBC_VERSION="2.13" +PTXCONF_GNU_TARGET="arm-v5te-linux-gnueabi" +PTXCONF_COMPILER_PREFIX="${PTXCONF_GNU_TARGET}-" +PTXCONF_COMPILER_PREFIX_KERNEL="${PTXCONF_COMPILER_PREFIX}" +PTXCONF_COMPILER_PREFIX_BOOTLOADER="${PTXCONF_COMPILER_PREFIX}" + +# +# extra toolchain options +# +PTXCONF_TARGET_EXTRA_CPPFLAGS="" +PTXCONF_TARGET_EXTRA_CFLAGS="" +PTXCONF_TARGET_EXTRA_CXXFLAGS="" +PTXCONF_TARGET_EXTRA_LDFLAGS="" +PTXCONF_KERNEL=y +# PTXCONF_KERNEL_INSTALL is not set +PTXCONF_KERNEL_MODULES=y +PTXCONF_KERNEL_MODULES_INSTALL=y +PTXCONF_KERNEL_MODULES_BUILD="modules" +PTXCONF_KERNEL_VERSION="2.6.28" +PTXCONF_KERNEL_MD5="d351e44709c9810b85e29b877f50968a" +PTXCONF_KERNEL_ARCH_STRING="arm" +# PTXCONF_KERNEL_IMAGE_BZ is not set +# PTXCONF_KERNEL_IMAGE_Z is not set +PTXCONF_KERNEL_IMAGE_U=y +# PTXCONF_KERNEL_IMAGE_VM is not set +# PTXCONF_KERNEL_IMAGE_VMLINUX is not set +# PTXCONF_KERNEL_IMAGE_RAW is not set +# PTXCONF_KERNEL_IMAGE_SIMPLE is not set +PTXCONF_KERNEL_IMAGE="uImage" +# PTXCONF_KERNEL_XZ is not set +# PTXCONF_KERNEL_LZOP is not set + +# +# patching & configuration +# +PTXCONF_KERNEL_SERIES="series" +PTXCONF_KERNEL_CONFIG="kernelconfig-${PTXCONF_KERNEL_VERSION}" + +# +# Development features +# +PTXCONF_KERNEL_EXTRA_MAKEVARS="CONFIG_DEBUG_SECTION_MISMATCH=y" +# PTXCONF_KERNEL_LOCAL_FLAG is not set +# PTXCONF_KERNEL_SYMLINK_IN_PROJECTDIR is not set +# PTXCONF_HOST_DTC is not set +# PTXCONF_DTC is not set + +# +# console options +# +PTXCONF_CONSOLE_NAME="ttyAM0" +PTXCONF_CONSOLE_SPEED="115200" + +# +# bootloaders +# +# PTXCONF_AT91BOOTSTRAP is not set +PTXCONF_BAREBOX=y +PTXCONF_BAREBOX_VERSION="2010.11.0" +PTXCONF_BAREBOX_MD5="4ba019cd0cc815ae4255a3525dde08ec" +PTXCONF_BAREBOX_CONFIG="barebox-${PTXCONF_BAREBOX_VERSION}.config" +PTXCONF_BAREBOX_ARCH_STRING="arm" +PTXCONF_BAREBOX_EXTRA_ENV=y +PTXCONF_BAREBOX_EXTRA_ENV_PATH="${PTXDIST_PLATFORMCONFIGDIR}/barebox-defaultenv" +PTXCONF_BOOTLETS=y +# PTXCONF_BOOTLETS_KERNEL is not set +PTXCONF_BOOTLETS_BOOTLOADER=y + +# +# Special options +# +# PTXCONF_BOOTLETS_MOBILESDRAM is not set +# PTXCONF_BOOTLETS_ENCRYPT is not set +PTXCONF_BOOTLOADER=y +# PTXCONF_GRUB is not set +# PTXCONF_U_BOOT_V2 is not set +# PTXCONF_U_BOOT is not set +# PTXCONF_X_LOAD is not set + +# +# flash +# +PTXCONF_FLASH_BLOCKSIZE="128k" + +# +# image creation options +# +# PTXCONF_IMAGE_CPIO is not set +# PTXCONF_IMAGE_CPIO_GZ is not set +PTXCONF_IMAGE_EXT2=y +PTXCONF_IMAGE_EXT2_SIZE=393592 +PTXCONF_IMAGE_EXT2_EXTRA_ARGS="" +# PTXCONF_IMAGE_EXT2_GZIP is not set +# PTXCONF_IMAGE_HD is not set + +# +# ipkg options +# +# PTXCONF_IMAGE_IPKG_PUSH_TO_REPOSITORY is not set +# PTXCONF_IMAGE_INSTALL_FROM_IPKG_REPOSITORY is not set +PTXCONF_IMAGE_IPKG_INDEX=y +PTXCONF_IMAGE_IPKG_EXTRA_ARGS="" +# PTXCONF_IMAGE_JFFS2 is not set +PTXCONF_IMAGE_KERNEL=y +# PTXCONF_IMAGE_KERNEL_INITRAMFS is not set +PTXCONF_IMAGE_KERNEL_INSTALL_EARLY=y +# PTXCONF_IMAGE_KERNEL_LZOP is not set +# PTXCONF_IMAGE_SQUASHFS is not set +PTXCONF_IMAGE_TGZ=y +# PTXCONF_IMAGE_UBI is not set +# PTXCONF_IMAGE_UBIFS is not set +# PTXCONF_IMAGE_UIMAGE is not set +PTXCONF_CROSS_MODULE_INIT_TOOLS=y +# PTXCONF_HOST_CDRKIT is not set +# PTXCONF_HOST_CMAKE is not set +# PTXCONF_HOST_CRAMFS is not set +# PTXCONF_HOST_DOSFSTOOLS is not set +# PTXCONF_HOST_E2FSPROGS is not set +PTXCONF_HOST_GENEXT2FS=y +# PTXCONF_HOST_GENPART is not set +# PTXCONF_HOST_GETTEXT is not set +# PTXCONF_HOST_LIBBLKID is not set +# PTXCONF_HOST_LIBBZ2 is not set +# PTXCONF_HOST_LIBCAP is not set +# PTXCONF_HOST_LIBLZO is not set +# PTXCONF_HOST_LIBUUID is not set +# PTXCONF_HOST_LZOP is not set +# PTXCONF_HOST_MKELFIMAGE is not set +# PTXCONF_HOST_MTD_UTILS is not set +# PTXCONF_HOST_MTOOLS is not set +# PTXCONF_HOST_OPENSSL is not set +# PTXCONF_HOST_SQUASHFS_TOOLS is not set +PTXCONF_HOST_UMKIMAGE=y +# PTXCONF_HOST_UTIL_LINUX_NG is not set +# PTXCONF_HOST_XL_TOOLS is not set +# PTXCONF_HOST_XZ is not set +# PTXCONF_HOST_ZLIB is not set diff --git a/configs/platform-chumby/platforms/bootlets.in b/configs/platform-chumby/platforms/bootlets.in new file mode 100644 index 0000000..543ec90 --- /dev/null +++ b/configs/platform-chumby/platforms/bootlets.in @@ -0,0 +1,61 @@ +## SECTION=bootloader + +menuconfig BOOTLETS + tristate + prompt "i.mX23 bootlets " +# select KERNEL +# select U-BOOT +# select ZIMAGE + help + Creates the binary boot stream required to bring up an i.MX23 CPU + based "chumby one" (aka "Falconwing") + +if BOOTLETS + +config BOOTLETS_KERNEL + bool + prompt "Kernel bootlet" + default y + help + Build a kernel bootlet and create a bootstream just starting a the + kernel from this BSP. + +config BOOTLETS_BOOTLOADER + bool + prompt "bootloader bootlet" + default y + help + Build a bootloader bootlet and create a bootstream just starting the + barebox bootloader from this BSP. + +comment "Special options" + +config BOOTLETS_MOBILESDRAM + bool + prompt "configure for mobile SDRAM" + help + If some kind of mobile SDRAM is in use, enable this entry. Note: The + "chumby one" uses a generic DDR SDRAM. + +config BOOTLETS_ENCRYPT + bool + prompt "support encryption" + help + Enabling this entry will encrypt the bootstream. Some i.MX23 based + platforms only booting encrypted bootstream images (like the + "i.MX23 EVK"). Other platforms (like the "chumby one") only booting + unencrypted bootstream images. + +if BOOTLETS_ENCRYPT + +config BOOTLETS_ZERO_ENCRYPT + bool + prompt "zeroed key" + help + Enabling this entry will encrypt the bootstream content with a zerod + key. Some platforms (like the "i.MX23 EVK") need this special kind + of key. + +endif + +endif diff --git a/configs/platform-chumby/projectroot/etc/hostname b/configs/platform-chumby/projectroot/etc/hostname new file mode 100644 index 0000000..bb4dbfe --- /dev/null +++ b/configs/platform-chumby/projectroot/etc/hostname @@ -0,0 +1 @@ +@HOSTNAME@-ChumbyOne diff --git a/configs/platform-chumby/projectroot/etc/io-env b/configs/platform-chumby/projectroot/etc/io-env new file mode 100644 index 0000000..e50af84 --- /dev/null +++ b/configs/platform-chumby/projectroot/etc/io-env @@ -0,0 +1,6 @@ +export TSLIB_TSDEVICE=/dev/input/event1 + +export QWS_MOUSE_PROTO=tslib:/dev/input/event1 + +# 70 mm by 53 mm is the correct visible size of the display +export QWS_DISPLAY=linuxfb:mmWidth=70:mmHeight=53 diff --git a/configs/platform-chumby/projectroot/etc/network/interfaces b/configs/platform-chumby/projectroot/etc/network/interfaces new file mode 100644 index 0000000..1acd6d4 --- /dev/null +++ b/configs/platform-chumby/projectroot/etc/network/interfaces @@ -0,0 +1,7 @@ +auto lo +iface lo inet loopback + +iface eth0 inet static + address 192.168.42.162 + gateway 192.168.23.1 + netmask 255.255.0.0 diff --git a/configs/platform-chumby/projectroot/etc/pointercal b/configs/platform-chumby/projectroot/etc/pointercal Binary files differnew file mode 100644 index 0000000..69e3fda --- /dev/null +++ b/configs/platform-chumby/projectroot/etc/pointercal diff --git a/configs/platform-chumby/projectroot/etc/profile.environment b/configs/platform-chumby/projectroot/etc/profile.environment new file mode 100644 index 0000000..3c6a63d --- /dev/null +++ b/configs/platform-chumby/projectroot/etc/profile.environment @@ -0,0 +1,19 @@ +# /etc/profile.environment - config for sub-shells +PS1="\\u@\\h:\\w " +PS2=" >" +PS4="+ " + +alias vim='vi' +alias l='ls -l' +alias ll='ls -al' +alias ..='cd ..' +alias ...='cd ../..' +alias md='mkdir' +alias rd='rmdir' + +export TSLIB_CONSOLEDEVICE=none +export TSLIB_TSDEVICE=/dev/input/event1 +export TSLIB_FBDEVICE=/dev/fb0 +#export TSLIB_CALIBFILE +#export TSLIB_CONFFILE +#export TSLIB_PLUGINDIR diff --git a/configs/platform-chumby/projectroot/etc/ts.conf b/configs/platform-chumby/projectroot/etc/ts.conf new file mode 100644 index 0000000..6cc41fa --- /dev/null +++ b/configs/platform-chumby/projectroot/etc/ts.conf @@ -0,0 +1,27 @@ +# Uncomment if you wish to use the linux input layer event interface +module_raw input + +# Uncomment if you're using a Sharp Zaurus SL-5500/SL-5000d +# module_raw collie + +# Uncomment if you're using a Sharp Zaurus SL-C700/C750/C760/C860 +# module_raw corgi + +# Uncomment if you're using a device with a UCB1200/1300/1400 TS interface +# module_raw ucb1x00 + +# Uncomment if you're using an HP iPaq h3600 or similar +# module_raw h3600 + +# Uncomment if you're using a Hitachi Webpad +# module_raw mk712 + +# Uncomment if you're using an IBM Arctic II +# module_raw arctic2 + +#module_raw dmc + +module pthres pmin=1 +#module variance delta=30 +#module dejitter delta=100 +module linear diff --git a/configs/platform-chumby/proprietary/elftosb2 b/configs/platform-chumby/proprietary/elftosb2 Binary files differnew file mode 100755 index 0000000..7b0fe8d --- /dev/null +++ b/configs/platform-chumby/proprietary/elftosb2 diff --git a/configs/platform-chumby/rules/bootlets.make b/configs/platform-chumby/rules/bootlets.make new file mode 100644 index 0000000..d9e4994 --- /dev/null +++ b/configs/platform-chumby/rules/bootlets.make @@ -0,0 +1,120 @@ +# -*-makefile-*- +# +# Copyright (C) 2010 by Juergen Beisert <jbe@pengutronix.de> +# +# See CREDITS for details about who has contributed to this project. +# +# For further information about the PTXdist project and license conditions +# see the README file. +# + +# +# We provide this package +# +PACKAGES-$(PTXCONF_BOOTLETS) += bootlets + +# +# Paths and names +# +BOOTLETS_VERSION := 10.07.11 +BOOTLETS := imx-bootlets-src-$(BOOTLETS_VERSION) +BOOTLETS_SUFFIX := tar.gz +BOOTLETS_URL := http://www.pengutronix.de/software/ptxdist/temporary-src/$(BOOTLETS).$(BOOTLETS_SUFFIX) +BOOTLETS_SOURCE := $(SRCDIR)/$(BOOTLETS).$(BOOTLETS_SUFFIX) +BOOTLETS_DIR := $(BUILDDIR)/$(BOOTLETS) +BOOTLETS_LICENSE := GPLv2 +BOOTLETS_MD5 := 8e64eaba3d7f80cd1e9a44e251fd5cd7 + +# ---------------------------------------------------------------------------- +# Get +# ---------------------------------------------------------------------------- + +$(BOOTLETS_SOURCE): + @$(call targetinfo) + @$(call get, BOOTLETS) + +# ---------------------------------------------------------------------------- +# Prepare (nothing) +# ---------------------------------------------------------------------------- + +BOOTLETS_COMPILE_DEPS := + +ifdef PTXCONF_BOOTLETS_KERNEL +BOOTLETS_COMPILE_DEPS += $(STATEDIR)/kernel.targetinstall.post +endif + +ifdef PTXCONF_BOOTLETS_BOOTLOADER +BOOTLETS_COMPILE_DEPS += $(STATEDIR)/barebox.targetinstall +endif + +$(STATEDIR)/bootlets.prepare: $(BOOTLETS_COMPILE_DEPS) + @$(call targetinfo) + @$(call touch) + +# ---------------------------------------------------------------------------- +# Compile +# ---------------------------------------------------------------------------- + +# do not use ':=' here! +BOOTLETS_MAKE_OPT = \ + BOARD=stmp378x_dev \ + CROSS_COMPILE=$(PTXCONF_GNU_TARGET)- \ + ARCH=mx23 \ + ELFTOSB="$(PTXDIST_PLATFORMCONFIGDIR)/proprietary/elftosb2 -f 37xx" + +ifdef PTXCONF_BOOTLETS_KERNEL +BOOTLETS_MAKE_OPT += linux_stream DFT_IMAGE=$(IMAGEDIR)/linuximage +endif + +ifdef PTXCONF_BOOTLETS_BOOTLOADER +BOOTLETS_MAKE_OPT += bootloader_stream DFT_UBOOT=$(BAREBOX_DIR)/barebox +endif + +ifdef PTXCONF_BOOTLETS_MOBILESDRAM +BOOTLETS_MAKE_OPT += MEM_TYPE=MEM_MDDR +else +BOOTLETS_MAKE_OPT += MEM_TYPE=MEM_DDR1 +endif + +ifdef PTXCONF_BOOTLETS_ENCRYPT +ifdef PTXCONF_BOOTLETS_ZERO_ENCRYPT +BOOTLETS_MAKE_OPT += ELFTOSB_KEY_PARAM="-z" +endif +else +BOOTLETS_MAKE_OPT += ELFTOSB_KEY_PARAM= +endif + +# Package's build system is broken +BOOTLETS_MAKE_PAR := NO + +# ---------------------------------------------------------------------------- +# Install +# ---------------------------------------------------------------------------- + +$(STATEDIR)/bootlets.install: + @$(call targetinfo) +ifdef PTXCONF_BOOTLETS_KERNEL + @cp $(BOOTLETS_DIR)/linux_stream $(IMAGEDIR)/sd_card_linux_bootstream +endif +ifdef PTXCONF_BOOTLETS_BOOTLOADER + @cp $(BOOTLETS_DIR)/bootloader_stream $(IMAGEDIR)/sd_card_bootloader_bootstream +endif + @$(call touch) + +# ---------------------------------------------------------------------------- +# Target-Install (nothing) +# ---------------------------------------------------------------------------- + +$(STATEDIR)/bootlets.targetinstall: + @$(call targetinfo) + @$(call touch) + +# ---------------------------------------------------------------------------- +# Clean +# ---------------------------------------------------------------------------- + +#$(STATEDIR)/bootlets.clean: +# @$(call targetinfo) +# @$(call clean_pkg, BOOTLETS) + +# vim: syntax=make |