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authorSascha Hauer <s.hauer@pengutronix.de>2018-05-09 14:17:06 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2018-05-09 14:17:06 +0200
commit091b51c0a9479d4d917d399e018f51db3d6332f9 (patch)
treeab5db151dfd29ade48b2f1bcb35ee4ce17ffa93b
parentcc234a70e5c237a9a81c30eb42455f466f095a73 (diff)
parent4b6d33c274abf515abc6749f40b4c84b0504f19e (diff)
downloadbarebox-091b51c0a9479d4d917d399e018f51db3d6332f9.tar.gz
Merge branch 'for-next/socfpga'
-rw-r--r--arch/arm/boards/ebv-socrates/pll_config.h6
-rw-r--r--arch/arm/boards/terasic-sockit/pll_config.h6
-rw-r--r--arch/arm/configs/socfpga_defconfig3
-rw-r--r--arch/arm/mach-socfpga/include/mach/pll_config.h4
-rw-r--r--drivers/net/Kconfig1
5 files changed, 8 insertions, 12 deletions
diff --git a/arch/arm/boards/ebv-socrates/pll_config.h b/arch/arm/boards/ebv-socrates/pll_config.h
index 083ebd4..e912912c 100644
--- a/arch/arm/boards/ebv-socrates/pll_config.h
+++ b/arch/arm/boards/ebv-socrates/pll_config.h
@@ -87,12 +87,6 @@
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
#define CONFIG_HPS_CLK_SDRVCO_HZ (666666666)
-#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
-#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
-#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
#define CONFIG_HPS_CLK_EMAC0_HZ (1953125)
#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
diff --git a/arch/arm/boards/terasic-sockit/pll_config.h b/arch/arm/boards/terasic-sockit/pll_config.h
index e064e2b..ef4a59a 100644
--- a/arch/arm/boards/terasic-sockit/pll_config.h
+++ b/arch/arm/boards/terasic-sockit/pll_config.h
@@ -87,12 +87,6 @@
#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
#define CONFIG_HPS_CLK_SDRVCO_HZ (800000000)
-#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
-#define CONFIG_HPS_CLK_OSC2_HZ (25000000)
-#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ (0)
-#define CONFIG_HPS_CLK_F2S_PER_REF_HZ (0)
-#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
-#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
#define CONFIG_HPS_CLK_EMAC0_HZ (1953125)
#define CONFIG_HPS_CLK_EMAC1_HZ (250000000)
#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
index dbc33f9..3a50bae 100644
--- a/arch/arm/configs/socfpga_defconfig
+++ b/arch/arm/configs/socfpga_defconfig
@@ -60,6 +60,7 @@ CONFIG_CMD_LED=y
CONFIG_CMD_SPI=y
CONFIG_CMD_LED_TRIGGER=y
CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_FIRMWARELOAD=y
CONFIG_CMD_OF_NODE=y
CONFIG_CMD_OF_PROPERTY=y
CONFIG_CMD_OFTREE=y
@@ -71,6 +72,7 @@ CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_OF_BAREBOX_ENV_IN_FS=y
CONFIG_DRIVER_SERIAL_NS16550=y
CONFIG_DRIVER_NET_DESIGNWARE=y
+CONFIG_DRIVER_NET_DESIGNWARE_SOCFPGA=y
CONFIG_MCI=y
CONFIG_MCI_DW=y
CONFIG_MFD_MC13XXX=y
@@ -81,6 +83,7 @@ CONFIG_LED_TRIGGERS=y
CONFIG_EEPROM_AT25=y
CONFIG_KEYBOARD_GPIO=y
CONFIG_GPIO_DESIGNWARE=y
+CONFIG_FIRMWARE_ALTERA_SOCFPGA=y
CONFIG_FS_EXT4=y
CONFIG_FS_TFTP=y
CONFIG_FS_NFS=y
diff --git a/arch/arm/mach-socfpga/include/mach/pll_config.h b/arch/arm/mach-socfpga/include/mach/pll_config.h
index 1a7e851..d6fb60d 100644
--- a/arch/arm/mach-socfpga/include/mach/pll_config.h
+++ b/arch/arm/mach-socfpga/include/mach/pll_config.h
@@ -1,3 +1,5 @@
+#ifndef _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_
+#define _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_
#include <mach/cyclone5-clock-manager.h>
@@ -54,3 +56,5 @@ static struct socfpga_cm_config cm_default_cfg = {
.alteragrp_mpu = CONFIG_HPS_ALTERAGRP_MPUCLK,
.alteregrp_main = CONFIG_HPS_ALTERAGRP_MAINCLK,
};
+
+#endif /* _MACH_SOCFPGA_PRELOADER_PLL_CONFIG_H_ */
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 09676b3..b633a3a 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -82,6 +82,7 @@ config DRIVER_NET_DESIGNWARE_GENERIC
config DRIVER_NET_DESIGNWARE_SOCFPGA
bool "Designware Universal MAC ethernet driver for SoCFPGA platforms"
depends on ARCH_SOCFPGA
+ select MFD_SYSCON
help
This option enables support for the Synopsys
Designware Core Univesal MAC 10M/100M/1G ethernet IP on SoCFPGA.