clk: layerscape: increase PLL divider array

Newer Layerscape SoCs like the LS1028a have more PLL dividers,
increase the divider array to accomodate this.

Link: https://lore.barebox.org/20240109161527.3237581-18-s.hauer@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c
index 6c69b5b3f3..44155692a8 100644
--- a/drivers/clk/clk-qoric.c
+++ b/drivers/clk/clk-qoric.c
@@ -27,6 +27,7 @@
 #define CGA_PLL4	4	/* only on clockgen-1.0, which lacks CGB */
 #define CGB_PLL1	4
 #define CGB_PLL2	5
+#define MAX_PLL_DIV	32
 
 struct clockgen_pll_div {
 	struct clk_hw *hw;
@@ -34,7 +35,7 @@ struct clockgen_pll_div {
 };
 
 struct clockgen_pll {
-	struct clockgen_pll_div div[8];
+	struct clockgen_pll_div div[MAX_PLL_DIV];
 };
 
 #define CLKSEL_VALID	1