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author | Stefan Kerkmann <s.kerkmann@pengutronix.de> | 2024-02-28 14:14:08 +0100 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2024-03-13 12:00:29 +0100 |
commit | 05d5bf40afb7b6c0c5bb3636151709d5aa700998 (patch) | |
tree | 9898164b9c5cafc71dbc6aab44fb9938b21b2fdf | |
parent | e7f3fc8f989adc641e35a3d49204aba7de613897 (diff) | |
download | barebox-05d5bf40afb7b6c0c5bb3636151709d5aa700998.tar.gz barebox-05d5bf40afb7b6c0c5bb3636151709d5aa700998.tar.xz |
arm: mach-imx: tzasc: lock id_swap_bypass bit
This commit ports U-Boot commit 1289ff7bd7e4 ("imx8m: lock
id_swap_bypass bit in tzc380 enable") to barebox. This is the original
commit message:
> According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock
> bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in
> order to avoid AXI bus errors when GPU is enabled on the platform.
> TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable
> derivatives, but is missing a lock settings to be applied.
>
> Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have
> it implemented.
>
> Since we're here, provide also names to bits from TRM instead of using
> BIT() macro in the code.
Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Signed-off-by: Stefan Kerkmann <s.kerkmann@pengutronix.de>
Link: https://lore.barebox.org/20240228-v2024-02-0-topic-imx8m-n-p-tzac-v2-1-ee1ae48dc399@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r-- | arch/arm/mach-imx/tzasc.c | 42 |
1 files changed, 32 insertions, 10 deletions
diff --git a/arch/arm/mach-imx/tzasc.c b/arch/arm/mach-imx/tzasc.c index 9c71108c99..1f8d7426c1 100644 --- a/arch/arm/mach-imx/tzasc.c +++ b/arch/arm/mach-imx/tzasc.c @@ -5,37 +5,59 @@ #include <mach/imx/imx8m-regs.h> #include <io.h> -#define GPR_TZASC_EN BIT(0) -#define GPR_TZASC_SWAP_ID BIT(1) -#define GPR_TZASC_EN_LOCK BIT(16) +#define GPR_TZASC_EN BIT(0) +#define GPR_TZASC_ID_SWAP_BYPASS BIT(1) +#define GPR_TZASC_EN_LOCK BIT(16) +#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17) -static void enable_tzc380(bool bypass_id_swap) +#define MX8M_TZASC_REGION_ATTRIBUTES_0 (MX8M_TZASC_BASE_ADDR + 0x108) +#define MX8M_TZASC_REGION_ATTRIBUTES_0_SP GENMASK(31, 28) + +static void enable_tzc380(bool bypass_id_swap, bool bypass_id_swap_lock) { u32 __iomem *gpr = IOMEM(MX8M_IOMUXC_GPR_BASE_ADDR); /* Enable TZASC and lock setting */ setbits_le32(&gpr[10], GPR_TZASC_EN); setbits_le32(&gpr[10], GPR_TZASC_EN_LOCK); + + /* + * According to TRM, TZASC_ID_SWAP_BYPASS should be set in + * order to avoid AXI Bus errors when GPU is in use + */ if (bypass_id_swap) - setbits_le32(&gpr[10], BIT(1)); + setbits_le32(&gpr[10], GPR_TZASC_ID_SWAP_BYPASS); + + /* + * imx8mn and imx8mp implements the lock bit for + * TZASC_ID_SWAP_BYPASS, enable it to lock settings + */ + if (bypass_id_swap_lock) + setbits_le32(&gpr[10], GPR_TZASC_ID_SWAP_BYPASS_LOCK); + /* * set Region 0 attribute to allow secure and non-secure * read/write permission. Found some masters like usb dwc3 * controllers can't work with secure memory. */ - writel(0xf0000000, MX8M_TZASC_BASE_ADDR + 0x108); + writel(MX8M_TZASC_REGION_ATTRIBUTES_0_SP, + MX8M_TZASC_REGION_ATTRIBUTES_0); } void imx8mq_tzc380_init(void) { - enable_tzc380(false); + enable_tzc380(false, false); } -void imx8mn_tzc380_init(void) __alias(imx8mm_tzc380_init); -void imx8mp_tzc380_init(void) __alias(imx8mm_tzc380_init); void imx8mm_tzc380_init(void) { - enable_tzc380(true); + enable_tzc380(true, false); +} + +void imx8mn_tzc380_init(void) __alias(imx8mp_tzc380_init); +void imx8mp_tzc380_init(void) +{ + enable_tzc380(true, true); } bool tzc380_is_enabled(void) |